Display substrate, display device, and method for manufacturing display substrate

Abstract

The present application provides a display substrate. A first frame area of the display substrate comprises a plurality of pads. At least one pad comprises: a first insulating layer located on the side of a plurality of data line leads facing away from a base substrate, wherein the first insulating layer comprises a first opening exposing at least a portion of at least one data line lead; a first metal layer located on the side of the plurality of data line leads and the first insulating layer facing away from the base substrate, wherein the first metal layer comprises a first bottom portion and a step portion surrounding the first bottom portion, the orthographic projection of the first bottom portion on the base substrate is located within the orthographic projection of the first opening on the base substrate, the first bottom portion is electrically connected to at least one data line lead among the plurality of data line leads, the step portion comprises a first step portion arranged in a direction parallel to the base substrate and a second step portion forming an included angle with the first step portion, and the second step portion connects the first bottom portion and the first step portion; and a second insulating layer located on the side of the first metal layer and the first insulating layer facing away from the base substrate, wherein the second insulating layer comprises a second opening exposing at least a portion of the first bottom portion of the first metal layer, and the orthographic projection of the second insulating layer on the base substrate covers the orthographic projections of the first step portion and the second step portion of the first metal layer on the base substrate.

Description

Display substrate, display device, and method for fabricating display substrate Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to a display substrate, a display device, and a method for preparing the display substrate. Background Technology

[0002] Active-matrix organic light-emitting diode (AMOLED) display panels are widely used in electronic products due to their flexibility, thinness, active light emission, high brightness, fast response speed, and bendability. As the number of signal lines in display panels increases, layered arrangement of these lines is necessary to achieve a narrow bezel effect. In the bezel area of ​​the display substrate, some pads used to connect to the driver chip are fabricated simultaneously using the multi-layer signal line manufacturing process. The stacking of multiple film layers can lead to excessively large step differences (i.e., significant height differences between different positions of the film layers) in the pads.

[0003] Summary of the Invention

[0004] On one hand, this disclosure provides a display substrate, comprising: a substrate including a display area and a first border area located on at least one side of the display area; a plurality of sub-pixels located on one side of the substrate and in the display area; a plurality of data lines located in the display area and electrically connected to the plurality of sub-pixels; a plurality of data line leads located in the first border area and electrically connected to the plurality of data lines; and a plurality of pads located in the first border area and electrically connected to the plurality of data line leads; wherein at least one of the plurality of pads comprises: a first insulating layer located on the side of the plurality of data line leads away from the substrate, the first insulating layer including a first opening exposing at least a portion of at least one of the plurality of data line leads; and a first metal layer located on the side of the plurality of data line leads away from the substrate and electrically connected to at least one of the plurality of data line leads through the first opening; wherein the first metal layer covers... The device includes a first bottom and a stepped portion surrounding the first bottom, wherein the orthographic projection of the first bottom on the substrate lies within the orthographic projection of the first opening on the substrate, and the first bottom is electrically connected to at least one of the plurality of data line leads. The stepped portion includes a first stepped portion located on the side of the first insulating layer away from the substrate and a second stepped portion forming an angle with the first stepped portion. The second stepped portion connects the first bottom and the first stepped portion, and the orthographic projection of the second stepped portion on the substrate lies within the orthographic projection of the first opening on the substrate. The device also includes a second insulating layer located on the side of the first metal layer and the first insulating layer away from the substrate, wherein the second insulating layer includes a second opening exposing at least a portion of the first bottom of the first metal layer, and the orthographic projection of the second insulating layer on the substrate covers the orthographic projections of the first stepped portion and the second stepped portion on the substrate.

[0005] In some embodiments, the orthographic projection of the second insulating layer on the substrate partially overlaps with the orthographic projection of the first bottom on the substrate, and the orthographic projection of the second opening on the substrate is located within the orthographic projection of the first opening on the substrate.

[0006] In some embodiments, the display substrate further includes: a second metal layer located on the side of the first metal layer and the second insulating layer away from the substrate, wherein the second metal layer is electrically connected to the first metal layer through the second opening, the orthographic projection of the second metal layer on the substrate does not overlap with the orthographic projection of the first step portion of the first metal layer on the substrate, and the orthographic projection of the second metal layer on the substrate covers the orthographic projection of the second opening on the substrate.

[0007] In some embodiments, the display substrate further includes: a third metal layer located on the side of the second metal layer opposite to the substrate, wherein the third metal layer is electrically connected to the second metal layer, and the orthographic projection of the third metal layer on the substrate covers the orthographic projection of the second metal layer on the substrate.

[0008] In some embodiments, the orthographic projection of the third metal layer on the substrate does not overlap with the orthographic projection of the first step portion of the first metal layer on the substrate, and the orthographic projection of the third metal layer on the substrate is located within the orthographic projection of the first opening on the substrate.

[0009] In some embodiments, the orthogonal projection of the third metal layer on the substrate covers the orthogonal projection of the first metal layer on the substrate.

[0010] In some embodiments, the orthographic projection of the third metal layer on the substrate is located within the orthographic projection of the first metal layer on the substrate, and overlaps with the orthographic projection portion of the first step portion on the substrate.

[0011] In some embodiments, the second insulating layer is an inorganic insulating layer or an organic insulating layer.

[0012] In some embodiments, the second insulating layer is an organic insulating layer, and the orthographic projection of the third metal layer on the substrate covers the orthographic projection of the second insulating layer on the substrate.

[0013] In some embodiments, the second insulating layer includes a first insulator layer and a second insulator layer, wherein the second insulator layer is located on the side of the first insulator layer opposite to the substrate.

[0014] In some embodiments, the material of the first insulator layer is an inorganic material, and the material of the second insulator layer is an organic material.

[0015] In some embodiments, the orthographic projections of the first insulator layer and the second insulator layer on the substrate both cover the orthographic projections of the first step portion and the second step portion of the first metal layer on the substrate.

[0016] In some embodiments, the orthographic projection of the first insulator layer on the substrate covers the orthographic projections of the first step portion and the second step portion of the first metal layer on the substrate, and the orthographic projection of the second insulator layer on the substrate does not overlap with the orthographic projection of the first opening on the substrate.

[0017] In some embodiments, the material of the first insulator layer is an organic material, and the material of the second insulator layer is an inorganic material. The orthographic projections of the first insulator layer and the second insulator layer on the substrate cover the orthographic projections of the first step portion and the second step portion of the first metal layer on the substrate.

[0018] In some embodiments, the display substrate further includes: a third insulating layer located on the side of the third metal layer away from the substrate, wherein the third insulating layer includes a third opening; and a fourth metal layer located on the side of the third metal layer and the third insulating layer away from the substrate, wherein the fourth metal layer is electrically connected to the third metal layer through the third opening.

[0019] In some embodiments, the orthographic projection of the first opening on the substrate lies within the orthographic projection of the third opening on the substrate, and the orthographic projection of the fourth metal layer on the substrate covers the orthographic projection of the third metal layer on the substrate.

[0020] In some embodiments, at least one of the plurality of sub-pixels includes a thin-film transistor, the thin-film transistor including: a gate metal layer on the substrate, a gate insulating layer on the side of the gate metal layer away from the substrate, and a first source-drain metal layer, a second source-drain metal layer and a third source-drain metal layer sequentially arranged on the side of the gate insulating layer away from the substrate.

[0021] In some embodiments, the plurality of data line leads are disposed on the same layer as the gate metal layer, the first insulating layer is disposed on the same layer as the gate insulating layer, the first metal layer is disposed on the same layer as the first source-drain metal layer, the second metal layer is disposed on the same layer as the second source-drain metal layer, and the third metal layer is disposed on the same layer as the third source-drain metal layer.

[0022] On the other hand, this disclosure provides a display device including the above-described display substrate.

[0023] In another aspect, this disclosure provides a method for fabricating the aforementioned display substrate, comprising: providing a substrate, the substrate including a display area and a first border area located on at least one side of the display area; fabricating a plurality of sub-pixels, a plurality of data lines, and a plurality of data line leads on one side of the substrate, the plurality of sub-pixels and the plurality of data lines being located in the display area and electrically connected to each other, the plurality of data line leads being located in the first border area and electrically connected to each other; fabricating a plurality of pads in the first border area, the step of fabricating at least one of the plurality of pads comprising: forming a first insulating layer on the side of the plurality of data line leads away from the substrate, the first insulating layer including a first opening exposing at least a portion of at least one of the plurality of data line leads; forming a first metal layer on the side of the plurality of data line leads away from the substrate, the first metal layer being electrically connected to at least one of the plurality of data line leads through the first opening, wherein... In the first metal layer, there are a first bottom and a stepped portion surrounding the first bottom. The orthographic projection of the first bottom on the substrate is located within the orthographic projection of the first opening on the substrate. The first bottom is electrically connected to at least one of the plurality of data line leads. The stepped portion includes a first stepped portion located on the side of the first insulating layer away from the substrate and a second stepped portion forming an angle with the first stepped portion. The second stepped portion connects the first bottom and the first stepped portion, and the orthographic projection of the second stepped portion on the substrate is located within the orthographic projection of the first opening on the substrate. A second insulating layer is formed on the side of the first metal layer and the first insulating layer away from the substrate. The second insulating layer includes a second opening that exposes at least a portion of the first bottom of the first metal layer. The orthographic projection of the second insulating layer on the substrate covers the orthographic projections of the first stepped portion and the second stepped portion of the first metal layer on the substrate.

[0024] In some embodiments, the method further includes: forming a second metal layer on the side of the first metal layer and the second insulating layer away from the substrate, wherein the second metal layer is electrically connected to the first metal layer through the second opening, the orthographic projection of the second metal layer on the substrate does not overlap with the orthographic projection of the first step portion of the first metal layer on the substrate, and the orthographic projection of the second metal layer on the substrate covers the orthographic projection of the second opening on the substrate.

[0025] In some embodiments, the method further includes: forming a third metal layer on the side of the second metal layer opposite to the substrate, wherein the third metal layer is electrically connected to the second metal layer, and the orthographic projection of the third metal layer on the substrate covers the orthographic projection of the second metal layer on the substrate.

[0026] In some embodiments, forming a second insulating layer on the side of the first metal layer and the first insulating layer away from the substrate includes: forming a second insulating layer on the side of the first metal layer and the first insulating layer away from the substrate using an inorganic material.

[0027] In some embodiments, forming a second insulating layer on the side of the first metal layer and the first insulating layer away from the substrate includes: forming a second insulating layer on the side of the first metal layer and the first insulating layer away from the substrate using an organic material.

[0028] In some embodiments, forming a second insulating layer on the side of the first metal layer and the first insulating layer away from the substrate includes: forming a first insulator layer on the side of the first metal layer and the first insulating layer away from the substrate using an inorganic material; and forming a second insulator layer on the side of the first insulator layer away from the substrate using an organic material.

[0029] In some embodiments, forming a second insulating layer on the side of the first metal layer and the first insulating layer away from the substrate includes: forming a first insulator layer on the side of the first metal layer and the first insulating layer away from the substrate using an organic material; and forming a second insulator layer on the side of the first insulator layer away from the substrate using an inorganic material.

[0030] On the other hand, this disclosure provides a method for fabricating the above-mentioned display substrate, comprising: providing a substrate, the substrate including a display area and a first border area located on at least one side of the display area; fabricating a plurality of sub-pixels, a plurality of data lines, and a plurality of data line leads on one side of the substrate, the plurality of sub-pixels and the plurality of data lines being located in the display area and electrically connected to each other, the plurality of data line leads being located in the first border area and electrically connected to each other; fabricating a plurality of pads in the first border area, the step of fabricating at least one of the plurality of pads comprising: forming a first insulating layer on the side of the plurality of data line leads away from the substrate, the first insulating layer including a first opening exposing at least a portion of at least one of the plurality of data line leads; forming a first metal layer on the side of the plurality of data line leads away from the substrate, the first metal layer being electrically connected to at least one of the plurality of data line leads through the first opening, wherein the first metal layer includes a first bottom and a stepped portion surrounding the first bottom, the orthographic projection of the first bottom on the substrate being located at the first opening. The first bottom is electrically connected to at least one of the plurality of data line leads within the orthographic projection of the opening on the substrate. The stepped portion includes a first stepped portion located on the side of the first insulating layer away from the substrate and a second stepped portion forming an angle with the first stepped portion. The second stepped portion connects the first bottom and the first stepped portion, and the orthographic projection of the second stepped portion on the substrate is located within the orthographic projection of the first opening on the substrate. A second insulating layer is formed on the side of the first metal layer and the first insulating layer away from the substrate, wherein the second insulating layer covers the orthographic projection of the first metal layer on the substrate. A second metal layer is formed on the side of the second insulating layer away from the substrate. The second metal layer is removed. A third metal layer is formed on the side of the second insulating layer away from the substrate. The third metal layer is removed. A second opening is formed on the second insulating layer, the second opening exposing at least a portion of the first bottom of the first metal layer, and the orthographic projection of the second insulating layer on the substrate covers the first stepped portion and the orthographic projection of the second stepped portion on the substrate. Attached Figure Description

[0031] To more clearly describe the technical solutions in the embodiments of this disclosure, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0032] Figure 1A is a schematic diagram of a display substrate according to an embodiment of the present disclosure;

[0033] Figure 1B is another schematic diagram of the display substrate according to an embodiment of the present disclosure;

[0034] Figure 2 is a partial schematic diagram of the first signal access area according to an embodiment of this disclosure;

[0035] Figure 3 is a magnified view of the details of region S in Figure 2;

[0036] Figure 4 is a schematic cross-sectional view of the display area of ​​the display substrate shown in Figure 1A, taken along line aa'.

[0037] Figures 5(a)-5(e) show schematic cross-sectional views of a pad fabrication process according to an embodiment of the present disclosure;

[0038] Figures 6(a)-6(e) show cross-sectional schematic diagrams of the pad fabrication process and pad structure of a display substrate according to an embodiment of the present disclosure;

[0039] Figures 7(a)-7(e) show cross-sectional schematic diagrams of the pad fabrication process and pad structure of the display substrate according to embodiments of the present disclosure;

[0040] Figures 8(a)-8(e) show cross-sectional schematic diagrams of the pad fabrication process and pad structure of the display substrate according to embodiments of the present disclosure;

[0041] Figures 9(a)-9(f) show cross-sectional schematic diagrams of the pad fabrication process and pad structure of the display substrate according to embodiments of the present disclosure;

[0042] Figures 10(a)-10(f) show cross-sectional schematic diagrams of the pad fabrication process and pad structure of the display substrate according to embodiments of the present disclosure;

[0043] Figure 11 shows a schematic cross-sectional view of the pads of a display substrate according to an embodiment of the present disclosure;

[0044] Figure 12 shows a schematic cross-sectional view of the pads of a display substrate according to an embodiment of the present disclosure;

[0045] Figure 13 shows a schematic cross-sectional view of the pads of a display substrate according to an embodiment of the present disclosure;

[0046] Figure 14 shows a schematic cross-sectional view of a display substrate according to an embodiment of the present disclosure.

[0047] It should be understood that the accompanying drawings are merely schematic illustrations of exemplary embodiments of the present disclosure and are not intended to limit the scope of the disclosure, and need not be drawn strictly to scale. Furthermore, in the drawings, the same or similar reference numerals are used to refer to the same or similar parts. Detailed Implementation

[0048] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0049] It is understood that the various figures in the embodiments of this disclosure are only used to schematically show the connection relationship between the various components. The dimensions of the various components in the figures are not drawn to scale, and their relative positional relationship may not completely correspond to the actual position.

[0050] In this disclosure, unless otherwise expressly specified and limited, the terms "installation," "connection," "joining," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this disclosure according to the specific circumstances.

[0051] In this disclosure, "electrical connection" includes the situation where components are connected together by a component having a certain electrical function. There are no particular limitations on the term "component having a certain electrical function," as long as it enables the transmission and reception of electrical signals between the connected components. Examples of "components having a certain electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0052] In this disclosure, the terms "film" and "layer" can be interchanged. For example, sometimes "conductive layer" can be replaced with "conductive film". Similarly, sometimes "insulating film" can be replaced with "insulating layer".

[0053] The "patterning process" as described in this disclosure includes processes such as depositing a film layer, coating photoresist, mask exposure, development, etching, and photoresist stripping. Deposition can be performed using any one or more methods selected from sputtering, evaporation, and chemical vapor deposition; coating can be performed using any one or more methods selected from spraying and spin coating; and etching can be performed using any one or more methods selected from dry etching and wet etching. A "thin film" refers to a thin film of a certain material fabricated on a substrate using a deposition or coating process. If the "thin film" does not require a patterning process during the entire fabrication process, it can also be called a "layer." If the "thin film" requires a patterning process during the entire fabrication process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern."

[0054] Figure 1A is a schematic diagram of a display substrate according to an embodiment of the present disclosure. Figure 1B is another schematic diagram of a display substrate according to an embodiment of the present disclosure. Both Figures 1A and 1B show planar schematic diagrams of the display substrate before the bending process.

[0055] In some examples, as shown in Figures 1A and 1B, the display substrate may include a display area AA and a peripheral area BB surrounding the display area AA. For example, the peripheral area BB may include a first border area B1 located on one side of the display area AA, and border areas located on other sides of the display area AA (e.g., a second border area B2, a third border area B3, and a fourth border area B4). The first border area B1 may be, for example, the bottom border of the display panel; the second border area B2 may be, for example, the top border of the display panel; the third border area B3 may be, for example, the left border of the display panel; and the fourth border area B4 may be, for example, the right border of the display panel.

[0056] In some examples, as shown in Figures 1A and 1B, the display area AA can be a flat area comprising multiple sub-pixels PX that make up a pixel array. These sub-pixels PX can be configured to display moving or still images. The display area AA can be referred to as the active area. In some examples, the display area AA can be rectangular. However, this embodiment is not limited to this. For example, the display area AA can be other shapes such as circular or elliptical. In some examples, the display panel can be a flexible panel, and therefore the display panel can be deformable, such as rolled, bent, folded, or rolled up.

[0057] In some examples, as shown in Figures 1A and 1B, the display area AA may include at least: multiple sub-pixels PX, multiple gate lines GL, and multiple data lines DL. The multiple gate lines GL may extend along a first direction X, and the multiple data lines DL may extend along a second direction Y. The orthogonal projections of the multiple gate lines GL and the multiple data lines DL onto the substrate may intersect to form multiple sub-pixel regions, each of which may contain one sub-pixel PX. The multiple data lines DL may be electrically connected to the multiple sub-pixels PX, and the multiple data lines DL may be configured to provide data signals to the multiple sub-pixels PX. The multiple gate lines GL may be electrically connected to the multiple sub-pixels PX, and the multiple gate lines GL may be configured to provide gate control signals to the multiple sub-pixels PX. In some examples, the gate control signals may include scan signals and light emission control signals, or may include scan signals, or may include scan signals, reset control signals, and light emission control signals.

[0058] In some examples, as shown in Figures 1A and 1B, the first direction X can be the extension direction of the grid line GL in the display area AA (e.g., the row direction), and the second direction Y can be the extension direction of the data line DL in the display area AA (e.g., the column direction). The first direction X and the second direction Y can intersect each other, for example, they can be perpendicular to each other.

[0059] In some examples, a pixel unit of the display area AA may include three sub-pixels, namely a red sub-pixel, a green sub-pixel, and a blue sub-pixel. However, this embodiment is not limited to this. In some examples, a pixel unit may include four sub-pixels, namely a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel.

[0060] In some examples, the shape of the subpixels can be rectangular, rhomboid, pentagonal, or hexagonal. When a pixel unit includes three subpixels, the three subpixels can be arranged horizontally side-by-side, vertically side-by-side, or in a triangular arrangement; when a pixel unit includes four subpixels, the four subpixels can be arranged horizontally side-by-side, vertically side-by-side, or in a square arrangement. However, this embodiment is not limited in this respect.

[0061] In some examples, a sub-pixel may include a pixel circuit and a light-emitting element electrically connected to the pixel circuit (indicated by L in FIG1A; note that for simplicity, the light-emitting element L is shown in only one sub-pixel PX in FIG1A, which does not represent a limitation of this disclosure). The pixel circuit may include multiple transistors and at least one capacitor. For example, the pixel circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure. In the above circuit structures, T refers to a thin-film transistor, C refers to a capacitor, the number before T represents the number of thin-film transistors in the circuit, and the number before C represents the number of capacitors in the circuit. In some examples, the multiple transistors in the pixel circuit may include P-type transistors and N-type transistors. However, this embodiment is not limited to this.

[0062] In some examples, multiple transistors in the pixel circuit can be employed as low-temperature polysilicon (LTPS) thin-film transistors (TFTs) and oxide (OPT) thin-film transistors (OTPTs). The active layer of the LTPS TFT is made of low-temperature polysilicon (LTPS), while the active layer of the OPT TFT is made of oxide. LTPS TFTs offer advantages such as high mobility and fast charging, while OPT TFTs offer advantages such as low leakage current. Integrating LTPS and OPT TFTs onto a single display substrate, i.e., an LTPS+Opide (LTPO) display substrate, leverages the advantages of both, enabling low-frequency driving, reducing power consumption, and improving display quality.

[0063] In some examples, the light-emitting element can be any of the following: a light-emitting diode (LED), an organic light-emitting diode (OLED), a quantum dot light-emitting diode (QLED), or a micro-LED (including mini-LED or micro-LED). For example, the light-emitting element can be an OLED, which can emit red, green, blue, or white light under the drive of its corresponding pixel circuit. The color of the light emitted by the light-emitting element can be determined as needed. In some examples, the light-emitting element may include an anode, a cathode, and an organic light-emitting layer located between the anode and cathode. The anode of the light-emitting element can be electrically connected to the corresponding pixel circuit. However, this embodiment is not limited in this respect.

[0064] In some examples, the display substrate can integrate a touch structure. The display substrate may include an organic light-emitting diode (OLED) display structure, a plasma display structure, or an electrophoretic display structure. For example, the display substrate may include an OLED display structure and a touch structure. The touch structure can be disposed on the encapsulation layer of the display structure, forming a Touch on Thin Film Encapsulation (TFE) structure. The integration of the display structure and the touch structure offers advantages such as thinness, lightness, and foldability, meeting the product requirements for flexible folding and narrow bezels.

[0065] In some examples, the touch structure on thin-film encapsulation mainly includes the Flexible Multi-Layer On Cell (FMLOC) structure and the Flexible Single-Layer On Cell (FSLOC) structure. The FMLOC structure operates based on mutual capacitance detection, typically using two metal layers to form the driving (Tx) electrode and the sensing (Rx) electrode. The integrated circuit (IC) detects the mutual capacitance between the driving and sensing electrodes to achieve touch action. The FSLOC structure operates based on self-capacitance (or voltage) detection, typically using a single metal layer to form the touch electrode. The integrated circuit detects the self-capacitance (or voltage) of the touch electrode to achieve touch action.

[0066] Figure 4 is a cross-sectional view of the display area of ​​the display substrate shown in Figure 1A, taken along line aa'. Figure 4 illustrates the structure of a sub-pixel in the display area as an example. In this example, multiple transistors in the pixel circuit are of the same type; for example, the multiple transistors in the pixel circuit can all be low-temperature polysilicon thin-film transistors (LTPS) or all be oxide thin-film transistors (OPS). In other examples, the multiple transistors in the pixel circuit can be both LTPS and OPS. Furthermore, this example illustrates a display panel integrating a mutual capacitance touch structure to form an FMLOC structure.

[0067] In some examples, as shown in Figure 4, the display area of ​​the display panel may include, in the direction perpendicular to the display panel, a substrate 100, and a circuit structure layer 20, a light-emitting structure layer 30, an encapsulation structure layer 40, a touch structure layer 50, and a color filter layer 60 sequentially disposed on the substrate 100. The display structure layer may include at least the circuit structure layer 20 and the light-emitting structure layer 30. The circuit structure layer 20 may include at least pixel circuits for multiple sub-pixels, each sub-pixel's pixel circuit including multiple transistors and at least one capacitor. The light-emitting structure layer 30 may include at least light-emitting elements for multiple sub-pixels.

[0068] In some examples, Figure 4 illustrates an example where each sub-pixel includes a thin-film transistor 21 and a capacitor 22. In some examples, the circuit structure layer 20 of the display area may include: a semiconductor layer, a first gate metal layer, a second gate metal layer, a first source-drain metal layer, a second source-drain metal layer, and a third source-drain metal layer disposed on the substrate 100. The multiple display area metal layers of the display structure layer in this example may include: a first gate metal layer, a second gate metal layer, a first source-drain metal layer, a second source-drain metal layer, and a third source-drain metal layer. A first gate insulating layer 201 may be disposed between the semiconductor layer and the first gate metal layer; a second gate insulating layer 202 may be disposed between the first gate metal layer and the second gate metal layer; an interlayer insulating layer 203 may be disposed between the second gate metal layer and the first source-drain metal layer; a passivation layer 204 and a first planarization layer 205 may be disposed between the first source-drain metal layer and the second source-drain metal layer; a second planarization layer 206 may be disposed between the second source-drain metal layer and the third source-drain metal layer; and a third planarization layer 207 may be disposed on the side of the third source-drain metal layer away from the substrate 100. The first gate insulating layer 201, the second gate insulating layer 202, the interlayer insulating layer 203, and the passivation layer 204 may be inorganic insulating layers, while the first planarization layer 205, the second planarization layer 206, and the third planarization layer 207 may be organic insulating layers. However, this embodiment is not limited to these limitations. In other examples, a buffer layer may be disposed on the side of the semiconductor layer closest to the substrate. This buffer layer prevents harmful substances from the substrate from penetrating the interior of the display substrate and also increases the adhesion of the film layers in the display substrate to the substrate. In still other examples, a bottom shielding metal layer (BSM) may be disposed on the side of the buffer layer closest to the substrate. This bottom shielding metal layer may be configured to at least partially cover the active layer of the thin-film transistor in the pixel circuitry to prevent external light from affecting the performance of the thin-film transistor. In still other examples, a passivation layer may be omitted between the first and second source-drain metal layers, and only a first planarization layer may be disposed between the first and second source-drain metal layers.

[0069] In some examples, as shown in FIG4, the semiconductor layer of the display area may include at least the active layer 210 of the thin-film transistor 21. The active layer 210 of the thin-film transistor 21 may include a first region 2101, a second region 2102, and a channel region 2100 located between the first region 2101 and the second region 2102. The first gate metal layer may include at least the gate 213 of the thin-film transistor 21 and the first electrode 221 of the capacitor 22. The orthographic projection of the gate 213 of the thin-film transistor 21 onto the substrate 100 may cover the orthographic projection of the channel region 2100 of the active layer 210 onto the substrate 100. The second gate metal layer may include at least the second electrode 222 of the capacitor 22. The orthographic projections of the second electrode 222 and the first electrode 221 of the capacitor 22 onto the substrate 100 may at least partially overlap, for example, they may coincide. The first source-drain metal layer may include at least the source 211 and the drain 212 of the thin-film transistor 21. The interlayer insulating layer 203 may have multiple vias (e.g., including a first pixel via and a second pixel via) in the display area. The interlayer insulating layer 203, the second gate insulating layer 202, and the first gate insulating layer 201 within the first pixel via can be removed, exposing at least a portion of the surface of the first region 2101 of the active layer 210. The interlayer insulating layer 203, the second gate insulating layer 202, and the first gate insulating layer 201 within the second pixel via can be removed, exposing at least a portion of the surface of the second region 2102 of the active layer 210. The source 211 of the thin-film transistor 21 can be electrically connected to the first region 2101 of the active layer 210 through the first pixel via, and the drain 212 can be electrically connected to the second region 2102 of the active layer 210 through the second pixel via. The second source-drain metal layer may include at least a first transition electrode 231. The first transition electrode 231 can be electrically connected to the drain 212 of the thin-film transistor 21 of the pixel circuit through a third pixel via formed by the passivation layer 204 and the first planarization layer 205. The third source-drain metal layer may include at least a second transition electrode 232. The second transition electrode 232 can be electrically connected to the first transition electrode 231 located in the second source-drain metal layer through a fourth pixel via formed by the second planarization layer 206. The second transition electrode 231 can be electrically connected to the first electrode 301 (e.g., anode) of the light-emitting element through a fifth pixel via formed by the third planarization layer 207. In this example, the electrical connection between the pixel circuit and the light-emitting element can be achieved through the first transition electrode 231 and the second transition electrode 232.

[0070] In some examples, the gate lines of the display area may be located, for example, in the first gate metal layer or the second gate metal layer; the data lines of the display area may be located, for example, in the second source-drain metal layer or the third source-drain metal layer; and the high-potential power lines of the display area may be located, for example, in at least one of the second and third source-drain metal layers. This embodiment is not limited in this respect. The circuit structure layer of this example may include three source-drain metal layers, which can avoid arranging too many traces in a single source-drain metal layer, thereby facilitating the realization of a narrow bezel structure.

[0071] In some examples, as shown in Figure 4, the light-emitting structure layer 30 may include a pixel definition layer 304 and multiple light-emitting elements. For example, each light-emitting element may include a stacked first electrode 301, an organic light-emitting layer 302, and a second electrode 303. The first electrode 301 of the light-emitting element can be an anode, and the first electrode 301 can be disposed on a third planarization layer 207 and electrically connected to a second transition electrode 232 through a fifth pixel via formed in the third planarization layer 207. The pixel definition layer 304 is disposed on the first electrode 301 and the third planarization layer 207, and the pixel definition layer 304 may have multiple pixel openings, one pixel opening exposing at least a portion of the surface of a corresponding first electrode 301. At least a portion of the organic light-emitting layer 302 can be disposed within a pixel opening and connected to the corresponding first electrode 301. The second electrode 303 can be disposed on the organic light-emitting layer 302 and connected to the organic light-emitting layer 302. The organic light-emitting layer 302 can emit light of a corresponding color under the drive of the first electrode 301 and the second electrode 303. An isolation pillar layer may also be provided on the side of the pixel definition layer 304 away from the substrate 100, and the isolation pillar layer may include multiple isolation pillars (PS).

[0072] In some examples, the organic light-emitting layer 302 of the light-emitting element may include an emitting layer (EML) and one or more films selected from the following: a hole injection layer (HIL), a hole transport layer (HTL), a hole block layer (HBL), an electron block layer (EBL), an electron injection layer (EIL), and an electron transport layer (ETL). Under the voltage drive of the first electrode 301 and the second electrode 303, the light-emitting properties of the organic material can be utilized to emit light at the required grayscale.

[0073] In some examples, the light-emitting layers of different colored light-emitting elements can be different. For example, a red light-emitting element includes a red light-emitting layer, a green light-emitting element includes a green light-emitting layer, and a blue light-emitting element includes a blue light-emitting layer. To reduce process complexity and improve yield, the hole injection layer and hole transport layer on one side of the light-emitting layer can be common layers, as can the electron injection layer and electron transport layer on the other side. In some examples, any one or more of the hole injection layer, hole transport layer, electron injection layer, and electron transport layer can be fabricated in a single process (single vapor deposition process or single inkjet printing process), and isolation can be achieved through surface steps of the formed film layers or through surface treatment. For example, any one or more of the hole injection layer, hole transport layer, electron injection layer, and electron transport layer corresponding to adjacent sub-pixels can be isolated. In some examples, the organic light-emitting layer can be formed by vapor deposition using a fine metal mask (FMM) or an open mask, or by inkjet printing.

[0074] In some examples, as shown in Figure 4, the encapsulation structure layer 40 may include a first encapsulation layer 401, a second encapsulation layer 402, and a third encapsulation layer 403 stacked in a direction perpendicular to the substrate. The first encapsulation layer 401 and the third encapsulation layer 403 may be made of inorganic materials such as silicon nitride, silicon oxide, or silicon oxynitride. Inorganic materials have high density and can prevent the intrusion of water, oxygen, etc. The second encapsulation layer 402 may be made of organic materials and may be disposed between the first encapsulation layer 401 and the third encapsulation layer 403 to ensure that external moisture cannot enter the light-emitting element. The second encapsulation layer 402 may be made of organic materials, for example, it may be a polymer material containing a desiccant or a polymer material that can block moisture, or it may be a polymer resin to planarize the surface of the display panel and relieve stress on the first encapsulation layer 401 and the third encapsulation layer 403. It may also include a desiccant or other water-absorbing material to absorb water, oxygen, and other substances that have intruded into the interior. However, this embodiment is not limited in this respect. For example, the encapsulation structure layer can adopt a five-layer stacked structure of inorganic / organic / inorganic / organic / inorganic.

[0075] In some examples, the touch structure layer of the display area may include: a plurality of first touch electrodes, a plurality of first connecting portions, a plurality of second touch electrodes, and a plurality of second connecting portions. The plurality of first touch electrodes may be arranged in the same layer, and adjacent first touch electrodes may be connected through the first connecting portions. The plurality of second touch electrodes may be arranged in the same layer, and adjacent second touch electrodes may be connected through the second connecting portions.

[0076] In some examples, as shown in FIG4, the touch structure layer 50 of the display area may include, in the direction perpendicular to the substrate, a touch buffer layer (TBL) 501, a first touch conductive layer 511, a touch interlayer insulating layer (TLD) 502, and a second touch conductive layer 512 disposed sequentially. The touch buffer layer 501 and the touch interlayer insulating layer 502 may be inorganic insulating layers, such as SiNx layers. For example, the first touch conductive layer 511 may include multiple first touch electrodes, multiple second touch electrodes, and multiple first connecting portions. The first touch electrodes and the first connecting portions may be an integral structure interconnected. The second touch conductive layer 512 may include multiple second connecting portions. The second connecting portions may be interconnected with adjacent second touch electrodes through vias formed in the touch interlayer insulating layer. However, this embodiment is not limited in this respect. In other examples, the first touch conductive layer may include: a plurality of first touch electrodes, a plurality of second touch electrodes, and a plurality of second connecting portions, wherein the second touch electrodes and the second connecting portions may be an integral structure interconnected with each other; the second touch conductive layer may include a plurality of first connecting portions, which may be interconnected with adjacent first touch electrodes through vias formed in the interlayer insulating layer. In some examples, the first touch electrodes may be driving (Tx) electrodes, and the second touch electrodes may be sensing (Rx) electrodes. Alternatively, the first touch electrodes may be sensing (Rx) electrodes, and the second touch electrodes may be driving (Tx) electrodes. This embodiment is not limited in this respect.

[0077] In some examples, the first and second touch electrodes may be rhomboid in shape, such as a regular rhombus, a horizontally elongated rhombus, or a vertically elongated rhombus. In other examples, the first and second touch electrodes may be any one or more of triangles, squares, trapezoids, parallelograms, pentagons, hexagons, and other polygons, which are not limited to the embodiments disclosed herein.

[0078] In some examples, the first and second touch electrodes can be in the form of transparent conductive electrodes. In other examples, the first and second touch electrodes can be in the form of a metal mesh, which can be formed by multiple interwoven metal wires. The metal mesh can include multiple mesh patterns, and the mesh pattern can be a polygon composed of multiple metal wires. The metal mesh-type first and second touch electrodes have advantages such as low resistance, small thickness, and fast response speed.

[0079] In some examples, as shown in FIG4, in a direction perpendicular to the substrate, the color filter on encapsulation (COE) 60 may include an insulating layer 601, a color filter layer, and an overcoat 602 disposed sequentially. The color filter layer includes a black matrix 610 and color filter units 611 disposed between the black matrix 610. The color filter units 611 may be, for example, red filter units, green filter units, or blue filter units.

[0080] In some examples, as shown in Figure 1A, the first bezel area B1 of the display panel may include a fan-out trace area B11 and a signal access area B12 arranged sequentially along a direction away from the display area AA. Figure 1A only illustrates a few traces within the first bezel area for illustrative purposes. This example does not limit the number of traces in the first bezel area.

[0081] In some examples, as shown in Figure 1A, the fan-out routing area B11 can be connected between the display area AA and the signal access area B12. The fan-out routing area B11 can have at least multiple data fan-out lines 42. These multiple data fan-out lines 42 can be electrically connected to multiple data lines DL within the display area AA; for example, the multiple data fan-out lines 42 and multiple data lines DL can be electrically connected in a one-to-one correspondence. The multiple data fan-out lines 42 can extend into the signal access area B12 using a fan-out routing method. The multiple data fan-out lines 42 and the multiple data lines DL can be located in different film layers, and the data fan-out lines 42 can be connected to the data lines DL through vias formed in the insulating layer.

[0082] In some examples, as shown in Figure 1A, the signal access area B12 may include at least one first signal access area B121. This example illustrates and explains using one first signal access area as an example. In other examples, the display panel is a large-size panel, and the display panel may include multiple first signal access areas, which may be arranged sequentially along a first direction X.

[0083] In some examples, as shown in Figure 1A, the first signal access area B121 can also be referred to as a driver chip (IC) setting area. The first signal access area B121 may be provided with multiple pads 31, which can be configured to be bonded to at least one driver chip. The driver chip can be configured to generate drive signals required to drive sub-pixels and provide the drive signals to the data lines DL of the display area AA. For example, the drive signals can be data signals for driving sub-pixels. In some examples, the driver chip can be a central processing unit, a digital signal processor, a system-on-a-chip (SoC), etc. For example, the driver chip can also include hardware circuitry and computer-executable code. The hardware circuitry can include conventional very-large-scale integrated circuits (VLSI) or gate arrays, as well as existing semiconductors or other discrete components such as logic chips, transistors, etc.; the hardware circuitry can also include field-programmable gate arrays, programmable array logic, programmable logic devices, etc.

[0084] In some examples, as shown in Figure 1A, the signal access area B12 may be provided with at least a plurality of data line leads 101. These data line leads 101 can be electrically connected to a plurality of data fan-out lines 42 in the fan-out routing area B11, for example, in a one-to-one correspondence. For example, the data line leads 101 and the connected data fan-out lines 42 can be an integrated structure interconnected. That is, the plurality of data line leads 101 are electrically connected to a plurality of data lines DL via the plurality of data fan-out lines 42, for example, in a one-to-one correspondence. The plurality of data line leads 101 can extend into the first signal access area B121 and be electrically connected to a plurality of pads 31 within the first signal access area B121. For example, the plurality of data line leads 101 and the plurality of pads 31 can be electrically connected in a one-to-one correspondence, or one data line lead 101 can be electrically connected to at least one pad 31. The data line leads 101 and the data fan-out lines 42 can transmit the data signals provided by the driver chip to the data lines DL of the display area.

[0085] In some examples, as shown in Figure 1B, the first border region B1 of the display substrate may include: a fan-out trace region B11, a bending region B13, and a signal access region B12 arranged sequentially along a direction away from the display region AA. Figure 1B only illustrates a few traces within the first border region for illustrative purposes. This example does not limit the number of traces in the first border region.

[0086] In some examples, as shown in Figure 1B, the bending region B13 can connect the fan-out trace region B11 and the signal access region B12, and can be configured to bend the signal access region B12 to the back of the display region AA. The bending region B13 can have at least multiple data bending connection lines 43. One end of the data bending connection line 43 can be connected to the data fan-out line 42 in the fan-out trace region B11, and the other end can be connected to the data line lead 101 in the signal access region B12. The multiple data bending connection lines 43 can be in the same layer, for example, located in the first source-drain metal layer or the second source-drain metal layer. The remaining structure of the first border region B1 in this example can be referred to the description of the foregoing embodiments, and will not be repeated here.

[0087] As shown in Figures 1A and 1B, the signal access area B12 may further include a second signal access area B122. The second signal access area B122 is provided with a plurality of contact pads 32 for bonding with the flexible circuit board. The pads referred to below in this disclosure refer to the pads 31 of the first signal access area B121, which are used for bonding with at least one driver chip.

[0088] Figure 2 is a partial enlarged view of the first signal access area according to an embodiment of the present disclosure. In some examples, as shown in Figure 2, the plurality of pads 31 of the first signal access area B121 can be arranged in multiple rows (e.g., four rows). The plurality of pads 31 in each row can be arranged sequentially along a first direction X, and the multiple rows of pads 31 can be arranged sequentially along a second direction Y. The pads 31 in adjacent rows can be staggered in the first direction X. However, this embodiment is not limited to this. In other examples, the plurality of pads of the first signal access area B121 can be arranged in a single row.

[0089] In some examples, the multiple pads 31 in the first signal access area can be divided into at least two groups. Figure 2 illustrates and explains two groups of pads (e.g., the first group of pads 31A and the second group of pads 31B). The second group of pads 31B can be located on the side of the first group of pads 31A away from the display area. The first group of pads 31A can include three rows of multiple pads 311 arranged along the first direction X. The second group of pads 31B can include one row of multiple pads 312 arranged along the first direction X. In some examples, the second group of pads 31B is used for input signals, which are converted by the bonded IC and output to the first group of pads 31A. The first group of pads 31A then transmits the signals (e.g., data signals) to multiple sub-pixels PX through multiple signal lines (e.g., multiple data lines DL). The first group of pads 31A and the second group of pads 31B can be staggered in the first direction X. For example, the pads in the first group of pads 31A and the second group of pads 31B may not be aligned in the second direction Y. There are gaps between adjacent pads within the same group, and gaps between pads in adjacent groups. In some embodiments, a group of pads may be one row, two rows, or three rows of pads. This disclosure does not limit the number of rows of pads or the number of pads in each row.

[0090] Figure 3 is a detailed enlarged view of region S in Figure 2. In some examples, as shown in Figure 3, multiple data line leads 101 can extend generally along the second direction Y between multiple pads 31. For example, two data line leads 101 can be provided between two adjacent pads 31 in a set of pads. A data line lead 101 can be electrically connected to at least one pad 31, for example, a data line lead 101 can be connected to one pad 31. The cross-sectional schematic diagram of the pads referred to below in this disclosure can be taken along line AA in Figure 3.

[0091] As the number of signal lines in display panels increases, achieving a narrow bezel effect typically requires layering the signal lines. For example, three source-drain metal layers can be fabricated, allowing signal lines to be routed separately within each layer, reducing the load on a single layer and effectively minimizing the bezel size. In the bezel area of ​​the display substrate, some pads used for connection to the driver chip (driver IC) are fabricated simultaneously using the three source-drain metal layers. However, stacking these three layers can cause excessively large pad step differences.

[0092] Figures 5(a)-5(e) show cross-sectional schematic diagrams of the pad fabrication process according to an embodiment of the present disclosure. The steps for fabricating the pads are as follows: A metal thin film, such as a gate metal thin film, is prepared on one side of a substrate 100. A data line lead 101 as shown in Figure 5(a) is formed by a patterning process. Then, a first insulating layer 102 is prepared. The first insulating layer 102 may be an insulating layer composed of a gate insulating layer and an interlayer insulating layer. A first opening 110 exposing at least a portion of the data line lead is etched on the first insulating layer 102. Next, a first source-drain metal thin film is formed on the side of the data line lead 101 and the first insulating layer 102 facing away from the substrate 100. The first source-drain metal thin film is patterned by a patterning process to form a first metal layer 1031 as shown in Figure 5(b). Next, a second insulating layer 104 as shown in Figure 5(c) is formed on the sidewall of the first metal layer 1031 to prevent the exposure of metal elements (e.g., Al) in the first metal layer, which could cause corrosion or dark spots. Next, a second source / drain metal film is formed. This second source / drain metal film is patterned using a patterning process to form a second metal layer 1032 as shown in Figure 5(d). Next, a third source / drain metal film is formed. This third source / drain metal film is patterned using a patterning process to form a third metal layer 1033 as shown in Figure 5(e). Around the edge of the first opening, a bump structure is formed, consisting of the first metal layer 1031, the second metal layer 1032, and the third metal layer 1033 stacked together. For the patterning process of the second source / drain metal layer, the photoresist thickness is typically 1.2 μm. Due to the fluidity of the photoresist, the photoresist thickness at the bump structure will be less than 1.2 μm. During the patterning etching of the second source / drain metal layer, the photoresist at the bump structure location will be completely consumed, and the exposed second metal layer will continue to be etched. This will cause damage to the bump structure, and the damage can extend along the entire surface of the bump location within the second metal layer, potentially leading to reliability anomalies. Similarly, for the patterning process of the third source / drain metal layer, the photoresist thickness is typically 1.5 μm. Due to the fluidity of the photoresist, the thickness at the protrusion structure will be less than 1.5 μm. During the patterning and etching of the third source / drain metal layer, the photoresist at the protrusion structure location will be completely consumed, and the exposed third metal layer will continue to be etched. This will cause damage to the protrusion structure, potentially leading to reliability anomalies.

[0093] To reduce the damage caused by the protruding structure, the inventors of this application employed a thickened photoresist layer in the patterning process of the second and third source / drain metal layers. For example, the photoresist thickness was increased from 1.2 μm to 1.5 μm in the patterning process of the second source / drain metal layer, and from 1.5 μm to 1.8 μm in the patterning process of the third source / drain metal layer. However, with the thickened photoresist, chloride ions from the etching gas remain within the photoresist, causing corrosion of the third metal layer. Besides causing corrosion of the third metal layer, the thickened photoresist also introduces the following problems: significantly increased AOI (Automatic Optic Inspection) equipment testing time; increased coating costs; and reduced exposure capacity.

[0094] In view of this, the inventors of this application propose a method that utilizes the high selectivity of etching the source and drain metal layers for the passivation layer. By changing the film structure design at the protrusion location and reducing the film stacking height, the problem of metal layer damage at the protrusion location can be solved without increasing the photoresist thickness. This pad structure can avoid the damage to the metal layer caused by the incomplete removal of residual chloride ions due to the use of thicker photoresist, while also improving exposure capacity and reducing coating costs.

[0095] Figures 6(a)-6(e) show cross-sectional schematic diagrams of the pad fabrication process and pad structure of a display substrate according to embodiments of the present disclosure. As shown in Figure 6(c), at least one of the plurality of pads in the display substrate provided in this application embodiment includes: a first insulating layer 102 located on the side of the plurality of data line leads 101 facing away from the substrate 100, the first insulating layer 102 including a first opening 110 exposing at least a portion of at least one of the plurality of data line leads 101; a first metal layer 1031 located on the side of the plurality of data line leads 101 facing away from the substrate, and electrically connected to at least one of the plurality of data line leads 101 through the first opening 110, wherein the first metal layer 1031 includes a first bottom 1031a and a stepped portion surrounding the first bottom, the orthographic projection of the first bottom 1031a on the substrate 100 lies within the orthographic projection of the first opening 110 on the substrate 100, the first bottom 1031a is electrically connected to at least one of the plurality of data line leads 101, and the stepped portion includes A first step portion 1031b and a second step portion 1031c forming an angle with the first step portion 1031b are located on the side of the first insulating layer 102 away from the substrate 100. The second step portion 1031c connects the first bottom 1031a and the first step portion 1031b, and the orthographic projection of the second step portion 1031c on the substrate 100 is located in the orthographic projection of the first opening 110 on the substrate 100. A second insulating layer 104 is located on the side of the first metal layer 1031 and the first insulating layer 102 away from the substrate 100. The second insulating layer 104 includes a second opening 120 that exposes at least a portion of the first bottom 1031a of the first metal layer 1031. The orthographic projection of the second insulating layer 104 on the substrate 100 covers the orthographic projections of the first step portion 1031b and the second step portion 1031c of the first metal layer 1031 on the substrate 100.

[0096] In an exemplary embodiment, as shown in FIG6(c), the orthographic projection of the second insulating layer 104 on the substrate 100 may overlap with the orthographic projection of the first bottom 1301a on the substrate 100, and the orthographic projection of the second opening 120 on the substrate 100 is located in the orthographic projection of the first opening 110 on the substrate 100.

[0097] It should be noted that the sidewall of the first insulating layer facing the first opening has a certain slope, and the second step covers the sidewall of the first insulating layer facing the first opening.

[0098] In this disclosure, "the orthographic projection of A covers the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B. "The orthographic projection of A lies within the orthographic projection of B" means that the boundary of the orthographic projection of A falls within the boundary range of the orthographic projection of B.

[0099] In an exemplary embodiment, as shown in FIG6(d), at least one of the plurality of pads of the display substrate further includes: a second metal layer 1032 located on the side of the first metal layer 1031 and the second insulating layer 104 away from the substrate 100, wherein the second metal layer 1032 is electrically connected to the first metal layer 1031 through the second opening 120, the orthographic projection of the second metal layer 1032 on the substrate 100 does not overlap with the orthographic projection of the first step portion 1031b of the first metal layer 1031 on the substrate 100, and the orthographic projection of the second metal layer 1032 on the substrate 100 covers the orthographic projection of the second opening 120 on the substrate 100, that is, the second metal layer 1032 is recessed into the first opening 110.

[0100] In an exemplary embodiment, as shown in Figures 6(e), 7(e), 8(e), 9(f), 11, 12, and 13, at least one of the plurality of pads of the display substrate further includes: a third metal layer 1033 located on the side of the second metal layer 1032 away from the substrate 100, wherein the third metal layer 1033 is electrically connected to the second metal layer 1032, and the orthographic projection of the third metal layer 1033 on the substrate 100 covers the orthographic projection of the second metal layer 1032 on the substrate.

[0101] In the display substrate provided in this disclosure, the orthogonal projection of the second insulating layer 104 onto the substrate 100 covers the orthogonal projections of the first step portion 1031b and the second step portion 1031c of the first metal layer 1031 onto the substrate 100. Since the etching selectivity of the second insulating layer 104 for the second metal layer 1032 is high—that is, when etching the second metal layer 1032, the second insulating layer 104, retracted into the first opening 110, can protect the first metal layer 1031 from being affected—the second metal layer 1032 can be retracted into the first opening 110, thereby reducing the film layer stacking height of the pad protrusion structure. This solves the problem of metal layer damage at the protrusion location without increasing the photoresist thickness. This pad structure avoids metal layer damage caused by using thicker photoresist, while simultaneously increasing exposure capacity and reducing coating costs.

[0102] In an exemplary embodiment, as shown in FIG6(e), the orthographic projection of the third metal layer 1033 on the substrate 100 overlaps the orthographic projection of the first metal layer 1031 on the substrate 100. In this embodiment, the second metal layer 1032 is recessed into the first opening, and the third metal layer 1033 covers the first metal layer 1031, effectively reducing the film layer stacking height of the pad protrusion structure.

[0103] In an exemplary embodiment, as shown in FIG7(e), the orthographic projection of the third metal layer 1033 on the substrate 100 does not overlap with the orthographic projection of the first step portion 1031b of the first metal layer 1031 on the substrate 100, and the orthographic projection of the third metal layer 1033 on the substrate 100 is located within the orthographic projection of the first opening on the substrate. In this embodiment, both the second metal layer 1032 and the third metal layer 1033 are recessed into the first opening, effectively reducing the film layer stacking height of the pad protrusion structure.

[0104] In an exemplary embodiment, as shown in FIG11, the orthographic projection of the third metal layer 1033 on the substrate 100 lies within the orthographic projection of the first metal layer 1031 on the substrate 100, and overlaps with the orthographic projection portion of the first step portion 1031b on the substrate 100. In this embodiment, the second metal layer 1032 is recessed into the first opening, and the third metal layer 1033 covers a portion of the first metal layer 1031, which also effectively reduces the film layer stacking height of the pad protrusion structure.

[0105] In some embodiments of this disclosure, the second insulating layer can be a single-layer insulating layer, which can be an inorganic material insulating layer or an organic material insulating layer. In the pads shown in Figures 6(e) and 7(e), the second insulating layer 104 is an inorganic material, and in the pads shown in Figure 8(e), the second insulating layer 104 is an organic material. For organic material insulating layers, due to their certain fluidity during preparation, they can better fill the height differences at different positions of the film layer, and overall more effectively reduce the problem of excessive step differences caused by film layer stacking in the pads.

[0106] In an exemplary embodiment, as shown in FIG8(e), the second insulating layer 104 is an organic material insulating layer, and the orthographic projection of the third metal layer 1033 on the substrate 100 covers the orthographic projection of the first metal layer 1031 on the substrate 100, and the orthographic projection of the third metal layer 1033 on the substrate 100 covers the orthographic projection of the second insulating layer 104 on the substrate 100. However, this is not mandatory; in some embodiments, the orthographic projection of the third metal layer on the substrate may not cover the orthographic projection of the second insulating layer on the substrate.

[0107] In some embodiments of this disclosure, the second insulating layer may include a first insulator layer and a second insulator layer, wherein the second insulator layer is located on the side of the first insulator layer opposite to the substrate.

[0108] In an exemplary embodiment, as shown in FIG9(f), the material of the first insulator layer 1041 is an inorganic material, and the material of the second insulator layer 1042 is an organic material. In the pad shown in FIG9(f), the orthographic projections of the first insulator layer 1041 and the second insulator layer 1042 on the substrate 100 both cover the orthographic projections of the first step portion 1031b and the second step portion 1031c of the first metal layer 1031 on the substrate 100. Optionally, in the pad shown in FIG12, the orthographic projection of the first insulator layer 1041 on the substrate 100 covers the orthographic projections of the first step portion 1031b and the second step portion 1031c of the first metal layer 1031 on the substrate 100, and the orthographic projection of the second insulator layer 1042 on the substrate 100 does not overlap with the orthographic projection of the first opening on the substrate 100.

[0109] In an exemplary embodiment, as shown in FIG13, the material of the first insulator layer 1041 is an organic material, and the material of the second insulator layer 1042 is an inorganic material. The orthographic projections of the first insulator layer 1041 and the second insulator layer 1042 on the substrate 100 both cover the orthographic projections of the first step portion 1031b and the second step portion 1031c of the first metal layer 1031 on the substrate 100.

[0110] In some embodiments of this disclosure, as shown in FIG14, the pads of the display substrate further include: a third insulating layer 106 located on the side of the third metal layer 1033 away from the substrate 100, wherein the third insulating layer 106 includes a third opening 130; and a fourth metal layer 107 located on the side of the third metal layer 1033 and the third insulating layer 106 away from the substrate 100, wherein the fourth metal layer 107 is electrically connected to the third metal layer 1033 through the third opening 130.

[0111] In an exemplary embodiment, as shown in FIG14, the orthographic projection of the first opening on the substrate 100 is located within the orthographic projection of the third opening 130 on the substrate 100, and the orthographic projection of the fourth metal layer 107 on the substrate 100 covers the orthographic projection of the third metal layer 1033 on the substrate 100.

[0112] In this disclosure, at least one sub-pixel in a plurality of sub-pixels located in the display area includes a thin-film transistor. FIG4 is a schematic cross-sectional view of the display area of ​​the display substrate shown in FIG1A along line aa'. FIG4 illustrates an example of each sub-pixel including at least one thin-film transistor 21 and a capacitor 22. As described above with reference to FIG4, the gate 213 of the thin-film transistor 21 and the first electrode 221 of the capacitor 22 are located in a first gate metal layer. A second gate insulating layer 202 is disposed on the side of the first gate metal layer away from the substrate, and a second gate metal layer is disposed on the side of the second gate insulating layer 202 away from the substrate. The second electrode 222 of the capacitor 22 is located in the second gate metal layer. A first source-drain metal layer, a second source-drain metal layer, and a third source-drain metal layer are sequentially arranged on the side of the second gate metal layer away from the substrate. The source 211 and drain 212 of the thin-film transistor 21 are located in the first source-drain metal layer, the first transition electrode 231 is located in the second source-drain metal layer, and the second transition electrode 232 is located in the third source-drain metal layer. An interlayer insulating layer 203 may be disposed between the second gate metal layer and the first source-drain metal layer. The pads in the first bezel region can be fabricated simultaneously during the fabrication process of the display area components. For example, the statement in this disclosure that "the plurality of data line leads are disposed on the same layer as the gate metal layer" may include: the plurality of data line leads 101 in the first bezel region may be disposed on the same layer as the first gate metal layer; or the plurality of data line leads 101 are located on the first gate metal layer and the second gate metal layer, and are alternately wired. The statement in this disclosure that "the first insulating layer is disposed on the same layer as the gate insulating layer" may include: the first insulating layer is disposed on the same layer as the second gate insulating layer and / or the interlayer insulating layer, that is, the "gate insulating layer" here may include the second gate insulating layer 202 and the interlayer insulating layer 203. The first metal layer may be disposed on the same layer as the first source-drain metal layer, the second metal layer may be disposed on the same layer as the second source-drain metal layer, and the third metal layer may be disposed on the same layer as the third source-drain metal layer.

[0113] The phrase "A and B in the same layer" as used in this disclosure refers to a layer structure formed by using the same film deposition process to form a film layer for a specific pattern, and then using the same photomask through a single patterning process. Depending on the specific pattern, the single patterning process may include multiple exposure, development, or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous, and these specific patterns may also be at different heights or have different thicknesses.

[0114] In embodiments of this disclosure, the thickness of the first metal layer can be For example The thickness of the second metal layer can be... For example The thickness of the third metal layer can be... For example Etc. Optionally, the thicknesses of the second metal layer and the third metal layer can be respectively...

[0115] In this disclosure, the gate insulating layer can be a single-layer thin film or a double-layer thin film as shown in this disclosure (e.g., the first insulating layer 102 in FIG. 6(a)). Those skilled in the art will understand that the double-layer thin film here is typically a gate insulating layer (GI) and an interlayer insulating layer (ILD). A passivation layer is also disposed between the first source-drain metal layer and the second source-drain metal layer of the thin film transistor to protect the sidewalls of the first source-drain metal layer. In some embodiments, when the second insulating layer is an inorganic material, the second insulating layer can be disposed in the same layer as the passivation layer. The thin film transistor can also be provided with a planarization layer as needed. In related technologies, the planarization layer is usually made of an organic material. When the second insulating layer is an organic material, the second insulating layer can be disposed in the same layer as the planarization layer. For touch display substrates, a first touch conductive layer and a second touch conductive layer for touch function are usually provided, as well as a touch interlayer insulating layer (TLD) located between the two. The first touch conductive layer and the second touch conductive layer are electrically connected through vias on the touch interlayer insulating layer. The third insulating layer in this disclosure can be disposed in the same layer as the inter-touch insulating layer, and the fourth metal layer can be disposed in the same layer as one of the first touch conductive layer and the second touch conductive layer. In addition, those skilled in the art will understand that, between the substrate and the multiple data line leads (i.e., the gate metal layer), a barrier layer, a buffer layer, a gate insulating layer, etc., can also be arranged, as indicated by film layer 105 in FIG6(a).

[0116] In this disclosure, the substrate can be a flexible substrate, specifically, it can be PEN resin, silicone resin, polyimide, etc. The first insulating layer, the second insulating layer disposed on the same layer as the passivation layer, and the third insulating layer can be any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and can be a single layer, multiple layers, or composite layers. The second insulating layer disposed on the same layer as the planarization layer can be an organic material, such as PEN resin, silicone resin, polyimide, etc. The first metal layer, the second metal layer, the third metal layer, and the fourth metal layer can be metallic materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or alloy materials of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), and can be a single-layer structure or a multi-layer composite structure, such as Ti / Al / Ti, Mo / Cu / Mo, etc.

[0117] On the other hand, this disclosure provides a display device, including the display substrate of the foregoing embodiments. The display device can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator.

[0118] On the other hand, this disclosure provides a method for manufacturing the above-mentioned display substrate. Figures 6(a)-6(e) show cross-sectional schematic diagrams of the pad fabrication process and pad structure of a display substrate according to one embodiment of this disclosure; Figures 7(a)-7(e) show cross-sectional schematic diagrams of the pad fabrication process and pad structure of a display substrate according to another embodiment of this disclosure; Figures 8(a)-8(e) show cross-sectional schematic diagrams of the pad fabrication process and pad structure of a display substrate according to another embodiment of this disclosure; Figures 9(a)-9(f) show cross-sectional schematic diagrams of the pad fabrication process and pad structure of a display substrate according to another embodiment of this disclosure.Specifically, the method includes: providing a substrate 100, the substrate including a display area and a first border area located on at least one side of the display area; fabricating a plurality of sub-pixels, a plurality of data lines, and a plurality of data line leads on one side of the substrate, the plurality of sub-pixels and the plurality of data lines being located in the display area and electrically connected, the plurality of data line leads being located in the first border area and electrically connected to the plurality of data lines; fabricating a plurality of pads in the first border area, the step of fabricating at least one of the plurality of pads including: forming a first insulating layer 102 on the side of the plurality of data line leads 101 facing away from the substrate 100, the first insulating layer 102 including a first opening 110 exposing at least a portion of at least one of the plurality of data line leads 101, forming as shown in Figures 6(a) and 7(a). The structures shown in Figures 8(a) and 9(a) are as follows: A first metal layer 1031 is formed on the side of the plurality of data line leads 101 away from the substrate 100. The first metal layer 1031 is electrically connected to at least one of the plurality of data line leads 101 through the first opening 110. The first metal layer includes a first bottom 1031a and a stepped portion surrounding the first bottom. The orthographic projection of the first bottom 1031a on the substrate 100 is located within the orthographic projection of the first opening 110 on the substrate 100. The first bottom 1031a is electrically connected to at least one of the plurality of data line leads 101. The stepped portion includes a first stepped portion 1031b located on the side of the first insulating layer 102 away from the substrate 100 and a second stepped portion 1031c forming an angle with the first stepped portion 1031b. The second stepped portion 1031c is connected to the first bottom. The first metal layer 1031a and the first step portion 1031b, and the second step portion 1031c are located in the orthogonal projection of the first opening 110 onto the substrate 100, forming the structure shown in FIG6(b), FIG7(b), FIG8(b), and FIG9(b); and a second insulating layer 104 is formed on the side of the first metal layer 1031 and the first insulating layer 102 away from the substrate 100, wherein the second insulating layer 104 includes a second opening 120 that exposes at least a portion of the first bottom 1031a of the first metal layer 1031, and the orthogonal projection of the second insulating layer 104 onto the substrate 100 covers the orthogonal projections of the first step portion 1031b and the second step portion 1031c onto the substrate 100, forming the structure shown in FIG6(c), FIG7(c), FIG8(c), FIG9(c), and FIG9(d).

[0119] In some embodiments, the method further includes: forming a second metal layer 1032 on the side of the first metal layer 1031 and the second insulating layer 104 away from the substrate 100, wherein the second metal layer 1032 is electrically connected to the first metal layer 1031 through the second opening 120, the orthographic projection of the second metal layer 1032 on the substrate 100 does not overlap with the orthographic projection of the first step portion 1031a of the first metal layer 1031 on the substrate 100, and the orthographic projection of the second metal layer 1032 on the substrate 100 covers the orthographic projection of the second opening 120 on the substrate 100, forming the structure shown in FIG6(d), FIG7(d), FIG8(d), and FIG9(e).

[0120] In some embodiments, the method further includes: forming a third metal layer 1033 on the side of the second metal layer 1032 facing away from the substrate 100, wherein the third metal layer 1033 is electrically connected to the second metal layer 1032, and the orthographic projection of the third metal layer 1033 on the substrate 100 covers the orthographic projection of the second metal layer 1032 on the substrate 100, forming the structure shown in FIG6(e), FIG7(e), FIG8(e), and FIG9(f).

[0121] In some embodiments, forming a second insulating layer 104 on the side of the first metal layer 1031 and the first insulating layer 102 away from the substrate 100 includes: forming the second insulating layer 104 on the side of the first metal layer 1031 and the first insulating layer 102 away from the substrate 100 using an inorganic material, forming the structure shown in FIG6(c) and FIG7(c).

[0122] In some embodiments, forming a second insulating layer 104 on the side of the first metal layer 1031 and the first insulating layer 102 away from the substrate 100 includes: forming the second insulating layer 104 on the side of the first metal layer 1031 and the first insulating layer 102 away from the substrate 100 using an organic material, forming the structure shown in FIG8(c).

[0123] In some embodiments, forming a second insulating layer 104 on the side of the first metal layer 1031 and the first insulating layer 102 away from the substrate 100 includes: forming a first insulator layer 1041 on the side of the first metal layer 1031 and the first insulating layer 102 away from the substrate 100 using an inorganic material, and forming a second insulator layer 1042 on the side of the first insulator layer 1041 away from the substrate 100 using an organic material, thus forming the structure shown in FIG9(d).

[0124] In some embodiments, forming a second insulating layer 104 on the side of the first metal layer 1031 and the first insulating layer 102 away from the substrate 100 includes: forming a first insulator layer 1041 on the side of the first metal layer 1031 and the first insulating layer 102 away from the substrate 100 using an organic material, and forming a second insulator layer 1042 on the side of the first insulator layer 1041 away from the substrate 100 using an inorganic material, forming the structure shown in FIG13.

[0125] On the other hand, this disclosure also provides another method for fabricating the above-mentioned display substrate. Figures 10(a)-10(f) show cross-sectional schematic diagrams of the pad fabrication process of a display substrate according to an embodiment of this disclosure. Specifically, the method includes: providing a substrate 100, the substrate including a display area and a first border area located on at least one side of the display area; fabricating a plurality of sub-pixels, a plurality of data lines and a plurality of data line leads on one side of the substrate, the plurality of sub-pixels and the plurality of data lines being located in the display area and electrically connected, the plurality of data line leads being located in the first border area and electrically connected to the plurality of data lines; fabricating a plurality of pads in the first border area, the step of fabricating at least one of the plurality of pads including: forming a first insulating layer 10 on the side of the plurality of data line leads 101 facing away from the substrate 100. 2. The first insulating layer 102 includes a first opening 110 that exposes at least a portion of at least one of the plurality of data line leads 101, forming the structure shown in FIG10(a); a first metal layer 1031 is formed on the side of the plurality of data line leads 101 facing away from the substrate 100, the first metal layer 1031 being electrically connected to at least one of the plurality of data line leads 101 through the first opening 110, wherein the first metal layer includes a first bottom 1031a and a stepped portion surrounding the first bottom, the orthographic projection of the first bottom 1031a on the substrate 100 being located at the first opening. Within the orthographic projection of the first opening 110 onto the substrate 100, the first bottom portion 1031a is electrically connected to at least one of the plurality of data line leads 101. The stepped portion includes a first stepped portion 1031b located on the side of the first insulating layer 102 away from the substrate 100, and a second stepped portion 1031c forming an angle with the first stepped portion 1031b. The second stepped portion 1031c connects the first bottom portion 1031a and the first stepped portion 1031b, and the orthographic projection of the second stepped portion 1031c onto the substrate 100 is located within the orthographic projection of the first opening 110 onto the substrate 100. The structure shown in FIG10(b) is formed; a second insulating layer 104 is formed on the side of the first metal layer 1031 and the first insulating layer 102 away from the substrate 100, wherein the second insulating layer 104 covers the orthogonal projection of the first metal layer 1031 on the substrate, forming the structure shown in FIG10(c); a second metal layer is formed on the side of the second insulating layer 104 away from the substrate 100; the second metal layer is removed, forming the structure shown in FIG10(d); a third metal layer is formed on the side of the second insulating layer 104 away from the substrate 100; the third metal layer is removed, forming the structure shown in FIG10(e).A second opening 120 is formed on the second insulating layer 104, the second opening 120 exposing at least a portion of the first bottom 1031a of the first metal layer 1031, and the orthographic projection of the second insulating layer 104 on the substrate 100 covers the orthographic projections of the first stepped portion 1031b and the second stepped portion 1031c of the first metal layer 1031 on the substrate 100.

[0126] In this method, the second insulating layer first completely covers the first metal layer, protecting it from the etching processes of the second and third metal layers. Finally, an opening is formed on the second insulating layer to expose at least a portion of the first metal layer. This method produces pads with only the first metal layer, avoiding film layer stacking on raised structures and significantly reducing the height difference between different pad arrangements. However, this method requires an additional mask compared to the methods described above; those skilled in the art can choose different fabrication methods based on the specific circumstances.

[0127] The method described above with reference to Figures 10(a)-10(f) is for a product whose source and drain electrodes include a first source / drain metal layer, a second source / drain metal layer, and a third source / drain metal layer. If the product has only one source / drain metal layer, the steps of "forming a second metal layer on the side of the second insulating layer 104 opposite to the substrate 100; removing the second metal layer" and "forming a third metal layer on the side of the second insulating layer 104 opposite to the substrate 100; removing the third metal layer" can be omitted. If the product has only two source / drain metal layers, the steps of "forming a third metal layer on the side of the second insulating layer 104 opposite to the substrate 100; removing the third metal layer" can be omitted.

[0128] As described above, the substrate of the display substrate disclosed herein can be a flexible substrate. During the fabrication process, multiple flexible substrates are typically prepared on a glass substrate, and the glass substrate is removed after all multiple display substrates have been fabricated. Because the display substrate provided by this disclosure does not require thickening of the photoresist, the exposure capacity of the fabrication process can be increased, the processing cycle time (tact time) can be reduced by 13 seconds per glass layer, and the photoresist coating cost can be reduced by 18% per layer.

[0129] In the accompanying drawings, the thickness of certain areas and layers may be exaggerated for clarity. The same reference numerals in the figures denote the same or similar structures, and therefore their detailed descriptions are omitted. The described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Numerous specific details are provided in the description of this disclosure to give a full understanding of embodiments of this disclosure. However, those skilled in the art will recognize that the technical solutions of this disclosure can be practiced without one or more of the specific details described, or other methods, components, materials, etc., can be employed. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring the main technical concept of this disclosure.

[0130] It will be understood that although the terms first, second, third, etc., may be used herein to describe various elements, components, areas, layers, and / or parts, these elements, components, areas, layers, and / or parts should not be limited by these terms. These terms are used only to distinguish one element, component, area, layer, or part from another. Therefore, the first element, component, area, layer, or part discussed above may be referred to as the second element, component, area, layer, or part without departing from the teachings of this disclosure.

[0131] Spatial relative terms such as “row,” “column,” “below,” “above,” “left,” “right,” etc., may be used herein for ease of description to describe the relationship between one element or feature illustrated in the figures and another element(s). It will be understood that these spatial relative terms are intended to cover different orientations of the device in use or operation other than those depicted in the figures. For example, if the device in the figure is flipped, then an element described as “below other elements or features” will be oriented “above other elements or features.” Thus, the exemplary term “below” can cover both orientations above and below. Devices may be oriented in other ways (rotated 90 degrees or otherwise) and the spatial relative descriptors used herein will be interpreted accordingly. Additionally, it will be understood that when a layer is referred to as “between two layers,” it may be the only layer between those two layers, or there may be one or more intermediate layers.

[0132] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprising” and / or “including”, when used in this specification, specify the presence of the stated features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. In the description of this specification, references to the terms “one embodiment,” “another embodiment,” etc., mean that a specific feature, structure, material, or characteristic described in connection with that embodiment is included in at least one embodiment of this disclosure. The illustrative expressions of the foregoing terms in this specification do not necessarily refer to the same embodiments or examples. Moreover, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Furthermore, those skilled in the art can combine the different embodiments or examples described herein and the features of the different embodiments or examples without contradiction.

[0133] It will be understood that when a component or layer is referred to as "on another component or layer," "connected to another component or layer," "coupled to another component or layer," or "adjacent to another component or layer," it may be directly on another component or layer, directly connected to another component or layer, directly coupled to another component or layer, or directly adjacent to another component or layer, or there may be intermediate components or layers. Conversely, when a component is referred to as "directly on another component or layer," "directly connected to another component or layer," "directly coupled to another component or layer," or "directly adjacent to another component or layer," no intermediate components or layers exist. However, in any case, "on" or "directly on" should not be interpreted as requiring a layer to completely cover the layer below.

[0134] Embodiments of this disclosure are described herein with reference to illustrative illustrations (and intermediate structures) of idealized embodiments. Therefore, variations in the illustrated shapes should be expected, for example, as a result of manufacturing techniques and / or tolerances. Consequently, embodiments of this disclosure should not be construed as limited to the specific shapes of the regions illustrated herein, but should include, for example, shape deviations due to manufacturing processes. Thus, the regions illustrated are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of a device and are not intended to limit the scope of this disclosure.

[0135] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having meanings consistent with their meanings in the relevant field and / or the context of this specification, and will not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0136] As those skilled in the art will understand, although the steps of the methods in this disclosure are described in a specific order in the accompanying drawings, this does not require or imply that the steps must be performed in that specific order unless the context clearly indicates otherwise. Additional or alternatively, multiple steps may be combined into a single step, and / or a single step may be broken down into multiple steps. Furthermore, other method steps may be inserted between steps. Inserted steps may represent improvements to the method described herein, or may be unrelated to the method. Moreover, a given step may not be fully completed before the next step begins.

[0137] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A display substrate, comprising: a substrate, comprising a display area and a first bezel area located at least one side of the display area; a plurality of sub-pixels located at one side of the substrate and in the display area; a plurality of data lines located in the display area and electrically connected with the plurality of sub-pixels; a plurality of data line leads located in the first bezel area and electrically connected with the plurality of data lines; a plurality of pads located in the first bezel area and electrically connected with the plurality of data line leads; wherein at least one pad of the plurality of pads comprises: a first insulating layer located at a side of the plurality of data line leads away from the substrate, the first insulating layer comprising a first opening exposing at least a portion of at least one data line lead of the plurality of data line leads; a first metal layer located at a side of the plurality of data line leads away from the substrate and electrically connected with at least one data line lead of the plurality of data line leads through the first opening; wherein the first metal layer comprises a first bottom and a stepped portion surrounding the first bottom, a projection of the first bottom on the substrate is located within a projection of the first opening on the substrate, the first bottom is electrically connected with at least one data line lead of the plurality of data line leads, the stepped portion comprises a first stepped portion located at a side of the first insulating layer away from the substrate and a second stepped portion at an angle with the first stepped portion, the second stepped portion connects the first bottom and the first stepped portion, and a projection of the second stepped portion on the substrate is located in a projection of the first opening on the substrate; and a second insulating layer located at a side of the first metal layer and the first insulating layer away from the substrate, wherein the second insulating layer comprises a second opening exposing at least a portion of the first bottom of the first metal layer, a projection of the second insulating layer on the substrate covers projections of the first stepped portion and the second stepped portion of the first metal layer on the substrate. 2.The display substrate of claim 1, wherein, the projection of the second insulating layer on the substrate partially overlaps with the projection of the first bottom on the substrate, and a projection of the second opening on the substrate is located in the projection of the first opening on the substrate.

3. The display substrate of claim 1 or 2, further comprising: a second metal layer located at a side of the first metal layer and the second insulating layer away from the substrate, wherein the second metal layer is electrically connected with the first metal layer through the second opening, a projection of the second metal layer on the substrate does not overlap with a projection of the first stepped portion of the first metal layer on the substrate, and a projection of the second metal layer on the substrate covers a projection of the second opening on the substrate.

4. The display substrate of claim 3, further comprising: A third metal layer is located on a side of the second metal layer away from the substrate, wherein the third metal layer is electrically connected with the second metal layer, and a projection of the third metal layer on the substrate covers a projection of the second metal layer on the substrate. 5.The display substrate of claim 4, wherein, The projection of the third metal layer on the substrate does not overlap with a projection of the first step portion of the first metal layer on the substrate, and the projection of the third metal layer on the substrate is located within a projection of the first opening on the substrate. 6.The display substrate of claim 4, wherein, The projection of the third metal layer on the substrate covers the projection of the first metal layer on the substrate. 7.The display substrate of claim 4, wherein, The projection of the third metal layer on the substrate is located within the projection of the first metal layer on the substrate, and partially overlaps with the projection of the first step portion on the substrate. 8.The display substrate according to any one of claims 1-7, wherein, The second insulating layer is an inorganic insulating layer or an organic insulating layer. 9.The display substrate of claim 6, wherein, The second insulating layer is an organic insulating layer, and the projection of the third metal layer on the substrate covers the projection of the second insulating layer on the substrate. 10.The display substrate of any one of claims 1-7, wherein, The second insulating layer includes a first insulating sub-layer and a second insulating sub-layer, and the second insulating sub-layer is located on a side of the first insulating sub-layer away from the substrate. 11.The display substrate of claim 10, wherein, The material of the first insulating sub-layer is an inorganic material, and the material of the second insulating sub-layer is an organic material. 12.The display substrate of claim 11, wherein, The projections of the first insulating sub-layer and the second insulating sub-layer on the substrate both cover the projections of the first step portion and the second step portion of the first metal layer on the substrate. 13.The display substrate of claim 11, wherein, The projection of the first insulating sub-layer on the substrate covers the projections of the first step portion and the second step portion of the first metal layer on the substrate, and the projection of the second insulating sub-layer on the substrate does not overlap with the projection of the first opening on the substrate. 14.The display substrate of claim 10, wherein, The material of the first insulating sub-layer is an organic material, the material of the second insulating sub-layer is an inorganic material, and the projections of the first insulating sub-layer and the second insulating sub-layer on the substrate both cover the projections of the first step portion and the second step portion of the first metal layer on the substrate.

15. The display substrate of claim 6, further comprising: A third insulating layer is located on a side of the third metal layer away from the substrate, wherein the third insulating layer includes a third opening; and A fourth metal layer is located on a side of the third metal layer and the third insulating layer away from the substrate, wherein the fourth metal layer is electrically connected with the third metal layer through the third opening. 16.The display substrate of claim 15, wherein, The projection of the first opening on the substrate is located within the projection of the third opening on the substrate, and the projection of the fourth metal layer on the substrate covers the projection of the third metal layer on the substrate. 17.The display substrate of claim 4, wherein, At least one of the plurality of sub-pixels comprises a thin film transistor, the thin film transistor comprising: a gate metal layer on the substrate base plate, a gate insulating layer on a side of the gate metal layer facing away from the substrate base plate, and a first source-drain metal layer, a second source-drain metal layer and a third source-drain metal layer arranged in sequence on a side of the gate insulating layer facing away from the substrate base plate. 18.The display substrate of claim 17, wherein, The plurality of data line leads are arranged in the same layer as the gate metal layer, the first insulating layer is arranged in the same layer as the gate insulating layer, the first metal layer is arranged in the same layer as the first source-drain metal layer, the second metal layer is arranged in the same layer as the second source-drain metal layer, and the third metal layer is arranged in the same layer as the third source-drain metal layer.

19. A display device comprising the display substrate according to any one of claims 1-18.

20. A method for manufacturing the display substrate according to any one of claims 1-18, comprising: providing a substrate base plate comprising a display area and a first bezel area on at least one side of the display area; preparing a plurality of sub-pixels, a plurality of data lines and a plurality of data line leads on one side of the substrate base plate, the plurality of sub-pixels and the plurality of data lines being located in the display area and electrically connected, and the plurality of data line leads being located in the first bezel area and electrically connected to the plurality of data lines; manufacturing a plurality of pads in the first bezel area, the step of manufacturing at least one pad of the plurality of pads comprising: forming a first insulating layer on a side of the plurality of data line leads facing away from the substrate base plate, the first insulating layer comprising a first opening exposing at least a portion of at least one data line lead of the plurality of data line leads; forming a first metal layer on a side of the plurality of data line leads facing away from the substrate base plate, the first metal layer being electrically connected to at least one data line lead of the plurality of data line leads through the first opening, wherein the first metal layer comprises a first bottom and a stepped portion surrounding the first bottom, a footprint of the first bottom on the substrate base plate is located within a footprint of the first opening on the substrate base plate, the first bottom is electrically connected to at least one data line lead of the plurality of data line leads, the stepped portion comprises a first stepped portion on a side of the first insulating layer facing away from the substrate base plate and a second stepped portion at an included angle with the first stepped portion, the second stepped portion connects the first bottom and the first stepped portion, and a footprint of the second stepped portion on the substrate base plate is located in a footprint of the first opening on the substrate base plate; and forming a second insulating layer on a side of the first metal layer and the first insulating layer facing away from the substrate base plate, wherein the second insulating layer comprises a second opening exposing at least a portion of the first bottom of the first metal layer, and a footprint of the second insulating layer on the substrate base plate covers footprints of the first stepped portion and the second stepped portion of the first metal layer on the substrate base plate.

21. The method of claim 20, further comprising: forming a second metal layer on a side of the first metal layer and the second insulating layer facing away from the substrate, wherein the second metal layer is electrically connected with the first metal layer through the second opening, a projection of the second metal layer on the substrate does not overlap with a projection of the first step portion of the first metal layer on the substrate, and the projection of the second metal layer on the substrate covers the projection of the second opening on the substrate.

22. The method of claim 21, further comprising: forming a third metal layer on a side of the second metal layer facing away from the substrate, wherein the third metal layer is electrically connected with the second metal layer, and a projection of the third metal layer on the substrate covers a projection of the second metal layer on the substrate.

23. The method of any one of claims 20-22, wherein, forming a second insulating layer on a side of the first metal layer and the first insulating layer facing away from the substrate includes forming the second insulating layer on the side of the first metal layer and the first insulating layer facing away from the substrate using an inorganic material.

24. The method of any one of claims 20-22, wherein, forming a second insulating layer on a side of the first metal layer and the first insulating layer facing away from the substrate includes forming the second insulating layer on the side of the first metal layer and the first insulating layer facing away from the substrate using an inorganic material.

25. The method of any one of claims 20-22, wherein, forming a second insulating layer on a side of the first metal layer and the first insulating layer facing away from the substrate includes: forming a first insulating sub-layer on a side of the first metal layer and the first insulating layer facing away from the substrate using an inorganic material; and forming a second insulating sub-layer on a side of the first insulating sub-layer facing away from the substrate using an organic material.

26. The method of any one of claims 20-22, wherein, forming a second insulating layer on a side of the first metal layer and the first insulating layer facing away from the substrate includes: forming a first insulating sub-layer on a side of the first metal layer and the first insulating layer facing away from the substrate using an organic material; and forming a second insulating sub-layer on a side of the first insulating sub-layer facing away from the substrate using an inorganic material.

27. A method for manufacturing the display substrate of claim 1, comprising: providing a substrate, the substrate comprising a display area and a first bezel area located at least one side of the display area; preparing a plurality of sub-pixels, a plurality of data lines and a plurality of data line leads on a side of the substrate, the plurality of sub-pixels and the plurality of data lines being located in the display area and electrically connected, the plurality of data line leads being located in the first bezel area and electrically connected with the plurality of data lines; manufacturing a plurality of pads in the first bezel area, the step of manufacturing at least one pad of the plurality of pads comprising: forming a first insulating layer on a side of the plurality of data line leads facing away from the substrate, the first insulating layer comprising a first opening exposing at least a portion of at least one data line lead of the plurality of data line leads; ​ A first metal layer is formed on a side of the plurality of data line leads away from the substrate, the first metal layer being electrically connected to at least one of the plurality of data line leads through the first opening, wherein the first metal layer includes a first bottom and a stepped portion surrounding the first bottom, a projection of the first bottom on the substrate is located within a projection of the first opening on the substrate, the first bottom is electrically connected to at least one of the plurality of data line leads, the stepped portion includes a first stepped portion on a side of the first insulating layer away from the substrate and a second stepped portion at an angle to the first stepped portion, the second stepped portion connects the first bottom and the first stepped portion, and a projection of the second stepped portion on the substrate is located in a projection of the first opening on the substrate; A second insulating layer is formed on a side of the first metal layer and the first insulating layer away from the substrate, wherein the second insulating layer covers a projection of the first metal layer on the substrate; A second metal layer is formed on a side of the second insulating layer away from the substrate; The second metal layer is removed; A third metal layer is formed on a side of the second insulating layer away from the substrate; The third metal layer is removed; and A second opening is formed on the second insulating layer, the second opening exposes at least a portion of the first bottom of the first metal layer, and a projection of the second insulating layer on the substrate covers a projection of the first stepped portion and the second stepped portion of the first metal layer on the substrate. ​

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