Pseudo-random sequence generation method, device, medium, and product

Abstract

The present disclosure provides a pseudo-random sequence generation method. The method comprises: performing first recursive XOR operation on an initial sequence value in a first initial m-sequence to obtain a first m-sequence; performing second recursive XOR operation on an initial sequence value in a second initial m-sequence to obtain a second m-sequence; and generating a pseudo-random sequence on the basis of the first m-sequence and the second m-sequence. The present disclosure further provides an electronic device, a computer-readable storage medium, and a computer program product.

Description

Methods, equipment, media, and products for generating pseudo-random sequences

[0001] Cross-references to related applications

[0002] This application claims priority to Chinese Patent Application No. 202410954958.8, filed with the Chinese Patent Office on July 16, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to, but is not limited to, the field of communication technology. Background Technology

[0004] Currently, pseudo-random sequences (Gold sequences) are used in the process of modulating or demodulating baseband signals in the field of communication.

[0005] However, in the conventional method of calculating Gold sequences, it is usually necessary to perform a modulo operation on the sequence value, which not only increases the complexity of the operation but also prolongs the operation time of the sequence, thus reducing the generation speed of Gold sequences. Summary of the Invention

[0006] This disclosure provides a method for generating pseudo-random sequences, an electronic device, a computer-readable storage medium, and a computer program product.

[0007] In a first aspect, embodiments of this disclosure provide a method for generating a pseudo-random sequence, the method comprising: performing a first recursive XOR operation on initial sequence values ​​in a first initial m-sequence to obtain a first m-sequence; performing a second recursive XOR operation on initial sequence values ​​in a second initial m-sequence to obtain a second m-sequence; and generating a pseudo-random sequence based on the first m-sequence and the second m-sequence.

[0008] Secondly, embodiments of this disclosure provide an electronic device, including: one or more processors; and a memory storing one or more programs thereon, wherein when the one or more programs are executed by the one or more processors, the one or more processors implement any of the pseudo-random sequence generation methods in the embodiments of this disclosure.

[0009] Thirdly, embodiments of this disclosure provide a computer-readable storage medium storing a computer program that, when executed by a processor, implements any of the pseudo-random sequence generation methods in embodiments of this disclosure.

[0010] Fourthly, embodiments of this disclosure provide a computer program product, which includes a computer program that, when executed by a processor, implements any of the pseudo-random sequence generation methods in embodiments of this disclosure. Attached Figure Description

[0011] In the accompanying drawings of the embodiments disclosed herein:

[0012] Figure 1 is a flowchart illustrating a method for generating a pseudo-random sequence according to an embodiment of this disclosure;

[0013] Figure 2 is a flowchart illustrating a method for generating a pseudo-random sequence according to an embodiment of this disclosure;

[0014] Figure 3 is a schematic diagram of the operation process of performing a first recursive XOR operation on the initial sequence values ​​in the first initial m sequence according to an embodiment of this disclosure;

[0015] Figure 4 is a schematic diagram of the operation process of performing a second recursive XOR operation on the initial sequence value in the second initial m sequence according to an embodiment of the present disclosure;

[0016] Figure 5 is a block diagram of a pseudo-random sequence generation device provided in an embodiment of this disclosure;

[0017] Figure 6 is a block diagram of an electronic device provided in an embodiment of this disclosure. Detailed Implementation

[0018] To enable those skilled in the art to better understand the technical solutions of this disclosure, the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings.

[0019] The present disclosure will be described more fully below with reference to the accompanying drawings; however, the embodiments shown may be embodied in different forms, and the present disclosure should not be construed as limited to the embodiments set forth below. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will enable those skilled in the art to fully understand the scope of the disclosure.

[0020] The accompanying drawings of the embodiments disclosed herein are provided to further illustrate the embodiments of this disclosure and form part of the specification. They are used together with the detailed embodiments to explain this disclosure and do not constitute a limitation thereof. The above and other features and advantages will become more apparent to those skilled in the art from the description of the detailed embodiments with reference to the accompanying drawings.

[0021] Where there is no conflict, the various embodiments of this disclosure and the features thereof in the embodiments may be combined with each other.

[0022] The terminology used in this disclosure is for the purpose of describing particular embodiments only and is not intended to limit the disclosure. The term "and / or" as used in this disclosure includes any and all combinations of one or more of the associated enumerated entries. The singular forms "a" and "the" as used in this disclosure are also intended to include the plural forms, unless the context clearly indicates otherwise. The terms "comprising," "made of," etc., as used in this disclosure specify the presence of the stated feature, integral, step, operation, element, and / or component, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof.

[0023] Unless otherwise specified, all terms used in this disclosure (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and this disclosure, and will not be interpreted as having an idealized or overly formal meaning, unless expressly so defined in this disclosure.

[0024] In the processing of baseband signals in communication systems, pseudo-random (Gold) sequences are typically used. For example, Gold sequences are used when the transmitting device scrambles the sequence to be transmitted, when the receiving device performs channel estimation, and when the receiving device descrambles the received signal. Therefore, Gold sequences are characterized by being called many times and having long generation sequences, and their generation time needs to be strictly limited to reduce the signal processing time in the communication system.

[0025] In some related implementations, the Gold sequence c(n) is calculated using formula (1): c(n)=(x1(n+N) C )+x2(n+N C ))mod2 (1)

[0026] Where x1(n+31)=(x1(n+3)+x1(n))mod2; x2(n+31)=(x2(n+3)+x2(n+2)+x2(n+1)+x2(n))mod2; x1(n) represents the first m-sequence, and x2(n) represents the second m-sequence; m-sequence is short for the longest linear feedback shift register sequence.

[0027] Where n represents the sequence index, n is an integer greater than or equal to 0, c(n) is the output Gold sequence, and N C For a preset quantity threshold (e.g., 1600), mod2 represents the modulo operation with respect to 2.

[0028] The initial sequence values ​​of x1(n) are fixed: x1(0) = 1, x1(n) = 0, where n = 0, 1, 2, ..., 30.

[0029] The initial sequence values ​​of x2(n) are given by C init Decide: C init It depends on the actual situation in the communication link.

[0030] However, in the process of using the above formula (1), the complexity of the operation is increased and the operation time of the sequence is extended due to the need to perform the remainder operation on each m sequence, which leads to a decrease in the generation speed of the Gold sequence.

[0031] To address the aforementioned issues, this disclosure provides a method for generating pseudo-random sequences, an electronic device, a computer-readable storage medium, and a computer program product to accelerate the generation of Gold sequences.

[0032] In a first aspect, embodiments of this disclosure provide a method for generating pseudo-random sequences.

[0033] The pseudo-random sequence generated in this embodiment can be applied in the process of scrambling the sequence to be transmitted by the transmitting device in a communication system, and / or in the process of channel estimation by the receiving device, and / or in the process of descrambling the received signal by the receiving device.

[0034] The above examples of pseudo-random sequence applications are merely illustrations. Applications can be tailored to specific scenarios, and this disclosure does not impose any restrictions on them. Further details will not be provided here.

[0035] Figure 1 is a schematic flowchart of a method for generating a pseudo-random sequence according to an embodiment of this disclosure. This method is applied to a pseudo-random sequence generation apparatus. As shown in Figure 1, the method includes, but is not limited to, the following steps S101 to S103.

[0036] Step S101: Perform a first recursive XOR operation on the initial sequence values ​​in the first initial m-sequence to obtain the first m-sequence.

[0037] The first recursive XOR operation is performed recursively, sequentially XORing the initial sequence values ​​in the first initial m-sequence to obtain each sequence value in the first m-sequence.

[0038] The principle of XOR operation is: when the initial sequence values ​​of the two XOR operations are the same, the XOR result is 0; when the initial sequence values ​​of the two XOR operations are different, the XOR result is 1. By using XOR operation, the sequence value of the first m sequence can be quickly determined.

[0039] For example, based on a preset recursive order, an XOR operation is performed on two initial sequence values ​​in the first initial m sequence to obtain a sequence value in the first m sequence; then, with a preset step size, the next two initial sequence values ​​that need to be XORed are taken from the first initial m sequence in turn, and the XOR operation is performed again to obtain the next sequence value in the first m sequence; and so on, the first m sequence can be obtained in the end.

[0040] By performing an XOR operation on the initial sequence values ​​in the first initial m-sequence using the above recursive method, the sequence values ​​in the first m-sequence can be calculated quickly. Compared with the operation of taking the remainder of 2 on the initial sequence values ​​in the prior art, the calculation speed of the sequence values ​​is greatly improved, so as to obtain the first m-sequence quickly and accurately.

[0041] Step S102: Perform a second recursive XOR operation on the initial sequence values ​​in the second initial m sequence to obtain the second m sequence.

[0042] The second recursive XOR operation is performed recursively, sequentially XORing the initial sequence values ​​in the second initial m-sequence to obtain each sequence value in the second m-sequence.

[0043] For example, based on a preset recursive order, an XOR operation is performed on four consecutive initial sequence values ​​in the second initial m sequence to obtain a sequence value in the second m sequence; then, with a preset step size, the next set of initial sequence values ​​that need to be XORed (i.e., the subsequent four consecutive initial sequence values) is taken from the second initial m sequence in turn, and the XOR operation is performed again to obtain the next sequence value in the second m sequence; and so on, until the second m sequence is finally obtained.

[0044] Step S103: Generate a pseudo-random sequence based on the first m sequence and the second m sequence.

[0045] In this process, a pseudo-random sequence can be obtained by performing an XOR operation between the first m-sequence and the second m-sequence.

[0046] For example, the first sequence value in the first m-sequence is XORed with the first sequence value in the second m-sequence to obtain the first sequence value in the pseudo-random sequence; the second sequence value in the first m-sequence is XORed with the second sequence value in the second m-sequence to obtain the second sequence value in the pseudo-random sequence; and so on, until the last sequence value in the pseudo-random sequence is obtained.

[0047] The pseudo-random sequence generation method in this embodiment, compared with the prior art's method of performing a modulo-2 operation on the sequence value, greatly reduces computational complexity by performing a first recursive XOR operation on the initial sequence value in the first initial m sequence and a second recursive XOR operation on the initial sequence value in the second initial m sequence. This accelerates the processing speed of the first and second initial m sequences, quickly and accurately obtains the first and second m sequences, and then generates a pseudo-random sequence based on the first and second m sequences, thereby improving the generation speed of the pseudo-random sequence.

[0048] In some embodiments, the second recursive XOR operation method can be determined in the following manner:

[0049] First, convert x2(n+31)=(x2(n+3)+x2(n+2)+x2(n+1)+x2(n))mod2 into the XOR operation formula:

[0050] in, The XOR operation is represented. For example, when x2(n+3) and x2(n+2) are the same, the XOR result is 0; when x2(n+3) and x2(n+2) are different, the XOR result is 1. Similarly, when x2(n+1) and x2(n) are the same, the XOR result is 0; when x2(n+1) and x2(n) are different, the XOR result is 1.

[0051] Then, substituting n = 0, 1, 2, ..., 30 into the XOR operation formula, we can obtain the following sequence of values:

[0052] The XOR operation has the following properties: if two values ​​are not the same, the XOR result is 1. If the two values ​​a and b are the same, the XOR result is 0.

[0053] Therefore, when n = 31,

[0054] Correspondingly, the following sequence values ​​can be obtained in sequence:

[0055] ...;

[0056] By summarizing the above sequence value operation process, the second recursive XOR operation method can be obtained as formula (2).

[0057] Using the same reasoning process as the inductive algorithm described above, the first recursive XOR operation can be obtained as formula (3).

[0058] Furthermore, the formula for calculating the Gold sequence c(n) can be determined as formula (4).

[0059] Where n is the sequence number of the sequence value; n and k are both integers greater than or equal to 0; x1(*) represents the sequence value in the first m-sequence with a preset processing bit width of one bit; and x2(*) represents the sequence value in the second m-sequence with a preset processing bit width of one bit.

[0060] In some exemplary embodiments, step S101, which involves performing a first recursive XOR operation on the initial sequence values ​​in the first initial m-sequence to obtain the first m-sequence, includes: performing an XOR operation on the nth initial sequence value and the (n+3)th initial sequence value in the first initial m-sequence to generate the (n+31)th sequence value in the first m-sequence; and determining the first m-sequence based on the multiple sequence values ​​in the first m-sequence.

[0061] Where 0≦n≦Nc, and Nc represents a preset quantity threshold. For example, setting Nc to 1600 means that the first m-sequence includes 1600 initial sequence values.

[0062] When performing an XOR operation on the nth initial sequence value and the (n+3)th initial sequence value in the first initial m sequence, the XOR operation can be performed on the nth initial sequence value and the (n+3)th initial sequence value. If the nth initial sequence value and the (n+3)th initial sequence value are the same, then the (n+31)th sequence value in the corresponding first m sequence is 0; if the nth initial sequence value and the (n+3)th initial sequence value are different, then the (n+31)th sequence value in the corresponding first m sequence is 1. Then, n is incremented by 1 (or n = n + a preset step size (e.g., 2, 3, etc.)) to determine the next set of two initial sequence values ​​that need to be XORed, and then the next round of XOR operation is performed, and so on, to determine multiple sequence values ​​in the first m sequence.

[0063] By using the XOR processing method described above, each initial sequence value in the first initial m-sequence is processed sequentially. Compared with the operation of taking the remainder of 2 on the initial sequence values, this method can greatly speed up the calculation and ensure the accuracy of the sequence values ​​in the first m-sequence obtained by calculation.

[0064] In some exemplary embodiments, step S102, which involves performing a second recursive XOR operation on the initial sequence values ​​in the second initial m-sequence to obtain the second m-sequence, includes: sequentially XORing the q-th initial sequence value, the (q+1)-th initial sequence value, the (q+2)-th initial sequence value, and the (q+3)-th initial sequence value in the second initial m-sequence to generate the (q+31)-th sequence value in the second m-sequence; and determining the second m-sequence based on the multiple sequence values ​​in the second m-sequence.

[0065] Where 0≦q≦Nc, and Nc represents a preset quantity threshold. For example, setting Nc to 1600 means that the second m-sequence includes 1600 initial sequence values.

[0066] When performing XOR operations on the q-th, q+1-th, q+2-th, and q+3-th initial sequence values ​​in the second initial m-sequence, the XOR operation can be performed first on the q-th and q+1-th initial sequence values ​​to obtain the first result. Then, the XOR operation can be performed on the q+2-th and q+3-th initial sequence values ​​to obtain the second result. The first and second results can then be XORed to obtain the q+31-th sequence value in the second m-sequence. Further, q is incremented by 1 (or q = q + a preset step size (e.g., 1, 2, 3, etc.)) to determine the next set of four initial sequence values ​​to be XORed. The next round of XOR operations is then performed, and so on, to determine multiple sequence values ​​in the second m-sequence.

[0067] By using the XOR processing method described above, each initial sequence value in the second initial m-sequence is processed sequentially. Compared with the operation of taking the remainder of 2 on the initial sequence values, this method can greatly speed up the calculation and ensure the accuracy of the sequence values ​​in the calculated second m-sequence.

[0068] In some exemplary embodiments, step S101, which involves performing a first recursive XOR operation on the initial sequence values ​​in the first initial m-sequence to obtain the first m-sequence, includes: performing a first recursive XOR operation on the initial sequence values ​​in the first initial m-sequence using a preset processing bit width as the processing unit to obtain the first m-sequence.

[0069] The preset processing bit width includes multiple bits. Multiple bits means that the preset processing bit width has multiple data units, each data unit being one bit.

[0070] In some related technologies, a bit is usually used as the processing unit, and the initial sequence value in the first initial m sequence is processed bit by bit (e.g., performing a modulo operation). When the data represented by the initial sequence value is large, the bit-by-bit processing method will increase the data processing time and reduce the operation speed.

[0071] In this embodiment of the disclosure, by using a method with a preset processing bit width as the processing unit to perform a first recursive XOR operation on the initial sequence value in the first initial m sequence, it is possible to process multiple bits simultaneously, which can greatly shorten the data processing time and thus improve the processing speed of the initial sequence value in the first initial m sequence.

[0072] Furthermore, by employing the first recursive XOR operation, multiple bits of the initial sequence value in the first initial m-sequence are processed simultaneously. This not only reduces the number of operations on the initial sequence value but also ensures the accuracy of the sequence value in the calculated first m-sequence.

[0073] In some exemplary embodiments, the preset processing bit width includes 2. p 1 bit.

[0074] Where p is an integer greater than or equal to 1.

[0075] For example, when p equals 3, the default processing bit width is 2. 3 = 8 bits; that is, using 8 bits as the processing unit, the first recursive XOR operation is performed on the initial sequence value in the first initial m sequence to obtain the first m sequence.

[0076] For example, when p equals 4, the default processing bit width is 2. 4 = 16 bits; that is, using 16 bits as the processing unit, the first recursive XOR operation is performed on the initial sequence value in the first initial m sequence to obtain the first m sequence.

[0077] For example, when p equals 5, the default processing bit width is 2. 5 = 32 bits; that is, using an int32 (i.e., 32 bits) as the processing unit, the first recursive XOR operation is performed on the initial sequence value in the first initial m sequence to obtain the first m sequence.

[0078] By using preset processing bit widths of different lengths as processing units, the initial sequence values ​​in the first initial m-sequence are subjected to a first recursive XOR operation, which enables parallel processing of the initial sequence values, thereby improving the data processing speed.

[0079] In some embodiments, a preset processing bit width can also be applied to the calculation process of the initial sequence values ​​in the second initial m sequence. By using the preset processing bit width as the processing unit, a second recursive XOR operation can be performed on the initial sequence values ​​in the second initial m sequence, which can also improve the calculation speed of each initial sequence value in the second initial m sequence, thereby speeding up the final acquisition of the pseudo-random sequence.

[0080] In some exemplary embodiments, before performing a first recursive XOR operation on the initial sequence values ​​in the first initial m-sequence using a preset processing bit width as the processing unit to obtain the first m-sequence, the method further includes: calculating the preset processing bit width based on the preset unit bit width and the number of parallel processes.

[0081] The preset unit bit width is determined based on the number of bits included in the initial sequence value. For example, if the initial sequence value includes 32 bits, then the preset unit bit width can be set to 32 bits.

[0082] The number of parallel processing operations is determined based on the data processing capabilities of the communication system. For example, if a communication system supports the simultaneous processing of 16 int32 data points, then the number of parallel processing operations can be set to 16.

[0083] By multiplying the preset unit bit width and the number of parallel processing operations, the preset processing bit width can be calculated. Based on this preset processing bit width, the first recursive XOR operation can be performed on the initial sequence values ​​in the first initial m sequence in parallel, so as to realize the simultaneous processing of the data with the preset processing bit width in the initial sequence values ​​in the first initial m sequence, reduce the number of operations on the initial sequence values, and thus speed up the processing speed of the initial sequence values ​​in the first initial m sequence.

[0084] In some exemplary embodiments, before performing a first recursive XOR operation on the initial sequence values ​​in the first initial m-sequence in step S101 to obtain the first m-sequence, the method further includes: storing each initial sequence value in a preset storage area.

[0085] The preset storage area is a pre-defined area used to store the initial sequence value. For example, one or more registers may be pre-defined as the preset storage area, or a certain cache area may be pre-defined as the preset storage area.

[0086] By storing each initial sequence value in a preset storage area, the corresponding initial sequence value can be quickly retrieved directly from the preset storage area in subsequent data processing. Then, XOR operations can be performed on each initial sequence value, which can speed up the processing speed of the m sequence.

[0087] In some embodiments, the initial sequence value stored in the preset storage area may be the initial sequence value in the first initial m sequence or the initial sequence value in the second initial m sequence, so as to facilitate subsequent operations on the first initial m sequence and the second initial m sequence and improve the processing speed of the sequence.

[0088] In some exemplary embodiments, the preset storage area includes multiple sub-regions; the number of initial sequence values ​​stored in each sub-region is the number of parallel processing values, and the bit width of the initial sequence values ​​stored in each sub-region is a preset unit bit width.

[0089] By using the number of parallel processing operations as the number of initial sequence values ​​stored in each sub-region, and using the preset unit bit width as the bit width of the initial sequence values ​​stored in each sub-region, it is easier to search and read the data stored in the preset storage area, thereby speeding up the acquisition of the initial sequence values.

[0090] For example, if the number of parallel processing operations is set to 16 and the preset unit bit width is 2... k If we have 16 bits, then the number of initial sequence values ​​stored in each sub-region is 16; correspondingly, the bit width of each initial sequence value is 2. k Each sub-region stores 16 bits. In other words, each sub-region stores 16 bits with a width of 2. k The initial sequence value of 2 bits is used to retrieve a 2-bit wide sequence value at a time each time the initial sequence value is read from the preset access area. k The system stores 16 initial sequence values ​​in each sub-region; and since each sub-region stores 16 initial sequence values, the initial sequence value at the corresponding position can be retrieved conveniently and quickly based on the sorting of the sub-regions. Here, k is an integer greater than or equal to 1.

[0091] For example, if you want to read the 8th initial sequence value in the first initial m-sequence, you only need to read the 8th stored data from the first sub-region to obtain the 8th initial sequence value, which has a bit width of 2. k One bit.

[0092] For example, if you want to read the 17th initial sequence value in the first initial m-sequence, you only need to read the first stored data from the second sub-region to obtain the 17th initial sequence value, which has a bit width of 2. k One bit.

[0093] By using the above-described data storage method to store the initial sequence values ​​in the first initial m-sequence and / or the second initial m-sequence, the data access efficiency can be greatly improved, thereby facilitating the operation of the first initial m-sequence and / or the second initial m-sequence and increasing the speed of sequence operation.

[0094] Figure 2 is a flowchart illustrating a method for generating a pseudo-random sequence according to an embodiment of this disclosure. In this method for generating a pseudo-random sequence, the preset processing bit width includes 2... k k bits, where k is an integer greater than or equal to 1.

[0095] As shown in Figure 2, the method for generating this pseudo-random sequence includes, but is not limited to, the following steps S201 to S205.

[0096] Step S201: Generate the initial sequence value of the first initial m sequence.

[0097] Wherein, the first initial sequence value in the first initial m sequence is: X1(0)=[x1(2 k -1),…,x1(1),x1(0)],

[0098] Where x1(30), x1(29), ..., x1(0) are known bits determined by the initial values; x1(2 k -1),...,x1(31) are values ​​determined according to formula (3). X1(0) represents a preset processing bit width of 2. k It is an integer data of 1 bit, and only one integer data can be operated on at a time.

[0099] Then, using the same method as the method for generating the first initial sequence value X1(0) above, other initial sequence values ​​of the first initial m sequence are generated: X1(1), X1(2), ..., X1(30).

[0100] Step S202: Using a preset processing bit width as the processing unit, perform a first recursive XOR operation on the initial sequence values ​​in the first initial m-sequence to generate the first m-sequence.

[0101] The preset processing bit width is 2. k k is a number of bits, where k is an integer greater than or equal to 1.

[0102] By setting the preset processing bit width to 1 bit in formula (3), it is equivalent to 2 k From these bits, we can obtain formula (5):

[0103] Where m = n / 2 k X1(*) indicates that the preset processing bit width is 2. k The sequence value in the first m-bit sequence.

[0104] Then, using the above formula (5), the values ​​of each sequence in the first m sequence can be calculated.

[0105] For example, when k = 5, it means that each sequence value in the first m-sequence has 2. k = 32 bits. If the first m-sequence is set to include 32 sequence values, then the sequence values ​​in the first m-sequence can be represented as: n is an integer greater than 992.

[0106] The other initial sequence values ​​in the first m-sequence can be calculated as follows:

[0107] in, This represents the 0th to 2nd bits of the sequence value X1(m). k -5bit, The second value of sequence X1(m) k -4bit; The second value of sequence X1(m) k -3bit; The second value of sequence X1(m) k -2 bits; The second value of sequence X1(m) k -1 bit.

[0108] In some embodiments, if [x1(30),x1(29),...,x1(0)]=[1,0,...,0] is set as a preset initial value, then

[0109] Correspondingly, according to formula (5), the values ​​of each sequence in the first m sequence can be obtained in sequence: X1(1), X1(2), ..., X1(30), X1(31)).

[0110] For example, Figure 3 is a schematic diagram of a first recursive XOR operation on the initial sequence values ​​in the first initial m sequence provided by an embodiment of this disclosure. As shown in Figure 3, the operation process includes the following steps:

[0111] Step S0: Using a shift-and-XOR method, the 0th to 27th bits of the sequence value X1(m+1) are calculated in parallel.

[0112] in,

[0113] m = 0, 1, ..., 29; This represents the XOR operation;

[0114] X1(m) 28:0 >>1 means shifting bits 0 to 28 of X1(m) to the right by 1 bit;

[0115] X1(m) 28:0 >>4 means shifting bits 0 to 28 of X1(m) 4 bits to the right.

[0116] In Figure 3, [0',1',2',3',…,31'] represents the sequence value X1(m+1), and [0,1,2,3,…,31] represents the sequence value X1(m).

[0117] Step S1: Calculate the 28th bit of the sequence value X1(m+1).

[0118] in,

[0119] Step S2: Calculate the 29th bit of the sequence value X1(m+1).

[0120] in,

[0121] Step S3: Calculate the 30th bit of the sequence value X1(m+1).

[0122] in,

[0123] Step S4: Calculate the 31st bit of the sequence value X1(m+1).

[0124] in,

[0125] X1(0), X1(1), ..., X1(m) are generated in the above manner, that is, the sequence values ​​in the first m sequence X1 are calculated in sequence.

[0126] It should be noted that while performing steps S201 to S202, steps S203 to S204 can also be performed simultaneously to obtain the sequence values ​​in the second m sequence.

[0127] Step S203: Generate the initial sequence value of the second initial m sequence.

[0128] Wherein, the first initial sequence value in the second initial m sequence is: X2(0)=[x2(2 k -1),…,x2(1),x2(0)],

[0129] Where x2(30), x2(29), ..., x2(0) are derived from C init A known, definite bit;

[0130] x2(2 k -1),...,x2(31) are values ​​determined according to formula (2). X2(0) represents a preset processing bit width of 2. k It is an integer data of 1 bit, and only one integer data can be operated on at a time.

[0131] Then, using the same method as the method for generating the first initial sequence value X2(0) above, other initial sequence values ​​for the second initial m sequence are generated: X2(1), X2(2), ..., X2(30).

[0132] Step S204: Using the prediction processing bit width as the processing unit, perform a second recursive XOR operation on the initial sequence value in the second initial m sequence to generate the second m sequence.

[0133] In this case, setting the preset processing bit width in formula (2) to 1 bit is equivalent to 2 k From these bits, we can obtain formula (6):

[0134] Where m = n / 2 k X2(*) indicates that the preset processing bit width is 2. k The sequence value in the second m-bit sequence.

[0135] Then, using the above formula (6), the values ​​of each sequence in the second m sequence can be calculated.

[0136] For example, when k = 5, it means that each sequence value in the second m-sequence has 2. k = 32 bits. If the second m-sequence is set to include 32 sequence values, then the sequence values ​​in the second m-sequence can be represented as: n is an integer greater than 992.

[0137] For example, Figure 4 is a schematic diagram of a second recursive XOR operation on the initial sequence values ​​in the second initial m sequence provided by an embodiment of this disclosure. As shown in Figure 4, the operation process includes the following steps:

[0138] Step S11: Using a shift-and-XOR method, calculate bits 0 to 27 of the sequence value X2(m+1) in parallel.

[0139] The calculation process for bits 0 to 27 of the sequence value X2(m+1) is as follows:

[0140] In this context, ">>" indicates moving to the right; This represents the XOR operation; m = 0, 1, ..., 29;

[0141] X2(m) 28:0 >>1 means shifting bits 0 to 28 of X2(m) to the right by 1 bit;

[0142] X2(m) 28:0 >>2 means shifting bits 0 to 28 of X2(m) to the right by 2 bits;

[0143] X2(m) 28:0 >>3 means shifting bits 0 to 28 of X2(m) 3 bits to the right;

[0144] X2(m) 28:0>>4 means shifting bits 0 to 28 of X2(m) to the right by 4 bits;

[0145] X2(m+1) 27:0 , representing bits 0 to 27 of X2(m+1) after shifting and XORing.

[0146] Step S12: Calculate the 28th bit of the sequence value X2(m+1).

[0147] in,

[0148] Step S13: Calculate the 29th bit of the sequence value X2(m+1).

[0149] in,

[0150] Step S14: Calculate the 30th bit of the sequence value X2(m+1).

[0151] in,

[0152] Step S15: Calculate the 31st bit of the sequence value X2(m+1).

[0153] in,

[0154] X2(0), X2(1), ..., X2(m) are generated in the above manner, that is, the sequence values ​​in the second m sequence X2 are calculated in sequence.

[0155] Step S205: Perform an XOR operation on the first m sequence and the second m sequence to generate a pseudo-random sequence.

[0156] One possible formula is: The Gold sequence C is obtained through calculation.

[0157] In this embodiment, the prediction processing bit width is 2. k Using bits as the processing unit, it can simultaneously process 2 k This method performs operations on a sequence of bits, achieving parallel output of multiple bits to obtain the first m-sequence and the second m-sequence. Then, the two m-sequences are XORed to obtain the final Gold sequence. Compared with the existing technology that processes data in one bit unit, this method greatly improves the processing speed of each m-sequence, thus enabling the Gold sequence to be calculated quickly and accurately, thereby improving the processing speed of communication data.

[0158] In some embodiments, the preset processing bit width can also be M*2. k 1 bit, where M = 2a 'a' is an integer greater than or equal to 0. Therefore, the default processing bit width is actually 2. k+a One bit.

[0159] Correspondingly, formula (5) can be changed to: Where m = n / 2 k .

[0160] Furthermore, a preset storage area (e.g., multiple registers) can be used to store multiple initial sequence values ​​in the first initial m sequence. Then, when performing an XOR operation, the corresponding initial sequence value can be directly retrieved from the preset storage area and the XOR operation can be performed to obtain the corresponding sequence value in the first m sequence.

[0161] For example, if M=16, then four registers can be used to store multiple initial sequence values ​​in the first initial m-sequence sequentially. Table 1 shows the multiple initial sequence values ​​in the first initial m-sequence stored in the four registers.

[0162] Table 1 shows multiple initial sequence values ​​stored in the register for the first initial m-sequence.

[0163] As shown in Table 1, vi0 represents the first register, which stores 16 initial sequence values, X1(m) to X1(m+15); vi1 represents the second register, which stores X1(m+16) to X1(m+31); vi2 represents the third register, which stores X1(m+32) to X1(m+47); and vi3 represents the fourth register, which stores X1(m+48) to X1(m+63). The four registers store a total of 64 initial sequence values.

[0164] When it is necessary to perform operations on the initial sequence values, the corresponding initial sequence values ​​can be retrieved from the above registers respectively. Then, by performing an XOR operation, the sequence value of the first m sequence can be quickly calculated.

[0165] For example, using the XOR instruction: `xor vi0,vi3,vo0`, the values ​​of each sequence in the first `m` sequence can be directly calculated. That is, `X1(m+31*2`. a ), ..., X1(m+31*2 a +M).

[0166] Where vi0 represents the first input value of the XOR instruction using the initial sequence stored in the first register, vi3 represents the second input value of the XOR instruction using the initial sequence stored in the third register, and vo0 represents the output value of the XOR instruction.

[0167] In some embodiments, if it is necessary to generate 32*2 4The initial value of *32 = 15872 bits can also be achieved by matrix transformation, thereby enabling parallel processing of M sequence values ​​with a preset unit width of 32 bits to obtain the first m sequence.

[0168] In some embodiments, a preset storage area (e.g., multiple registers) can be used to store multiple initial sequence values ​​in the second initial m sequence; then, when performing an XOR operation, the corresponding initial sequence value can be directly retrieved from the preset storage area and the XOR operation can be performed to obtain the corresponding sequence value in the second m sequence.

[0169] For example, if M=16, then four registers can be used to store multiple initial sequence values ​​in the second initial m-sequence sequentially. Table 2 shows the multiple initial sequence values ​​in the second initial m-sequence stored in the four registers.

[0170] Table 2 shows multiple initial sequence values ​​from the second initial m-sequence stored in the register.

[0171] As shown in Table 2, v0 represents the first register, which stores 16 initial sequence values, X2(m) to X2(m+15); v1 represents the second register, which stores X2(m+16) to X2(m+31); v2 represents the third register, which stores X2(m+32) to X2(m+47); and v3 represents the fourth register, which stores X2(m+48) to X2(m+63). The four registers store a total of 64 initial sequence values.

[0172] When it is necessary to perform operations on the initial sequence values, the corresponding initial sequence values ​​can be retrieved from the above registers respectively. Then, by performing an XOR operation, the sequence value of the second m sequence can be quickly calculated.

[0173] For example, with a preset processing bit width of 2 k+a When the number of bits is 1, formula (6) can be changed to:

[0174] Where m = n / 2 k .

[0175] Then, according to the modified formula above, the sequence value of the second m sequence can be obtained by performing the following three XOR operations using the XOR instruction. That is, X2(m+31*2) a ), ..., X2(m+31*2 a +M).

[0176] First XOR operation: xor vi0,vi1,vo1;

[0177] The second XOR operation: xor vi2,vi3,vo2;

[0178] The third XOR operation: xor vo1,vo2,vo3;

[0179] Where vi0 represents the first input value of the first XOR operation using the initial sequence stored in the first register v0, vi1 represents the second input value of the first XOR operation using the initial sequence stored in the second register v1, and vo1 represents the output value of the first XOR operation.

[0180] vi2 indicates that the initial sequence stored in the third register v2 is used as the first input value of the second XOR operation, vi3 indicates that the initial sequence stored in the fourth register v3 is used as the second input value of the second XOR operation, and vo2 indicates the output value of the second XOR operation.

[0181] Then, the output values ​​vo1 and vo2 of the first XOR operation are used as the input values ​​for the third XOR operation to obtain the final output value vo3, which is the sequence value in the second m sequence.

[0182] Using the above method, only three XOR operations are needed on the initial sequence value to obtain the sequence value in the second m sequence, which can greatly reduce the number of operations on the second m sequence and thus improve the operation speed of the second m sequence.

[0183] For example, if 2 a =16, then 31*2 a =496, the values ​​of each sequence in the second m-sequence can be calculated using the following formula: Where m = n / 2 k .

[0184] The first m-sequence and the second m-sequence are obtained by calculating them in the above manner, which reduces the number of operations and shifting operations, thereby improving the processing speed of the first m-sequence and the second m-sequence. Table 3 shows the comparison of the number of operations between the m-sequence generation method in this embodiment and other generation methods.

[0185] Table 3 Comparison of the number of operations on the m-sequence

[0186] As shown in Table 3, the method for generating the m-sequence in this embodiment can greatly reduce the number of XOR calculations and shift calculations, thereby enabling the first m-sequence and the second m-sequence to be obtained quickly and accurately, and accelerating the final generation of the Gold sequence.

[0187] Thirdly, embodiments of this disclosure provide an apparatus for generating pseudo-random sequences.

[0188] Figure 5 is a block diagram of a pseudo-random sequence generation device provided in an embodiment of this disclosure. This pseudo-random sequence generation device can be installed in embedded operating system servers and / or digital signal processing (DSP) platform servers with various bit widths.

[0189] As shown in Figure 5, the pseudo-random sequence generation device 500 includes, but is not limited to, the following modules.

[0190] The first operation module 501 is configured to perform a first recursive XOR operation on the initial sequence value in the first initial m sequence to obtain the first m sequence.

[0191] The second operation module 502 is configured to perform a second recursive XOR operation on the initial sequence value in the second initial m sequence to obtain the second m sequence;

[0192] The generation module 503 is configured to generate a pseudo-random sequence based on the first m sequence and the second m sequence.

[0193] It should be noted that the pseudo-random sequence generation device in this embodiment can implement any of the pseudo-random sequence generation methods in this disclosure.

[0194] According to the embodiments of the present disclosure, the pseudo-random sequence generation apparatus, compared with the prior art's method of performing a modulo-2 operation on the sequence value, can greatly reduce the computational complexity by using a first operation module to perform a first recursive XOR operation on the initial sequence value in the first initial m sequence and a second operation module to perform a second recursive XOR operation on the initial sequence value in the second initial m sequence. This accelerates the processing speed of the first and second initial m sequences, quickly and accurately obtains the first and second m sequences, and then uses the generation module to generate a pseudo-random sequence based on the first and second m sequences, thereby improving the generation speed of the pseudo-random sequence.

[0195] It should be clarified that the present invention is not limited to the specific configurations and processes described in the above embodiments and shown in the figures. For the sake of convenience and brevity, detailed descriptions of known methods are omitted here, and the specific working processes of the systems, modules, and units described above can be referred to the corresponding processes in the foregoing method embodiments, which will not be repeated here.

[0196] Fourthly, embodiments of this disclosure provide an electronic device, a computer-readable storage medium, and a computer program product.

[0197] Figure 6 shows a block diagram of an electronic device provided in an embodiment of the present disclosure.

[0198] As shown in Figure 6, the electronic device includes at least one processor 601, at least one memory 602, and one or more I / O interfaces 603. The processor 601, memory 602, and I / O interfaces 603 are interconnected via a bus 604. The memory 602 stores one or more computer programs, which are executed by the at least one processor 601 to enable the at least one processor 601 to implement any of the pseudo-random sequence generation methods described in the above embodiments.

[0199] The modules in the aforementioned electronic device can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in the processor of the computer device in hardware form or independent of it, or stored in the memory of the computer device in software form, so that the processor can call and execute the operations corresponding to each module.

[0200] This disclosure also provides a computer-readable storage medium storing a computer program thereon, wherein the computer program, when executed by a processor, implements any of the pseudo-random sequence generation methods described in the above embodiments. The computer-readable storage medium may be a volatile or non-volatile computer-readable storage medium.

[0201] This disclosure also provides a computer program product, including computer-readable code, or a non-volatile computer-readable storage medium carrying computer-readable code. When the computer-readable code is run in the processor of an electronic device, the processor in the electronic device executes the above-described method for generating pseudo-random sequences.

[0202] Those skilled in the art will understand that all or some of the steps, systems, and devices disclosed above, as well as the functional modules / units, can be implemented as software, firmware, hardware, or suitable combinations thereof. In hardware implementations, the division between functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed collaboratively by several physical components.

[0203] Some or all of the physical components may be implemented as software executed by a processor, such as a central processing unit, digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit (ASIC). Such software may be distributed on a computer-readable storage medium, which may include computer storage media (or non-transitory media) and communication media (or transient media). As is known to those skilled in the art, the term computer storage medium includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable program instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM), static random access memory (SRAM), flash memory or other memory technologies, portable compact disc read-only memory (CD-ROM), digital versatile disc (DVD) or other optical disc storage, magnetic cartridges, magnetic tape, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and is accessible to a computer. Furthermore, as is known to those skilled in the art, communication media typically contain computer-readable program instructions, data structures, program modules, or other data in modulated data signals such as carrier waves or other transmission mechanisms, and may include any information delivery medium.

[0204] The computer-readable program instructions described herein can be downloaded from computer-readable storage media to various computing / processing devices, or downloaded via a network, such as the Internet, local area network, wide area network, and / or wireless network, to an external computer or external storage device. The network may include copper transmission cables, fiber optic transmission, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards them to the computer-readable storage media in the respective computing / processing device.

[0205] Computer program instructions used to perform the operations of this disclosure may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Smalltalk, C++, etc., and conventional procedural programming languages ​​such as the "C" language or similar programming languages. The computer-readable program instructions may execute entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving a remote computer, the remote computer may be connected to the user's computer via any type of network—including a local area network (LAN) or a wide area network (WAN)—or may be connected to an external computer (e.g., via the Internet using an Internet service provider). In some embodiments, electronic circuitry, such as programmable logic circuitry, field-programmable gate arrays (FPGAs), or programmable logic arrays (PLAs), is personalized by utilizing state information from the computer-readable program instructions to implement various aspects of this disclosure.

[0206] The computer program product described herein can be implemented specifically through hardware, software, or a combination thereof. In one alternative embodiment, the computer program product is specifically embodied in a computer storage medium; in another alternative embodiment, the computer program product is specifically embodied in a software product, such as a software development kit (SDK), etc.

[0207] Various aspects of this disclosure are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this disclosure. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions.

[0208] These computer-readable program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to produce a machine such that, when executed by the processor of the computer or other programmable data processing apparatus, they create means for implementing the functions / actions specified in one or more blocks of the flowchart and / or block diagram. These computer-readable program instructions can also be stored in a computer-readable storage medium that causes a computer, programmable data processing apparatus, and / or other device to operate in a particular manner; thus, the computer-readable medium storing the instructions comprises an article of manufacture that includes instructions for implementing aspects of the functions / actions specified in one or more blocks of the flowchart and / or block diagram.

[0209] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable data processing apparatus, or other device to produce a computer-implemented process, thereby causing the instructions that execute on the computer, other programmable data processing apparatus, or other device to perform the functions / actions specified in one or more boxes of a flowchart and / or block diagram.

[0210] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of an instruction containing one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than those marked in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, the execution order of which may be determined based on the functions involved in each block. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0211] Example embodiments have been disclosed herein, and while specific terminology has been used, it is intended and should be interpreted only in a general illustrative sense and is not intended to be limiting. In some instances, it will be apparent to those skilled in the art that features, characteristics, and / or elements described in conjunction with particular embodiments may be used alone, or in combination with features, characteristics, and / or elements described in conjunction with other embodiments, unless otherwise expressly indicated. Therefore, those skilled in the art will understand that various changes in form and detail may be made without departing from the scope of this disclosure.

Claims

1. A method for generating a pseudo-random sequence, comprising: performing a first recursive XOR operation on initial sequence values in a first initial m-sequence to obtain a first m-sequence; performing a second recursive XOR operation on initial sequence values in a second initial m-sequence to obtain a second m-sequence; generating a pseudo-random sequence according to the first m-sequence and the second m-sequence.

2. The method of claim 1, wherein, The performing of the first recursive XOR operation on the initial sequence values in the first initial m-sequence to obtain the first m-sequence comprises: performing XOR operation on an n th initial sequence value and an n+3 th initial sequence value in the first initial m-sequence to generate an n+31 th sequence value in the first m-sequence, 0≦n≦Nc, Nc representing a preset quantity threshold; determining the first m-sequence according to a plurality of sequence values in the first m-sequence.

3. The method of claim 1, wherein, The performing of the second recursive XOR operation on the initial sequence values in the second initial m-sequence to obtain the second m-sequence comprises: performing XOR operation on a q th initial sequence value, a q+1 th initial sequence value, a q+2 th initial sequence value and a q+3 th initial sequence value in the second initial m-sequence in sequence to generate a q+31 th sequence value in the second m-sequence, 0≦q≦Nc, Nc representing a preset quantity threshold; determining the second m-sequence according to a plurality of sequence values in the second m-sequence.

4. The method of claim 1, wherein, The performing of the first recursive XOR operation on the initial sequence values in the first initial m-sequence to obtain the first m-sequence comprises: performing the first recursive XOR operation on the initial sequence values in the first initial m-sequence in a preset processing bit width as a processing unit to obtain the first m-sequence, wherein the preset processing bit width comprises a plurality of bits.

5. The method of claim 4, wherein, The preset processing bit width includes 2 p bits, and p is an integer greater than or equal to 1.

6. The method of claim 4, wherein, before the performing of the first recursive XOR operation on the initial sequence values in the first initial m-sequence in the preset processing bit width as the processing unit to obtain the first m-sequence, the method further comprises: calculating the preset processing bit width according to a preset unit bit width and a parallel processing quantity; wherein the preset unit bit width is a bit width determined based on a number of bits included in the initial sequence values.

7. The method of any one of claims 1 to 6, wherein, before the performing of the first recursive XOR operation on the initial sequence values in the first initial m-sequence to obtain the first m-sequence, the method further comprises: storing each of the initial sequence values into a preset storage area.

8. The method of claim 7, wherein, The preset storage area comprises a plurality of sub-areas; a number of initial sequence values stored in each of the sub-areas is the parallel processing quantity, and a bit width of the initial sequence values stored in each of the sub-areas is the preset unit bit width.

9. An electronic device comprising a memory and a processor; the memory stores a computer program executable by the processor, and the computer program, when executed by the processor, implements the method for generating a pseudo-random sequence according to any one of claims 1 to 8.

10. A computer readable storage medium having stored thereon a computer program, the computer program, when executed by a processor, implements the method for generating a pseudo-random sequence according to any one of claims 1 to 8.

11. A computer program product comprising a computer program which, when executed by a processor, implements the method of generating a pseudo-random sequence according to any one of claims 1 to 8.

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