Display device

Abstract

Provided is a display device having high display quality. The display device includes: pixels in which threshold value correction of a drive transistor can be performed; and first and second spacers. The pixels include first to third vertical transistors and a light-emitting element. The second spacer is provided on the first spacer. The first vertical transistor has a region located inside first and second openings provided in the first spacer. The second and third vertical transistors each have regions located inside third and fourth openings provided in the second spacer. The third and fourth openings are provided so as to overlap the first vertical transistor. Thus, the channel length of the first vertical transistor is equal to or greater than the channel lengths of the second and third vertical transistors. The first vertical transistor functions as a drive transistor. The second and third vertical transistors function as switches.

Description

display device

[0001] 1. Field of the Invention One embodiment of the present invention relates to a display device, a semiconductor device, a display module, and an electronic device. 1. Field of the Invention One embodiment of the present invention relates to a method for manufacturing a display device and a method for manufacturing a semiconductor device.

[0002] One embodiment of the present invention is not limited to the above technical field, and examples of the technical field of one embodiment of the present invention include semiconductor devices, display devices, light-emitting devices, power storage devices, memory devices, electronic devices, lighting devices, input devices (e.g., touch sensors), input / output devices (e.g., touch panels), driving methods thereof, and manufacturing methods thereof.

[0003] Semiconductor devices having transistors are widely used in display devices and electronic devices, and there is a demand for higher integration and higher speed of the semiconductor devices. For example, when a semiconductor device is applied to a high-resolution display device, a highly integrated semiconductor device is required. As one means for increasing the integration degree of transistors, the development of fine-sized transistors is underway.

[0004] In recent years, there has been a demand for display devices applicable to virtual reality (VR), augmented reality (AR), substitutional reality (SR), or mixed reality (MR). VR, AR, SR, and MR are collectively referred to as XR (Extended Reality). Display devices for XR are desired to have high resolution and high color reproducibility in order to enhance the sense of realism and immersion. Examples of display devices applicable to such devices include liquid crystal display devices, organic electroluminescence (EL) elements, and light-emitting devices including light-emitting elements (also referred to as light-emitting devices) such as light-emitting diodes (LEDs).

[0005] Patent Document 1 discloses a display device for VR that uses an organic EL element (also called an organic EL device).

[0006] International Publication No. 2018 / 087625

[0007] Takashi Koida, "High Mobility Transparent Conductive Film," National Institute of Advanced Industrial Science and Technology, AIST Photovoltaic Power Generation Research Results Report 2019, Internet <URL: https: / / unit.aist.go.jp / rpd-envene / PV / ja / results / 2019 / oral / T13.pdf>

[0008] A pixel having a light-emitting element is provided with a driving transistor. The driving transistor is a transistor that has a function of controlling a current flowing through the light-emitting element. The driving transistor can control the current flowing through the light-emitting element based on, for example, an image signal. Here, the electrical characteristics of the driving transistor may vary from pixel to pixel due to, for example, the manufacturing process of the display device. For example, the threshold voltage of the driving transistor may vary from pixel to pixel.

[0009] The luminance of a light-emitting element is determined by the magnitude of the drain current of the drive transistor. Therefore, if there is variation in the electrical characteristics of the drive transistors among the multiple pixels that make up the screen of a display device, even if the same image signal is supplied to the multiple pixels, the luminance of each pixel will differ. In particular, variation in threshold voltage has a significant impact on the degradation of the display quality of the display device.

[0010] One method for reducing the variation in the threshold voltage of the driving transistor is to correct the threshold voltage. The correction can be performed, for example, by incorporating a correction circuit into the pixel. However, in this case, the number of transistors is greater than in a pixel without a correction circuit. Therefore, a display device having pixels with a correction circuit incorporated therein may have lower resolution than a display device having pixels without a correction circuit incorporated therein.

[0011] Therefore, an object of one embodiment of the present invention is to provide a display device with high display quality. Another object of one embodiment of the present invention is to provide a high-resolution display device. Another object of one embodiment of the present invention is to provide a display device that operates at high speed. Another object of one embodiment of the present invention is to provide a display device including a transistor with a small size. Another object of one embodiment of the present invention is to provide a display device including a transistor with high on-state current. Another object of one embodiment of the present invention is to provide a display device with favorable electrical characteristics. Another object of one embodiment of the present invention is to provide a novel display device, a novel semiconductor device, and a manufacturing method thereof.

[0012] Note that the description of these problems does not preclude the existence of other problems. Note that one embodiment of the present invention does not necessarily solve all of these problems. Note that problems other than these can be extracted from the description of the specification, drawings, claims, etc.

[0013] One embodiment of the present invention includes a pixel, a first insulating layer, and a second insulating layer. The pixel includes a first vertical transistor, a second vertical transistor, a third vertical transistor, and a light-emitting element. The first vertical transistor includes a first bottom electrode and a second bottom electrode. The first to third vertical transistors each include a conductive layer. The first insulating layer is provided over the first bottom electrode and the second bottom electrode. The second insulating layer is provided over the first insulating layer and the conductive layer. The light-emitting element is provided over the second insulating layer. The first insulating layer has a first opening overlapping with the first bottom electrode and a second opening overlapping the first bottom electrode. the second insulating layer has a third opening overlapping with the conductive layer and a fourth opening overlapping with the conductive layer; the first vertical transistor has a region located inside the first opening and a region located inside the second opening; the second vertical transistor has a region located inside the third opening; the third vertical transistor has a region located inside the fourth opening; and the conductive layer functions as a gate electrode of the first vertical transistor, a bottom electrode of the second vertical transistor, and a bottom electrode of the third vertical transistor.

[0014] Alternatively, in the above aspect, the thickness of the first insulating layer in the region overlapping with the first lower electrode may be equal to or greater than the thickness of the second insulating layer in the region overlapping with the conductive layer.

[0015] Alternatively, in the above aspect, the semiconductor layer and the conductive layer of the first vertical transistor may have a region located inside the first opening and a region located inside the second opening, the semiconductor layer of the second vertical transistor and the gate electrode of the second vertical transistor may have a region located inside the third opening, and the semiconductor layer of the third vertical transistor and the gate electrode of the third vertical transistor may have a region located inside the fourth opening.

[0016] Alternatively, in the above aspect, the third opening may have a region overlapping with the first opening, and the fourth opening may have a region overlapping with the second opening.

[0017] Alternatively, in the above aspect, the semiconductor layers of the first to third vertical transistors may each contain indium.

[0018] Alternatively, in the above aspect, the pixel may include a fourth vertical transistor and a fifth vertical transistor, the first insulating layer being provided on a lower electrode of the fourth vertical transistor, the second insulating layer being provided on the lower electrode of the fifth vertical transistor, the first insulating layer having a fifth opening overlapping with the lower electrode of the fourth vertical transistor, the second insulating layer having a sixth opening overlapping with the lower electrode of the fifth vertical transistor, the fourth vertical transistor having a region located inside the fifth opening, the fifth vertical transistor having a region located inside the sixth opening, the second bottom electrode being electrically connected to the lower electrode of the fourth vertical transistor, the upper electrode of the third vertical transistor being electrically connected to the lower electrode of the fifth vertical transistor, and the upper electrode of the fourth vertical transistor being electrically connected to one electrode of the light-emitting element.

[0019] Alternatively, in the above aspect, the semiconductor layer of the fourth vertical transistor and the gate electrode of the fourth vertical transistor may have a region located inside the fifth opening, and the semiconductor layer of the fifth vertical transistor and the gate electrode of the fifth vertical transistor may have a region located inside the sixth opening.

[0020] Alternatively, in the above aspect, the semiconductor layer of the fourth vertical transistor and the semiconductor layer of the fifth vertical transistor may each contain indium.

[0021] Alternatively, one embodiment of the present invention includes a pixel, a first insulating layer, and a second insulating layer. The pixel includes a first transistor, a second transistor, a third transistor, and a light-emitting element. The first transistor includes a first conductive layer, a second conductive layer, a third conductive layer, a first semiconductor layer, and a third insulating layer. The first insulating layer is provided over the first conductive layer and the second conductive layer. The first insulating layer has a first opening reaching the first conductive layer and a second opening reaching the second conductive layer. The first semiconductor layer has a region in contact with the first conductive layer and a region in contact with the second conductive layer. a third insulating layer is provided on the first semiconductor layer so as to have a region located inside the first opening and a region located inside the second opening; a third conductive layer is provided on the third insulating layer so as to have a region facing the first semiconductor layer with the third insulating layer sandwiched between them inside the first opening and the second opening; the second transistor has a third conductive layer, a fourth conductive layer, a fifth conductive layer, the second semiconductor layer, and a fourth insulating layer; has a third conductive layer, a sixth conductive layer, a seventh conductive layer, a third semiconductor layer, and a fourth insulating layer, the second insulating layer is provided on the third conductive layer, the fourth conductive layer and the sixth conductive layer are provided on the second insulating layer, the second insulating layer and the fourth conductive layer have a third opening reaching the third conductive layer, the second insulating layer and the sixth conductive layer have a fourth opening reaching the third conductive layer, the second semiconductor layer has a region in contact with the third conductive layer, a region in contact with the fourth conductive layer, and a region located inside the third opening, and the third semiconductor layer has a region in contact with the third conductive layer , a region in contact with the sixth conductive layer, and a region located inside the fourth opening; the fourth insulating layer is provided on the second semiconductor layer and the third semiconductor layer so as to have a region located inside the third opening and a region located inside the fourth opening; the fifth conductive layer is provided on the fourth insulating layer inside the third opening so as to have a region facing the second semiconductor layer with the fourth insulating layer therebetween; the seventh conductive layer is provided on the fourth insulating layer inside the fourth opening so as to have a region facing the third semiconductor layer with the fourth insulating layer therebetween; and the light-emitting element isThe display device is provided on the fifth conductive layer, the seventh conductive layer, and the fourth insulating layer.

[0022] Alternatively, in the above aspect, the thickness of the first insulating layer in the region overlapping with the first conductive layer may be equal to or greater than the thickness of the second insulating layer in the region overlapping with the third conductive layer.

[0023] Alternatively, in the above aspect, the third opening may have a region overlapping with the first opening, and the fourth opening may have a region overlapping with the second opening.

[0024] Alternatively, in the above embodiment, the first to third semiconductor layers may each contain indium.

[0025] Alternatively, in the above aspect, the pixel includes a fourth transistor and a fifth transistor, the fourth transistor includes an eighth conductive layer, a ninth conductive layer, a tenth conductive layer, a fourth semiconductor layer, and a third insulating layer, the fifth transistor includes a fifth conductive layer, an eleventh conductive layer, a twelfth conductive layer, a fifth semiconductor layer, and a fourth insulating layer, the first insulating layer is provided on the eighth conductive layer, and the ninth conductive layer is provided on the first insulating layer. the first insulating layer and the ninth conductive layer have a fifth opening reaching the eighth conductive layer; the fourth semiconductor layer has a region in contact with the eighth conductive layer and a region in contact with the ninth conductive layer; the fourth semiconductor layer has a region located inside the fifth opening; the third insulating layer is provided on the fourth semiconductor layer so as to have a region located inside the fifth opening; and the tenth conductive layer faces the fourth semiconductor layer inside the fifth opening, with the third insulating layer sandwiched therebetween. the fifth semiconductor layer is provided on the third insulating layer so as to have a region in contact with the eleventh conductive layer, the eleventh conductive layer is provided on the third insulating layer, the second insulating layer is provided on the tenth conductive layer and the eleventh conductive layer, the twelfth conductive layer is provided on the second insulating layer, the second insulating layer and the twelfth conductive layer have a sixth opening that reaches the eleventh conductive layer, and the fifth semiconductor layer has a region in contact with the eleventh conductive layer, a region in contact with the twelfth conductive layer, and a region located inside the sixth opening. The fourth insulating layer may be provided on the fifth semiconductor layer so as to have a region located inside the sixth opening, the fifth conductive layer may be provided on the fourth insulating layer so as to have a region inside the sixth opening that faces the fifth semiconductor layer with the fourth insulating layer sandwiched therebetween, the second conductive layer may be electrically connected to the eighth conductive layer, the sixth conductive layer may be electrically connected to the eleventh conductive layer, and the ninth conductive layer may be electrically connected to one electrode of the light-emitting element.

[0026] Alternatively, in the above embodiment, the fourth semiconductor layer and the fifth semiconductor layer may each contain indium.

[0027] According to one embodiment of the present invention, a display device with high display quality can be provided. According to one embodiment of the present invention, a high-resolution display device can be provided. According to one embodiment of the present invention, a display device that operates at high speed can be provided. According to one embodiment of the present invention, a display device including a micro-sized transistor can be provided. According to one embodiment of the present invention, a display device including a transistor with high on-state current can be provided. According to one embodiment of the present invention, a display device with favorable electrical characteristics can be provided. According to one embodiment of the present invention, a novel display device, a novel semiconductor device, and a manufacturing method thereof can be provided.

[0028] Note that the description of these effects does not preclude the existence of other effects. One embodiment of the present invention does not necessarily have all of these effects. Effects other than these can be extracted from the description in the specification, drawings, and claims.

[0029] FIGS. 1A and 1B are circuit diagrams showing an example of a pixel configuration. FIG. 1C is a plan view showing an example of a pixel configuration. FIGS. 2A and 2B are plan views showing an example of a pixel configuration. FIG. 3 is a cross-sectional view showing an example of a pixel configuration. FIGS. 4A and 4B are cross-sectional views showing an example of a pixel configuration. FIG. 5A is a perspective view showing an example of a semiconductor device. FIG. 5B is a plan view showing an example of a semiconductor device. FIG. 6A is a cross-sectional view showing an example of a semiconductor device. FIG. 6B is a plan view showing an example of a semiconductor device. FIG. 7A is a plan view showing an example of a semiconductor device. FIG. 7B is a cross-sectional view showing an example of a semiconductor device. FIG. 8 is a cross-sectional view showing an example of a semiconductor device. FIGS. 9A and 9B are cross-sectional views showing an example of a semiconductor device. FIG. 10 is a cross-sectional view showing an example of a semiconductor device. FIGS. 11A and 11B are cross-sectional views showing an example of a semiconductor device. FIGS. 12A and 12B are cross-sectional views showing an example of a semiconductor device. FIG. 13A is a cross-sectional view showing an example of a semiconductor device. FIG. 13B is a plan view showing an example of a semiconductor device. FIG. 14A is a timing chart showing an example of a pixel driving method. FIG. 14B is a circuit diagram showing an example of a pixel driving method. FIGS. 15A and 15B are circuit diagrams showing an example of a pixel driving method. FIGS. 16A1, 16A2, 16A3, 16A4, 16A5, 16A6, 16A7, and 16B1, 16B2, 16B3, 16B4, 16B5, and 16B6 are diagrams illustrating electrical connections. FIGS. 17A and 17B are diagrams illustrating the carrier concentration dependence of Hall mobility. FIG. 17C is a cross-sectional view illustrating an indium oxide film. FIGS. 18A and 18B are perspective views illustrating a configuration example of a display module. FIG. 19 is a cross-sectional view illustrating a configuration example of a display device. FIG. 20 is a cross-sectional view illustrating a configuration example of a display device. FIG. 21 is a cross-sectional view illustrating a configuration example of a display device. 22A, 22B, 22C, 22D, 22E, and 22F are diagrams showing examples of electronic devices, and 23A, 23B, 23C, 23D, 23E, 23F, 23G, and 23H are diagrams showing examples of electronic devices.

[0030] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it will be readily understood by those skilled in the art that various changes can be made in form and detail without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments shown below.

[0031] In the configuration of the invention described below, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings, and repeated explanations are omitted. Also, when similar functions are indicated, the same hatching pattern may be used and no particular reference numeral may be used. Furthermore, multiple layers that can be formed in the same process may be denoted by the same hatching pattern.

[0032] For ease of understanding, the position, size, range, etc. of each component shown in the drawings may not represent the actual position, size, range, etc. Therefore, the disclosed invention is not necessarily limited to the position, size, range, etc. disclosed in the drawings.

[0033] In this specification, ordinal numbers such as "first" and "second" are used to avoid confusion between components, and do not indicate any order or ranking, such as the order of processes, stacking order, or arrangement order. Furthermore, even if a term is not accompanied by an ordinal number in this specification, ordinal numbers may be accompanied in the claims to avoid confusion between components. Furthermore, even if a term is accompanied by an ordinal number in this specification, ordinal numbers may be accompanied by a different ordinal number in the claims. Furthermore, even if a term is accompanied by an ordinal number in this specification, ordinal numbers may be omitted in the claims.

[0034] It should be noted that the terms "film" and "layer" can be interchangeable in some cases or depending on the situation. For example, the term "conductive layer" can be changed to the term "conductive film." Or, for example, the term "insulating film" can be changed to the term "insulating layer."

[0035] Furthermore, the terms "electrode" and "wiring" used in this specification and the like do not limit the functionality of these components. For example, an "electrode" may be used as part of a "wiring," and vice versa. Furthermore, the terms "electrode" and "wiring" also include cases where multiple "electrodes" or "wirings" are integrally formed.

[0036] In this specification and the like, an oxynitride refers to a material having a composition in which oxygen is contained in a larger amount than nitrogen, and a nitride oxide refers to a material having a composition in which nitrogen is contained in a larger amount than oxygen.

[0037] In this specification, space groups are expressed using short notation in international notation (or Hermann-Mauguin notation). Crystal planes and crystal orientations are expressed using Miller indices. In crystallography, space groups, crystal planes, and crystal orientations are expressed by adding a superscript bar to the numbers. However, in this specification, due to formatting restrictions, numbers may be expressed by adding a minus sign (-) before them instead of adding a bar above them. Individual orientations indicating directions within a crystal are expressed with [ ], collective orientations indicating all equivalent orientations are expressed with < >, individual planes indicating crystal planes are expressed with ( ), and collective planes with equivalent symmetry are expressed with {}.

[0038] In this specification and the like, the term "island-like" refers to a state in which two or more layers made of the same material and formed in the same process are physically separated.

[0039] Furthermore, in this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10 degrees or more and 10 degrees or less. Therefore, it also includes cases in which the angle is -5 degrees or more and 5 degrees or less. Furthermore, "substantially parallel" refers to a state in which two straight lines are arranged at an angle of -20 degrees or more and 20 degrees or less. Furthermore, "perpendicular" refers to a state in which two straight lines are arranged at an angle of 80 degrees or more and 100 degrees or less. Therefore, it also includes cases in which the angle is 85 degrees or more and 95 degrees or less. Furthermore, "substantially perpendicular" refers to a state in which two straight lines are arranged at an angle of 70 degrees or more and 110 degrees or less.

[0040] In this specification and the like, a structure in which at least light-emitting layers are separately formed for light-emitting elements with different emission wavelengths is sometimes referred to as an SBS (Side By Side) structure. The SBS structure allows the materials and configuration to be optimized for each light-emitting element, increasing the degree of freedom in selecting materials and configurations and facilitating improvements in brightness and reliability.

[0041] In this specification and the like, a light-emitting element has an EL layer between a pair of electrodes. The EL layer has at least a light-emitting layer. Here, examples of layers (also referred to as functional layers) included in the EL layer include a light-emitting layer, a carrier injection layer (hole injection layer and electron injection layer), a carrier transport layer (hole transport layer and electron transport layer), and a carrier block layer (hole block layer and electron block layer). Note that the carrier injection layer, carrier transport layer, and carrier block layer may not be clearly distinguishable from each other depending on their cross-sectional shapes, characteristics, etc. In addition, one layer may have two or three functions of the carrier injection layer, carrier transport layer, and carrier block layer.

[0042] In this specification, a tapered shape refers to a shape in which at least a portion of the side surface of a structure is inclined relative to the substrate surface or the surface to be formed. For example, it is preferable to have a region in which the angle (also referred to as the taper angle) between the inclined side surface and the substrate surface or the surface to be formed is less than 90 degrees. Note that the side surface of the structure, the substrate surface, and the surface to be formed do not necessarily need to be completely flat, and may be approximately planar with a slight curvature or approximately planar with a slight unevenness.

[0043] In this specification, when the side surface of a layer has a tapered shape, the outermost part of the side surface of the layer is referred to as the edge of the layer unless otherwise specified. For example, when the bottom surface edge of a layer is located outward from the top surface edge, the bottom surface edge of the layer is simply referred to as the edge unless otherwise specified.

[0044] Furthermore, in this specification, terms indicating positions such as "upper," "lower," "left," and "right" are used for convenience in describing the positional relationship between components with reference to the drawings. Furthermore, the positional relationship between components changes as appropriate depending on the direction in which each component is depicted. Therefore, the terms are not limited to those described in the specification, and can be rephrased appropriately depending on the situation.

[0045] In this specification and the like, a metal oxide refers to an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as oxide semiconductors or simply as OS), and the like. For example, when a metal oxide is used for a semiconductor layer of a transistor, the metal oxide may be referred to as an oxide semiconductor. In other words, an OS transistor can be rephrased as a transistor including a metal oxide or an oxide semiconductor. Note that metal oxides containing nitrogen may also be collectively referred to as metal oxides. Furthermore, metal oxides containing nitrogen may also be referred to as metal oxynitrides.

[0046] Embodiment 1 In this embodiment, a display device or the like according to one embodiment of the present invention will be described with reference to drawings.

[0047] One embodiment of the present invention relates to a pixel having a light-emitting element. The pixel includes a plurality of transistors functioning as switches, for example, four transistors. The pixel also includes, for example, one driving transistor that controls a current flowing through the light-emitting element. The pixel has a function of correcting the threshold voltage of the driving transistor.

[0048] In this specification and the like, the threshold voltage of a transistor refers to the gate voltage (Vg) when a channel is formed in the transistor. Specifically, the threshold voltage of a transistor may refer to the gate voltage (Vg) at the intersection of a line obtained by extrapolating a tangent with a maximum slope in a curve (Vg-√Id characteristics) plotted with the gate voltage (Vg) on ​​the horizontal axis and the square root of the drain current (Id) on the vertical axis, and the line where the square root of the drain current (Id) is 0 (Id is 0 A). Alternatively, the threshold voltage of a transistor may refer to the value of Id [A] × L [μm] / W [μm], where L is the channel length and W is the channel width, of 1 × 10 −９ It may refer to the gate voltage (Vg) at which the voltage is [A].

[0049] In a display device according to one embodiment of the present invention, a transistor provided in a pixel is a vertical transistor. In this specification and the like, a vertical transistor refers to a transistor in which a drain current component flows along a direction perpendicular or substantially perpendicular to a reference plane. That is, in a vertical transistor, the drain current flows vertically. Note that a vertical transistor is also referred to as a vertical channel transistor, a vertical channel transistor, or a VFET (Vertical Field Effect Transistor). Here, the reference plane can be, for example, the top surface of a substrate or the top surface of a base insulating layer.

[0050] The vertical transistor has a lower electrode and an upper electrode. The upper electrode is located at a higher height from a reference plane than the lower electrode. An insulating layer functioning as a spacer is provided between the lower electrode and the upper electrode. An opening is provided in the spacer, reaching the lower electrode, and a semiconductor layer is provided so as to have a region located inside the opening. For example, the semiconductor layer is provided along the sidewall of the opening. In the semiconductor layer, the region along the sidewall of the opening can be used as a channel formation region of the transistor. Therefore, the channel length of the vertical transistor can be set by the film thickness of the spacer. Note that in the following description, the insulating layer functioning as a spacer may be simply referred to as a spacer, but the term "spacer" may also be interpreted as an insulating layer or an interlayer insulating layer.

[0051] In this specification and the like, the sidewall of an opening refers to the side surface inside the opening of the layer in which the opening is formed.

[0052] In a vertical transistor, one of the lower electrode and the upper electrode can be one of the source electrode and the drain electrode. The other of the lower electrode and the upper electrode can be the other of the source electrode and the drain electrode. Here, the vertical transistor can have multiple lower electrodes. In this case, the spacer can have multiple openings reaching the lower electrode, specifically, the same number as the number of lower electrodes. The semiconductor layer is provided so as to have regions located inside each of the multiple openings. In a vertical transistor configured as described above, one of the multiple lower electrodes can be used as a source electrode, and the other can be used as a drain electrode.

[0053] In vertical transistors, the channel length is not affected by the performance of the exposure equipment used to fabricate the transistors, so the channel length can be made shorter than the limit resolution of the exposure equipment. Therefore, the channel length of vertical transistors can be made shorter than that of planar transistors. Therefore, vertical transistors can have a larger on-state current than planar transistors. As described above, by using vertical transistors in pixels, a display device that operates faster than when planar transistors are used can be realized.

[0054] On the other hand, shortening the channel length of the transistor may result in a larger change in current in the saturation region in the Id-Vd characteristics. Therefore, shortening the channel length of the drive transistor may result in a change in the drain current based on a change in the source-drain voltage of the drive transistor. A potential corresponding to an image signal is supplied to the gate of the drive transistor. Therefore, if the drain current changes based on a change in the source-drain voltage of the drive transistor, the light-emitting brightness of the light-emitting element becomes unstable. For these reasons, it is preferable to make the channel length of the drive transistor longer than the channel length of the transistor functioning as a switch. This allows the drive transistor to be a transistor with a small change in current in the saturation region in the Id-Vd characteristics. Therefore, a display device with high display quality can be realized.

[0055] In this specification, a small change in current (small slope) in the saturation region in the Id-Vd characteristics of a transistor is referred to as "high saturation." On the other hand, a large change in current (large slope) in the saturation region in the Id-Vd characteristics of a transistor is referred to as "low saturation."

[0056] In a display device according to one embodiment of the present invention, vertical transistors included in a pixel are stacked. Specifically, some of the vertical transistors included in a pixel are provided in a lower layer, and the remaining transistors are provided in an upper layer. For example, a driving transistor is provided in the lower layer.

[0057] The driving transistor is provided so as to have a region located inside each of the plurality of openings. Specifically, the driving transistor is provided in the pixel so that the semiconductor layer, gate insulating layer, and gate electrode of the driving transistor have a region located inside each of the plurality of openings. This allows the channel length to be longer than when the driving transistor is provided so as to have a region located inside a single opening. This increases the saturation of the driving transistor. This therefore improves the display quality of the display device.

[0058] The driving transistor may have a plurality of lower electrodes provided on the same formation surface. Thus, the driving transistor may have one of the plurality of lower electrodes as a source electrode and another as a drain electrode. For example, when the driving transistor has a first lower electrode and a second lower electrode, the first lower electrode may be one of the source electrode and the drain electrode, and the second lower electrode may be the other of the source electrode and the drain electrode.

[0059] On the other hand, the transistor functioning as a switch is provided so as to have a region located inside one of the openings, for example. This allows the on-current of the transistor functioning as a switch to be larger than the on-current of the drive transistor, thereby increasing the drive speed of the display device.

[0060] As mentioned above, the channel length of the vertical transistor can be set by the film thickness of the spacer. Therefore, by increasing the film thickness of the lower spacer, the channel length of the driving transistor can be increased. Therefore, the saturation of the driving transistor can be increased without increasing the area occupied by the pixel.

[0061] As described above, the drive transistor is provided so as to have an area located inside each of the plurality of openings. On the other hand, the transistor functioning as a switch is provided so as to have an area located inside, for example, one of the openings. As a result, the transistor functioning as a switch can occupy a smaller area than the drive transistor.

[0062] Therefore, in a display device according to one embodiment of the present invention, at least two transistors functioning as switches are provided in the upper row so as to have an overlapping region with the driving transistor. This allows the pixel to occupy a smaller area than when, for example, there is zero or one vertical transistor having an overlapping region with the driving transistor. Therefore, the resolution of the display device can be improved. The transistor having an overlapping region with the driving transistor can be used, for example, as a transistor for correcting the threshold voltage of the driving transistor. By correcting the threshold voltage of the driving transistor, the variation in the threshold voltage between pixels can be reduced. Therefore, display unevenness can be reduced.

[0063] As described above, in the display device according to one embodiment of the present invention, the threshold voltage of the driving transistor can be corrected and the area occupied by the pixel can be reduced. Therefore, according to one embodiment of the present invention, a display device with high display quality can be realized.

[0064] 1A is a circuit diagram illustrating a configuration example of a pixel PIX1, which is a pixel that can be included in a display device of one embodiment of the present invention. Note that the pixel PIX1 is also referred to as a subpixel. Pixels other than the pixel PIX1 may also be referred to as subpixels.

[0065] The pixel PIX1 includes a pixel circuit PIXC1 and a light-emitting element ED. The pixel circuit PIXC1 includes a transistor Tr1, a transistor Tr2, a transistor Tr3, a transistor Tr4, and a transistor Tr5. In other words, the pixel circuit PIXC1 is a 5Tr (transistor) 1C (capacitor) type pixel circuit.

[0066] In pixel PIX1, one of the source and drain of transistor Tr1 is connected to wiring PL1. The gate of transistor Tr1 is connected to one of the source and drain of transistor Tr2 and one of the source and drain of transistor Tr3. The other of the source and drain of transistor Tr2 is connected to wiring PL2.

[0067] One of the source and drain of the transistor Tr4 is connected to one electrode of the light-emitting element ED. The other electrode of the light-emitting element ED is connected to the wiring COM. Here, the one electrode of the light-emitting element ED is also called a pixel electrode. Furthermore, the wiring COM can be shared, for example, between all the pixels PIX1. Therefore, the other electrode of the light-emitting element ED can also be called a common electrode.

[0068] The other of the source and drain of transistor Tr1 is connected to the other of the source and drain of transistor Tr4. The other of the source and drain of transistor Tr4 is connected to one electrode of capacitor C1. The other of the source and drain of transistor Tr3 is connected to one of the source and drain of transistor Tr5. One of the source and drain of transistor Tr5 is connected to the other electrode of capacitor C1. The other of the source and drain of transistor Tr5 is connected to wiring SL.

[0069] The gates of the transistors Tr2 and Tr5 are connected to the wiring GL1, the gates of the transistors Tr3 and Tr4 are connected to the wiring GL2, and the gates of the transistors Tr4 and Tr5 are connected to the wiring GL3.

[0070] The transistor Tr1 functions as a drive transistor. The transistor Tr1 has a function of controlling the amount of current flowing through the light-emitting element ED. The transistor Tr1 can control the current flowing through the light-emitting element ED based on, for example, an image signal. Specifically, the transistor Tr1 has a function of flowing a current of a magnitude corresponding to the image signal through the light-emitting element ED. When the gate potential of the transistor Tr1 has a magnitude corresponding to the image signal, a current of a magnitude corresponding to the image signal flows through the light-emitting element ED.

[0071] The transistors Tr2 to Tr5 function as switches. The transistor Tr2 controls the conduction / non-conduction state between the wiring PL2 and the gate of the transistor Tr1 and between the source and the drain of the transistor Tr3 and the gate of the transistor Tr1, and between the source and the drain of the transistor Tr3 and the other electrode of the capacitor C1, based on the potential of the wiring GL2. The transistor Tr4 controls the conduction / non-conduction state between the source and the drain of the transistor Tr1 and between one electrode of the capacitor C1 and one electrode of the light-emitting element ED and the other electrode of the capacitor C1, based on the potential of the wiring GL3. The transistor Tr5 has a function of controlling conduction and non-conduction between the wiring SL and the other of the source and drain of the transistor Tr3 and the other electrode of the capacitor C1 based on the potential of the wiring GL1.

[0072] In this specification, a "conductive state" refers to a state in which a current can flow between two input / output terminals, and a "non-conductive state" refers to a state in which the two input / output terminals are considered to be electrically disconnected. In addition, in this specification, the on state of a switch falls under the category of a "conductive state," and the off state of a switch falls under the category of a "non-conductive state." Therefore, in this specification, the "conductive state" and the "on state" of a switch are interchangeable, and the "non-conductive state" and the "off state" are interchangeable.

[0073] A power supply potential is supplied to the wiring PL1, the wiring PL2, and the wiring COM. For example, when one electrode of the light-emitting element ED functions as an anode and the other electrode of the light-emitting element ED functions as a cathode, the potential of the wiring PL1 is set higher than the potential of the wiring COM. The potential of the wiring PL2 can be set higher than the potential of the wiring COM and lower than the potential of the wiring PL1. As described above, when the transistor Tr4 is set to a conductive state, a current having a magnitude corresponding to an image signal flows from the wiring PL1 to the wiring COM.

[0074] As will be described in detail later, the pixel circuit PIXC1 includes, for example, transistors Tr2 to Tr4, which allows the threshold voltage of transistor Tr1 to be corrected. This reduces variations in the threshold voltage of transistor Tr1 for each pixel PIX1. This reduces display unevenness, thereby realizing a display device with high display quality. The pixel circuit PIXC1 can be said to have a correction circuit including transistors Tr2 to Tr4.

[0075] It is preferable to use OS transistors as the transistors Tr1 to Tr5. OS transistors have higher field-effect mobility than, for example, a transistor using amorphous silicon. Therefore, by using OS transistors as the transistors Tr1 to Tr5, the display device of one embodiment of the present invention can be driven at high speed.

[0076] Furthermore, the OS transistor has a significantly small source-drain leakage current (also referred to as off-state current) in an off state. Therefore, by using OS transistors as the transistors Tr2, Tr3, and Tr5, the charge accumulated in the capacitor C1 and the charge accumulated in the gate of the transistor Tr1 can be held for a long period of time. This allows image data written to the pixel PIX1 to be held for a long period of time, thereby reducing the frequency of a refresh operation (resupply of an image signal to the pixel PIX1). Therefore, the power consumption of the display device of one embodiment of the present invention can be reduced.

[0077] To increase the emission luminance of the light-emitting element ED, it is necessary to increase the amount of current flowing through the light-emitting element ED. To achieve this, it is necessary to increase the source-drain voltage of the transistor Tr1 connected to the wiring PL and the transistor T4 connected to one electrode of the light-emitting element ED. OS transistors have a higher source-drain breakdown voltage than transistors using silicon (also called Si transistors). Therefore, a high voltage can be applied between the source and drain of an OS transistor. Therefore, by using the transistors Tr1 and Tr4 as OS transistors, the amount of current flowing through the light-emitting element ED can be increased. Therefore, the emission luminance of the light-emitting element ED can be increased.

[0078] An OS transistor can reduce the change in source-drain current with respect to a change in gate-source voltage compared to a Si transistor. Therefore, by using an OS transistor as the transistor Tr1 functioning as a driving transistor, the current flowing between the source and drain can be precisely controlled by changing the gate-source voltage. This allows for precise control of the amount of current flowing through the light-emitting element ED. This allows for precise control of the luminance of light emitted by the pixel PIX1. This increases the number of gray levels that the pixel PIX1 can display.

[0079] 1A, all of the transistors Tr1 to Tr5 are n-channel transistors, but at least one of the transistors Tr1 to Tr5 may be a p-channel transistor in some cases, as well as other transistors described in this specification.

[0080] As the light-emitting element ED, for example, an OLED (organic light-emitting diode) or a QLED (quantum-dot light-emitting diode) is preferably used. Examples of the light-emitting material contained in the light-emitting element ED include a fluorescent material (fluorescent material), a phosphorescent material (phosphorescent material), a material that exhibits thermally activated delayed fluorescence (thermally activated delayed fluorescence: TADF material), and an inorganic compound (e.g., a quantum dot material). Furthermore, an LED such as a micro LED (light-emitting diode) can also be used as the light-emitting element ED.

[0081] 1B is a circuit diagram showing an example of the configuration of pixel PIX2. Pixel PIX2 has a pixel circuit PIXC2 and a light-emitting element ED. Below, differences in configuration from pixel PIX1 will be mainly described, and descriptions of similar configurations will be omitted as appropriate.

[0082] The pixel circuit PIXC2 includes a transistor Tr1, a transistor Tr2, a transistor Tr6, a transistor Tr7, and a capacitor C2, that is, the pixel circuit PIXC2 is a 4Tr1C type pixel circuit.

[0083] In pixel PIX2, the other of the source and drain of transistor Tr1 is connected to one of the source and drain of transistor Tr7, which is connected to one of the electrodes of capacitor C2, which is connected to one of the electrodes of light-emitting element ED.

[0084] The gate of transistor Tr1 is connected to one of the source and drain of transistor Tr2, which is connected to one of the source and drain of transistor Tr6, which is connected to the other electrode of capacitor C2.

[0085] The other of the source and drain of the transistor Tr6 is connected to a wiring SL. The other of the source and drain of the transistor Tr7 is connected to a wiring INIL. The gate of the transistor Tr6 is connected to a wiring GL4. The gate of the transistor Tr2 is connected to a wiring GL5. The gate of the transistor Tr7 is connected to a wiring GL6.

[0086] In the pixel circuit PIXC2, the transistors Tr2, Tr6, and Tr7 function as switches. The transistor Tr2 controls the conduction / non-conduction state between the wiring PL2 and the gate of the transistor Tr1, one of the source and drain of the transistor Tr6, and the other electrode of the capacitor C2, based on the potential of the wiring GL5. The transistor Tr6 controls the conduction / non-conduction state between the wiring SL and the gate of the transistor Tr1, one of the source and drain of the transistor Tr6, and the other electrode of the capacitor C2, based on the potential of the wiring GL4. The transistor Tr7 controls the conduction / non-conduction state between the wiring INIL and the other of the source and drain of the transistor Tr1, one electrode of the capacitor C2, and one electrode of the light-emitting element ED, based on the potential of the wiring GL6.

[0087] A power supply potential is supplied to the wiring INIL. For example, a potential for resetting the potential of one electrode of the light-emitting element ED is supplied to the wiring INIL.

[0088] Like the pixel circuit PIXC1, the pixel circuit PIXC2 can also correct the threshold voltage of the transistor Tr1 that functions as a drive transistor.

[0089] It is preferable to use an OS transistor as the transistor Tr7. As described above, an OS transistor has higher field-effect mobility than, for example, a transistor using amorphous silicon. Therefore, by using an OS transistor as the transistor Tr7, a display device can be driven at high speed.

[0090] Fig. 1C is a plan view showing an example of the configuration of the pixel circuit PIXC1 shown in Fig. 1A. Fig. 1C shows an example of the configuration of transistors Tr1 to Tr5 and capacitor C1. Figs. 2A and 2B are plan views showing some of the elements shown in Fig. 1C. Fig. 2A shows an example of the configuration of transistors Tr1, Tr4, and capacitor C1. Fig. 2B shows an example of the configuration of transistors Tr2, Tr3, and Tr5.

[0091] The following description of the configuration of the transistor Tr3 can also be applied to the transistor Tr6 included in the pixel circuit PIXC2 shown in FIG. 1B.

[0092] Figure 3 is a cross-sectional view taken along dashed line A1-A2 in Figures 1C, 2A, and 2B. Figure 3 shows an example configuration of the light-emitting element ED, as well as transistors Tr1 to Tr5 and capacitor C1. Note that some of the elements shown in Figure 3 are omitted in Figures 1C, 2A, and 2B, such as the insulating layer. Some of the components are also omitted in the subsequent plan views showing example configurations of the display device.

[0093] Fig. 4A is a cross-sectional view taken along dashed line A3-A4 shown in Fig. 1C, Fig. 2A, and Fig. 2B. Fig. 4A shows an example of the configuration of the capacitor C1 and the light-emitting element ED.

[0094] 1C to 3 show an example in which transistors Tr1 to Tr5, capacitor C1, light-emitting element ED, insulating layer 102, insulating layer 110, insulating layer 210, insulating layer 310, protective layer 305, and adhesive layer 303 are provided between substrate 101 and substrate 301. As shown in FIG. 3, insulating layer 102 is provided on substrate 101 and functions as a base insulating layer. In addition, insulating layer 102 can function as an interlayer insulating layer. Furthermore, insulating layer 110, insulating layer 210, and insulating layer 310 function as interlayer insulating layers.

[0095] The transistors Tr1 to Tr5, the capacitor C1, the insulating layer 110, and the insulating layer 210 are provided over the insulating layer 102. The insulating layer 210 is provided over the insulating layer 110. The insulating layer 310 is provided over the transistors Tr2, Tr3, and Tr5. The light-emitting element ED is provided over the insulating layer 310. The protective layer 305 is provided over the light-emitting element ED. Furthermore, the substrate 301 is attached to the protective layer 305 with an adhesive layer 303.

[0096] Transistor Tr1 includes conductive layers 111a, 111b, 112a, a semiconductor layer 113a, an insulating layer 105, and a conductive layer 115a. Transistor Tr2 includes conductive layers 115a, 212a, a semiconductor layer 213a, an insulating layer 205, and a conductive layer 215a. Transistor Tr3 includes conductive layers 115a, 212b, a semiconductor layer 213b, an insulating layer 205, and a conductive layer 215b. Transistor Tr4 includes conductive layers 111c, 112b, a semiconductor layer 113b, an insulating layer 105, and a conductive layer 115b. The transistor Tr5 includes a conductive layer 115c, a conductive layer 212c, a semiconductor layer 213c, an insulating layer 205, and a conductive layer 215a. The capacitor C1 includes a conductive layer 112c, a semiconductor layer 113c, an insulating layer 105, and a conductive layer 115c. Note that FIGS. 3 and 4A show an example in which the conductive layers 111a, 111b, 111c, 115a, 115b, and 115c have a three-layer stacked structure. Also, FIGS. 3 and 4A show an example in which the conductive layers 112a, 112b, 112c, 212a, 212b, 212c, 215a, and 215b have a two-layer stacked structure.

[0097] The light-emitting element ED includes a pixel electrode 311, a layer 313, and a common electrode 315. The layer 313 includes at least a light-emitting layer. The layer 313 can be called an EL layer. The common electrode is also called a counter electrode.

[0098] The conductive layer 111a functions as one of a source electrode and a drain electrode of the transistor Tr1, the conductive layer 111b functions as the other of the source electrode and the drain electrode of the transistor Tr1, and the conductive layer 111c functions as one of a source electrode and a drain electrode of the transistor Tr4.

[0099] The conductive layer 112a functions as a wiring for passing current from one of the conductive layers 111a and 111b to the other. The conductive layer 112b functions as the other of the source electrode and drain electrode of the transistor Tr4. The conductive layer 112c functions as one electrode of the capacitor C1.

[0100] The insulating layer 105 functions as a gate insulating layer for the transistor Tr1, a gate insulating layer for the transistor Tr4, and a dielectric layer for the capacitor C1. The conductive layer 115a functions as a gate electrode for the transistor Tr1, one of a source electrode and a drain electrode for the transistor Tr2, and one of a source electrode and a drain electrode for the transistor Tr3. The conductive layer 115b functions as a gate electrode for the transistor Tr4. The conductive layer 115c functions as the other electrode of the capacitor C1 and one of a source electrode and a drain electrode for the transistor Tr5.

[0101] The conductive layer 212a functions as the other of the source and drain electrodes of the transistor Tr2, the conductive layer 212b functions as the other of the source and drain electrodes of the transistor Tr3, and the conductive layer 212c functions as the other of the source and drain electrodes of the transistor Tr5.

[0102] The insulating layer 205 functions as a gate insulating layer for the transistor Tr2, the transistor Tr3, and the transistor Tr5. The conductive layer 215a functions as a gate electrode for the transistor Tr2 and the transistor Tr5. The conductive layer 215b functions as a gate electrode for the transistor Tr3.

[0103] At least a part of the conductive layer 111a functions as a wiring PL1. At least a part of the conductive layer 115b functions as a wiring GL3. At least a part of the conductive layer 212a functions as a wiring PL2. At least a part of the conductive layer 212c functions as a wiring SL. At least a part of the conductive layer 215a functions as a wiring GL1. At least a part of the conductive layer 215b functions as a wiring GL2.

[0104] The conductive layers 111a, 111b, and 111c are provided over the insulating layer 102 and are provided on the same formation surface. The conductive layers 111a, 111b, and 111c can be formed in the same process and made of the same material. The insulating layer 110 is provided over the conductive layers 111a, 111b, and 111c and the insulating layer 102.

[0105] The top surface of the insulating layer 102 is preferably flat. This allows layers over the insulating layer 102 to be provided on a flat surface. For example, the conductive layer 111a, the conductive layer 111b, and the conductive layer 111c can be provided on a flat surface.

[0106] The conductive layers 112a, 112b, and 112c are provided over the insulating layer 110 and are on the same formation surface. The conductive layers 112a, 112b, and 112c can be formed in the same process and can include the same material. The semiconductor layer 113a is provided over the conductive layers 111a, 111b, and 112a. The semiconductor layer 113b is provided over the conductive layers 111c and 112b. The semiconductor layer 113c is provided over the conductive layer 112c. The insulating layer 105 is provided over the semiconductor layers 113a, 113b, 113c, and the insulating layer 110. The conductive layers 115a, 115b, and 115c are provided over the insulating layer 105 and are on the same formation surface. The conductive layer 115a, the conductive layer 115b, and the conductive layer 115c can be formed in the same process and can be made of the same material.

[0107] The top surface of the insulating layer 110 is preferably flat. This allows layers over the insulating layer 110 to be provided on a flat surface. For example, the conductive layer 112a, the conductive layer 112b, and the conductive layer 112c can be provided on the flat surface.

[0108] The insulating layer 210 is provided over the conductive layer 115a, the conductive layer 115b, the conductive layer 115c, and the insulating layer 105. The conductive layer 212a, the conductive layer 212b, and the conductive layer 212c are provided over the insulating layer 210 and are provided on the same formation surface. The conductive layer 212a, the conductive layer 212b, and the conductive layer 212c can be formed in the same process and can be made of the same material.

[0109] The top surface of the insulating layer 210 is preferably flat. This allows the layers on the insulating layer 210 to be provided on a flat surface. For example, the conductive layer 212a, the conductive layer 212b, and the conductive layer 212c can be provided on the flat surface.

[0110] The semiconductor layer 213a is provided over the conductive layer 115a and the conductive layer 212a. The semiconductor layer 213b is provided over the conductive layer 115a and the conductive layer 212b. The semiconductor layer 213c is provided over the conductive layer 115c and the conductive layer 212c. The insulating layer 205 is provided over the semiconductor layer 213a, the semiconductor layer 213b, the semiconductor layer 213c, and the insulating layer 210. The conductive layer 215a and the conductive layer 215b are provided on the insulating layer 205 and are provided on the same formation surface. The conductive layer 215a and the conductive layer 215b can be formed in the same process and can be made of the same material.

[0111] The insulating layer 310 is provided over the conductive layer 215a, the conductive layer 215b, and the insulating layer 205. The pixel electrode 311 is provided over the insulating layer 310. The layer 313 is provided over the pixel electrode 311. The common electrode 315 is provided over the layer 313. The protective layer 305 is provided over the common electrode 315. The protective layer 305 has a function of, for example, suppressing oxidation of the common electrode 315. The protective layer 305 also has a function of, for example, suppressing impurities (such as moisture and oxygen) from entering the light-emitting element ED.

[0112] The upper surface of the insulating layer 310 is preferably flat, so that the layers on the insulating layer 310 can be provided on the flat surface. For example, the pixel electrode 311 can be provided on the flat surface.

[0113] The conductive layer 112a has a region overlapping with the conductive layer 111a with the insulating layer 110 interposed therebetween and a region overlapping with the conductive layer 111b. The conductive layer 112b has a region overlapping with the conductive layer 111c with the insulating layer 110 interposed therebetween. The conductive layer 212a has a region overlapping with the conductive layer 115a with the insulating layer 210 interposed therebetween. The conductive layer 212b has a region overlapping with the conductive layer 115a with the insulating layer 210 interposed therebetween and a region overlapping with the conductive layer 115c with the insulating layer 210 interposed therebetween. The conductive layer 212c has a region overlapping with the conductive layer 115b with the insulating layer 210 interposed therebetween and a region overlapping with the conductive layer 115c with the insulating layer 210 interposed therebetween.

[0114] The insulating layer 110 and the conductive layer 112a have an opening 121a_1 that reaches the conductive layer 111a and an opening 121a_2 that reaches the conductive layer 111b. The insulating layer 110 and the conductive layer 112b have an opening 121b that reaches the conductive layer 111c. The insulating layer 210 and the conductive layer 212a have an opening 221a that reaches the conductive layer 115a. The insulating layer 210 and the conductive layer 212b have an opening 221b that reaches the conductive layer 115a. The insulating layer 210 and the conductive layer 212c have an opening 221c that reaches the conductive layer 115c.

[0115] In this specification, when the same reference numeral is used for multiple elements, and particularly when it is necessary to distinguish between them, an identification symbol such as "_1", "[n]", "[m, n]" may be added to the reference numeral. Furthermore, when an identification symbol such as "_1", "[n]", "[m, n]" is added to a reference numeral in drawings or the like, the identification symbol may not be added if it is not necessary to distinguish between them in this specification. For example, opening 121a_1 and opening 121a_2 may be collectively referred to as opening 121a.

[0116] The opening 121a_1 and the opening 121a_2 include an opening in the insulating layer 110 and an opening in the conductive layer 112a. The opening 121b includes an opening in the insulating layer 110 and an opening in the conductive layer 112b. The opening 221a includes an opening in the insulating layer 210 and an opening in the conductive layer 212a. The opening 221b includes an opening in the insulating layer 210 and an opening in the conductive layer 212b. The opening 221c includes an opening in the insulating layer 210 and an opening in the conductive layer 212c.

[0117] The semiconductor layer 113a has a region in contact with the conductive layer 111a, a region in contact with the conductive layer 111b, and a region in contact with the conductive layer 112a. The semiconductor layer 113a has a region located inside the opening 121a_1 and a region located inside the opening 121a_2. The semiconductor layer 113a has a region along the side surface of the opening 121a_1 of the insulating layer 110 and a region along the side surface of the opening 121a_2. The semiconductor layer 113a can also have a region located over the conductive layer 112a.

[0118] The semiconductor layer 113b has a region in contact with the conductive layer 111c and a region in contact with the conductive layer 112b. The semiconductor layer 113b has a region located inside the opening 121b. The semiconductor layer 113b has a region along the side surface of the opening 121b in the insulating layer 110. The semiconductor layer 113b can also have a region located on the conductive layer 112b.

[0119] The semiconductor layer 213a has a region in contact with the conductive layer 115a and a region in contact with the conductive layer 212a. The semiconductor layer 213b has a region in contact with the conductive layer 115a and a region in contact with the conductive layer 212b. The semiconductor layer 213c has a region in contact with the conductive layer 115c and a region in contact with the conductive layer 212c. The semiconductor layer 213a can have a region located inside the opening 221a and a region located on the conductive layer 212a. Similarly, the semiconductor layer 213b can have a region located inside the opening 221b and a region located on the conductive layer 212b. Furthermore, the semiconductor layer 213c can have a region located inside the opening 221c and a region located on the conductive layer 212c. The semiconductor layer 213a has a region along the side surface of the opening 221a of the insulating layer 210. Similarly, the semiconductor layer 213b has a region along the side surface of the opening 221b of the insulating layer 210. The semiconductor layer 213c has a region along the side surface of the opening 221c of the insulating layer 210.

[0120] 1C to 4A show examples in which the end of the semiconductor layer 113a coincides or approximately coincides with the end of the conductive layer 112a, the end of the semiconductor layer 113b coincides or approximately coincides with the end of the conductive layer 112b, the end of the semiconductor layer 113c coincides or approximately coincides with the end of the conductive layer 112c, the end of the semiconductor layer 213a coincides or approximately coincides with the end of the conductive layer 212a, the end of the semiconductor layer 213b coincides or approximately coincides with the end of the conductive layer 212b, and the end of the semiconductor layer 213c coincides or approximately coincides with the end of the conductive layer 212c. In this case, for example, when the conductive layers 112a, 112b, 112c, and the semiconductor layers 113a, 113b, and 113c are formed by lithography, the conductive films that become the conductive layers 112a, 112b, and 112c can be processed using the same mask as that used to process the semiconductor films that become the semiconductor layers 113a, 113b, and 113c. Similarly, for example, when the conductive layers 212a, 212b, 212c, and the semiconductor layers 213a, 213b, and 213c are formed by lithography, the conductive films that become the conductive layers 212a, 212b, and 212c can be processed using the same mask as that used to process the semiconductor films that become the semiconductor layers 213a, 213b, and 213c. Therefore, the number of masks used in manufacturing a display device can be reduced, which is preferable compared to the case where the mask used in processing the conductive film and the mask used in processing the semiconductor film are different.

[0121] Note that "edges that are aligned or approximately aligned" can also be said to mean that the edges are aligned or approximately aligned. When the edges are aligned or approximately aligned, and when the shapes in plan view are aligned or approximately aligned, it can be said that at least a portion of the contours of the stacked layers overlap in plan view. For example, this includes cases where the upper and lower layers are processed using the same mask pattern or partially the same mask pattern. However, strictly speaking, the contours may not overlap, and the upper layer may be located inside the lower layer, or the upper layer may be located outside the lower layer. In these cases, it is also said that the edges are approximately aligned, or that the shapes in plan view are approximately aligned.

[0122] The insulating layer 105 is provided over the semiconductor layer 113a, the semiconductor layer 113b, the semiconductor layer 113c, and the insulating layer 110 so as to have a region located inside the opening 121a_1, a region located inside the opening 121a_2, and a region located inside the opening 121b. The insulating layer 205 is provided over the semiconductor layer 213a, the semiconductor layer 213b, the semiconductor layer 213c, and the insulating layer 210 so as to have a region located inside the opening 221a, a region located inside the opening 221b, and a region located inside the opening 221c.

[0123] The conductive layer 115a, the conductive layer 115b, and the conductive layer 115c are provided over the insulating layer 105 as described above. The conductive layer 115a is provided in the opening 121a_1 and the opening 121a_2 so as to have a region facing the semiconductor layer 113a with the insulating layer 105 sandwiched therebetween. The conductive layer 115b is provided in the opening 121b so as to have a region facing the semiconductor layer 113b with the insulating layer 105 sandwiched therebetween. The conductive layer 115c is provided so as to have a region overlapping with the conductive layer 112c and the semiconductor layer 113c. The conductive layer 115a can be provided so as to fill the opening 121a_1 and the opening 121a_2. The conductive layer 115b can be provided so as to fill the opening 121b.

[0124] The conductive layer 215a and the conductive layer 215b are provided on the insulating layer 205 as described above. The conductive layer 215a is provided so as to have a region facing the semiconductor layer 213a in the opening 221a with the insulating layer 205 therebetween, and a region facing the semiconductor layer 213c in the opening 221c with the insulating layer 205 therebetween. The conductive layer 215b is provided so as to have a region facing the semiconductor layer 213b in the opening 221b with the insulating layer 205 therebetween.

[0125] The gate electrodes of transistors Tr1 and Tr4 have regions located within openings formed in the insulating layer 110. The gate electrodes of transistors Tr2, Tr3, and Tr5 have regions located within openings formed in the insulating layer 210. The insulating layer 210 is provided on the insulating layer 110. Therefore, transistors Tr1 and Tr4 can be considered to be transistors provided in the lower tier. Transistors Tr2, Tr3, and Tr5 can be considered to be transistors provided in the upper tier. Note that one electrode of capacitor C1 uses a conductive layer provided on the same formation surface as the other of the source and drain electrodes of the transistors provided in the lower tier. Therefore, capacitor C1 can be considered to be provided in the lower tier. From the above, FIG. 2A is a plan view showing an example configuration of elements provided in the lower tier. Also, FIG. 2B is a plan view showing an example configuration of elements provided in the upper tier.

[0126] FIG. 5A is a perspective view showing an example of the configuration of a semiconductor device including a transistor 10A. FIG. 5B is a plan view showing an example of the configuration of a semiconductor device including a transistor 10A. In FIG. 5B, hatching patterns of some elements are omitted. FIG. 6A is a cross-sectional view taken along dashed line B1-B2 shown in FIG. 5B. FIG. 6B is a cross-sectional view taken along dashed line B3-B4 shown in FIG. 6A. FIG. 6B can also be considered a plan view. The transistor 10A can be applied to, for example, a transistor included in a pixel circuit PIXC1 and a transistor included in a pixel circuit PIXC2.

[0127] 6A, an insulating layer 12 functioning as a base insulating layer is provided on a substrate 11, and a transistor 10A is provided on the insulating layer 12. Note that the insulating layer 12 can also function as an interlayer insulating layer.

[0128] The transistor 10A includes a conductive layer 21 functioning as one of a source electrode and a drain electrode, a conductive layer 22 functioning as the other of the source electrode and the drain electrode, a semiconductor layer 23, an insulating layer 15 functioning as a gate insulating layer, and a conductive layer 25 functioning as a gate electrode. Note that the hatching pattern of the conductive layer 25 is omitted in FIG. 5B .

[0129] Furthermore, an insulating layer 20 is provided on the conductive layer 21 and on the insulating layer 12, and a conductive layer 22 is provided on the insulating layer 20. The conductive layer 22 has a region that overlaps with the conductive layer 21 via the insulating layer 20. The conductive layer 22 is provided at a position higher than the conductive layer 21 from the upper surface of the insulating layer 12. Therefore, the conductive layer 21 can be used as a lower electrode, and the conductive layer 22 can be used as an upper electrode.

[0130] The insulating layer 20 and the conductive layer 22 have an opening 31 that reaches the conductive layer 21. The opening 31 includes an opening 31_1 in the insulating layer 20 and an opening 31_2 in the conductive layer 22. Inside the opening 31, a semiconductor layer 23, an insulating layer 15 on the semiconductor layer 23, and a conductive layer 25 on the insulating layer 15 are provided. The semiconductor layer 23 has a region along the sidewall of the opening 31.

[0131] FIG. 5B shows an example in which the shape of the opening 31 in plan view is circular. By making the shape of the opening 31 circular in plan view, the processing accuracy when forming the opening 31 can be improved. Therefore, the opening 31 can be formed in a fine size. However, the present invention is not limited to this. In plan view, the opening 31 can be, for example, a circle or a substantially circle such as an ellipse, a polygon such as a triangle, a quadrangle (including a rectangle, a diamond, and a square), a pentagon, or a star-shaped polygon, or a polygon with rounded corners. Note that the circle is not limited to a perfect circle. Furthermore, the polygon may be either a concave polygon (a polygon with at least one interior angle exceeding 180 degrees) or a convex polygon (a polygon with all interior angles equal to or less than 180 degrees).

[0132] 6A shows an example in which the end of the opening 31_2 of the conductive layer 22 coincides with or substantially coincides with the end of the opening 31_1 of the insulating layer 20. It can also be said that the shape of the opening 31_2 in a plan view coincides with or substantially coincides with the shape of the opening 31_1 in a plan view.

[0133] 6A shows an example in which the conductive layer 21 has a three-layer structure including a conductive layer 21_1, a conductive layer 21_2 on the conductive layer 21_1, and a conductive layer 21_3 on the conductive layer 21_2. Also, FIG. 6A shows an example in which the conductive layer 22 has a two-layer structure including a conductive layer 22_1 and a conductive layer 22_2 on the conductive layer 22_1. Furthermore, FIG. 6A shows an example in which the conductive layer 25 has a two-layer structure including a conductive layer 25_1 and a conductive layer 25_2 on the conductive layer 25_1. The conductive layer 25_1 can be provided inside the opening 31 so as to extend along the side and top surfaces of the insulating layer 15. The conductive layer 25_2 can be provided so as to fill the opening 31.

[0134] In the semiconductor layer 23, a region in contact with the conductive layer 21 functions as one of the source region and the drain region of the transistor 10A. In addition, in the semiconductor layer 23, a region in contact with the conductive layer 22 functions as the other of the source region and the drain region of the transistor 10A. Furthermore, in the semiconductor layer 23, a region between the source region and the drain region functions as a channel formation region of the transistor 10A.

[0135] FIG. 6A shows an example in which a recess is provided in the conductive layer 21_3. The recess is provided to overlap the opening 31. By having the recess in the conductive layer 21, the height of the lower surface of the insulating layer 15 inside the opening 31 and the height of the lower surface of the conductive layer 25 can be made lower than the height of the upper surface of the conductive layer 21 that contacts the insulating layer 20, compared to when the recess is not provided. This prevents the formation of a so-called offset region, where a gate electric field is not applied, in a region other than the source and drain regions of the semiconductor layer 23. Furthermore, by having the recess in the conductive layer 21 that overlaps the opening 31, the contact area between the conductive layer 21 and the semiconductor layer 23 can be increased compared to when the recess is not provided. As a result, the on-current of the transistor 10A can be increased.

[0136] For example, a metal oxide can be used for the semiconductor layer 23. Indium oxide (also referred to as indium oxide) is preferably used as the metal oxide. This allows the transistor 10A to have a large on-state current. Furthermore, the transistor 10A can have a small off-state current. Note that indium oxide will be described in detail in Embodiment 2.

[0137] A metal oxide other than indium oxide may be used for the semiconductor layer 23. Examples of metal oxides other than indium oxide include oxides containing indium (In), gallium (Ga), and zinc (Zn) (also referred to as IGZO). By using IGZO for the semiconductor layer 23, the transistor 10A can have a low off-state current.

[0138] The thickness of the semiconductor layer 23 is preferably 1 nm or more and 50 nm or less, more preferably 2 nm or more and 30 nm or less, more preferably 2.5 nm or more and 20 nm or less, more preferably 5 nm or more and 20 nm or less, and even more preferably 5 nm or more and 10 nm or less. It is preferable that at least a portion of the semiconductor layer 23 has a region with the above-described thickness. For example, it is preferable that the channel formation region of the semiconductor layer 23 has a region with the above-described thickness. By setting the thickness of the semiconductor layer 23 within the above range, the crystallinity of the semiconductor layer 23 can be improved. By improving the crystallinity of the semiconductor layer 23, the semiconductor layer 23 can have crystal grains.

[0139] In the transistor 10A, a drain current flows from one of the conductive layer 21 and the conductive layer 22 to the other of the conductive layer 21 and the conductive layer 22. The drain current flows along the side surface of the opening 31_1 in the insulating layer 20. Therefore, in the transistor 10A, the drain current has a component that flows, for example, in a direction perpendicular or approximately perpendicular to the top surface of the insulating layer 12. Therefore, the transistor 10A is a vertical transistor.

[0140] The channel length of a transistor is the distance between the source region and the drain region. The channel length L of the transistor 10A can be the length of the region in the semiconductor layer 23 along the side surface of the opening 31_1 in the insulating layer 20. From the above, it can be said that the channel length L of the transistor 10A is determined by the thickness of the insulating layer 20 on the conductive layer 21. Therefore, the insulating layer 20 controls the distance between the source region and the drain region of the transistor 10A and functions as a spacer for controlling the channel length L of the transistor 10A. In FIG. 6A , the channel length L of the transistor 10A is indicated by a dashed double-headed arrow.

[0141] In the semiconductor layer 23, the length of at least a portion of the region of the conductive layer 22 along the side surface of the opening 31_2 may be included in the channel length L. For example, when a metal material such as tungsten is used for the conductive layer 22_1, the interface between the conductive layer 22_1 and the semiconductor layer 23 may be oxidized due to contact with the semiconductor layer 23. This may increase the contact resistance between the conductive layer 22_1 and the semiconductor layer 23. Therefore, in the semiconductor layer 23, the region of the conductive layer 22_1 along the side surface of the opening 31_2 may be used as a channel formation region. In this case, the sum of the length of the region of the semiconductor layer 23 along the side surface of the opening 31_1 of the insulating layer 20 and the length of the region of the conductive layer 22_1 along the side surface of the opening 31_2 may be defined as the channel length L. In the semiconductor layer 23, the length of at least a portion of the region of the semiconductor layer 23 along the side surface of the recess of the conductive layer 21 may be included in the channel length L.

[0142] The channel length of a planar transistor is limited by the exposure limit of photolithography, making further miniaturization difficult. However, the channel length L of the transistor 10A can be set by the film thickness of the insulating layer 20. Therefore, the channel length L of the transistor 10A can be made into a very fine structure that is equal to or less than the exposure limit of photolithography (e.g., 60 nm or less, 50 nm or less, 40 nm or less, 30 nm or less, 20 nm or less, or 10 nm or less, and 0.1 nm or more, 1 nm or more, or 5 nm or more). Therefore, the channel length of the transistor 10A can be made shorter than that of a planar transistor. As a result, the transistor 10A can have a larger on-state current than a planar transistor.

[0143] As described above, the transistor 10A can be suitably used as a transistor having a function as a switch, which allows a display device to be driven at higher speed than when a planar transistor is used as a transistor having a function as a switch.

[0144] Specifically, the transistor 10A can be suitably used as the transistors Tr2 to Tr5 shown in Figures 1A to 3. The transistor 10A can also be suitably used as the transistors Tr6 and Tr7 shown in Figure 1B.

[0145] When the transistor 10A is applied to the transistor Tr2, the conductive layer 21, the conductive layer 22, the opening 31, the semiconductor layer 23, the insulating layer 15, and the conductive layer 25 correspond to the conductive layer 115a, the conductive layer 212a, the opening 221a, the semiconductor layer 213a, the insulating layer 205, and the conductive layer 215a, respectively. When the transistor 10A is applied to the transistor Tr3, the conductive layer 21, the conductive layer 22, the opening 31, the semiconductor layer 23, the insulating layer 15, and the conductive layer 25 correspond to the conductive layer 115a, the conductive layer 212b, the opening 221b, the semiconductor layer 213b, the insulating layer 205, and the conductive layer 215b, respectively. When the transistor 10A is applied to the transistor Tr4, the conductive layer 21, the conductive layer 22, the opening 31, the semiconductor layer 23, the insulating layer 15, and the conductive layer 25 correspond to the conductive layer 111c, the conductive layer 112b, the opening 121b, the semiconductor layer 113b, the insulating layer 105, and the conductive layer 115b, respectively. When the transistor 10A is applied to the transistor Tr5, the conductive layer 21, the conductive layer 22, the opening 31, the semiconductor layer 23, the insulating layer 15, and the conductive layer 25 correspond to the conductive layer 115c, the conductive layer 212c, the opening 221c, the semiconductor layer 213c, the insulating layer 205, and the conductive layer 215a, respectively. Here, the substrate 11 corresponds to, for example, the substrate 101 shown in FIG. 3. The insulating layer 12 corresponds to, for example, the insulating layer 102 shown in FIG. 3. The insulating layer 20 corresponds to, for example, the insulating layer 110 and the insulating layer 210 shown in FIG. 3.

[0146] Note that the channel length L of the transistor 10A is determined by the thickness of the insulating layer 20 over the conductive layer 21, and therefore the channel length does not affect the area occupied by the transistor 10A, for example, the area of ​​the transistor 10A in a plan view. Setting the channel length L of the transistor 10A to, for example, 1 μm or less, 500 nm or less, or 300 nm or less can improve productivity, yield, and the like in forming the insulating layer 20, forming the opening 31_1 in the insulating layer 20, and the like.

[0147] The channel length L of the transistor 10A is preferably shorter than at least the channel width of the transistor 10A. The channel length L of the transistor 10A is preferably 0.1 to 0.99 times, more preferably 0.5 to 0.8 times, the channel width of the transistor 10A. With such a structure, a transistor with good electrical characteristics and high reliability can be realized.

[0148] 6B , a conductive layer 25_1 can be provided to cover the conductive layer 25_2, an insulating layer 15 can be provided to cover the conductive layer 25_1, and a semiconductor layer 23 can be provided to cover the insulating layer 15. For example, when the shape of the opening 31_1 is circular in a plan view, the conductive layer 25_2 can be provided at the center of the circle. Furthermore, the outer periphery of the conductive layer 25_1, the outer periphery of the insulating layer 15, and the outer periphery of the semiconductor layer 23 can be concentric with the center of the opening 31_1.

[0149] As a result, the side surface of the conductive layer 25 faces the side surface of the semiconductor layer 23 via the insulating layer 15. That is, inside the opening 31_1, the entire periphery of the semiconductor layer 23 becomes the channel formation region of the transistor 10A. In this case, for example, the channel width of the transistor 10A is determined by the length of the periphery of the semiconductor layer 23 inside the opening 31_1. In other words, it can be said that the channel width of the transistor 10A is determined by the width of the opening 31_1 (or the diameter if the shape of the opening 31_1 in a plan view is circular). In FIGS. 6A and 6B, the width D of the opening 31 is shown. In FIG. 6B, the channel width W of the transistor 10A is shown.

[0150] Increasing the width D of the opening 31 increases the channel width per unit area, thereby increasing the on-current. Meanwhile, the area occupied by the transistor 10A, for example, the area of ​​the transistor 10A in a plan view, is roughly determined by the width D of the opening 31. Reducing the width D of the opening 31 reduces the area occupied by the transistor 10A, thereby reducing the area occupied by the pixel. This allows for the realization of a high-definition display device.

[0151] The width D of the opening 31 may vary in the depth direction. Here, the shortest distance between the two side surfaces of the insulating layer 20 on the opening 31_1 side in a cross-sectional view is used as the width D. In other words, the minimum width of the opening 31_1 is used as the width D of the opening 31. Alternatively, the width of the opening 31_1 at the highest position in the insulating layer 20, the width of the opening 31_1 at the lowest position, the width of the opening 31_1 at a midpoint between these, or the average value of these three widths may be used as the width D. Here, an example is shown in which the width D is determined using the width of the opening 31_1, but the method for determining the width D is not particularly limited. For example, the shortest distance between the two side surfaces of the conductive layer 22 on the opening 31_2 side may be used as the width D. Alternatively, the width of the opening 31_2 at the highest position in the conductive layer 22, the width of the opening 31_2 at the lowest position, the width of the opening 31_2 at a midpoint between these, or the average value of these three widths may be used as the width D. When the opening 31 is circular in plan view, the width D of the opening 31 corresponds to the diameter of the opening 31. In this case, the channel width W can be calculated as, for example, "D×π".

[0152] 6A and 6B, when the film thickness of the semiconductor layer 23 is defined as thickness Tsc, the channel width W can also be calculated as, for example, "(D-Tsc) x π". Here, the width D can be the outer diameter of the semiconductor layer 23. Furthermore, "D-Tsc" can be the arithmetic mean of the outer diameter and the inner diameter of the semiconductor layer 23 in the cross section shown in FIG. 6B.

[0153] When the opening 31 is formed by photolithography, the width D of the opening 31 is limited by the exposure limit of the photolithography. The width D of the opening 31 is, for example, preferably 5 nm to 100 nm, more preferably 5 nm to 60 nm, still more preferably 10 nm to 50 nm, still more preferably 10 nm to 40 nm, and even more preferably 20 nm to 30 nm.

[0154] Fig. 7A is a plan view showing a configuration example of a semiconductor device including transistor 10B. In Fig. 7A, as in Fig. 5B, the hatching pattern of conductive layer 25 is omitted. Fig. 7B is a cross-sectional view taken along dashed dotted line B1-B2 shown in Fig. 7A. In the following, the configuration example of transistor 10B will be mainly described in terms of differences from transistor 10A, and descriptions of similar configurations will be omitted as appropriate.

[0155] The transistor 10B has a conductive layer 21a and a conductive layer 21b as lower electrodes. The conductive layer 21a and the conductive layer 21b are provided on the insulating layer 12 and are provided on the same surface where they are to be formed. As will be described in detail later, the conductive layer 21a functions as one of the source electrode and drain electrode of the transistor 10B. The conductive layer 21b functions as the other of the source electrode and drain electrode of the transistor 10B. Here, in the transistor 10B, the conductive layer 22 functions as, for example, a wiring.

[0156] The insulating layer 20 and the conductive layer 22 have an opening 31a that reaches the conductive layer 21a and an opening 31b that reaches the conductive layer 21b. The opening 31a includes an opening 31a_1 in the insulating layer 20 and an opening 31a_2 in the conductive layer 22. The opening 31b includes an opening 31b_1 in the insulating layer 20 and an opening 31b_2 in the conductive layer 22. A semiconductor layer 23, an insulating layer 15 on the semiconductor layer 23, and a conductive layer 25 on the insulating layer 15 are provided inside the opening 31a and inside the opening 31b. The semiconductor layer 23 has a region along the sidewall of the opening 31a and a region along the sidewall of the opening 31b.

[0157] The transistor 10B shown in Figures 7A and 7B is a transistor in which a semiconductor layer 23, an insulating layer 15, and a conductive layer 25 are provided so as to have regions located inside two openings provided in the insulating layer 20 and the conductive layer 22, respectively.

[0158] 7B shows an example in which the conductive layer 21a has a three-layer laminated structure of a conductive layer 21a_1, a conductive layer 21a_2 on the conductive layer 21a_1, and a conductive layer 21a_3 on the conductive layer 21a_2, similar to the conductive layer 21 shown in FIG. 6A. Also shown is an example in which the conductive layer 21b has a three-layer laminated structure of a conductive layer 21b_1, a conductive layer 21b_2 on the conductive layer 21b_1, and a conductive layer 21b_3 on the conductive layer 21b_2. Furthermore, FIG. 7B shows an example in which the conductive layers 21a and 21b have recesses, similar to the conductive layer 21 shown in FIG. 6A.

[0159] In the semiconductor layer 23 of the transistor 10B, a region in contact with the conductive layer 21a functions as one of the source region and drain region of the transistor 10B. In addition, in the semiconductor layer 23 of the transistor 10B, a region in contact with the conductive layer 21b functions as the other of the source region and drain region of the transistor 10B. In addition, in the semiconductor layer 23, a region along the side surface of the opening 31a_1 of the insulating layer 20 functions as a first channel formation region of the transistor 10B. In addition, in the semiconductor layer 23, a region along the side surface of the opening 31b_1 of the insulating layer 20 functions as a second channel formation region of the transistor 10B.

[0160] In the transistor 10B, a drain current flows from one of the conductive layers 21a and 21b to the other of the conductive layers 21a and 21b via the conductive layer 22. The drain current flows along the side surface of the opening 31a_1 in the insulating layer 20 and the side surface of the opening 31b_1. Thus, in the transistor 10B, the drain current has a component that flows, for example, in a direction perpendicular or substantially perpendicular to the top surface of the insulating layer 12. Therefore, not only the transistor 10A but also the transistor 10B is a vertical transistor.

[0161] The channel length of the transistor 10B can be the sum of the length L1 of the region along the side surface of the opening 31a_1 of the insulating layer 20 in the semiconductor layer 23 and the length L2 of the region along the side surface of the opening 31b_1. In FIG. 7B , the lengths L1 and L2 are indicated by dashed double-headed arrows. Note that in the semiconductor layer 23 of the transistor 10B, the region along the side surface of the opening 31a_2 of the conductive layer 22, the region along the side surface of the opening 31b_2 of the conductive layer 22, and the region along the top surface of the conductive layer 22 are not included in the channel formation region of the transistor 10B. That is, the region between the first channel formation region and the second channel formation region in the semiconductor layer 23 is not included in the channel formation region of the transistor 10B because a drain current can flow through the conductive layer 22. The conductive layer 22 functions as a wiring for flowing a drain current from one of the first channel formation region and the second channel formation region to the other of the first channel formation region and the second channel formation region.

[0162] The transistor 10B can have a longer channel length than the transistor 10A. For example, if the thickness of the insulating layer 20 in the region overlapping with the lower electrode is the same, the channel length of the transistor 10B is twice that of the transistor 10A. Note that three or more openings may be provided in the insulating layer 20 and the conductive layer 22, and the semiconductor layer 23, the insulating layer 15, and the conductive layer 25 of the transistor 10B may be provided so as to have regions located inside each of these openings. The channel length of the transistor 10B can be increased by increasing the number of openings provided in the insulating layer 20 and the conductive layer 22. Here, when three or more openings are provided, the transistor 10B can have three or more conductive layers functioning as lower electrodes, specifically, the same number as the openings. In this case, one of the three or more conductive layers functioning as lower electrodes can function as a source electrode, another as a drain electrode, and the remaining layers as wirings.

[0163] As described above, the shorter the channel length of a transistor, the larger the on-state current of the transistor. On the other hand, shortening the channel length of a transistor may reduce the saturation of the transistor. Therefore, shortening the channel length of a driving transistor may cause the drain current to change depending on a change in the source-drain voltage of the driving transistor. Because a potential corresponding to an image signal is supplied to the gate of the driving transistor, the change in the drain current may cause instability in the light-emitting element's emission luminance. For these reasons, it is preferable to make the channel length of the driving transistor longer than the channel length of the transistor functioning as a switch. This allows the driving transistor to have high saturation, thereby achieving a display device with high display quality. Note that, as described above, by using the transistor 10A as a transistor functioning as a switch, the on-state current of the transistor functioning as a switch can be larger than the on-state current of the driving transistor. As described above, one embodiment of the present invention can achieve a display device that can be driven at high speed and has high display quality.

[0164] For these reasons, the transistor 10B can be suitably used as the transistor Tr1 that functions as a driving transistor. By using the transistor 10B as the transistor Tr1, the transistor Tr1 can have high saturation properties, thereby realizing a display device with high display quality.

[0165] 7B , the insulating layer 20 corresponds to the insulating layer 110. In the example shown in FIG. ... conductive layer 21 a, the conductive layer 21 b, the conductive layer 22, the opening 31 a, the opening 31 b, the semiconductor layer 23, the insulating layer 15, and the conductive layer 25 correspond to the conductive layer 111 a, the conductive layer 111 b, the conductive layer 112 a, the opening 121 a_1, the opening 121 a_2, the semiconductor layer 113 a, the insulating layer 105, and the conductive layer 115 a, respectively.

[0166] As shown in FIG. 3 , the transistor Tr1 functioning as a driving transistor is provided in the lower stage. As described above, the channel length of a vertical transistor can be set by the film thickness of a spacer. In FIG. 3 , the thickness of the insulating layer 110 in a region that overlaps with the conductive layer 111a but does not overlap with the opening 121a_1 is indicated as thickness T1. Also, in FIG. 3 , the thickness of the insulating layer 210 in a region that overlaps with the conductive layer 115a but does not overlap with either the opening 221a or the opening 221b is indicated as thickness T2. The thickness of the insulating layer 110 in a region that overlaps with the conductive layer 111b and the region that overlaps with the conductive layer 111c can also be defined as thickness T1. The thickness of the insulating layer 210 in a region that overlaps with the conductive layer 115b and the region that overlaps with the conductive layer 115c can also be defined as thickness T2. If the upper surface of conductive layer 111a is not flat, the difference between the height of the upper surface of insulating layer 110 from the reference plane and the height of the upper surface of conductive layer 111a in the region in contact with semiconductor layer 113a from the reference plane can be defined as thickness T1. If the upper surface of conductive layer 115a is not flat, the difference between the height of the upper surface of insulating layer 210 from the reference plane and the height of the upper surface of conductive layer 115a in the region in contact with semiconductor layer 213a from the reference plane can be defined as thickness T2.

[0167] It is preferable that the thickness T1 is equal to or greater than the thickness T2. This allows the channel length of the transistor Tr1 to be at least twice as long as the channel lengths of the transistors Tr2, Tr3, and Tr5. Therefore, by setting the thickness T1 to be equal to or greater than the thickness T2, the saturation of the driving transistor can be increased without increasing the area occupied by the pixel. Specifically, the saturation of the transistor Tr1 can be increased without increasing the area occupied by the pixel PIX1 shown in FIG. 1A or the pixel PIX2 shown in FIG. 1B.

[0168] In the examples shown in FIGS. 1C to 3 , transistor Tr4 is provided in the lower stage, similar to transistor Tr1. Therefore, if thickness T1 is made thicker than thickness T2, the channel length of transistor Tr4 becomes longer than the channel lengths of transistors Tr2, Tr3, and Tr5. Therefore, the on-current of transistor Tr4 may become smaller than the on-currents of transistors Tr2, Tr3, and Tr5. However, the electrical characteristics of transistor Tr1 have a greater effect on the magnitude of the current flowing, for example, from wiring PL1 to wiring COM than the electrical characteristics of transistor Tr4. Therefore, even if the channel length of transistor Tr4 becomes longer, the current flowing between the drain and source of transistor Tr4 is less likely to become smaller. Specifically, the decrease in the drain-source current when the channel length of transistor Tr4 is increased is smaller than the decrease in the drain-source current when the channel length of transistor Tr2, transistor Tr3, or transistor Tr5 is increased. Therefore, even if the channel length of transistor Tr4 is increased, the effect on the drive speed of the display device is smaller than, for example, when the channel lengths of transistors Tr2, Tr3, and Tr5 are increased. Therefore, even if thickness T1 is increased, the effect on the drive speed of the display device is smaller than, for example, when thickness T2 is increased.

[0169] As described above, the transistor 10B applicable to the transistor Tr1 is provided so as to have regions located inside each of the multiple openings provided in the insulating layer 20 and the conductive layer 22. On the other hand, the transistor 10A applicable to a transistor functioning as a switch is provided so as to have a region located inside, for example, one opening 31. As described above, the transistor functioning as a switch can occupy a smaller area than the transistor Tr1 functioning as a drive transistor. For example, the transistors Tr2 to Tr5 can each occupy a smaller area than the transistor Tr1.

[0170] Therefore, in a display device according to one embodiment of the present invention, at least two transistors functioning as switches are provided in the upper row so as to have a region overlapping with the transistor Tr1. This can reduce the area occupied by a pixel compared to a case where, for example, there is no transistor or one transistor having a region overlapping with the transistor Tr1. Therefore, the resolution of the display device can be increased.

[0171] 1C and 3 show an example in which the transistors Tr2 and Tr3 have regions overlapping with the transistor Tr1. Specifically, an example is shown in which the opening 221a in which the transistor Tr2 is provided has a region overlapping with the opening 121a_1. Also, an example is shown in which the opening 221b in which the transistor Tr3 is provided has a region overlapping with the opening 121a_2. Note that the opening 221a may have a region overlapping with the opening 121a_2, and the opening 221b may have a region overlapping with the opening 121a_1. Furthermore, one or both of the openings 221a and 221b may have a region overlapping with the region between the openings 121a_1 and 121a_2.

[0172] Here, if the top surfaces of the conductive layers 115a, 115b, and 115c are flat, the thickness T2 can be easily controlled. Therefore, the channel lengths of the transistors Tr2, Tr3, and Tr5 can be easily controlled, which is preferable. For example, after forming conductive films to become the conductive layers 115a, 115b, and 115c, planarization treatment is performed on the conductive films, and then the conductive films are processed to form the conductive layers 115a, 115b, and 115c, each of which has a flat top surface. For example, chemical mechanical polishing (CMP) treatment can be used as the planarization treatment.

[0173] As shown in FIG. 4A , the insulating layer 110 has an opening 126a that reaches the conductive layer 111b and an opening 126b that reaches the conductive layer 111c. A conductive layer 136a is provided inside the opening 126a, and a conductive layer 136b is provided inside the opening 126b. The conductive layer 136a functions as a plug for connecting the conductive layer 111b to the conductive layer 112c. The conductive layer 136b functions as a plug for connecting the conductive layer 111c to the conductive layer 112c. As described above, the conductive layer 111b and the conductive layer 111c are connected via the conductive layer 136a, the conductive layer 112c, and the conductive layer 136b. The conductive layer 136a may have a region in contact with the upper surface of the conductive layer 111b and a region in contact with the lower surface of the conductive layer 112c, for example. The conductive layer 136b may have a region in contact with the upper surface of the conductive layer 111c and a region in contact with the lower surface of the conductive layer 112c, for example.

[0174] 3, the insulating layer 210 has an opening 226 that reaches the conductive layer 115c. A conductive layer 236 is provided inside the opening 226. The conductive layer 236 functions as a plug for connecting the conductive layer 115c and the conductive layer 212b. The conductive layer 236 may have a region in contact with the upper surface of the conductive layer 115c and a region in contact with the lower surface of the conductive layer 212b, for example.

[0175] The semiconductor layer 113b, the insulating layer 105, and the insulating layer 210 have an opening 125 that reaches the conductive layer 112b. A conductive layer 135 is provided inside the opening 125. A conductive layer 212d is provided over the conductive layer 135 and the insulating layer 210. A semiconductor layer 213d can be provided over the conductive layer 212d. An insulating layer 205 can be provided over the semiconductor layer 213d.

[0176] The conductive layer 135 functions as a plug for connecting the conductive layer 112b and the conductive layer 212d. For example, the conductive layer 135 may have a region in contact with the upper surface of the conductive layer 112b and a region in contact with the lower surface of the conductive layer 212d.

[0177] The conductive layer 212d can be formed in the same process and made of the same material as the conductive layers 212a, 212b, and 212c. The semiconductor layer 213d can be formed in the same process and made of the same material as the semiconductor layers 213a, 213b, and 213c. Edges of the semiconductor layer 213d can coincide or approximately coincide with edges of the conductive layer 212d.

[0178] The semiconductor layer 213d, the insulating layer 205, and the insulating layer 310 have an opening 225 that reaches the conductive layer 212d. A conductive layer 235 is provided inside the opening 225. The conductive layer 235 functions as a plug for connecting the conductive layer 212d to the pixel electrode 311. The conductive layer 235 may have a region in contact with the top surface of the conductive layer 212d, and may also have a region in contact with the bottom surface of the pixel electrode 311, for example. Note that the conductive layer 235 may be in contact with the top surface of the semiconductor layer 213d but may not be in contact with the top surface of the conductive layer 212d.

[0179] As described above, the conductive layer 112b and the conductive layer 212d are connected to each other via the conductive layer 135, and the conductive layer 212d and the pixel electrode 311 are connected to each other via the conductive layer 235. Therefore, the conductive layer 112b and the pixel electrode 311 are connected to each other via the conductive layer 135, the conductive layer 212d, and the conductive layer 235.

[0180] 1C to 2B show an example in which the planar shapes of openings 125, 126a, 126b, 225, and 226 are rectangular with rounded corners, but the planar shapes of the openings are not limited to this. The planar shapes of openings 125, 126a, 126b, 225, and 226 can be, for example, the shape of opening 31. The planar shapes of openings 126b, 225, and 226 can be, for example, circular.

[0181] 1C and 3 show an example in which opening 225 overlaps with opening 125, and opening 226 overlaps with opening 126a. This allows the area occupied by pixel circuit PIXC1 to be smaller than when opening 225 does not overlap with opening 125 and opening 226 does not overlap with opening 126a. Note that opening 225 does not have to overlap with opening 125, and opening 226 does not have to overlap with opening 126a. In this case, the degree of freedom in the layout of pixel circuit PIXC1 can be increased compared to when opening 225 overlaps with opening 125 and opening 226 overlaps with opening 126a.

[0182] 4B is a diagram showing an example in which the conductive layer 112c, the semiconductor layer 113c, the insulating layer 105, and the conductive layer 115c shown in FIG. 4A have a region located inside the opening 126a and a region located inside the opening 126b. Note that the display device shown in FIG. 4B may have a structure without the conductive layer 136a and the conductive layer 136b.

[0183] 4B includes a conductive layer 112c that is provided on the top surface of the insulating layer 110, as well as along the side surfaces of the openings 126a and 126b of the insulating layer 110. The conductive layer 112c may have a region in contact with the conductive layer 111b and a region in contact with the conductive layer 111c. This allows the conductive layer 111b and the conductive layer 111c to be connected to each other via the conductive layer 112c.

[0184] The insulating layer 105 is provided, for example, along the top surface and side surfaces of the semiconductor layer 113c so as to have a region located inside the opening 126a and a region located inside the opening 126b. The conductive layer 115c is provided on the insulating layer 105 so as to have a region located inside the opening 126a and a region located inside the opening 126b. The conductive layer 115c can be provided so as to fill the openings 126a and 126b. Specifically, the conductive layer 115c can be provided so as to fill the openings 126a and 126b inside the insulating layer 105.

[0185] As described above, the capacitor C1 shown in FIG. 4B is a trench-type MIM (Metal-Insulator-Metal) capacitor. The capacitor C1 shown in FIG. 4B has an MIM structure formed not only on the top surface of the conductive layer 112c but also along the side surfaces. Therefore, the capacitor C1 shown in FIG. 4B can have a larger capacitance value without increasing the occupied area, compared to the capacitor C1 shown in FIG. 4A. Meanwhile, the display device shown in FIG. 4B can have the conductive layer 112c, the semiconductor layer 113c, and the insulating layer 105 thicker relative to the occupied area of ​​the openings 121a_1 and 121a_2, compared to the display device shown in FIG. 4A. For example, the capacitor C1 shown in FIG. 4A is a parallel-plate capacitor.

[0186] In this specification, a trench-type capacitor refers to a capacitor in which one electrode, a dielectric layer, and the other electrode have a region located inside an opening in an interlayer insulating layer.

[0187] FIG. 4B shows an example in which the conductive layer 111b has a recess at a position overlapping the opening 126a. FIG. 4B also shows an example in which the conductive layer 111c has a recess at a position overlapping the opening 126b. The recess in the conductive layer 111b shown in FIG. 4B allows for a larger contact area between the conductive layer 111b and the conductive layer 112c compared to when the conductive layer 111b does not have a recess. This reduces the contact resistance between the conductive layer 111b and the conductive layer 112c. Similarly, the recess in the conductive layer 111c shown in FIG. 4B allows for a larger contact area between the conductive layer 111c and the conductive layer 112c compared to when the conductive layer 111c does not have a recess. This reduces the contact resistance between the conductive layer 111c and the conductive layer 112c. As a result, a display device that operates at high speed can be realized.

[0188] 3 does not include the conductive layer 112a, the semiconductor layer 113c, and the semiconductor layer 213d. Also, FIG. 8 shows an example in which the end of the semiconductor layer 113b does not coincide with the end of the conductive layer 112b, the end of the semiconductor layer 213a does not coincide with the end of the conductive layer 212a, the end of the semiconductor layer 213b does not coincide with the end of the conductive layer 212b, and the end of the semiconductor layer 213c does not coincide with the end of the conductive layer 212c. When manufacturing the display device having the configuration shown in FIG. 8, for example, a mask used for processing the semiconductor films that become the semiconductor layers 113a and 113b is different from a mask used for processing the conductive films that become the conductive layers 112b and 112c. Further, a mask used for processing the semiconductor film to be the semiconductor layer 213a, the semiconductor layer 213b, and the semiconductor layer 213c is different from a mask used for processing the conductive film to be the conductive layer 212a, the conductive layer 212b, and the conductive layer 212c.

[0189] 8, the transistor Tr1 does not include the conductive layer 112a. In this case, in the semiconductor layer 113a, not only the first region along the side surface of the opening 121a_1 of the insulating layer 110 and the second region along the side surface of the opening 121a_2, but also a third region between the first and second regions can be used as the channel formation region of the transistor Tr1. The third region of the semiconductor layer 113a includes a region provided along the top surface of the insulating layer 110.

[0190] FIG. 8 shows the length L1 of the first region, the length L2 of the second region, and the length L3 of the third region. The channel length of the transistor Tr1 shown in FIG. 8 can be the sum of the lengths L1, L2, and L3. The channel length of the transistor Tr1 shown in FIG. 8 can be increased by the length L3 compared to the channel length of the transistor Tr1 shown in FIG. 3. On the other hand, when the transistor Tr1 has the conductive layer 112a as shown in FIG. 3, the channel length of the transistor Tr1 can be made proportional to, for example, the thickness T1. Therefore, for example, by controlling the thickness T1, it becomes easier to control the channel length of the transistor Tr1. In other words, it becomes easier to set the channel length of the transistor Tr1 to a desired length.

[0191] 8 does not have a semiconductor layer 113c on a conductive layer 112c. By not providing the semiconductor layer 113c, which has a higher electrical resistance than the conductive layer 112c, between the conductive layer 112c and the insulating layer 105, which functions as a dielectric layer, charge can be stored in the capacitor C1 and released at high speed.

[0192] 8, the opening 125 does not need to be provided in the semiconductor layer 113b. This makes it easy to form the opening 125. Furthermore, in the display device shown in FIG. 8, the semiconductor layer 213d is not provided on the conductive layer 212d, so the opening 225 does not need to be provided in the semiconductor layer. This makes it easy to form the opening 225.

[0193] Although FIG. 8 illustrates an example in which the end of the semiconductor layer 113b is located inside the end of the conductive layer 112b, it may be located outside. When the end of the semiconductor layer 113b is located inside the end of the conductive layer 112b, the area occupied by the transistor Tr4 can be smaller than when it is located outside. On the other hand, when the end of the semiconductor layer 113b is located outside the end of the conductive layer 112b, the contact area between the semiconductor layer 113b and the conductive layer 112b can be larger than when it is located inside. Therefore, the contact resistance between the semiconductor layer 113b and the conductive layer 112b can be reduced. Similarly, FIG. 8 illustrates an example in which the end of the semiconductor layer 213a is located inside the end of the conductive layer 212a, but it may be located outside. Furthermore, FIG. 8 illustrates an example in which the end of the semiconductor layer 213b is located inside the end of the conductive layer 212b, but it may be located outside. Furthermore, although the end of the semiconductor layer 213c is located inside the end of the conductive layer 212c, it may be located outside.

[0194] Note that only a part of the configuration shown in Fig. 8 may be applied to the display device shown in Fig. 3. For example, the display device shown in Fig. 8 may be provided with a conductive layer 112a.

[0195] <Configuration Example of Semiconductor Device> Below, a configuration example of the transistor 10A different from that shown in FIG. 6A will be described. Note that descriptions of the same configuration as that shown in FIG. 6A and the like will be omitted as appropriate. The configuration of the transistor 10A described below can also be applied to the transistor 10B as appropriate.

[0196] 9A is a diagram showing an example in which the semiconductor layer 23 shown in FIG. 6A has a two-layer structure including a semiconductor layer 23_1 and a semiconductor layer 23_2 on the semiconductor layer 23_1. In this case, it is preferable to use a metal oxide (typically indium oxide) applicable to the semiconductor layer 23 as the semiconductor layer 23_1, and a metal oxide whose conduction band minimum is located closer to the vacuum level than the conduction band minimum of the semiconductor layer 23_1 as the semiconductor layer 23_2. In this case, the semiconductor layer 23_1 can mainly function as a current path (channel). That is, the semiconductor layer 23_1 has a channel formation region on the surface on the semiconductor layer 23_2 side and in the vicinity thereof.

[0197] The above-described structure can reduce carriers trapped at the interface of the semiconductor layer 23_1 and in the vicinity thereof. In addition, the channel can be located away from the surface of the insulating layer 15, reducing the influence of surface scattering. This can increase the field-effect mobility of the transistor.

[0198] Examples of metal oxides that can be used for the semiconductor layer 23_2 include indium gallium oxide (In—Ga oxide), In—Zn oxide, indium tin oxide (In—Sn oxide, also referred to as ITO), indium titanium oxide (In—Ti oxide), indium aluminum zinc oxide (In—Al—Zn oxide, also referred to as IAZO), In—Ga—Zn oxide, indium tin zinc oxide (In—Sn—Zn oxide), indium titanium zinc oxide (In—Ti—Zn oxide), and indium tin oxide containing silicon oxide (ITSO). Alternatively, zinc oxide, aluminum zinc oxide (Al—Zn oxide, also referred to as AZO), and aluminum tin oxide (Al—Sn oxide) can be used.

[0199] Specifically, the In—Zn oxide used in the semiconductor layer 23_2 can have a composition of In:Zn=1:1 (atomic ratio) or a composition thereabout, an In:Zn=2:1 (atomic ratio) or a composition thereabout, or an In:Zn=4:1 (atomic ratio) or a composition thereabout. Specifically, the IGZO used in the semiconductor layer 23_2 can have a composition of In:Ga:Zn=1:1:1 (atomic ratio) or a composition thereabout, an In:Ga:Zn=1:3:2 (atomic ratio) or a composition thereabout, or an In:Ga:Zn=1:3:4 (atomic ratio) or a composition thereabout. Note that a composition thereabout includes a range of ±30% of the desired atomic ratio.

[0200] The crystallinity of the metal oxide included in the semiconductor layer 23_2 is not particularly limited. For example, the semiconductor layer 23_2 may include one or more of an amorphous semiconductor (a semiconductor having an amorphous structure), a single-crystal semiconductor (a semiconductor having a single-crystal structure), or a semiconductor having crystallinity other than single crystal (a microcrystalline semiconductor, a polycrystalline semiconductor, or a semiconductor having a crystalline region in part).

[0201] FIG. 9B shows an example in which a semiconductor layer 23_3 is provided under the semiconductor layer 23_1 shown in FIG. 9A . In this case, the semiconductor layer 23 has a three-layer structure. The resistivity of the semiconductor layer 23_3 is preferably higher than that of the semiconductor layer 23_1. By providing the semiconductor layer 23_3 with high resistivity between the semiconductor layer 23_1 and the conductive layer 21 or the conductive layer 22, a negative shift in the threshold voltage or a decrease in on-current can be suppressed. Therefore, the threshold voltage of the transistor 10A is shifted positively, and the transistor 10A can be made normally off. As described above, the electrical characteristics of the transistor 10A can be improved, and the reliability of the transistor 10A can be improved.

[0202] The thickness of the semiconductor layer 23_3 is preferably thinner than the thickness of the semiconductor layer 23_1. Specifically, the semiconductor layer 23_3 preferably has a region with a thickness of 0.1 nm to 3 nm, more preferably has a region with a thickness of 0.1 nm to 2 nm. Alternatively, the semiconductor layer 23_3 more preferably has a region with a thickness of 0.5 nm to 3 nm, and even more preferably has a region with a thickness of 0.5 nm to 2 nm. With such a structure, the contact resistance between the semiconductor layer 23_1 and the conductive layer 21 or the conductive layer 22 can be prevented from increasing.

[0203] Specifically, the semiconductor layer 23_3 can be made of gallium oxide, zinc oxide, In—Ga oxide, gallium zinc oxide (Ga—Zn oxide, also referred to as GZO), Al—Zn oxide, In—Ga—Zn oxide, or the like.

[0204] When the semiconductor layer 23 has a stacked structure, the semiconductor layer 23 can also be formed using, for example, a sputtering method and an ALD method. For example, as shown in FIG. 9A , when the semiconductor layer 23 has a two-layer structure of a semiconductor layer 23_1 and a semiconductor layer 23_2, the semiconductor layer 23_1 can be formed by an ALD method, and the semiconductor layer 23_2 can be formed by a sputtering method. Because the ALD method is a film formation method with superior coverage compared to the sputtering method, forming the semiconductor layer 23_1 by the ALD method can improve the coverage of the semiconductor layer 23. Furthermore, damage to the underlayer (here, the conductive layer 21 or the conductive layer 22) can be reduced, the formation of a mixed layer at the interface between the underlayer and the semiconductor layer 23 can be suppressed, and crystallinity can be improved. Furthermore, forming the semiconductor layer 23_2 by a sputtering method can improve productivity.

[0205] Alternatively, the semiconductor layer 23_1 may be formed by sputtering, and the semiconductor layer 23_2 may be formed by ALD. Even if pinholes or discontinuities are formed in the semiconductor layer 23_1 formed by sputtering, the portions overlapping the pinholes or discontinuities can be filled with the semiconductor layer 23_2 formed by ALD, which has good coverage.

[0206] 10 shows an example in which the ratio of the film thickness of the semiconductor layer 23 at the top surface of the conductive layer 22 or 21 (hereinafter referred to as the "first film thickness") to the film thickness of the portion of the semiconductor layer 23 at the sidewall of the opening 31 (hereinafter referred to as the "second film thickness") is different. For example, when a portion of the semiconductor layer 23 is formed by sputtering, the ratio of the first film thickness to the second film thickness of the semiconductor layer 23 may be different. For example, the ratio of the second film thickness to the first film thickness may be less than 1, less than 0.8, or less than 0.5. In particular, the closer the taper angle of the side surface of the insulating layer 20 in the opening 31 is to 90 degrees, the smaller the ratio of the second film thickness to the first film thickness of the semiconductor layer 23 tends to be. Note that the ratio of the film thickness of the portion of the conductive layer 22 (hereinafter referred to as the "top surface") at the sidewall or bottom of the opening 31 (hereinafter referred to as the "bottom surface") may be different. For example, the ratio of the film thickness of the portion where the sidewall or bottom of the opening 31 is the formation surface to the film thickness of the portion where the top surface of the conductive layer 22 is the formation surface may be less than 1, less than 0.8, or less than 0.5.

[0207] 11A is a diagram showing an example in which the insulating layer 20 has a three-layer structure including an insulating layer 20_1, an insulating layer 20_2 on the insulating layer 20_1, and an insulating layer 20_3 on the insulating layer 20_2. It is preferable to use barrier insulating layers against oxygen as the insulating layers 20_1 and 20_3. This can prevent the conductive layers 21 and 22 from being oxidized and thus prevent the resistance from increasing. It is preferable to use a material with a low dielectric constant as the insulating layer 20_2.

[0208] For example, it is preferable to use silicon nitride or aluminum oxide for the insulating layer 20_1 and the insulating layer 20_3, and to use silicon oxide for the insulating layer 20_2. Note that each of the insulating layer 20_1 and the insulating layer 20_3 may have a stacked structure of two or more layers.

[0209] 11B is a diagram showing an example in which, of the conductive layer 25_1 and the conductive layer 25_2, only the conductive layer 25_1 has a region located inside the opening 31. When the width of the opening 31 is small relative to the film thicknesses of the semiconductor layer 23, the insulating layer 15, and the conductive layer 25_1, the conductive layer 25 may have the configuration shown in FIG. 11B. On the other hand, when the width of the opening 31 is large relative to the film thicknesses of the semiconductor layer 23, the insulating layer 15, and the conductive layer 25_1, both the conductive layer 25_1 and the conductive layer 25_2 have a region located inside the opening 31, as shown in FIG. 6A, for example.

[0210] Fig. 12A is a diagram showing an example in which the side surface of the conductive layer 22 in the opening 31 has a tapered shape. Fig. 12B is a diagram showing an example in which the side surface of the conductive layer 22 and the side surface of the insulating layer 20 in the opening 31 each have a tapered shape.

[0211] By tapering the sidewalls of the opening 31, the coverage of the semiconductor layer 23, the insulating layer 15, etc. can be improved, and defects such as voids can be reduced. When the sidewalls of the opening 31 are tapered, for example, the taper angle (angle θ22) of the side surface of the conductive layer 22 in the opening 31 and the taper angle (angle θ20) of the side surface of the insulating layer 20 in the opening 31 are preferably 45 degrees or more and less than 90 degrees. Specifically, an angle of 80 degrees or more and less than 90 degrees is preferable, as this allows for miniaturization or high integration of the semiconductor device. Alternatively, an angle of 45 degrees or more and less than 80 degrees, or 50 degrees or more and less than 75 degrees is preferable, as this improves the coverage of the film formed in the opening 31.

[0212] Also, for example, it is preferable that angle θ22 is smaller than angle θ20. With such a configuration, the coverage of the semiconductor layer 23 and the like on the side surface of the conductive layer 22 in the opening 31 is improved, and defects such as voids can be reduced. Furthermore, when the insulating layer 20 has a laminated structure, the inclination of the side surface of each layer in the opening 31 may be different. Similarly, when the conductive layer 22 has a laminated structure, the inclination of the side surface of each layer in the opening 31 may be different.

[0213] Fig. 13A is a diagram showing an example of a semiconductor device including a transistor 10A, which includes an insulating layer 26, a conductive layer 27, and an insulating layer 28. Fig. 13B is a cross-sectional view taken along dashed dotted line B3-B4 shown in Fig. 13A. Fig. 13B can also be considered a plan view.

[0214] 13A , conductive layer 27 is located on insulating layer 20, and insulating layer 28 is located on conductive layer 27 and insulating layer 20. Furthermore, conductive layer 22_1 is located on insulating layer 28. An opening 31 reaching conductive layer 21 is provided in insulating layer 20, conductive layer 27, insulating layer 28, and conductive layer 22. Insulating layer 26 is located between insulating layer 20, conductive layer 27, insulating layer 28, and conductive layer 22 and semiconductor layer 23. Here, in the semiconductor device shown in FIGS. 13A and 13B , opening 31 provided in insulating layer 20, conductive layer 27, and insulating layer 28 is referred to as opening 31_1.

[0215] As shown in Figure 13A and other figures, the conductive layer 21 has a first recess and a second recess located outside the first recess. The first recess is deeper than the second recess. In other words, the bottom surface of the first recess is located lower (closer to the insulating layer 12) than the bottom surface of the second recess. Furthermore, the side surface of the second recess coincides or nearly coincides with the side surface of the insulating layer 20 in the opening 31, and the side surface of the first recess coincides or nearly coincides with the surface of the insulating layer 26 facing the semiconductor layer 23. Hereinafter, the first recess and the second recess may be collectively referred to as recesses.

[0216] 13A and other drawings, insulating layer 26 contacts the bottom surface and side surfaces of the second recess formed in conductive layer 21, and also contacts the side surfaces of insulating layer 20 and conductive layer 22 within opening 31. Semiconductor layer 23 contacts the bottom surface and side surfaces of the first recess formed in conductive layer 21, insulating layer 26, and the top surface of conductive layer 22. Insulating layer 15 is located inside semiconductor layer 23 within opening 31, and conductive layer 25 is located inside insulating layer 15 within opening 31.

[0217] 13A may have a structure in which the insulating layer 26 does not cover at least a part of the side surface of the conductive layer 22. In this case, the side surface of the conductive layer 22 that is not covered with the insulating layer 26 is in contact with the semiconductor layer 23. Therefore, the contact resistance between the semiconductor layer 23 and the conductive layer 22 can be reduced.

[0218] 13A shows an example in which the insulating layer 26 has a single-layer structure. However, the insulating layer 26 can have a laminated structure of two or more layers. For example, the insulating layer 26 can have a two-layer structure of a first insulating layer and a second insulating layer. The first insulating layer contacts the side surface of the insulating layer 20 in the opening 31, and the second insulating layer is located between the insulating layer 26 and the semiconductor layer 23.

[0219] The first insulating layer and the second insulating layer can be formed using the insulating materials described in the "Insulating Layer" section below. For example, the first insulating layer can be formed using a barrier insulating layer against hydrogen, and the second insulating layer can be formed using an insulating layer having a region containing excess oxygen. This structure can reduce oxygen vacancies and / or hydrogen in the semiconductor layer 23. Therefore, the electrical characteristics of the transistor can be improved, and the reliability of the transistor can be enhanced. For example, it is preferable to use silicon nitride as the first insulating layer and silicon oxide or silicon oxynitride as the second insulating layer.

[0220] The semiconductor layer 23 has a region that overlaps with the conductive layer 27 with the insulating layer 26 interposed therebetween and with the conductive layer 25 with the insulating layer 15 interposed therebetween. At least part of this region functions as a channel formation region of the transistor 10A shown in FIG. 13A .

[0221] In the transistor 10A shown in FIG. 13A, the conductive layer 25 functions as a first gate electrode, the insulating layer 15 functions as a first gate insulating layer, the conductive layer 27 functions as a second gate electrode, and the insulating layer 26 functions as a second gate insulating layer.

[0222] In the transistor 10A shown in FIG. 13A , one of the conductive layer 27 and the conductive layer 25 can be used as a gate electrode, and the other can be used as a back gate electrode. The transistor 10A shown in FIG. 13A may have a particularly preferable structure in which the conductive layer 25 is used as a gate electrode and the conductive layer 27 is used as a back gate electrode. By using the conductive layer 25, which has a wider region facing the semiconductor layer 23 than the conductive layer 27, as a gate electrode, the gate electric field is applied to the semiconductor layer 23 more efficiently, which may improve the electrical characteristics of the transistor. Note that when the conductive layer 25 functions as a gate electrode and the conductive layer 27 functions as a back gate electrode, the insulating layer 15 functions as a gate insulating layer, and the insulating layer 26 functions as a back gate insulating layer.

[0223] 13A includes a conductive layer that functions as a backgate electrode, and therefore the threshold voltage of the transistor 10A can be controlled by the potential applied to the conductive layer. Therefore, by controlling the threshold voltage, a normally-off transistor can be easily realized.

[0224] 13B , a conductive layer 25_1 can be provided to cover the conductive layer 25_2, an insulating layer 15 can be provided to cover the conductive layer 25_1, a semiconductor layer 23 can be provided to cover the insulating layer 15, and an insulating layer 26 can be provided to cover the semiconductor layer 23. For example, when the shape of the opening 31_1 is circular in a plan view, the conductive layer 25_2 can be provided at the center of the circle. Furthermore, the outer periphery of the conductive layer 25_1, the outer periphery of the insulating layer 15, the outer periphery of the semiconductor layer 23, and the outer periphery of the insulating layer 26 can be concentric with the center of the opening 31_1.

[0225] 13B, a conductive layer 27 is provided so as to surround the entire outer periphery of the insulating layer 26. As a result, the electric field of the conductive layer 27 can be applied to the entire cross section shown in FIG.

[0226] The conductive layer 27 can be made of a conductive material that can be used for the conductive layer 25 .

[0227] The insulating layer 28 functions as an interlayer insulating layer. The insulating layer 28 can be made of an insulating material that can be used for the insulating layer 20.

[0228] <Example of Pixel Driving Method> Fig. 14A is a timing chart showing an example of a method for driving the pixel PIX1 shown in Fig. 1A. Fig. 14A shows changes over time in the potentials of the wirings GL1, GL2, GL3, and SL. In the diagram showing the driving method, a high potential is indicated by "H" and a low potential is indicated by "L."

[0229] In this specification and the like, when potentials applied to the source and drain of a transistor are compared, the larger potential is referred to as a "high potential" and the smaller potential is referred to as a "low potential." For example, when different potentials are applied to the source and drain of a transistor, the larger potential is referred to as a "high potential" and the smaller potential is referred to as a "low potential." Furthermore, a "high potential" potential applied to the gate of a transistor refers to a potential that is equal to or greater than the threshold voltage and that causes the transistor to be in a conductive state.

[0230] 14A , the operation of pixel PIX1 in the periods P1, P2, and P3 will be mainly described. Here, FIGS. 14B, 15A, and 15B show the potentials of the wirings GL1, GL2, GL3, SL, PL1, PL2, and COM and the states of the transistors Tr1 to Tr5 in the periods P1, P2, and P3, respectively. Specifically, a conductive state is indicated by a circle, and a non-conductive state is indicated by an x.

[0231] 14B, 15A, and 15B, a node where the other of the source and drain of transistor Tr1, the other of the source and drain of transistor Tr4, and one electrode of capacitor C1 are connected is referred to as node A. Also, a node where the other of the source and drain of transistor Tr3, one of the source and drain of transistor Tr5, and the other electrode of capacitor C1 are connected is referred to as node B.

[0232] In the periods P1 to P3, the potential Vdata of the image signal is applied to the wiring SL. The potentials Vano, V0, and Vcat are applied to the wirings PL1, PL2, and COM, respectively. The potential V0 is preferably higher than the threshold voltage Vth of the transistor Tr1 and the sum of the threshold voltage Vthe of the light-emitting element ED and the potential Vcat, and lower than the sum of the threshold voltage Vth of the transistor Tr1 and the potential Vano.

[0233] In the period P1, an initialization operation is performed. In the period P1, the potentials of the wirings GL1 and GL2 are set to low, and the potential of the wiring GL3 is set to high. Therefore, as shown in FIG. 14B , the transistor Tr4 is turned on, and the transistors Tr2, Tr3, and Tr5 are turned off.

[0234] In this specification, the threshold voltage of a light-emitting element refers to the lower limit of the potential difference between the cathode and anode when the light-emitting element emits light. That is, when the voltage applied to the light-emitting element, i.e., the potential difference between the cathode and anode in the light-emitting element, is below the threshold voltage, the light-emitting element does not emit light. On the other hand, when the voltage applied to the light-emitting element is equal to or higher than the threshold voltage, the light-emitting element emits light. For this reason, the threshold voltage of a light-emitting element is also called the light-emission start voltage.

[0235] In the period P1, the potential at the node A can be initialized to a potential close to the threshold voltage Vthe of the light-emitting element ED.

[0236] During the period P2, the potential Vdata of the wiring SL and the threshold voltage Vth of the transistor Tr1 are acquired. During the period P2, the potential of the wiring GL1 is set to high, and the potentials of the wirings GL2 and GL3 are set to low. Therefore, as shown in FIG. 15A , the transistors Tr2 and Tr5 are turned on, and the transistors Tr3 and Tr4 are turned off. During the period P2, the potential of the wiring SL becomes the potential Vdata corresponding to the data d.

[0237] During period P2, the operation during period P1 applies potential V0 to the gate of transistor Tr1, causing transistor Tr1 to enter a conductive state. Therefore, the charge in capacitor C1 is released via transistor Tr1, and the potential at node A, which was at potential Vcat, begins to rise. Eventually, when the potential at node A reaches V0-Vth, the gate voltage of transistor Tr1 decreases to the threshold voltage Vth, causing transistor Tr1 to enter a non-conductive state. Furthermore, potential Vdata is applied to node B.

[0238] During the period P3, the light-emitting element ED emits light. During the period P3, the potential of the wiring GL1 is set to low, and the potentials of the wirings GL2 and GL3 are set to high. Therefore, as shown in FIG. 15B, the transistors Tr2 and Tr5 are turned off, and the transistors Tr3 and Tr4 are turned on. Note that when transitioning from the period P2 to the period P3, it is preferable to first switch the potential applied to the wiring GL1 to high or low, and then switch the potential applied to the wirings GL2 and GL3 from low to high. This can suppress a change in the potential at the node A due to the switching of the potential applied to the wiring GL1.

[0239] During the period P3, the potential Vdata is applied to the gate of the transistor Tr1 through the above operation, and the gate voltage Vgs of the transistor Tr1 becomes Vdata-V0+Vth. Therefore, the gate voltage Vgs of the transistor Tr1 can be set to a value obtained by adding the threshold voltage Vth.

[0240] Specifically, the current value supplied to the light emitting element ED is I ＯＬＥＤ Then, I ＯＬＥＤ =0.5β(Vgs-Vth) ２ Here, β is a parameter specific to the transistor, and specifically, β=(W / L)·μ ＦＥ where W is the channel width of the transistor, L is the channel length of the transistor, and μ ＦＥ Here, when the gate voltage Vgs=Vdata−V0+Vth is substituted, IＯＬＥＤ =0.5β(Vdata-V0) ２ It is expressed as:

[0241] That is, in the pixel PIX1 shown in FIG. 1A, the variation in the threshold voltage Vth of the transistor Tr1 for each pixel affects the current value I ＯＬＥＤ Furthermore, even if the threshold voltage Vth fluctuates due to deterioration of the transistor Tr1, the current I ＯＬＥＤ Therefore, pixel PIX1 can be said to be a pixel capable of correcting the threshold voltage of the drive transistor. By correcting the threshold voltage of the drive transistor, display unevenness can be reduced. Therefore, a display device with high display quality can be realized.

[0242] <Definition of Connection> In this specification, "connection" includes, for example, "electrical connection." When the term "electrical connection" is used to define the connection relationship between circuit elements as an object, "electrical connection" includes, for example, "direct connection" and "indirect connection." "A and B are directly connected" refers to a case where A and B are connected without a circuit element (e.g., a transistor or a switch; wiring is not considered a circuit element). On the other hand, "A and B are indirectly connected" refers to a case where A and B are connected via one or more circuit elements. A, B, and C, which will be described later, represent objects such as elements, circuits, wiring, electrodes, terminals, semiconductor layers, and conductive layers.

[0243] Here, when "A and B are indirectly connected," it refers to the following connection relationship, for example. That is, assuming that a circuit is operating, if there is a time during the operation of the circuit when electrical signal transmission or potential interaction occurs between A and B, such a circuit can be defined as an entity, with "A and B being indirectly connected." Even if there is a time during the operation of the circuit when electrical signal transmission or potential interaction does not occur between A and B, it can be defined as "A and B being indirectly connected" if there is a time during the operation of the circuit when electrical signal transmission or potential interaction occurs between A and B. Note that "A and B are indirectly connected" is a definition of the connection relationship between circuit elements as an entity. Therefore, for example, even when a power supply potential is not supplied to a circuit and the circuit is not operating, the circuit can be defined as "A and B being indirectly connected" (however, for example, this is limited to the case where electrical signal transmission or potential interaction occurs between A and B during the operation of the circuit when a power supply potential is supplied to the circuit and the circuit is operating).

[0244] Specific examples of "indirect connection" are shown below. First, an example of "A and B are indirectly connected" is when A and B are connected via the source and drain of one or more transistors, as shown in FIGS. 16A1 and 16A2. Another example of "A and B are indirectly connected" is when A and B are connected via one or more switches. When "A and B are indirectly connected," it is assumed that, assuming the circuit is operating, there is at least one time when one transistor between A and B is in an on state, a conductive state, or a state in which a current can flow. Note that "A and B are indirectly connected" also includes cases where one transistor between A and B is in an off state or a non-conductive state. When "A and B are indirectly connected," if multiple transistors are connected between A and B, it is assumed that, assuming the circuit is operating, each of the multiple transistors between A and B is in an on state, a conductive state, or a state in which a current can flow at least one time. In other words, when "A and B are indirectly connected," it is not necessary for all of the multiple transistors to be in an on state, a conductive state, or a state in which current can flow simultaneously. Therefore, when "A and B are indirectly connected," it also includes cases where the multiple transistors between A and B are in an off state or a non-conductive state at the same time or at different times. As another example, as shown in FIG. 16A3, when A and C are connected via the source and drain of transistor TrP and B and C are connected via the source and drain of transistor TrQ, it can be defined as "A and C are indirectly connected," "B and C are indirectly connected," or "A and B are indirectly connected." However, as will be described later, when a constant potential V is supplied to C from a power supply, GND, etc., it can be said that "A and C are indirectly connected" or "B and C are indirectly connected," but it cannot be said that "A and B are indirectly connected."

[0245] While we have provided examples of cases where an "indirect connection" can and cannot be established, we will now present another example of a case where an "indirect connection" cannot be established. Even if an electrical signal exchange or potential interaction occurs between A and B during the operation of the circuit, there are exceptional cases where it cannot be said that "A and B are indirectly connected." An example of such an exceptional case is when A and B are connected via an insulator. In other words, when A and B are connected via an insulator, it cannot be said that "A and B are indirectly connected." A specific example of a case where A and B are connected via an insulator is when a capacitive element is connected between A and B, as shown in FIG. 16A4. Another example of a case where A and B are connected via an insulator is when a gate insulating film of a transistor is interposed between A and B, as shown in FIG. 16A5. In this case, it cannot be said that "A (the gate of the transistor) and B (the source or drain of the transistor) are indirectly connected."

[0246] Another example of a case where it cannot be said that "A and B are indirectly connected" is a case where there is no timing when an electrical signal is exchanged or when potential interaction occurs between A and B. An example of this is when, as shown in Figures 16A6 and 16A7, multiple transistors are connected via their sources and drains to the path from A to B, and a constant potential V is supplied to a node between the transistors from a power supply, GND, or the like. In this case, it cannot be said that "A and B are indirectly connected," but it is possible to say that "A and V are indirectly connected" or "B and V are indirectly connected." In addition, in Figure 16A3, if A and C are connected via the source and drain of transistor TrP, and B and C are connected via the source and drain of transistor TrQ, and a constant potential V is supplied to C from a power supply or GND, etc., the connection relationship will be the same as in Figures 16A6 and 16A7, so it cannot be said that "A and B are indirectly connected," but it can be said that "A and C are indirectly connected," or "B and C are indirectly connected."

[0247] Although an example of "indirect connection" has been given above, as an example, the definition of "indirect connection" is included in the definition of "electrical connection," so if "A and B are indirectly connected," it can also be said that "A and B are electrically connected."

[0248] Next, specific examples of "direct connection" are shown. Examples of "A and B are directly connected" include cases where A and B are connected without any circuit element between them, as shown in FIGS. 16B1, 16B2, and 16B3. When A and B are connected to a power supply that supplies a constant potential V or GND without any circuit element between them, as shown in FIGS. 16B4 and 16B5, it can be said that "A and B are directly connected," "A and V are directly connected," or "B and V are directly connected." It can also be said that "A and B are directly connected," when A (or B) is connected to a constant potential V via the source and drain of a transistor, as shown in FIG. 16B6. Because A and V or B and V are connected via the source and drain of a transistor, they cannot be said to be directly connected, but rather that "A and V are indirectly connected" or "B and V are indirectly connected."

[0249] Although an example of "direct connection" has been given above, as an example, the definition of "direct connection" is included in the definition of "electrical connection," so when "A and B are directly connected," it can also be said that "A and B are electrically connected."

[0250] <Constituent Materials of Display Device> Materials that can be used in the display device of this embodiment will be described below. Note that unless otherwise specified, each layer that constitutes the display device of this embodiment may have a single-layer structure or a stacked-layer structure.

[0251] [Semiconductor Layer] For the semiconductor layer of the transistor according to one embodiment of the present invention (the semiconductor layer 23, the semiconductor layer 113a, the semiconductor layer 113b, the semiconductor layer 113c, the semiconductor layer 213a, the semiconductor layer 213b, the semiconductor layer 213c, the semiconductor layer 213d, etc.), for example, a metal oxide can be used. The metal oxide preferably has a band gap of 2 eV or more, preferably 2.5 eV or more, more preferably 3.0 eV or more.

[0252] It is preferable to use indium oxide as the semiconductor layer. Alternatively, a metal oxide other than indium oxide may be used as the semiconductor layer. In this case, for example, gallium oxide or zinc oxide can be used as the semiconductor layer. When a metal oxide other than indium oxide is used as the semiconductor layer, the metal oxide preferably contains one or more elements selected from indium, element M, and zinc. The element M is one or more elements selected from aluminum, gallium, silicon, yttrium, tin, copper, vanadium, chromium, manganese, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, calcium, strontium, barium, cobalt, and antimony. In particular, it is preferable that the element M is one or more elements selected from aluminum, gallium, yttrium, and tin.

[0253] As the metal oxide used for the semiconductor layer, IGZO can be used. Alternatively, an oxide containing indium, tin, and zinc (also referred to as ITZO (registered trademark)) can be used. Alternatively, an oxide containing indium, gallium, tin, and zinc can be used. Alternatively, an oxide containing indium (In), aluminum (Al), and zinc (Zn) (also referred to as IAZO) can be used. Alternatively, an oxide containing indium (In), aluminum (Al), gallium (Ga), and zinc (Zn) (also referred to as IAGZO) can be used.

[0254] Furthermore, the metal oxide containing indium and the element M preferably has a stacked structure of multiple oxide layers with different chemical compositions. For example, consider an oxide layer with a two-layer structure consisting of a first layer and a second layer located immediately above the first layer. The atomic ratio of the element M to the main component metal element in the metal oxide used for the first layer is preferably greater than the atomic ratio of the element M to the main component metal element in the metal oxide used for the second layer. Furthermore, the atomic ratio of the element M to In in the metal oxide used for the first layer is preferably greater than the atomic ratio of the element M to In in the metal oxide used for the second layer. This configuration can suppress the diffusion of impurities and oxygen from structures formed below the first layer into the second layer.

[0255] In addition, the atomic ratio of In to the element M in the metal oxide used for the second layer is preferably larger than the atomic ratio of In to the element M in the metal oxide used for the first layer. With this structure, an OS transistor having this structure can have large on-state current and high frequency characteristics.

[0256] Specifically, for example, the metal oxide used in the first layer may have a composition of In:M:Zn = 1:3:2 (atomic ratio) or a composition thereabout, In:M:Zn = 1:3:4 (atomic ratio) or a composition thereabout, or In:M:Zn = 1:1:0.5 (atomic ratio) or a composition thereabout. Furthermore, the metal oxide used in the second layer may have a composition of In:M:Zn = 1:1:1 (atomic ratio) or a composition thereabout, In:M:Zn = 1:1:1.2 (atomic ratio) or a composition thereabout, In:M:Zn = 1:1:2 (atomic ratio) or a composition thereabout, or In:M:Zn = 4:2:3 (atomic ratio) or a composition thereabout. Note that a composition thereabout includes a range of 0.70 to 1.3 times the desired atomic ratio. For example, when the desired atomic ratio is 4, the atomic ratio of the neighboring composition is 2.8 or more and 5.2 or less.

[0257] In order to reduce the off-state current of a transistor, it is preferable to use, for example, IGZO as the metal oxide used in the semiconductor layer. When the semiconductor layer contains IGZO, the amount of current flowing between the source and drain of the transistor when the gate-source voltage is 0 V is 1×10 per 1 μm of channel width at room temperature. −２０ A or less, 1 x 10 at 85°C −１８ A or less, or 1 x 10 at 125°C −１６ In this specification, the state in which the amount of current flowing between the source and drain when the gate-source voltage of a transistor is 0 V is extremely small is referred to as normally-off.

[0258] As described above, in a transistor containing IGZO in the semiconductor layer, when the gate-source voltage is lower than the threshold voltage, the amount of current flowing per 1 μm of channel width is 1×10 −１６ A or less, preferably 1 x 10 −１８ A or less, more preferably 1×10 −２０ In some cases, the amount of current flowing per 1 μm of channel width may be 1×10 −２０ A or less, more preferably 1×10 −２２ A or less, more preferably 1×10 −２４ In this specification, the operation of the transistor in this region may be referred to as an off state. In addition, the current flowing through the transistor at this time may be referred to as an off-state current.

[0259] The structure of a metal oxide can be divided into a single-crystal structure and other structures (non-single-crystal structures). Examples of non-single-crystal structures include a c-axis aligned crystalline (CAAC) structure, a polycrystalline (polycrystalline) structure, a nanocrystalline (nc) structure, a pseudo-amorphous (a-like) structure, and an amorphous structure. The structure of the metal oxide of one embodiment of the present invention is not particularly limited, and any of the above structures can be used. However, use of a crystalline metal oxide, typified by a CAAC structure, an nc structure, or the like, is preferable because it enables a highly reliable display device.

[0260] As described in the above embodiment, the metal oxide preferably contains at least indium. In particular, it is preferable that the metal oxide contains indium and zinc. In addition to these, it is preferable that the metal oxide contains element M. As element M, one or more elements selected from aluminum, gallium, silicon, yttrium, tin, copper, vanadium, chromium, manganese, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, calcium, strontium, barium, cobalt, and antimony can be used. In particular, element M is preferably one or more of aluminum, gallium, yttrium, and tin. Furthermore, element M more preferably contains one or both of aluminum, gallium, yttrium, and tin.

[0261] Specifically, for example, it is preferable to use indium oxide as the metal oxide. In particular, it is preferable to use crystalline indium oxide. Details of crystalline indium oxide will be described later. Furthermore, the metal oxide may be In—Ga—Zn oxide (indium-gallium-zinc oxide), Ga—Zn oxide, or gallium oxide.

[0262] The metal oxide may have an atomic ratio of In:Ga:Zn=1:3:4, 1:3:2, 1:1:0.5, 1:1:1, 4:2:3, or 3:1:2. The metal oxide may have an atomic ratio of In:Zn=4:1.

[0263] The metal oxide can be preferably formed by sputtering or ALD. When the metal oxide is formed by sputtering, a film with high crystallinity or high film density can be formed. Furthermore, when the metal oxide is formed by ALD, atoms can be deposited layer by layer, which has the advantages of enabling film formation with fewer defects such as pinholes, film formation with excellent coverage, and film formation at low temperatures. After the metal oxide is formed, it is preferable to perform an impurity removal treatment to remove impurities (typically, impurities such as water, hydrogen, carbon, and nitrogen) from the metal oxide film. Examples of impurity removal treatments include plasma treatment, microwave treatment, and heat treatment.

[0264] The semiconductor layer may be made of a semiconductor material other than a metal oxide, such as a semiconductor made of a single element or a compound semiconductor.

[0265] Examples of semiconductors made of elemental elements that can be used as semiconductor materials include silicon and germanium. Examples of silicon that can be used as semiconductor materials include single-crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon. Examples of polycrystalline silicon include low-temperature polysilicon (LTPS).

[0266] Compound semiconductors that can be used for the semiconductor material include silicon carbide, silicon germanium, gallium arsenide, indium phosphide, boron nitride, and boron arsenide. Boron nitride that can be used for the semiconductor layer preferably has an amorphous structure. Boron arsenide that can be used for the semiconductor layer preferably has a cubic crystal structure. Other examples of compound semiconductors include organic semiconductors and nitride semiconductors. The aforementioned oxide semiconductors are also a type of compound semiconductor. These semiconductor materials may contain impurities as dopants.

[0267] [Insulating Layer] It is preferable to use an inorganic insulating film for each of the insulating layers (insulating layer 12, insulating layer 15, insulating layer 20, insulating layer 26, insulating layer 28, insulating layer 102, insulating layer 105, insulating layer 110, insulating layer 205, insulating layer 210, insulating layer 310, etc.) of the display device. Examples of inorganic insulating films include an oxide insulating film, a nitride insulating film, an oxynitride insulating film, and a nitride oxide insulating film. Examples of oxide insulating films include a silicon oxide film, an aluminum oxide film, a magnesium oxide film, a gallium oxide film, a germanium oxide film, an yttrium oxide film, a zirconium oxide film, a lanthanum oxide film, a neodymium oxide film, a hafnium oxide film, a tantalum oxide film, a cerium oxide film, a gallium zinc oxide film, and a hafnium aluminate film. Examples of nitride insulating films include a silicon nitride film and an aluminum nitride film. Examples of the oxynitride insulating film include a silicon oxynitride film, an aluminum oxynitride film, a gallium oxynitride film, an yttrium oxynitride film, and a hafnium oxynitride film. Examples of the nitride oxide insulating film include a silicon nitride oxide film and an aluminum nitride oxide film. An insulating layer included in a display device may be an organic insulating film.

[0268] For example, as transistors become more miniaturized and highly integrated, problems such as leakage current may occur due to thinner gate insulating layers. Using a high-dielectric-constant (high-k) material for the gate insulating layer allows for lower voltage operation of the transistor while maintaining the physical film thickness. It also allows for thinner equivalent oxide thickness (EOT) of the gate insulating layer. On the other hand, using a material with a low dielectric constant for an insulating layer functioning as an interlayer insulating layer can reduce parasitic capacitance between wiring. Therefore, it is preferable to select materials according to the function of the insulating layer. Note that materials with a low dielectric constant also have high dielectric strength. Materials with a low dielectric constant can also be used for insulating layers functioning as base insulating layers.

[0269] Examples of materials with a high relative dielectric constant include aluminum oxide, gallium oxide, hafnium oxide, tantalum oxide, zirconium oxide, hafnium zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.

[0270] Examples of materials with a low dielectric constant include inorganic insulating materials such as silicon oxide, silicon oxynitride, and silicon nitride oxide, and resins such as polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, and acrylic resin. Other inorganic insulating materials with a low dielectric constant include silicon oxide containing fluorine, silicon oxide containing carbon, and silicon oxide containing carbon and nitrogen. Another example is silicon oxide having vacancies. These silicon oxides may contain nitrogen.

[0271] Furthermore, a material capable of exhibiting ferroelectricity may be used for the insulating layer of the display device. Examples of materials capable of exhibiting ferroelectricity include metal oxides such as hafnium oxide, zirconium oxide, and hafnium zirconium oxide. Examples of materials capable of exhibiting ferroelectricity include a material obtained by adding element J1 (here, element J1 is one or more selected from zirconium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) to hafnium oxide. Here, the ratio of the number of hafnium atoms to the number of element J1 atoms can be appropriately set; for example, the ratio of the number of hafnium atoms to the number of element J1 atoms can be set to 1:1 or close to that. Examples of materials capable of exhibiting ferroelectricity include a material obtained by adding element J2 (here, element J2 is one or more selected from hafnium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) to zirconium oxide. The ratio of the number of zirconium atoms to the number of atoms of element J2 can be set appropriately, for example, the ratio of the number of zirconium atoms to the number of atoms of element J2 can be set to 1:1 or close to that. Furthermore, as a material that can have ferroelectricity, lead titanate (PbTiO Ｘ Piezoelectric ceramics having a perovskite structure, such as barium strontium titanate (BST), strontium titanate, lead zirconate titanate (PZT), strontium bismuth tantalate (SBT), bismuth ferrite (BFO), or barium titanate, may also be used.

[0272] Furthermore, examples of materials that may exhibit ferroelectricity include metal nitrides containing element M1, element M2, and nitrogen. Here, element M1 is one or more elements selected from aluminum, gallium, indium, etc. Furthermore, element M2 is one or more elements selected from boron, scandium, yttrium, lanthanum, cerium, neodymium, europium, titanium, zirconium, hafnium, vanadium, niobium, tantalum, chromium, etc. The ratio of the number of atoms of element M1 to the number of atoms of element M2 can be appropriately set. Furthermore, metal oxides containing element M1 and nitrogen may exhibit ferroelectricity even without containing element M2. Furthermore, examples of materials that may exhibit ferroelectricity include materials in which element M3 is added to the above metal nitrides. Furthermore, element M3 is one or more elements selected from magnesium, calcium, strontium, zinc, cadmium, etc. Here, the ratio of the number of atoms of the element M1, the number of atoms of the element M2, and the number of atoms of the element M3 can be set appropriately.

[0273] Furthermore, materials that can have ferroelectricity include SrTaO ２ N and BaTaO ２ Perovskite-type oxynitrides such as N, GaFeO with κ-alumina structure ３ etc.

[0274] In the above description, metal oxides and metal nitrides are used as examples, but the present invention is not limited to these. For example, metal oxynitrides in which nitrogen is added to the aforementioned metal oxides, or metal oxynitrides in which oxygen is added to the aforementioned metal nitrides, may also be used.

[0275] Furthermore, as a material capable of exhibiting ferroelectricity, for example, a mixture or compound made of multiple materials selected from the materials listed above can be used. Alternatively, the insulating layer functioning as the dielectric of the capacitor can be a laminated structure made of multiple materials selected from the materials listed above. However, since the crystal structure (characteristics) of the materials listed above may change depending not only on the film formation conditions but also on various processes, in this specification, a material that exhibits ferroelectricity is referred to not only as a ferroelectric but also as a material capable of exhibiting ferroelectricity.

[0276] In this specification, a layer of a material that can have ferroelectricity may be referred to as a ferroelectric layer, a metal oxide film, or a metal nitride film. Also, in this specification, a device having such a ferroelectric layer, a metal oxide film, or a metal nitride film may be referred to as a ferroelectric device.

[0277] Ferroelectricity is believed to be exhibited by the displacement of oxygen or nitrogen in crystals contained in the ferroelectric layer due to an external electric field. Furthermore, it is believed that the exhibiting of ferroelectricity depends on the crystal structure of the crystals contained in the ferroelectric layer. Therefore, for an insulating layer to exhibit ferroelectricity, the insulating layer must contain crystals. In particular, an insulating layer containing crystals having an orthorhombic crystal structure is preferred because it exhibits ferroelectricity. The crystal structure of the crystals contained in the insulating layer may be one or more selected from the group consisting of tetragonal, orthorhombic, monoclinic, and hexagonal. The insulating layer may also have an amorphous structure. In this case, the insulating layer may have a composite structure having an amorphous structure and a crystalline structure.

[0278] Metal oxides containing either or both of hafnium and zirconium are also insulating materials that have the function of capturing or fixing hydrogen. Therefore, by using a metal oxide containing either or both of hafnium and zirconium in at least a part of a gate insulating layer, hydrogen contained in the metal oxide layer can be captured or fixed, thereby reducing the hydrogen concentration in the metal oxide layer. Furthermore, a transistor having such a gate insulating layer can function as a Ferroelectric Field Effect Transistor (FeFET).

[0279] Furthermore, adding a Group 3 element in the periodic table to an oxide containing one or both of hafnium and zirconium increases the oxygen vacancy concentration in the oxide, making it easier to form crystals with an orthorhombic crystal structure. This is preferable because it increases the proportion of crystals with an orthorhombic crystal structure and increases the remanent polarization. On the other hand, adding too much of the Group 3 element may reduce the crystallinity of the oxide, making it difficult to exhibit ferroelectricity. Therefore, the content of the Group 3 element in the oxide containing one or both of hafnium and zirconium is preferably 0.1 atomic% to 10 atomic%, more preferably 0.1 atomic% to 5 atomic%, and even more preferably 0.1 atomic% to 3 atomic%. Here, the content of the Group 3 element refers to the ratio of the number of atoms of the Group 3 element to the sum of the number of atoms of all metal elements contained in the layer. The Group 3 element is preferably one or more selected from scandium, lanthanum, and yttrium, and more preferably one or both of lanthanum and yttrium.

[0280] Furthermore, a transistor using a metal oxide can have stable electrical characteristics by being surrounded by an insulating layer that has a function of suppressing the permeation of impurities and oxygen. The insulating layer that has a function of suppressing the permeation of impurities and oxygen can be, for example, a single-layer or stacked insulating layer containing one or more elements selected from boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum. Specifically, the insulating layer that has a function of suppressing the permeation of impurities and oxygen can be made of a metal oxide such as aluminum oxide, magnesium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide; a nitride such as aluminum nitride or silicon nitride; or a nitride oxide such as silicon nitride oxide.

[0281] Specifically, examples of materials for the insulating layer that have the function of suppressing the permeation of impurities such as water and hydrogen, and oxygen, include metal oxides such as aluminum oxide, magnesium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, and oxides containing aluminum and hafnium (hafnium aluminate). Examples of nitrides include aluminum nitride, aluminum titanium nitride, silicon nitride oxide, and silicon nitride. Examples of nitride oxides include silicon nitride oxide. Examples of materials for the insulating layer that have the function of suppressing the permeation of oxygen include gallium oxide.

[0282] Furthermore, an insulating layer, such as a gate insulating layer, that is in contact with a metal oxide layer or that is provided near the metal oxide layer is preferably an insulating layer having a region containing excess oxygen. For example, when an insulating layer having a region containing excess oxygen is in contact with a metal oxide layer or is located near the metal oxide layer, oxygen vacancies in the metal oxide layer can be reduced. Examples of insulating materials that easily form a region containing excess oxygen include silicon oxide, silicon oxynitride, and silicon oxide having vacancies. Examples of insulating layers that easily form a region containing excess oxygen include a silicon oxide film, a silicon oxynitride film, and a silicon oxide film having vacancies.

[0283] An insulating layer in contact with a metal oxide layer or an insulating layer provided near the metal oxide layer is preferably a barrier insulating layer against hydrogen. When the insulating layer has a barrier property against hydrogen, it can suppress diffusion of hydrogen into the metal oxide layer. The barrier insulating layer against hydrogen can also be said to have a function of suppressing diffusion of hydrogen.

[0284] Examples of insulating materials having the function of capturing or fixing hydrogen include metal oxides such as oxides containing hafnium, oxides containing magnesium, oxides containing aluminum, oxides containing aluminum and hafnium (hafnium aluminate), hafnium silicate, etc. These metal oxides may further contain zirconium, such as oxides containing hafnium and zirconium (hafnium zirconium oxide).

[0285] An insulating layer having the function of capturing or fixing hydrogen preferably has an amorphous structure. In a metal oxide having an amorphous structure, some oxygen atoms have dangling bonds, which enhances the ability to capture or fix hydrogen. Therefore, when the insulating layer has an amorphous structure, the function of capturing or fixing hydrogen can be enhanced.

[0286] By making the insulating layer an amorphous structure, it is possible to suppress the formation of crystal grain boundaries. By suppressing the formation of crystal grain boundaries, it is possible to improve the flatness of the insulating layer. This makes it possible to uniformize the film thickness distribution of the insulating layer and reduce areas with extremely thin film thickness, thereby improving the breakdown voltage of the insulating layer. It is also possible to uniformize the film thickness distribution of a film provided on the insulating layer. Furthermore, by suppressing the formation of crystal grain boundaries in the insulating layer, it is possible to reduce leakage current caused by defect levels at the crystal grain boundaries. Therefore, the insulating layer can function as an insulating film with low leakage current.

[0287] The insulating layer may have a crystalline region and / or a grain boundary in a part thereof.

[0288] The ability to capture or fix a corresponding substance can also be said to have the property of making it difficult for the corresponding substance to diffuse. Therefore, the ability to capture or fix a corresponding substance can be rephrased as barrier properties.

[0289] Examples of materials for the barrier insulating layer against hydrogen include aluminum oxide, magnesium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium (hafnium aluminate), oxides containing hafnium and zirconium, silicon nitride, and silicon nitride oxide.

[0290] The inorganic insulating layers cited as insulating layers having the function of capturing or fixing hydrogen and insulating layers having the function of suppressing hydrogen diffusion also have barrier properties against oxygen. Examples of materials for the oxygen barrier insulating layer include oxides containing one or both of aluminum and hafnium, magnesium oxide, gallium zinc oxide, silicon nitride, and silicon nitride oxide. Examples of oxides containing one or both of aluminum and hafnium include aluminum oxide, hafnium oxide, oxides containing aluminum and hafnium (hafnium aluminate), and hafnium silicate.

[0291] [Conductive Layer] The conductive layers (conductive layer 21, conductive layer 21a, conductive layer 21b, conductive layer 22, conductive layer 25, conductive layer 27, conductive layer 111a, conductive layer 111b, conductive layer 111c, conductive layer 112a, conductive layer 112b, conductive layer 112c, conductive layer 115a, conductive layer 115b, conductive layer 115c, conductive layer 135, conductive layer 136a, conductive layer 136b, conductive layer 212a, conductive layer 212b, conductive layer 212c, conductive layer 212d, conductive layer 215a, conductive layer 215b, conductive layer 235, conductive layer For each of the metals (e.g., tantalum, chromium, copper, silver, gold, platinum, zinc, tantalum, nickel, titanium, iron, cobalt, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum), it is preferable to use a metal element selected from the group consisting of aluminum, chromium, copper, silver, gold, platinum, zinc, tantalum, nickel, titanium, iron, cobalt, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum, or an alloy containing the aforementioned metal elements, or an alloy combining the aforementioned metal elements. As an alloy containing the aforementioned metal elements, a nitride of the alloy or an oxide of the alloy may be used. For example, it is preferable to use tantalum nitride, titanium nitride, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, or an oxide containing lanthanum and nickel. Furthermore, a semiconductor with high electrical conductivity, typified by polycrystalline silicon containing an impurity element such as phosphorus, or a silicide such as nickel silicide may also be used.

[0292] In addition, conductive materials containing nitrogen, such as nitrides containing tantalum, nitrides containing titanium, nitrides containing molybdenum, nitrides containing tungsten, nitrides containing ruthenium, nitrides containing tantalum and aluminum, or nitrides containing titanium and aluminum; conductive materials containing oxygen, such as ruthenium oxide, oxides containing strontium and ruthenium, or oxides containing lanthanum and nickel; and materials containing metal elements, such as titanium, tantalum, or ruthenium, are preferred because they are conductive materials that are resistant to oxidation, have a function of suppressing oxygen diffusion, or maintain conductivity even after absorbing oxygen. Examples of conductive materials containing oxygen include indium oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide (ITO), indium tin oxide containing titanium oxide, indium tin oxide containing silicon (ITSO), In—Zn oxide, and indium zinc oxide containing tungsten oxide. In this specification and the like, a conductive film formed using a conductive material containing oxygen may be referred to as an oxide conductive film.

[0293] Conductive materials containing tungsten, copper, or aluminum as a main component are preferred because they have high conductivity.

[0294] A plurality of conductive layers formed from the above materials may be stacked. For example, a stacked structure may be formed by combining the above-mentioned material containing a metal element and a conductive material containing oxygen. A stacked structure may be formed by combining the above-mentioned material containing a metal element and a conductive material containing nitrogen. A stacked structure may be formed by combining the above-mentioned material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen.

[0295] When a metal oxide is used for the channel formation region of a transistor, the conductive layer that functions as a gate electrode preferably has a stacked structure that combines a material containing the metal element and a conductive material containing oxygen. In this case, the conductive material containing oxygen is preferably provided on the channel formation region side. By providing the conductive material containing oxygen on the channel formation region side, oxygen desorbed from the conductive material is easily supplied to the channel formation region.

[0296] 6A , materials that can be used for the conductive layer 21_1, the conductive layer 21_2, the conductive layer 21_3, the conductive layer 22_1, the conductive layer 22_2, the conductive layer 25_1, and the conductive layer 25_2 will be described below. Here, the conductive layer 21a_1 and the conductive layer 21b_1 shown in FIG. 7B can be made of a material that can be used for the conductive layer 21_1. Similarly, the conductive layer 21a_2 and the conductive layer 21b_2 shown in FIG. 7B can be made of a material that can be used for the conductive layer 21_2. Furthermore, the conductive layer 21a_3 and the conductive layer 21b_3 shown in FIG. 7B can be made of a material that can be used for the conductive layer 21_3.

[0297] The conductive layer 21_1 is preferably made of a conductive material that is resistant to oxidation or a conductive material that has a function of suppressing oxygen diffusion. For example, a conductive material containing nitrogen can be used for the conductive layer 21_1. Examples of conductive materials containing nitrogen include titanium nitride and tantalum nitride. For the conductive layer 21_2, a material having higher conductivity than the conductive layer 21_1, such as a metal material, can be used. Examples of metal materials include tungsten, copper, and aluminum. For the conductive layer 21_3, a conductive material containing oxygen can be used, such as a metal oxide having conductivity (also referred to as an oxide conductor). Examples of oxide conductors include ITO, ITSO, and In—Zn oxide.

[0298] A conductive material containing oxygen can maintain its conductivity even after absorbing oxygen. Therefore, when a metal oxide is used for the semiconductor layer 23, a decrease in the conductivity of the conductive layer 21 due to oxygen contained in the semiconductor layer 23 can be suppressed by using a conductive material containing oxygen for the conductive layer 21_3 in contact with the semiconductor layer 23. Furthermore, when a metal oxide is used for the semiconductor layer 23, an oxide conductor has lower contact resistance with the semiconductor layer 23 than tungsten, copper, aluminum, or the like. Therefore, by using an oxide conductor for the conductive layer 21_3, the contact resistance between the conductive layer 21 and the semiconductor layer 23 can be lowered compared to, for example, when the conductive layer 21_3 is not provided. As a result, for example, the transistor 10A can be a transistor with a large on-state current.

[0299] Furthermore, by using a conductive material that is resistant to oxidation or a conductive material that has a function of suppressing oxygen diffusion as the conductive layer 21_1, it is possible to suppress oxidation of the conductive layer 21 due to oxygen contained in the insulating layer 12 and a decrease in the conductivity of the conductive layer 21. Furthermore, by using a material that has higher conductivity than the conductive layer 21_1 as the conductive layer 21_2, it is possible to increase the conductivity of the conductive layer 21 compared to, for example, a case in which the conductive layer 21_2 is not provided.

[0300] The above-described material that can be used for the conductive layer 21 can be used not only for the conductive layer 111a, the conductive layer 111b, and the conductive layer 111c included in the display device of one embodiment of the present invention, but also for the conductive layer 115a, the conductive layer 115b, and the conductive layer 115c.

[0301] The conductive layer 22_1 is preferably made of a material having higher conductivity than the conductive layer 22_2. For example, a material that can be used for the conductive layer 21_2 can be used for the conductive layer 22_1. Furthermore, a conductive material containing oxygen is preferably used for the conductive layer 22_2, which has a contact area with the semiconductor layer 23 larger than that of the conductive layer 22_1. For example, a material that can be used for the conductive layer 21_3 can be used for the conductive layer 22_2.

[0302] Note that a conductive material containing oxygen may be used for the conductive layer 22_1, and a material having higher conductivity than the conductive layer 22_1 may be used for the conductive layer 22_2. In this case, an oxide conductor having a lower contact resistance with the semiconductor layer 23 than, for example, tungsten, copper, aluminum, or the like is used for the layer of the conductive layer 22 closest to the channel formation region of the semiconductor layer 23. Therefore, the current path between the source and the drain can be made shorter than when tungsten, copper, aluminum, or the like is used for the conductive layer 21_1.

[0303] It is preferable to use a conductive material that is resistant to oxidation or a conductive material that has a function of suppressing oxygen diffusion as the conductive layer 25_1, which can suppress the conductive layer 25 from being oxidized due to oxygen contained in the insulating layer 20, for example, and thereby suppress the conductivity of the conductive layer 25 from decreasing.

[0304] When a metal oxide is used for the semiconductor layer 23, the conductive layer 25_1 is preferably made of a conductive material containing oxygen and a metal element contained in the semiconductor layer 23. The conductive layer 25_1 is preferably made of a conductive material containing nitrogen. The conductive layer 25_1 may be made of one or more materials selected from ITO, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, In—Zn oxide, and ITSO. The conductive layer 25_1 may be made of indium gallium zinc oxide containing nitrogen. Using such a material may allow hydrogen contained in the semiconductor layer 23 to be captured. For example, hydrogen introduced from the insulating layer 20 may be captured.

[0305] The conductive layer 25_2 can be made of a material having higher conductivity than the conductive layer 25_1, such as a metal material. Examples of the metal material include tungsten, copper, and aluminum. By using a material having higher conductivity than the conductive layer 25_1 for the conductive layer 25_2, the conductivity of the conductive layer 25 can be increased compared to a case where the conductive layer 25_2 is not provided.

[0306] The above-described material that can be used for the conductive layer 25 can be used for the conductive layer 215a and the conductive layer 215b included in the display device of one embodiment of the present invention, for example.

[0307] [Pixel Electrode and Common Electrode] A material highly transparent to visible light can be used for one or both of the pixel electrode 311 and the common electrode 315. Alternatively, a material that reflects visible light can be used for one of the pixel electrode 311 and the common electrode 315, and a material highly transparent to visible light can be used for the other of the pixel electrode 311 and the common electrode 315. Materials that can be used for the pixel electrode 311 and the common electrode 315 include metals, alloys, electrically conductive compounds, and mixtures thereof. Specific examples of such materials include metals such as aluminum, magnesium, titanium, chromium, manganese, iron, cobalt, nickel, copper, gallium, zinc, indium, tin, molybdenum, tantalum, tungsten, palladium, gold, platinum, silver, yttrium, and neodymium, as well as alloys containing appropriate combinations of these metals. Examples of the material include indium tin oxide (In—Sn oxide, also referred to as ITO), In—Si—Sn oxide (also referred to as ITSO), indium zinc oxide (In—Zn oxide), and In—W—Zn oxide. Examples of the material include aluminum alloys (aluminum alloys) such as an alloy of aluminum, nickel, and lanthanum (Al—Ni—La), and silver alloys such as an alloy of silver and magnesium and an alloy of silver, palladium, and copper (Ag—Pd—Cu, also referred to as APC). Other examples of the material include elements belonging to Group 1 or Group 2 of the periodic table (e.g., lithium, cesium, calcium, and strontium), rare earth metals such as europium and ytterbium, and alloys containing appropriate combinations of these elements, as well as graphene.

[0308] [Protective Layer] The protective layer 305 may have a single layer structure or a stacked structure of two or more layers. The conductivity of the protective layer 305 does not matter. The protective layer 305 can be made of at least one of an insulating film, a semiconductor film, and a conductive film.

[0309] The protective layer 305 having an inorganic film can prevent the common electrode 315 from being oxidized and prevent impurities (such as moisture and oxygen) from entering the light-emitting element ED, thereby preventing deterioration of the light-emitting element ED and improving the reliability of the display device.

[0310] The protective layer 305 can be formed using an inorganic insulating film such as an insulating oxide film, an insulating nitride film, an oxynitride insulating film, or an insulating nitride oxide film. The protective layer 305 can be an insulating layer containing an inorganic material. The protective layer 305 can be formed using an inorganic insulating film such as an insulating oxide film, an insulating nitride film, an oxynitride insulating film, or an insulating nitride oxide film. The protective layer 305 can have a single-layer structure or a stacked-layer structure. Examples of oxide insulating films include a silicon oxide film, an aluminum oxide film, a magnesium oxide film, an indium gallium zinc oxide film, a gallium oxide film, a germanium oxide film, an yttrium oxide film, a zirconium oxide film, a lanthanum oxide film, a neodymium oxide film, a hafnium oxide film, and a tantalum oxide film. Examples of nitride insulating films include a silicon nitride film and an aluminum nitride film. Examples of oxynitride insulating films include a silicon oxynitride film and an aluminum oxynitride film. Examples of nitride oxide insulating films include a silicon nitride oxide film and an aluminum nitride oxide film. In particular, the protective layer 305 preferably includes a nitride insulating film or a nitride oxide insulating film, and more preferably includes a nitride insulating film.

[0311] The protective layer 305 may be an inorganic film containing In—Sn oxide (ITO), In—Zn oxide, Ga—Zn oxide, Al—Zn oxide, In—Ga—Zn oxide (IGZO), or the like. The inorganic film preferably has high resistance, specifically, preferably has higher resistance than the common electrode 315. The inorganic film may further contain nitrogen.

[0312] When light emitted from the light-emitting element ED is extracted through the protective layer 305, it is preferable that the protective layer 305 has high transparency to visible light. For example, ITO, IGZO, and aluminum oxide are preferable because they are inorganic materials that have high transparency to visible light.

[0313] For example, a stacked structure of an aluminum oxide film and a silicon nitride film on the aluminum oxide film, or a stacked structure of an aluminum oxide film and an IGZO film on the aluminum oxide film can be used for the protective layer 305. By using such a stacked structure, impurities (water, oxygen, etc.) can be prevented from entering the EL layer side.

[0314] The protective layer 305 may be made of an organic material. For example, the protective layer 305 may be made of an acrylic resin, a polyimide resin, an epoxy resin, an imide resin, a polyamide resin, a polyimideamide resin, a silicone resin, a siloxane resin, a benzocyclobutene-based resin, a phenolic resin, or a precursor of any of these resins. The protective layer 305 may also be made of an organic material such as polyvinyl alcohol (PVA), polyvinyl butyral, polyvinylpyrrolidone, polyethylene glycol, polyglycerin, pullulan, water-soluble cellulose, or an alcohol-soluble polyamide resin. The protective layer 305 may also contain both inorganic and organic materials.

[0315] The protective layer 305 may have a two-layer structure formed by using different film formation methods. Specifically, the first layer of the protective layer 305 may be formed by the ALD method, and the second layer of the protective layer 305 may be formed by the sputtering method.

[0316] [Adhesive Layer] The adhesive layer 303 can be made of various curable adhesives, such as a photo-curable adhesive (e.g., an ultraviolet-curable adhesive), a reactive curable adhesive, a thermosetting adhesive, or an anaerobic adhesive. Examples of such adhesives include epoxy resin, acrylic resin, silicone resin, phenolic resin, polyimide resin, imide resin, PVC (polyvinyl chloride) resin, PVB (polyvinyl butyral) resin, and EVA (ethylene vinyl acetate) resin. Materials with low moisture permeability, such as epoxy resin, are particularly preferred. Two-component resins may also be used. Alternatively, an adhesive sheet may be used, for example.

[0317] [Substrate] There are no significant limitations on the material of the substrate 11 and the substrate 101, but they must at least have heat resistance sufficient to withstand subsequent heat treatment. For example, a single crystal semiconductor substrate made of silicon or silicon carbide, a polycrystalline semiconductor substrate, a compound semiconductor substrate such as silicon germanium, an SOI substrate, a glass substrate, a quartz substrate, a sapphire substrate, a ceramic substrate, or an organic resin substrate may be used as the substrate 11 and the substrate 101. Furthermore, these substrates on which semiconductor elements are provided may also be used as the substrate 11 and the substrate 101. Furthermore, a printed circuit board may also be used as the substrate 11 and the substrate 101. The semiconductor substrate and the insulating substrate may have a circular or rectangular shape.

[0318] Flexible substrates may be used as the substrate 11 and the substrate 101, and, for example, transistors may be formed directly on the flexible substrate. In this case, the insulating layer 12 may not be provided on the substrate 11. Alternatively, the insulating layer 102 may not be provided on the substrate 101. Alternatively, a peeling layer may be provided between the substrate 11 or the substrate 101 and the transistors or the like. The peeling layer can be used to separate a display device, after a part or all of the display device is completed thereon, from the substrate and transfer it to another substrate. In this case, for example, the transistors can be transferred to a substrate with poor heat resistance or a flexible substrate.

[0319] The substrate 301 can be made of glass, quartz, ceramics, sapphire, resin, metal, alloy, semiconductor, or the like. A material that transmits light is used for the substrate on the side from which light from the light-emitting element ED is extracted. Furthermore, using a flexible material for the substrate 301 can increase the flexibility of the display device. A polarizing plate may also be used for the substrate 301. Furthermore, a lamination film or a base film may also be used for the substrate 301.

[0320] The substrate 301 can be made of polyester resin such as polyethylene terephthalate (PET) or polyethylene naphthalate (PEN), polyacrylonitrile resin, acrylic resin, polyimide resin, polymethyl methacrylate resin, polycarbonate (PC) resin, polyethersulfone (PES) resin, polyamide resin (nylon, aramid, or the like), polysiloxane resin, cycloolefin resin, polystyrene resin, polyamideimide resin, polyurethane resin, polyvinyl chloride resin, polyvinylidene chloride resin, polypropylene resin, polytetrafluoroethylene (PTFE) resin, ABS resin, cellulose nanofiber, or the like. The substrate 301 can also be made of glass having a thickness sufficient to provide flexibility.

[0321] When a film is used as a substrate, the film may absorb water, which may cause changes in shape, such as wrinkles, in the display device. Therefore, it is preferable to use a film with low water absorption for the substrate. For example, it is preferable to use a film with a water absorption rate of 1% or less, more preferably 0.1% or less, and even more preferably 0.01% or less.

[0322] Various optical members can be disposed on the outside of the substrate 301. Examples of optical members include a polarizing plate (e.g., a circular polarizing plate), a retardation plate, a light diffusion layer (e.g., a diffusion film), an anti-reflection layer, and a light-collecting film. In addition, a surface protection layer such as an anti-static film that suppresses the adhesion of dust, a water-repellent film that makes it difficult for dirt to adhere, a hard coat film that suppresses the occurrence of scratches during use, or an impact absorbing layer may be disposed on the outside of the substrate 301. For example, a glass layer or a silica layer (SiO ｘ The surface protection layer can be preferably formed of a material such as DLC (diamond-like carbon), aluminum oxide (AlO ｘ ), polyester-based materials, polycarbonate-based materials, etc. may be used for the surface protection layer. It is preferable to use a material with high transmittance to visible light for the surface protection layer. It is also preferable to use a material with high hardness for the surface protection layer.

[0323] When a circularly polarizing plate is superimposed on a display device, it is preferable to use a substrate with high optical isotropy as the substrate of the display device. A substrate with high optical isotropy can also be said to have small birefringence (small amount of birefringence).

[0324] The absolute value of the retardation (phase difference) of a substrate having high optical isotropy is preferably 30 nm or less, more preferably 20 nm or less, and even more preferably 10 nm or less.

[0325] Examples of films with high optical isotropy include triacetyl cellulose (TAC, also called cellulose triacetate) films, cycloolefin polymer (COP) films, cycloolefin copolymer (COC) films, and acrylic films.

[0326] The above is the description of materials that can be used for the display device of this embodiment mode.

[0327] This embodiment mode can be combined with other embodiment modes as appropriate. In addition, in this specification, when a plurality of configuration examples are shown in one embodiment mode, the configuration examples can be combined as appropriate.

[0328] Embodiment 2 In this embodiment, an indium oxide film that can be used for a semiconductor layer of a transistor included in a semiconductor device of one embodiment of the present invention will be described.

[0329] In this specification and the like, indium oxide having at least a crystalline portion or a crystalline region in a film is referred to as crystalline indium oxide (crystal IO) or crystalline indium oxide (crystalline IO). Examples of crystalline IO or crystalline IO include single-crystalline indium oxide, polycrystalline indium oxide, and microcrystalline indium oxide.

[0330] Indium oxide is a semiconductor material having physical properties that are completely different from those of oxide semiconductors such as In—Ga—Zn oxide (hereinafter also referred to as IGZO) and zinc oxide.

[0331] The carrier concentration dependence of the Hall mobility of indium oxide, silicon, and IGZO will be explained. FIG. 17A shows the carrier concentration dependence of the Hall mobility of silicon (Si) and indium oxide (InO Ｘ ) and FIG. 17B is a schematic diagram showing the carrier concentration dependence of the hole mobility for IGZO.

[0332] First, IGZO tends to exhibit higher hole mobility as the carrier concentration increases, as shown by the arrows in Figure 17B. On the other hand, indium oxide tends to exhibit higher hole mobility as the carrier concentration decreases, as shown by the arrows in Figure 17A (see Non-Patent Document 1). This trend is similar to that of silicon; the lower the dopant (impurity) concentration in the material, the less impurity scattering there is and the higher the hole mobility. In other words, the higher the purity and intrinsic indium oxide, the higher the hole mobility. From these results, it can be said that indium oxide, unlike IGZO, is a material with physical properties similar to those of silicon. Note that the characteristics of indium oxide shown in Figure 17A are assumed to be single crystal. Therefore, when indium oxide is non-single crystal (e.g., polycrystalline), the characteristics may differ from those shown in Figure 17A.

[0333] 17A, the range R1 of low carrier concentration has extremely high hole mobility, and therefore can be said to be a range of carrier concentration suitable for, for example, a channel formation region of a transistor. For example, in the case of indium oxide, the range R1 is a range where the carrier concentration value is 1×10 １５ cm −３ The range includes, for example, 1×10 １４ cm −３ That's it, 1 x 10 １８ cm −３ By sufficiently reducing the carrier concentration, the Hall mobility value can be increased to 270 cm ２ It is expected that the resistance can be increased to about / (V·s).

[0334] In addition, in indium oxide, the region where the carrier concentration is in the range R1 may contain an element that lowers the carrier concentration. Examples of elements that lower the carrier concentration include magnesium, calcium, zinc, cadmium, and copper. By substituting these elements for indium, the carrier concentration can be lowered. Examples of elements that lower the carrier concentration include nitrogen, phosphorus, arsenic, and antimony. For example, by substituting nitrogen, phosphorus, arsenic, or antimony for oxygen, the carrier concentration can be lowered.

[0335] On the other hand, the range R2 with a high carrier concentration has a low electrical resistance, and can be said to be a range of carrier concentrations suitable for, for example, the source and drain regions of a transistor, a resistor, or a transparent conductive film. ２０ cm −３ The range includes, for example, 1×10 １９ cm −３ That's it, 1 x 10 ２２ cm −３ By increasing the carrier concentration sufficiently, the resistivity can be reduced to 1×10 −４ It is expected that the resistivity can be reduced to Ω·cm or less.

[0336] In the indium oxide, the region having a carrier concentration in the range R2 may contain an element that increases the carrier concentration. For example, it is preferable that the indium oxide contains an element that is common to the source electrode and the drain electrode of the transistor. Examples of elements that increase the carrier concentration include titanium, zirconium, hafnium, tantalum, tungsten, molybdenum, tin, silicon, and boron. In particular, it is more preferable to use an element whose oxide has conductive or semiconductive properties.

[0337] In this way, indium oxide uses a region with a low carrier concentration as the channel formation region of a transistor, and a region with a high carrier concentration as the source and drain regions of the transistor. In other words, indium oxide can be said to be an oxide capable of valence electron control. Note that IGZO may experience strain in the source and drain regions due to stress from electrodes in contact with the IGZO, resulting in the formation of n-type regions. On the other hand, unlike IGZO, indium oxide is capable of valence electron control, and therefore does not require strain to be formed in the film as with IGZO. Less strain in the film is expected to improve reliability. For example, by separately creating a region with a carrier concentration in the range R1 shown in FIG. 17A and a region with a carrier concentration in the range R2 in the indium oxide film, a so-called n-i-n junction (a junction between an n-type region, an i-type region, and an n-type region) can be created. Note that valence electron control in transistors using silicon is generally known. On the other hand, valence electron control in transistors using indium oxide is a novel technical concept that would not normally be conceived.

[0338] By using the above technical concept, the transistor having indium oxide in this specification and the like has two or more, preferably three or more, more preferably four or more, and most preferably five of the following characteristics (1) to (5): (1) high on-current (in other words, high mobility); (2) low off-current; (3) normally-off operation; (4) high reliability; and (5) high cutoff frequency (fT). For example, the transistor having indium oxide in this specification and the like has high mobility, low off-current, and is normally-off operation. The transistor has high mobility and is different from a normally-on transistor.

[0339] Next, an indium oxide film applied to a transistor will be described. The indium oxide film preferably has crystallinity (i.e., has crystal grains). Examples of films having crystal grains include single-crystal films, polycrystalline films, and amorphous films containing crystal grains (also called microcrystalline films). In particular, the indium oxide film is preferably a polycrystalline film, and more preferably a single-crystal film. A single-crystal film does not have grain boundaries. Impurities (typically, insulating impurities, insulating oxides, etc.) that hinder carrier flow tend to segregate at grain boundaries. The use of a single-crystal film can suppress carrier scattering at grain boundaries, thereby realizing a transistor exhibiting high field-effect mobility. Furthermore, the use of a single-crystal film has the excellent effect of suppressing variations in transistor characteristics due to the grain boundaries.

[0340] Furthermore, polycrystalline films are preferable because they can reduce carrier scattering and exhibit high field-effect mobility compared to microcrystalline or amorphous films. When using a polycrystalline film, it is preferable to use a film with as large a crystal grain size as possible and with few crystal grain boundaries. Note that in a transistor using an indium oxide polycrystalline film, if there is no crystal grain boundary in the channel formation region or no crystal grain boundary is observed, the channel formation region is located within a single crystal region included in the polycrystalline film, and therefore the transistor can be considered to be using single-crystal indium oxide.

[0341] The crystallinity of indium oxide can be analyzed by, for example, X-ray diffraction (XRD), transmission electron microscope (TEM), or electron diffraction (ED). Alternatively, a combination of these methods may be used for analysis.

[0342] In this specification and the like, a semiconductor layer in which no crystal grain boundary is observed in the channel formation region, a semiconductor layer in which the channel formation region is included in one crystal grain, or a semiconductor layer in which the crystal axis direction is the same in at least two regions in the channel formation region can be called a single crystal film. Also, a semiconductor layer in which, in the channel formation region, within one crystal grain, the direction of another crystal axis continuously changes around a certain crystal axis or a certain crystal orientation as the axis of rotation can be called a single crystal film.

[0343] The channel formation region refers to a region of the semiconductor layer that overlaps (or faces) the gate electrode via the gate insulating layer, and is located between the region in contact with the source electrode and the region in contact with the drain electrode. The current path in the channel formation region is the shortest distance between the source electrode and the drain electrode. Therefore, the crystal grains, crystal grain boundaries, crystal axes, crystal orientation, etc. in the channel formation region can be confirmed by observing a cross section including the semiconductor layer, the source electrode, and the drain electrode.

[0344] The indium oxide film in the channel formation region preferably has a lower impurity concentration. Impurities in the indium oxide film in the channel formation region can be a scattering source of carriers, which can cause a decrease in field-effect mobility. These impurities can also inhibit the crystal growth of the indium oxide film. Examples of impurities in the indium oxide film include boron and silicon. The indium oxide film preferably contains these impurities at concentrations of 0.1% or less, and more preferably 0.01% (100 ppm) or less. Carbon, hydrogen, and the like are elements that can be contained in the film-forming gas or precursor during film formation, and may remain in the indium oxide film in greater amounts than the above-mentioned impurities.

[0345] The indium oxide film in the channel formation region may contain an element that can become the same trivalent cation as indium, as long as the crystal maintains a cubic crystal structure (bixbyite type). Examples of such an element include Group 13 elements of the periodic table, such as gallium and aluminum, and Group 3 elements of the periodic table. These elements exist mainly as trivalent cations in oxides, and therefore the carrier concentration of indium oxide can be maintained low.

[0346] By using such an indium oxide film in a transistor, the field effect mobility of the transistor can be increased to 50 cm ２ / (V·s) or more, preferably 100 cm ２ / (V·s) or more, more preferably 150 cm ２ / (V·s) or more, more preferably 200 cm ２ / (V·s) or more, more preferably 250 cm ２ / (V·s) or more.

[0347] One of the features of an indium oxide film is that it has higher oxygen permeability (diffusibility) than an IGZO film. As shown in FIG. 17C, an indium oxide film (InO Ｘ Oxygen (O) diffusing into the indium oxide film passes through the indium oxide film and becomes oxygen molecules (O ２ ) and is released as water molecules (H ２ O) may be released in the film. Ｏ In the case where an indium oxide film is present, oxygen atoms diffuse to compensate for the oxygen vacancies. Since oxygen diffuses easily in the indium oxide film, it can be said that oxygen vacancies are more easily compensated for in the indium oxide film than in the IGZO film.

[0348] As described above, an indium oxide film can more easily reduce oxygen vacancies in the film than an IGZO film. Therefore, by using such an indium oxide film in a transistor, a transistor exhibiting extremely high reliability can be realized.

[0349] Furthermore, as shown in FIG. 17C, the indium oxide film diffuses hydrogen. Hydrogen that diffuses into the indium oxide film from the outside passes through the indium oxide film and becomes hydrogen molecules (H ２ ) or reacts with the oxygen contained in the film and is released as water molecules.

[0350] A transistor using an indium oxide film is an accumulation-type transistor that uses electrons as majority carriers. Assuming that the carrier relaxation time is constant, the smaller the effective mass of the electrons (carriers), the higher the electron mobility. In other words, by using indium oxide, which has a small effective mass of electrons, for a transistor, the on-state current or field-effect mobility of the transistor can be increased.

[0351] Table 1 shows the results of single crystal indium oxide (here, In ２ O ３ ) and single-crystal silicon (Si). As shown in Table 1, indium oxide is characterized by a small effective mass of electrons and a large effective mass of holes. Indium oxide also has the characteristic that the effective mass of electrons is almost independent of the crystal orientation. Therefore, by using crystalline indium oxide in a transistor, a transistor with high field-effect mobility and high frequency characteristics (also called f characteristics) can be realized. Furthermore, since the effective mass of holes is large, a transistor with extremely small off-current can be realized. For example, by applying an indium oxide film to a vertical transistor, the off-current per 1 μm of channel width can be reduced to 1 fA (1×10) in an environment of 125° C. −１５ A) or less, or 1aA (1 x 10 −１８ A) or less, and under room temperature (25°C) conditions, −１８ A) or less, or 1zA (1 x 10 −２１ Furthermore, as shown in Table 1, indium oxide has a smaller effective mass of electrons and a larger effective mass of holes than silicon, and therefore may be able to realize a transistor with higher field-effect mobility and lower off-state current than a Si transistor.

[0352]

[0353] It is preferable to provide a seed layer so as to be in contact with at least a portion of the crystalline indium oxide film. The seed layer is preferably made of a material containing crystals with a small difference in lattice constant (also called lattice mismatch) with indium oxide. This can improve the crystallinity of the indium oxide film. Note that a substrate (e.g., a single-crystal substrate) may be used as one of the layers in contact with at least a portion of the crystalline indium oxide film.

[0354] One method for evaluating the degree of lattice mismatch is to use the value of the lattice mismatch shown below. The lattice mismatch Δa [%] of the crystals of the formed film (here, the indium oxide film) with respect to the crystals of the seed layer is expressed as Δa = ((L １ -L ２ ) / L ２ ) × 100, where L １ is the length or lattice constant of the unit lattice vector of the crystal of the formed film, and L ２ is the length of the unit lattice vector or the lattice constant of the crystal of the seed layer.

[0355] The smaller the absolute value of the lattice mismatch Δa between the seed layer and the indium oxide film, the more preferable, and it is most preferably 0. For example, Δa can be set to −5% or more and 5% or less, preferably −4% or more and 4% or less, more preferably −3% or more and 3% or less, and even more preferably −2% or more and 2% or less.

[0356] Here, the indium oxide crystal has a cubic crystal structure (bixbyite type). For example, the crystal of yttria-stabilized zirconia (YSZ) can have a cubic crystal structure (fluorite type). The lattice mismatch of the indium oxide crystal with the cubic YSZ crystal is in the range of −2% to 2%, and a single crystal film of indium oxide can be epitaxially grown on the YSZ substrate.

[0357] It should be noted that the crystal structure of the seed layer and the crystal structure of the indium oxide film may not necessarily have the same crystal system or crystal orientation. For example, a film having crystals of a hexagonal or trigonal structure may be used under an indium oxide film having crystals of a cubic structure. For example, by setting the crystal orientation of the surface of the seed layer to

[001] and the crystal orientation of the underside of the indium oxide film to

[111] , the requirements related to the crystal orientation necessary for epitaxial growth can be satisfied. Examples of hexagonal or trigonal crystals include wurtzite structure, YbFe ２ O ４ Type structure, Yb ２ Fe ３ O ７ YbFeFe alloys have the following structures: ２ O ４ Type structure or Yb ２ Fe ３ O ７ An example of a crystal having such a structure is IGZO.

[0358] This embodiment mode can be combined with other embodiment modes as appropriate. In addition, in this specification, when a plurality of configuration examples are shown in one embodiment mode, the configuration examples can be combined as appropriate.

[0359] Embodiment 3 In this embodiment, a display device according to one embodiment of the present invention and a display module including the display device will be described.

[0360] 18A is a perspective view of a display module 380 including the display device of one embodiment of the present invention. The display module 380 includes a display device 300A and an FPC 398. Note that the display device included in the display module 380 is not limited to the display device 300A and may be a display device 300B or a display device 300C described later.

[0361] Examples of a module including the display device of one embodiment of the present invention include a module in which a connector such as a flexible printed circuit (hereinafter referred to as FPC) or a tape carrier package (TCP) is attached to the display device, and a module in which an integrated circuit (IC) is mounted by a chip-on-glass (COG) method, a chip-on-film (COF) method, or the like.

[0362] The display module 380 includes a substrate 391 and a substrate 399. The display module 380 includes a display portion 397. The display portion 397 is a region that displays an image in the display module 380 and is a region where light from each pixel provided in a pixel portion 394 (described later) can be viewed.

[0363] 18B is a perspective view schematically illustrating the configuration on the substrate 391 side. A circuit portion 392, a pixel circuit portion 393 on the circuit portion 392, and a pixel portion 394 on the pixel circuit portion 393 are stacked on the substrate 391. A terminal portion 395 for connecting to an FPC 398 is provided in a portion of the substrate 391 that does not overlap with the pixel portion 394. The terminal portion 395 and the circuit portion 392 are connected by a wiring portion 396 composed of a plurality of wirings.

[0364] The pixel portion 394 has a plurality of periodically arranged pixels 394a. An enlarged view of one pixel 394a is shown on the right side of FIG. 18B . FIG. 18B shows an example in which one pixel 394a has a sub-pixel 385R that emits red light, a sub-pixel 385G that emits green light, and a sub-pixel 385B that emits blue light. The pixel described in Embodiment 1 can be applied to the sub-pixels 385R, 385G, and 385B. For example, the pixel PIX1 shown in FIG. 1A or the pixel PIX2 shown in FIG. 1B can be applied to the sub-pixels 385R, 385G, and 385B.

[0365] The pixel arrangement in the display device of this embodiment is not particularly limited, and various methods can be applied. Examples of pixel arrangements include a stripe arrangement, an S-stripe arrangement, a matrix arrangement, a delta arrangement, a Bayer arrangement, and a pentile arrangement. Figure 18B shows an example in which a stripe arrangement is applied to the pixel arrangement.

[0366] The pixel circuit section 393 has a plurality of pixel circuits 393a arranged periodically.

[0367] One pixel circuit 393a is a circuit that controls driving of a plurality of elements included in one pixel 394a. One pixel circuit 393a can be configured to have three circuits that control light emission of one light-emitting element. The pixel circuit described in Embodiment 1 can be applied to the pixel circuit 393a. For example, the pixel circuit PIXC1 shown in FIG. 1A or the pixel circuit PIXC2 shown in FIG. 1B can be applied to the pixel circuit 393a.

[0368] The circuit portion 392 includes a circuit for driving each pixel circuit 393 a of the pixel circuit portion 393. For example, the circuit portion 392 preferably includes one or both of a gate line driver circuit and a source line driver circuit. In addition, the circuit portion 392 may include at least one of an arithmetic circuit, a memory circuit, a power supply circuit, and the like.

[0369] The FPC 398 functions as wiring for supplying a video signal, a power supply potential, or the like from the outside to the circuit portion 392. An IC may be mounted on the FPC 398.

[0370] The display module 380 can be configured such that one or both of the pixel circuit portion 393 and the circuit portion 392 are provided overlapping below the pixel portion 394, thereby making it possible to extremely increase the aperture ratio (effective display area ratio) of the display portion 397. In addition, the pixels 394a can be arranged at extremely high density, making it possible to extremely increase the resolution of the display portion 397.

[0371] Because such a display module 380 has extremely high resolution, it can be suitably used in virtual reality (VR) devices such as head-mounted displays (HMDs) or glasses-type augmented reality (AR) devices. For example, even in a configuration in which the display unit of the display module 380 is viewed through lenses, the display module 380 has an extremely high-resolution display unit 397, so that even when the display unit is enlarged with the lenses, the pixels are not visible, allowing for a highly immersive display. Furthermore, the display module 380 is not limited to this, and can be suitably used in electronic devices with relatively small displays. For example, it can be suitably used in the display unit of a wearable electronic device such as a wristwatch.

[0372] In this specification, etc., a device fabricated using a metal mask or an FMM (fine metal mask, high-resolution metal mask) may be referred to as a device with an MM (metal mask) structure. Also, in this specification, etc., a device fabricated without using a metal mask or an FMM may be referred to as a device with an MML (metal maskless) structure.

[0373] [Configuration Example 1 of Display Device] A cross-sectional view of a display device 300 A is shown in Fig. 19. The display device 300 A is an example of a display device to which an MML (metal maskless) structure is applied.

[0374] The island-shaped light-emitting layers in the light-emitting elements of a display device employing the MML structure are formed by depositing a light-emitting layer on one surface and then processing it using photolithography. This allows for the realization of high-definition display devices or display devices with high aperture ratios, which have been difficult to achieve until now. Furthermore, since the light-emitting layers can be created separately for each color, a display device with extremely vivid images, high contrast, and high display quality can be realized. For example, if a display device is composed of three types of light-emitting elements, namely, light-emitting elements that emit blue light, light-emitting elements that emit green light, and light-emitting elements that emit red light, the deposition of the light-emitting layers and the processing by photolithography can be repeated three times to form the three types of island-shaped light-emitting layers.

[0375] Because devices with an MML structure can be manufactured without using a metal mask, they can exceed the upper limit of resolution imposed by the alignment accuracy of the metal mask. Furthermore, when devices are manufactured without using a metal mask, the equipment required for manufacturing the metal mask and the metal mask cleaning process are unnecessary. Furthermore, since photolithography processing can be performed using the same or similar equipment as that used to manufacture transistors, there is no need to introduce special equipment to manufacture devices with an MML structure. As such, the MML structure allows for low manufacturing costs, making it suitable for mass production of devices.

[0376] In a display device to which the MML structure is applied, there is no need to artificially increase the resolution by applying a special pixel arrangement such as a pentile arrangement, and therefore it is possible to realize a display device with high resolution (for example, 500 ppi or more, 1000 ppi or more, 2000 ppi or more, 3000 ppi or more, or 5000 ppi or more) using a so-called stripe arrangement in which R, G, and B sub-pixels are each arranged in one direction.

[0377] Furthermore, by providing a sacrificial layer on the light-emitting layer, damage to the light-emitting layer during the manufacturing process of the display device can be reduced, and the reliability of the light-emitting element can be improved. Note that the sacrificial layer may remain in the completed display device or may be removed during the manufacturing process. For example, the sacrificial layer 318a shown in FIG. 19 is a part of the sacrificial layer provided on the light-emitting layer.

[0378] Furthermore, by employing a film formation step using an area mask and a processing step using a resist mask, a light-emitting element can be manufactured through a relatively simple process.

[0379] A display device 300A illustrated in Figure 19 is a cross-sectional schematic diagram of a display device of one embodiment of the present invention. The display device 300A has a structure in which a pixel circuit, a driver circuit, and the like are provided over a substrate 410. The substrate 410 corresponds to, for example, the substrate 391 illustrated in Figures 18A and 18B and also corresponds to the substrate 101 and the substrate 11 described in Embodiment 1. Note that in the display device 300A in Figure 19, in addition to the element layer 601, the element layer 602, and the element layer 603, a wiring layer 604 is also illustrated. The wiring layer 604 is a layer in which wirings are provided.

[0380] A pixel circuit of the display device is preferably provided in the element layer 602. A driver circuit of the display device (either a gate driver or a source driver, or both) is preferably provided in the element layer 601. The element layer 601 may also be provided with one or more types of circuits such as an arithmetic circuit and a memory circuit.

[0381] The element layer 601 includes, for example, a substrate 410 over which the transistor 400 is formed. A wiring layer 604 is provided above the transistor 400, and the wiring layer 604 includes a wiring that connects the transistor 400 to a conductive layer or a transistor (conductive layer 515 in FIG. 19 ) provided in the element layer 602. An element layer 602 and an element layer 603 are provided above the wiring layer 604, and the element layer 602 includes, for example, a transistor 550 and a transistor 560. The element layer 603 includes light-emitting elements (light-emitting elements EDR, EDG, and EDB in FIG. 19 ).

[0382] The light-emitting elements EDR, EDG, and EDB correspond to the light-emitting element ED described in Embodiment 1. The transistors 550 and 560 correspond to the transistors described in Embodiment 1. The transistors 550 and 560 can each correspond to, for example, any of the transistors Tr1 to Tr7 described in Embodiment 1. Note that FIG. 19 shows an example in which the transistors 550 and 560 are vertical transistors.

[0383] 19 shows an example in which the upper electrode of the transistor 550 is connected to the pixel electrode of the light-emitting element EDR, the pixel electrode of the light-emitting element EDG, or the pixel electrode of the light-emitting element EDB. In this case, the transistor 550 corresponds to, for example, the transistor Tr4 included in the pixel circuit PIXC1 shown in FIG. 1A or the transistor Tr7 included in the pixel circuit PIXC2 shown in FIG. 1B. Note that the transistor 550 may also correspond to the transistor Tr1 included in the pixel circuit PIXC2.

[0384] The transistor 560 can correspond to, for example, the transistor Tr2, the transistor Tr3, or the transistor Tr5 described in Embodiment 1. Note that a lower electrode or an upper electrode of the transistor 560 may be connected to a pixel electrode of the light-emitting element EDR, a pixel electrode of the light-emitting element EDG, or a pixel electrode of the light-emitting element EDB. In this case, the transistor 560 can correspond to, for example, the transistor Tr7.

[0385] The transistor 400 is an example of a transistor included in the element layer 601. The transistors 550 and 560 are examples of transistors included in the element layer 602. The light-emitting elements EDR, EDG, and EDB are examples of light-emitting elements included in the element layer 603.

[0386] The substrate 410 can be made of a material that can be used for the substrate 101 described in Embodiment 1. Note that in this embodiment, the substrate 410 will be described as a semiconductor substrate containing silicon as a material. Therefore, the transistor included in the element layer 601 can be a Si transistor.

[0387] The transistor 400 includes an element isolation layer 412, a conductive layer 416, an insulating layer 415, an insulating layer 417, a semiconductor region 413 formed of a part of the substrate 410, and low-resistance regions 414a and 414b. Although FIG. 19 illustrates a structure in which the source or drain of the transistor 400 is connected to the conductive layer 515 provided in the element layer 602 through the conductive layer 428, the conductive layer 430, and the conductive layer 456, the connection structure of the display device of one embodiment of the present invention is not limited thereto. For example, the source or drain of the transistor 400 may be connected to a lower electrode, an upper electrode, or a gate electrode of the transistor 550 through the conductive layer 428, the conductive layer 430, the conductive layer 456, or the like. Alternatively, the source or drain of the transistor 400 may be connected to a lower electrode, an upper electrode, or a gate electrode of the transistor 560 through the conductive layer 428, the conductive layer 430, the conductive layer 456, or the like.

[0388] The transistor 400 can be a Fin type by, for example, covering the top surface and the side surfaces in the channel width direction of the semiconductor region 413 with a conductive layer 416 functioning as a gate electrode via an insulating layer 415 functioning as a gate insulating layer. By making the transistor 400 a Fin type, the effective channel width can be increased, and the on-state characteristics of the transistor 400 can be improved. Furthermore, the contribution of the electric field of the gate electrode can be increased, and the off-state characteristics of the transistor 400 can be improved. The transistor 400 may be a planar type instead of a Fin type.

[0389] Note that the transistor 400 may be either a p-channel transistor or an n-channel transistor. Alternatively, a plurality of transistors 400 may be provided and both p-channel and n-channel transistors may be used.

[0390] 18B. Specifically, the transistor 400 can be provided in a gate line driver circuit, a source line driver circuit, an arithmetic circuit, a memory circuit, a power supply circuit, or the like.

[0391] 19, an insulating layer 420 and an insulating layer 422 are stacked in this order over the transistor 400. A conductive layer 428 is embedded in the insulating layer 420 and the insulating layer 422.

[0392] 19 , an insulating layer 424, an insulating layer 426, an insulating layer 450, an insulating layer 452, and an insulating layer 454 are stacked in this order. A conductive layer 430 is embedded in the insulating layer 424 and the insulating layer 426, and a conductive layer 456 is embedded in the insulating layer 450, the insulating layer 452, and the insulating layer 454.

[0393] An insulating layer 513 and an insulating layer 516 are stacked in this order over the insulating layer 454 and the conductive layer 456. A conductive layer 514 is embedded in the insulating layer 516 and the insulating layer 513. A conductive layer 515 is provided over the conductive layer 514 and the insulating layer 516. As described above, the transistor 400 can be connected to the conductive layer 515. Alternatively, a lower electrode, an upper electrode, or a drain electrode of the transistor 550 may be connected to the source or drain of the transistor 400. Alternatively, a lower electrode, an upper electrode, or a drain electrode of the transistor 560 may be connected to the source or drain of the transistor 400.

[0394] An insulating layer 110, an insulating layer 105, an insulating layer 210, an insulating layer 205, and an insulating layer 310 are stacked in this order over the insulating layer 516 and the conductive layer 515. A transistor 550 is provided over the insulating layer 516. The transistor 550 has a region located inside an opening in the insulating layer 110. In FIG. 19 , the insulating layer 105 serves as a gate insulating layer of the transistor 550. The insulating layer 210 is provided over the transistor 550.

[0395] A transistor 560 is provided over the insulating layer 105. The transistor 560 has a region located inside an opening in the insulating layer 210. In FIG. 19 , the gate insulating layer of the transistor 560 is the insulating layer 205. The insulating layer 310 is provided over the transistor 560.

[0396] A conductive layer 586 is embedded in the insulating layer 105 and the insulating layer 210 over the upper electrode of the transistor 550. A conductive layer 596 is provided over the conductive layer 586 and the insulating layer 210. A conductive layer 598 is embedded in the insulating layer 205 and the insulating layer 310 over the conductive layer 596. A pixel electrode 311a of the light-emitting element EDR, a pixel electrode 311b of the light-emitting element EDG, and a pixel electrode 311c of the light-emitting element EDB are provided over the conductive layer 598 and the insulating layer 310. The upper electrode of the transistor 550 is connected to the pixel electrode 311a, the pixel electrode 311b, and the pixel electrode 311c through the conductive layer 586, the conductive layer 596, and the conductive layer 598.

[0397] The conductive layer 586 can correspond to the conductive layer 135 shown in FIG. 3 in Embodiment 1, for example. The conductive layer 596 can correspond to the conductive layer 212d, for example. The conductive layer 598 can correspond to the conductive layer 235, for example. Note that although FIG. 19 shows an example in which the semiconductor layer 597 is provided over the conductive layer 596 and under the insulating layer 205, the semiconductor layer 597 does not necessarily have to be provided. The semiconductor layer 597 can correspond to the semiconductor layer 213d shown in FIG. 3 in Embodiment 1, for example.

[0398] The insulating layer 420, the insulating layer 422, the insulating layer 426, the insulating layer 452, the insulating layer 454, the insulating layer 516, the insulating layer 110, the insulating layer 210, and the insulating layer 310 function as interlayer insulating layers.

[0399] The insulating layer 424, the insulating layer 450, and the insulating layer 513 are preferably formed using an insulating film (also referred to as a barrier insulating film) having a barrier property against one or more selected from hydrogen, oxygen, and water, for example, aluminum oxide and silicon nitride.

[0400] The conductive layer 428, the conductive layer 430, the conductive layer 456, the conductive layer 514, the conductive layer 515, the conductive layer 586, the conductive layer 596, and the conductive layer 598 function as plugs or wirings. A plurality of conductive layers functioning as plugs or wirings may be collectively denoted by the same reference numeral. Furthermore, in this specification and the like, the wiring and the plug connected to the wiring may be integrated. That is, there are cases where a part of the conductive layer functions as the wiring, and cases where a part of the conductive layer functions as the plug.

[0401] The material of the conductive layer functioning as a plug or wiring can be one or more conductive materials selected from metal materials, alloy materials, metal nitride materials, and metal oxide materials, and can be used as a single layer or a stacked layer. It is preferable to use a high-melting-point material such as tungsten or molybdenum, which has both heat resistance and conductivity, and tungsten is preferred. Alternatively, it is preferable to form the layer using a low-resistance conductive material such as aluminum or copper. The use of a low-resistance conductive material can reduce wiring resistance. Alternatively, it is preferable to use a conductive material that has barrier properties against one or more selected from hydrogen, oxygen, and water. For example, tantalum nitride is preferably used. Furthermore, by stacking tantalum nitride and highly conductive tungsten, hydrogen diffusion can be suppressed while maintaining the conductivity of the wiring.

[0402] On the insulating layer 310, the light emitting elements EDR, EDG, EDB, and the connection portion 340 are formed.

[0403] The connection portion 340 may be called a cathode contact portion, and is connected to the cathode electrodes of the light-emitting elements EDR, EDG, and EDB. In the connection portion 340 shown in Fig. 19, a conductive layer formed using the same process and material as the pixel electrodes 311a to 311c is connected to a common electrode 315, which will be described later. Note that Fig. 19 shows an example in which the conductive layer is connected to the common electrode 315 via a common layer 314, which will be described later, but the conductive layer and the common electrode 315 may also be in direct contact.

[0404] The connection portion 340 may be provided so as to surround the four sides of the display portion in a plan view, or may be provided within the display portion (for example, between adjacent light-emitting elements) (not shown).

[0405] The light-emitting element EDR includes a pixel electrode 311a, a layer 313a over the pixel electrode 311a, a common layer 314 over the layer 313a, and a common electrode 315 over the common layer 314. The light-emitting element EDG includes a pixel electrode 311b, a layer 313b over the pixel electrode 311b, a common layer 314 over the layer 313b, and a common electrode 315 over the common layer 314. The light-emitting element EDB includes a pixel electrode 311c, a layer 313c over the pixel electrode 311c, a common layer 314 over the layer 313c, and a common electrode 315 over the common layer 314. Here, the pixel electrode 311a, the pixel electrode 311b, and the pixel electrode 311c correspond to the pixel electrode 311 described in Embodiment 1. The layer 313a, the layer 313b, the layer 313c, and the common layer 314 correspond to the layer 313 described in Embodiment 1.

[0406] The display device 300A has an SBS structure.

[0407] The layer 313a is formed so as to cover the upper surface and side surfaces of the pixel electrode 311a. Similarly, the layer 313b is formed so as to cover the upper surface and side surfaces of the pixel electrode 311b. Similarly, the layer 313c is formed so as to cover the upper surface and side surfaces of the pixel electrode 311c. Therefore, the entire region where the pixel electrodes 311a, 311b, and 311c are provided can be used as the light-emitting region of the light-emitting elements EDR, EDG, and EDB, thereby increasing the aperture ratio of the pixel.

[0408] In the light-emitting element EDR, the layer 313a and the common layer 314 can be collectively referred to as the EL layer. Similarly, in the light-emitting element EDG, the layer 313b and the common layer 314 can be collectively referred to as the EL layer. Similarly, in the light-emitting element EDB, the layer 313c and the common layer 314 can be collectively referred to as the EL layer.

[0409] The EL layer has at least a light-emitting layer. The light-emitting layer contains one or more light-emitting substances. As the light-emitting substance, a substance that emits light of a color such as blue, purple, blue-purple, green, yellow-green, yellow, orange, or red is appropriately used. Furthermore, a substance that emits near-infrared light can also be used as the light-emitting substance.

[0410] Examples of light-emitting substances that the light-emitting element has include fluorescent substances (fluorescent materials), phosphorescent substances (phosphorescent materials), substances that exhibit thermally activated delayed fluorescence (thermally activated delayed fluorescence: TADF materials), and inorganic compounds (quantum dot materials, etc.).

[0411] The light-emitting layer may contain one or more organic compounds (host materials, assist materials, etc.) in addition to a light-emitting substance (guest material). As the one or more organic compounds, one or both of a substance with high hole-transport properties (hole-transport material) and a substance with high electron-transport properties (electron-transport material) can be used. Furthermore, as the one or more organic compounds, a bipolar substance (a substance with high electron-transport properties and high hole-transport properties) or a TADF material may be used.

[0412] In addition to the light-emitting layer, the EL layer may include one or more of a layer containing a substance with high hole-injecting properties (hole-injecting layer), a layer containing a hole-transporting material (hole-transporting layer), a layer containing a substance with high electron-blocking properties (electron-blocking layer), a layer containing a substance with high electron-injecting properties (electron-injecting layer), a layer containing an electron-transporting material (electron-transporting layer), and a layer containing a substance with high hole-blocking properties (hole-blocking layer).In addition, the EL layer may include one or both of a bipolar substance and a TADF material.

[0413] The light-emitting element can be made of either a low-molecular-weight compound or a high-molecular-weight compound, and may contain an inorganic compound. The layers constituting the light-emitting element can be formed by a method such as a vapor deposition method (including a vacuum vapor deposition method), a transfer method, a printing method, an inkjet method, or a coating method.

[0414] The light-emitting element may have a single structure (a structure having only one light-emitting unit) or a tandem structure (a structure having multiple light-emitting units). The light-emitting unit has at least one light-emitting layer. The tandem structure is a structure in which multiple light-emitting units are connected in series via a charge-generating layer. When a voltage is applied between a pair of electrodes, the charge-generating layer injects electrons into one of the two light-emitting units and holes into the other. The tandem structure allows the light-emitting element to emit light with high brightness. Furthermore, the tandem structure can reduce the current required to achieve the same brightness compared to a single structure, thereby improving reliability. The tandem structure can also be called a stack structure.

[0415] Furthermore, by providing a microcavity structure to the light-emitting element, color purity can be improved.

[0416] The layers 313a to 313c are processed into island shapes by photolithography. Therefore, the angles between the top surface and the side surface of each of the layers 313a to 313c at the edges are close to 90 degrees. On the other hand, for example, an organic film formed using FMM tends to become gradually thinner closer to the edges. For example, the top surface is formed in a sloped shape over a range of 1 μm to 10 μm to the edges, making it difficult to distinguish between the top surface and the side surface.

[0417] The layers 313a to 313c have a clear distinction between the top surface and the side surface. As a result, in the adjacent layers 313a and 313b, one side surface of the layer 313a and one side surface of the layer 313b are arranged opposite each other. This is the same for any combination of the layers 313a to 313c.

[0418] The layers 313a to 313c each include at least a light-emitting layer. For example, it is preferable that the layer 313a includes a light-emitting layer that emits red (R) light, the layer 313b includes a light-emitting layer that emits green (G) light, and the layer 313c includes a light-emitting layer that emits blue (B) light. Furthermore, the respective light-emitting layers may be of a color other than the above, such as cyan, magenta, yellow, or white.

[0419] The layers 313a to 313c preferably include a light-emitting layer and a carrier transport layer (electron transport layer or hole transport layer) on the light-emitting layer. Since the surfaces of the layers 313a to 313c may be exposed during the manufacturing process of the display device, providing the carrier transport layer on the light-emitting layer can prevent the light-emitting layer from being exposed to the outermost surface and reduce damage to the light-emitting layer. This can improve the reliability of the light-emitting element.

[0420] The common layer 314 includes, for example, an electron injection layer or a hole injection layer. Alternatively, the common layer 314 may include a stack of an electron transport layer and an electron injection layer, or a stack of a hole transport layer and a hole injection layer. The common layer 314 is shared by the light-emitting elements EDR, EDG, and EDB. Note that the common layer 314 does not necessarily have to be provided, and the entire EL layer of the light-emitting element may be provided in an island shape, like the layers 313a to 313c.

[0421] 19 , the common electrode 315 is shared by the light-emitting elements EDR, EDG, and EDB. The common electrode 315 shared by the plurality of light-emitting elements is connected to a conductive layer included in the connection portion 340.

[0422] The insulating layer 325 preferably functions as a barrier insulating layer against water and / or oxygen. This structure can suppress the entry of impurities (typically, water and / or oxygen) that may diffuse into each light-emitting element from the outside. With this structure, a highly reliable light-emitting element and a highly reliable display device can be provided.

[0423] The insulating layer 325 can be the above-described oxygen barrier insulating layer, and is preferably formed using aluminum oxide or silicon nitride.

[0424] The insulating layer 325 preferably has a low impurity concentration. This can prevent impurities from entering the EL layer from the insulating layer 325 and causing deterioration of the EL layer. Furthermore, by reducing the impurity concentration in the insulating layer 325, the barrier properties against water and / or oxygen can be improved. For example, it is desirable that the insulating layer 325 has a sufficiently low hydrogen concentration and / or carbon concentration.

[0425] An insulating layer containing an organic material can be suitably used as the insulating layer 327. As the organic material, a photosensitive resin is preferably used, and for example, a photosensitive resin composition containing an acrylic resin is preferably used. Note that in this specification and the like, the term "acrylic resin" does not refer only to polymethacrylic acid ester or methacrylic resin, but may refer to all acrylic polymers in a broad sense.

[0426] The organic materials that can be used for the insulating layer 327 are not limited to those described above. For example, the insulating layer 327 may be made of acrylic resin, polyimide resin, epoxy resin, polyamide resin, polyimideamide resin, silicone resin, siloxane resin, benzocyclobutene resin, phenolic resin, or precursors of these resins. The insulating layer 327 may also be made of organic materials such as polyvinyl alcohol (PVA), polyvinyl butyral (PVB), polyvinylpyrrolidone, polyethylene glycol, polyglycerin, pullulan, water-soluble cellulose, or alcohol-soluble polyamide resin. The insulating layer 327 may also be made of, for example, a photoresist as a photosensitive resin. Examples of photosensitive resins include positive-type materials and negative-type materials.

[0427] The insulating layer 327 may be made of a material that absorbs visible light. The insulating layer 327 absorbs light emitted from a light-emitting element, thereby preventing light from leaking from the light-emitting element to an adjacent light-emitting element through the insulating layer 327 (stray light). This can improve the display quality of the display device. Furthermore, since the display quality can be improved without using a polarizing plate in the display device, the display device can be made lighter and thinner.

[0428] Examples of materials that absorb visible light include materials containing pigments such as black, materials containing dyes, light-absorbing resin materials (e.g., polyimide), and resin materials that can be used for color filters (color filter materials). In particular, using a resin material in which two or more color filter materials are laminated or mixed can enhance the visible light blocking effect, making it preferable. In particular, mixing three or more color filter materials can make it possible to form a black or nearly black resin layer.

[0429] Note that the insulating layer 327 preferably has a tapered shape on the side surface. By forming the side surface edge of the insulating layer 327 into a forward tapered shape (less than 90 degrees, preferably 60 degrees or less, and more preferably 45 degrees or less), the common layer 314 and the common electrode 315 provided on the side surface edge of the insulating layer 327 can be formed with good coverage without causing discontinuities or local thinning of the film. This can improve the in-plane uniformity of the common layer 314 and the common electrode 315, thereby improving the display quality of the display device.

[0430] In addition, in a cross-sectional view of the display device, the upper surface of the insulating layer 327 preferably has a convex curved shape. The convex curved shape of the upper surface of the insulating layer 327 preferably has a shape that bulges gently toward the center. By forming the insulating layer 327 in such a shape, the common layer 314 and the common electrode 315 can be formed with good coverage over the entire insulating layer 327.

[0431] The insulating layer 327 is formed in a region between two EL layers (for example, the region between the layer 313a and the layer 313b), with a portion of the insulating layer 327 sandwiched between a side edge of one EL layer (for example, the layer 313a) and a side edge of the other EL layer (for example, the layer 313b).

[0432] It is also preferable that one end of the insulating layer 327 overlaps with the pixel electrode 311a, which functions as a pixel electrode, and the other end of the insulating layer 327 overlaps with the pixel electrode 311b, which functions as a pixel electrode. This structure allows the end of the insulating layer 327 to be formed on a flat or substantially flat region of the layer 313a (layer 313b). Therefore, it is relatively easy to process the insulating layer 327 into a tapered shape as described above.

[0433] As described above, by providing the insulating layer 327 or the like, it is possible to prevent discontinuities and locally thin portions from being formed in the common layer 314 and the common electrode 315 from the flat or substantially flat region of the layer 313 a to the flat or substantially flat region of the layer 313 b. This makes it possible to prevent poor connection between the light-emitting elements in the common layer 314 and the common electrode 315 due to discontinuities and an increase in electrical resistance due to locally thin portions.

[0434] The display device of this embodiment can reduce the distance between light-emitting elements. Specifically, the distance between light-emitting elements, the distance between EL layers, or the distance between pixel electrodes can be less than 10 μm, 8 μm or less, 5 μm or less, 3 μm or less, 2 μm or less, 1 μm or less, 500 nm or less, 200 nm or less, 100 nm or less, 90 nm or less, 70 nm or less, 50 nm or less, 30 nm or less, 20 nm or less, 15 nm or less, or 10 nm or less. In other words, the display device of this embodiment has a region where the distance between two adjacent island-shaped EL layers is 1 μm or less, preferably a region where the distance is 0.5 μm (500 nm) or less, and more preferably a region where the distance is 100 nm or less. In this way, by reducing the distance between light-emitting elements, a display device with high definition and a large aperture ratio can be provided.

[0435] A protective layer 305 is provided on the light-emitting element. The protective layer 305 functions as a passivation film that protects the light-emitting element. By providing the protective layer 305 that covers the light-emitting element, impurities such as water and oxygen can be prevented from entering the light-emitting element, and the reliability of the light-emitting element can be improved.

[0436] The protective layer 305 and the substrate 301 are bonded via an adhesive layer 303. A solid sealing structure, a hollow sealing structure, or the like can be applied to seal the light-emitting element. In FIG. 19 , the space between the substrate 410 and the substrate 301 is filled with the adhesive layer 303, and a solid sealing structure is applied. Alternatively, the space may be filled with an inert gas (nitrogen, argon, or the like), and a hollow sealing structure may be applied. In this case, the adhesive layer 303 may be provided so as not to overlap with the light-emitting element. Furthermore, the space may be filled with a resin different from the frame-shaped adhesive layer 303.

[0437] The display device 300A is a top-emission type. In a top-emission type, a transistor or the like can be arranged overlapping the light-emitting region of a light-emitting element, and therefore the aperture ratio of the pixel can be increased compared to a bottom-emission type. Light emitted by the light-emitting element is emitted toward the substrate 301. Therefore, it is preferable to use a material that is highly transparent to visible light for the substrate 301. The pixel electrode contains a material that reflects visible light, and the counter electrode (common electrode 315) contains a material that transmits visible light.

[0438] Note that the display device of one embodiment of the present invention may not be a top emission type but may be a bottom emission type in which light emitted from a light-emitting element is emitted toward the substrate 410. In this case, a substrate that has high transmittance to visible light is selected as the substrate 410.

[0439] 20 is a cross-sectional view showing a configuration example of a display device 300B. The display device 300B differs from the display device 300A in that it has an element layer 605 between a wiring layer 604 and an element layer 602. The following mainly describes the differences from the display device 300A, and omits descriptions of similar configurations as appropriate.

[0440] In the display device 300B, an insulating layer 453, an insulating layer 576 over the insulating layer 453, an insulating layer 457 over the insulating layer 576, and an insulating layer 458 over the insulating layer 457 are provided between the insulating layer 452 and the insulating layer 513. The element layer 605 includes a transistor 570. The transistor 570 is provided between the insulating layer 453 and the insulating layer 513.

[0441] The transistor 570 includes a semiconductor layer 571, an insulating layer 573, a conductive layer 574, a pair of conductive layers 575, an insulating layer 576, and a conductive layer 577. The transistor 570 is a planar transistor in which the semiconductor layer is formed on a plane.

[0442] The insulating layer 453 is preferably formed using an insulating film having a barrier property against one or more selected from hydrogen, oxygen, and water, similarly to the insulating layers 424, 450, and 513. For example, one or more selected from aluminum oxide and silicon nitride can be used.

[0443] A conductive layer 577 is provided over the insulating layer 453, and an insulating layer 576 is provided to cover the conductive layer 577. The conductive layer 577 functions as a first gate electrode of the transistor 570, and part of the insulating layer 576 functions as a first gate insulating layer. An oxide insulating film such as a silicon oxide film is preferably used for at least a portion of the insulating layer 576 that is in contact with the semiconductor layer 571. The top surface of the insulating layer 576 is preferably planarized. A pair of conductive layers 575 is provided on and in contact with the semiconductor layer 571 and functions as a source electrode and a drain electrode.

[0444] The semiconductor layer 571 is provided over an insulating layer 576. The semiconductor layer 571 can be formed using a material that can be used for the semiconductor layer 23, the semiconductor layer 113a, the semiconductor layer 113b, the semiconductor layer 113c, the semiconductor layer 213a, the semiconductor layer 213b, the semiconductor layer 213c, the semiconductor layer 213d, etc. The semiconductor layer 571 can be formed using, for example, a metal oxide.

[0445] An insulating layer 457 is provided to cover top surfaces and side surfaces of the pair of conductive layers 575 and side surfaces of the semiconductor layer 571. The insulating layer 457 functions as a barrier layer that prevents impurities such as water or hydrogen from diffusing into the semiconductor layer 571 and prevents oxygen from being released from the semiconductor layer 571. The insulating layer 457 can be formed using the same material as that used for the insulating layer 453.

[0446] The insulating layer 458 and the insulating layer 457 have openings that reach the semiconductor layer 571. An insulating layer 573 in contact with a top surface of the semiconductor layer 571 and a conductive layer 574 are buried in the openings. The conductive layer 574 functions as a second gate electrode, and the insulating layer 573 functions as a second gate insulating layer.

[0447] The top surfaces of the conductive layer 574, the insulating layer 573, and the insulating layer 458 are planarized so that their heights are the same or approximately the same, and an insulating layer 513 is provided to cover them. The insulating layer 513 functions as a barrier layer that prevents impurities such as water or hydrogen from diffusing into the transistor 570. The insulating layer 513 can be formed using the same material as that used for the insulating layer 453.

[0448] In the display device 300B, the conductive layer 514 is provided so as to be embedded not only in the insulating layer 516 and the insulating layer 513 but also in the insulating layer 458 and the insulating layer 457. The display device 300B may be configured without the insulating layer 454, the conductive layer 456, and the like.

[0449] The transistor 570 has a structure in which a semiconductor layer in which a channel is formed is sandwiched between two gates. The two gates may be connected and the transistor may be driven by supplying the same signal to them. Alternatively, the threshold voltage of the transistor may be controlled by applying a potential for controlling the threshold voltage to one of the two gates and a potential for driving to the other.

[0450] 18B, the transistor 570 can be provided in the circuit portion 392 shown in FIG. 18B, similarly to the transistor 400. Specifically, the transistor 400 can be provided in a gate line driver circuit, a source line driver circuit, an arithmetic circuit, a memory circuit, a power supply circuit, or the like.

[0451] 21 shows a cross-sectional view illustrating a configuration example of a display device 300C. The display device 300C differs from the display device 300A in the configurations of, for example, the light-emitting elements EDR, EDG, and EDB. Below, differences from the display device 300A will be mainly described, and descriptions of similar configurations will be omitted as appropriate.

[0452] The element layer 603 of the display device 300C differs from the element layer 603 of the display device 300A mainly in that the same configuration is applied to the layers 313a to 313c, and further in that colored layers 328R, 328G, and 328B are provided.

[0453] The layers 313a to 313c are formed in the same process using the same material. The layers 313a to 313c are separated from each other. By providing an island-shaped EL layer for each light-emitting element, leakage current (also referred to as lateral leakage current) between adjacent light-emitting elements can be suppressed. This prevents unintended light emission due to crosstalk and suppresses color mixing between adjacent light-emitting elements, thereby achieving a display device with extremely high contrast.

[0454] 21 emit white light. The white light emitted by the light-emitting elements EDR, EDG, and EDB passes through the colored layers 328R, 328G, and 328B, thereby obtaining light of a desired color.

[0455] The light emitted from the light emitting elements EDR, EDG, and EDB passes through the colored layers 328R, 328G, and 328B, respectively, and is extracted to the outside of the display device 300C as red, green, and blue light.

[0456] Alternatively, for example, the light-emitting elements EDR, EDG, and EDB shown in FIG. 21 emit blue light. In this case, the layers 313a to 313c each include one or more light-emitting layers that emit blue light. In the subpixels that emit blue light, the blue light emitted by the light-emitting element EDB can be extracted. Furthermore, in the subpixels that emit red light and the subpixels that emit green light, color conversion layers can be provided between the light-emitting element EDR and the coloring layer 328R and between the light-emitting element EDG and the coloring layer 328G to convert the blue light emitted by the light-emitting element EDR or the light-emitting element EDG into light with a longer wavelength, thereby extracting red or green light. By extracting light that has passed through the color conversion layer through the coloring layer, light other than the desired color can be absorbed by the coloring layer, thereby improving the color purity of the light emitted by the subpixels.

[0457] The colored layer is a colored layer that selectively transmits light in a specific wavelength range and absorbs light in other wavelength ranges. For example, a red color filter that transmits light in the red wavelength range, a green color filter that transmits light in the green wavelength range, a blue color filter that transmits light in the blue wavelength range, etc. Each colored layer can be made of one or more of a metal material, a resin material, a pigment, and a dye.

[0458] This embodiment mode can be combined with other embodiment modes as appropriate. In addition, in this specification, when a plurality of configuration examples are shown in one embodiment mode, the configuration examples can be combined as appropriate.

[0459] Embodiment 4 In this embodiment, an application example of a semiconductor device of one embodiment of the present invention will be described with reference to drawings.

[0460] The semiconductor device of one embodiment of the present invention can be used in, for example, electronic components, mainframes, space equipment, data centers (also referred to as DCs), and various electronic devices. By using the semiconductor device of one embodiment of the present invention, low power consumption and high performance can be achieved for the electronic components, mainframes, space equipment, data centers, and various electronic devices.

[0461] Furthermore, a display device including the semiconductor device of one embodiment of the present invention can be used as a display portion of various electronic devices. A display device including the semiconductor device of one embodiment of the present invention can easily achieve high definition and high resolution.

[0462] Examples of electronic devices include electronic devices with relatively large screens such as television sets, desktop or notebook computers, computer monitors, digital signage, large game machines such as pachinko machines, as well as digital cameras, digital video cameras, digital photo frames, mobile phones, portable game machines, personal digital assistants, and sound playback devices.

[0463] In particular, the display device of one embodiment of the present invention can have high resolution and can therefore be suitably used in electronic devices having a relatively small display area. Examples of such electronic devices include wristwatch-type and bracelet-type information terminals (wearable devices), and head-mounted wearable devices such as VR devices such as head-mounted displays, AR glasses-type devices, and mixed reality (MR) devices.

[0464] The display device of one embodiment of the present invention preferably has extremely high resolution, such as HD (1280 × 720 pixels), FHD (1920 × 1080 pixels), WQHD (2560 × 1440 pixels), WQXGA (2560 × 1600 pixels), 4K (3840 × 2160 pixels), or 8K (7680 × 4320 pixels). A resolution of 4K, 8K, or higher is particularly preferable. Furthermore, the pixel density (resolution) of the display device of one embodiment of the present invention is preferably 100 ppi or more, 300 ppi or more, 500 ppi or more, 1000 ppi or more, 2000 ppi or more, 3000 ppi or more, 5000 ppi or more, or 7000 ppi or more. By using a display device having such high resolution and / or high resolution, it is possible to further enhance the sense of realism, depth, and the like. The display device of one embodiment of the present invention is not particularly limited in terms of the screen ratio (aspect ratio). For example, the display device can support various screen ratios such as 1:1 (square), 4:3, 16:9, or 16:10.

[0465] The electronic device of this embodiment may have a sensor (including the function of detecting, detecting, or measuring force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared rays).

[0466] The electronic device of the present embodiment can have various functions, such as a function to display various information (still images, videos, text images, etc.) on a display unit, a touch panel function, a function to display a calendar, date, time, etc., a function to execute various software (programs), a wireless communication function, and a function to read out programs or data recorded on a recording medium.

[0467] 22A to 22F , an example of a wearable device that can be worn on the head will be described. These wearable devices have at least one of the following functions: a function to display AR content, a function to display VR content, a function to display Substitutional Reality (SR) content, and a function to display MR content. By having an electronic device have the function to display at least one of AR, VR, SR, and MR content, it is possible to enhance the sense of immersion of the user.

[0468] The electronic device 800 shown in Figure 22A has a pair of display panels 810, a pair of housings 811, a communication unit (not shown), a pair of mounting units 813, a control unit 814, an imaging unit (not shown), a pair of optical members 816, a frame 817, and a pair of nose pads 818.

[0469] The display device of one embodiment of the present invention can be applied to the display panel 810. Therefore, an electronic device capable of displaying images with extremely high resolution can be provided. Furthermore, the semiconductor device of one embodiment of the present invention can be applied to the control unit 814. This can reduce the power consumption of the electronic device.

[0470] The electronic device 800 can project an image displayed on the display panel 810 onto a display area 819 of the optical member 816. Because the optical member 816 is translucent, the user can see the image displayed in the display area superimposed on a transmitted image visually recognized through the optical member 816. Therefore, the electronic device 800 is an electronic device capable of AR display.

[0471] The electronic device 800 may be provided with a camera capable of capturing an image in front of it as an imaging unit. The electronic device 800 may also be provided with an acceleration sensor such as a gyro sensor, thereby detecting the orientation of the user's head and displaying an image corresponding to that orientation in the display area 819.

[0472] The communication unit has a wireless communication device, and can supply a video signal, etc. Instead of or in addition to the wireless communication device, a connector to which a cable through which a video signal and a power supply potential are supplied may be provided.

[0473] The electronic device 800 is also provided with a battery, which can be charged wirelessly and / or wired.

[0474] The housing 811 may be provided with a touch sensor module. The touch sensor module has a function of detecting a touch on the outer surface of the housing 811. The touch sensor module can detect a tap operation, a slide operation, or the like by the user and perform various processes. For example, a tap operation can perform a process such as pausing or resuming a video, and a slide operation can perform a process such as fast-forwarding or fast-rewinding. Furthermore, providing a touch sensor module on each of the two housings 811 can widen the range of operations.

[0475] The electronic device 830A shown in FIG. 22B and the electronic device 830B shown in FIG. 22C each have a pair of display units 840, a housing 841, a communication unit 842, a pair of mounting units 843, a control unit 844, a pair of imaging units 845, and a pair of lenses 846.

[0476] The display device of one embodiment of the present invention can be applied to the display portion 840. Therefore, an electronic device capable of displaying images with extremely high resolution can be provided. This allows a user to feel a high sense of immersion. Furthermore, the semiconductor device of one embodiment of the present invention can be applied to the control portion 844. This allows the power consumption of the electronic device to be reduced.

[0477] The display unit 840 is provided inside the housing 841 at a position that can be viewed through a lens 846. In addition, by displaying different images on the pair of display units 840, it is possible to perform three-dimensional display using parallax.

[0478] The electronic device 830A and the electronic device 830B can be said to be electronic devices for VR. A user wearing the electronic device 830A or the electronic device 830B can view an image displayed on the display unit 840 through the lens 846.

[0479] It is preferable that the electronic device 830A and the electronic device 830B each have a mechanism for adjusting the left-right positions of the lens 846 and the display unit 840 so that the lens 846 and the display unit 840 are optimally positioned according to the position of the user's eyes. It is also preferable that the electronic device 830A and the electronic device 830B each have a mechanism for adjusting the focus by changing the distance between the lens 846 and the display unit 840.

[0480] The mounting unit 843 allows the user to mount the electronic device 830A or the electronic device 830B on the head. Note that, in Fig. 22B and other figures, the mounting unit 843 is shaped like the temples of glasses, but is not limited to this. The mounting unit 843 may be shaped like a helmet or a band, for example.

[0481] The imaging unit 845 has a function of acquiring external information. Data acquired by the imaging unit 845 can be output to the display unit 840. An image sensor can be used for the imaging unit 845. Furthermore, multiple cameras may be provided to support multiple angles of view, such as telephoto and wide angle.

[0482] Note that, although an example in which the electronic devices 830A and 830B have the imaging unit 845 has been shown here, the electronic devices 830A and 830B do not necessarily have the imaging unit 845 if a distance measuring sensor (hereinafter also referred to as a detection unit) capable of measuring the distance to an object is provided. That is, the imaging unit 845 is one aspect of the detection unit. As the detection unit, for example, an image sensor or a range image sensor such as a LIDAR (Light Detection and Ranging) can be used. By using an image obtained by a camera and an image obtained by a range image sensor, more information can be obtained, enabling more accurate gesture operations.

[0483] The electronic device 830A may have a vibration mechanism that functions as a bone conduction earphone. For example, a configuration having such a vibration mechanism can be applied to one or more of the display unit 840, the housing 841, and the wearing unit 843. This allows a user to enjoy video and audio simply by wearing the electronic device 830A, without the need for separate audio equipment such as headphones, earphones, or speakers.

[0484] The electronic device 830A and the electronic device 830B may each have an input terminal to which a cable can be connected for supplying a video signal from a video output device or the like and power for charging a battery provided in the electronic device.

[0485] The electronic device of one embodiment of the present invention may have a function of wireless communication with an earphone 820. The earphone 820 includes a communication unit (not shown) and has a wireless communication function. The earphone 820 can receive information (e.g., audio data) from the electronic device through the wireless communication function. For example, the electronic device 800 shown in FIG. 22A has a function of transmitting information to the earphone 820 through the wireless communication function.

[0486] The electronic device may also have an earphone unit. The electronic device 830B shown in Fig. 22C has an earphone unit 847. For example, the earphone unit 847 and the control unit 844 may be configured to be connected to each other by wire. A portion of the wiring connecting the earphone unit 847 and the control unit 844 may be disposed inside the housing 841 or the attachment unit 843. The earphone unit 847 and the attachment unit 843 may also have a magnet. This allows the earphone unit 847 to be fixed to the attachment unit 843 by magnetic force, which is preferable as it makes storage easier.

[0487] The electronic device may have an audio output terminal to which earphones or headphones can be connected. The electronic device may also have one or both of an audio input terminal and an audio input mechanism. For example, a sound collection device such as a microphone can be used as the audio input mechanism. By having the audio input mechanism, the electronic device may be endowed with the functionality of a so-called headset.

[0488] 22D and 22E show perspective views of a goggle-type electronic device 860A for VR. Each of FIGS. 22D and 22E shows an example in which a pair of curved display devices 870 (display device 870_R and display device 870_L) is housed within a housing 875. Electronic device 860A also includes a motion detection unit 871, a gaze detection unit 872, a calculation unit 873, a communication unit 874, a lens 876, operation buttons 877, a mounting device 878, a sensor 879, a dial 880, and the like.

[0489] By having two display devices 870, the user can view one display device per eye. This allows for high-resolution images to be displayed even when performing 3D display using parallax. Furthermore, the display device 870 is curved in an arc shape roughly centered on the user's eye. This allows the distance from the user's eye to the display surface of the display device 870 to be constant, allowing the user to view more natural images. Even if the display device 870 exhibits viewing angle dependency, in which the brightness or chromaticity of light changes depending on the viewing angle, the user's eye can be positioned in the normal direction to the display surface of the display device 870. This effectively eliminates the effect, particularly in the horizontal direction, and allows for the display of more realistic images.

[0490] As shown in Fig. 22E, lens 876 is positioned between display device 870 and the user's eyes. Fig. 22E shows an example in which dial 880 is provided to change the position of the lens for diopter adjustment. Note that if electronic device 860A has an autofocus function, dial 880 for diopter adjustment may not be provided.

[0491] 22F shows a goggle-type electronic device 860B having one display device 870. With such a configuration, the number of parts can be reduced.

[0492] The display device 870 can display two images, one for the right eye and one for the left eye, side by side in two left and right areas. This makes it possible to display a stereoscopic image using binocular parallax. Note that the display device 870 may display two different images side by side using parallax, or may display two identical images side by side without using parallax.

[0493] Alternatively, a single image visible to both eyes may be displayed across the entire area of ​​the display device 870. This allows a panoramic image to be displayed across both ends of the field of view, enhancing the sense of realism.

[0494] The display device of one embodiment of the present invention can be applied to the display device 870. The display device of one embodiment of the present invention has extremely high definition, and therefore, even when an image is enlarged using the lens 876, pixels are not visible to a user, and a more realistic image can be displayed.

[0495] 23A is a mobile phone (smartphone), which is a type of information terminal. The information terminal 5500 has a housing 5510 and a display unit 5511. The display unit 5511 is provided with a touch panel and the housing 5510 is provided with buttons as input interfaces.

[0496] 23B is a diagram showing the appearance of an information terminal 5900, which is an example of a wearable terminal. The information terminal 5900 includes a housing 5901, a display portion 5902, operation buttons 5903, a crown 5904, and a band 5905.

[0497] 23C also illustrates a notebook information terminal 5300. The notebook information terminal 5300 illustrated in FIG. 23C includes, for example, a housing 5330a including a display unit 5331 and a housing 5330b including a keyboard unit 5350.

[0498] 23A to 23C are taken as examples of electronic devices, but information terminals other than smartphones, wearable terminals, and notebook information terminals can also be applied. Examples of information terminals other than smartphones, wearable terminals, and notebook information terminals include PDAs (Personal Digital Assistants), desktop information terminals, and workstations.

[0499] 23D is a diagram showing the appearance of a camera 8000 with a viewfinder 8100 attached. The camera 8000 has a housing 8001, a display unit 8002, operation buttons 8003, and a shutter button 8004. A detachable lens 8006 is attached to the camera 8000. The viewfinder 8100 has a housing 8101, a display unit 8102, and a button 8103.

[0500] Note that the camera 8000 may have the lens 8006 and the housing integrated together.

[0501] The camera 8000 can capture an image by pressing a shutter button 8004 or touching a display portion 8002 that functions as a touch panel.

[0502] The housing 8001 has a mount with electrodes, and can be connected to a finder 8100 as well as, for example, a strobe device.

[0503] The housing 8101 is attached to the camera 8000 by a mount that engages with the mount of the camera 8000. The viewfinder 8100 can display an image received from the camera 8000 on a display portion 8102.

[0504] The button 8103 functions as a power button.

[0505] The display device of one embodiment of the present invention can be applied to a display portion 8002 of a camera 8000 and a display portion 8102 of a finder 8100. Note that the camera 8000 may have a built-in finder.

[0506] 23E is a diagram showing the appearance of a portable game machine 5200, which is an example of a game machine. The portable game machine 5200 includes a housing 5201, a display portion 5202, and buttons 5203.

[0507] Furthermore, the images of the portable game console 5200 can be output by a display device provided in a television device, a display for a personal computer, a game display, or a head-mounted display.

[0508] A low-power consumption portable game console 5200 can be realized by applying the display device described in the above embodiment to the portable game console 5200. In addition, the low power consumption can reduce heat generation from a circuit, thereby reducing the influence of heat on the circuit itself, peripheral circuits, and modules.

[0509] 23E illustrates a portable game machine as an example of a game machine, but the electronic device of one embodiment of the present invention is not limited to this. Examples of the electronic device of one embodiment of the present invention include a stationary game machine, an arcade game machine installed in an entertainment facility (e.g., an arcade game center or an amusement park), and a pitching machine for batting practice installed in a sports facility.

[0510] 23F is a perspective view of a television set. The television set 9000 includes a housing 9002, a display 9001, speakers 9003, operation keys 9005 (including a power switch or an operation switch), connection terminals 9006, and a sensor 9007 (for example, a sensor having a function of measuring force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light (including infrared rays), liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, or odor; or a sensor having a function of sensing or detecting odor or light (including infrared rays)). The storage device of one embodiment of the present invention can be included in the television set. The television set can include, for example, a display 9001 having a screen size of 50 inches or more or 100 inches or more.

[0511] A low-power television set 9000 can be realized by applying the display device described in the above embodiment to the television set 9000. Furthermore, low power consumption can reduce heat generation from a circuit, thereby reducing the influence of heat generation on the circuit itself, peripheral circuits, and modules.

[0512] [Mobile Body] The display device according to one embodiment of the present invention can also be applied to the vicinity of the driver's seat of an automobile, which is a mobile body.

[0513] Fig. 23G is a diagram showing the area around the windshield in the interior of a car, illustrating display panels 5701, 5702, and 5703 attached to the dashboard, as well as display panel 5704 attached to a pillar.

[0514] The display panels 5701 to 5703 can display various information such as navigation information, a speedometer, a tachometer, a mileage, a fuel gauge, a gear status, or air conditioning settings. The display items and layouts displayed on the display panels can be changed as needed to suit the user's preferences, improving the design. The display panels 5701 to 5703 can also be used as lighting devices.

[0515] The display panel 5704 can complement the view blocked by the pillar (blind spot) by displaying an image from an imaging means provided on the vehicle body. That is, by displaying an image from an imaging means provided on the outside of the vehicle, blind spots can be complemented and safety can be improved. Furthermore, by displaying an image that complements the invisible part, safety can be confirmed more naturally and without discomfort. The display panel 5704 can also be used as a lighting device.

[0516] The display device of one embodiment of the present invention can be applied to the display panels 5701 to 5704, for example.

[0517] Although an automobile is described above as an example of a moving object, the moving object is not limited to an automobile. For example, examples of the moving object include a train, a monorail, a ship, and an aircraft (e.g., a helicopter, an unmanned aerial vehicle (drone), an airplane, and a rocket), and the display device of one embodiment of the present invention can be applied to these moving objects.

[0518] 23H illustrates an example of a digital signage that can be attached to a wall. FIG. 23H illustrates a state in which a digital signage 6200 is attached to a wall 6201. The display device of one embodiment of the present invention can be applied to, for example, a display portion of the digital signage 6200. The digital signage 6200 may be provided with an interface such as a touch panel.

[0519] Although the above description shows an example of an electronic device that can be mounted on a wall as an example of an electronic signboard, the type of electronic signboard is not limited to this. For example, electronic signboards can be mounted on a pole, placed on a stand on the ground, or installed on the roof or side wall of a building.

[0520] This embodiment mode can be combined with other embodiment modes as appropriate. In addition, in this specification, when a plurality of configuration examples are shown in one embodiment mode, the configuration examples can be combined as appropriate.

[0521] 10A: transistor, 10B: transistor, 11: substrate, 12: insulating layer, 15: insulating layer, 20: insulating layer, 20_1: insulating layer, 20_2: insulating layer, 20_3: insulating layer, 21: conductive layer, 21_1: conductive layer, 21_2: conductive layer, 21_3: conductive layer, 21a: conductive layer, 21a_1: conductive layer, 21a_2: conductive layer, 21a_3: conductive layer, 21b: conductive layer, 21b_1: conductive layer, 21b_2: conductive layer, 21b_3: conductive layer, 22: conductive layer, 22_1: conductive layer, 22_2: conductive layer, 23: semiconductor layer, 23_1: semiconductor layer, 23_2: semiconductor layer, 23_3: semiconductor layer , 25: conductive layer, 25_1: conductive layer, 25_2: conductive layer, 26: insulating layer, 27: conductive layer, 28: insulating layer, 31: opening, 31_1: opening, 31_2: opening, 31a: opening, 31a_1: opening, 31a_2: opening, 31b: opening, 31b_1: opening, 31b_2: opening, 101: substrate, 102: insulating layer, 105: insulating layer, 110: insulating layer, 111a: conductive layer, 111b: conductive layer, 111c: conductive layer, 112a: conductive layer, 112b: conductive layer, 112c: conductive layer, 113a: semiconductor layer, 113b: semiconductor layer, 113c: semiconductor layer, 115a: conductive conductive layer, 115b: conductive layer, 115c: conductive layer, 121a: opening, 121a_1: opening, 121a_2: opening, 121b: opening, 125: opening, 126a: opening, 126b: opening, 135: conductive layer, 136a: conductive layer, 136b: conductive layer, 205: insulating layer, 210: insulating layer, 212a: conductive layer, 212b: conductive layer, 212c: conductive layer, 212d: conductive layer, 213a: semiconductor layer, 213b: semiconductor layer, 213c: semiconductor layer, 213d: semiconductor layer, 215a: conductive layer, 215b: conductive layer, 221a: opening, 221b: opening, 221c: opening , 225: opening, 226: opening, 235: conductive layer, 236: conductive layer, 300A: display device, 300B: display device, 300C: display device, 301: substrate, 303: adhesive layer, 305: protective layer, 310: insulating layer, 311: pixel electrode, 311a: pixel electrode, 311b: pixel electrode, 311c: pixel electrode, 313: layer, 313a: layer, 313b: layer, 313c: layer, 314: common layer, 315: common electrode, 318a: sacrificial layer, 325: insulating layer, 327: insulating layer, 328B: colored layer, 328G: colored layer, 328R: colored layer, 340: connection portion, 380: display module,385B: subpixel, 385G: subpixel, 385R: subpixel, 391: substrate, 392: circuit section, 393: pixel circuit section, 393a: pixel circuit, 394: pixel section, 394a: pixel, 395: terminal section, 396: wiring section, 397: display section, 398: FPC, 399: substrate, 400: transistor, 410: substrate, 412: element isolation layer, 413: semiconductor region, 414a: low resistance region, 414b: low resistance region, 415: insulating layer, 416: conductive layer, 417: insulating layer, 420: insulating layer, 422: insulating layer, 424: insulating layer, 426: insulating layer, 428: conductive layer, 430: conductive layer , 450: insulating layer, 452: insulating layer, 453: insulating layer, 454: insulating layer, 456: conductive layer, 457: insulating layer, 458: insulating layer, 513: insulating layer, 514: conductive layer, 515: conductive layer, 516: insulating layer, 550: transistor, 560: transistor, 570: transistor, 571: semiconductor layer, 573: insulating layer, 574: conductive layer, 575: conductive layer, 576: insulating layer, 577: conductive layer, 586: conductive layer, 596: conductive layer, 597: semiconductor layer, 598: conductive layer, 601: element layer, 602: element layer, 603: element layer, 604: wiring layer, 605: element layer, 800: Electronic device, 810: display panel, 811: housing, 813: wearing unit, 814: control unit, 816: optical member, 817: frame, 818: nose pad, 819: display area, 820: earphone, 830A: electronic device, 830B: electronic device, 840: display unit, 841: housing, 842: communication unit, 843: wearing unit, 844: control unit, 845: imaging unit, 846: lens, 847: earphone unit, 860A: electronic device, 860B: electronic device, 870: display device, 870_L: display device, 870_R: display device, 871: motion detection unit, 872: gaze detection unit, 873: calculation unit , 874: communication unit, 875: housing, 876: lens, 877: operation button, 878: attachment, 879: sensor, 880: dial, 5200: portable game console, 5201: housing, 5202: display unit, 5203: button, 5300: notebook information terminal, 5330a: housing, 5330b: housing, 5331: display unit, 5350: keyboard unit, 5500: information terminal, 5510: housing, 5511: display unit, 5701: display panel, 5702: display panel, 5703: display panel, 5704: display panel, 5900: information terminal, 5901: housing, 5902: display unit,5903: operation buttons, 5904: crown, 5905: band, 6200: digital signage, 6201: wall, 8000: camera, 8001: housing, 8002: display unit, 8003: operation buttons, 8004: shutter button, 8006: lens, 8100: viewfinder, 8101: housing, 8102: display unit, 8103: button, 9000: television device, 9001: display unit, 9002: housing, 9003: speaker, 9005: operation keys, 9006: connection terminal, 9007: sensor,

Claims

a pixel, a first insulating layer, and a second insulating layer; the pixel includes a first vertical transistor, a second vertical transistor, a third vertical transistor, and a light-emitting element; the first vertical transistor has a first bottom electrode and a second bottom electrode; the first to third vertical transistors each have a conductive layer; the first insulating layer is provided on the first lower electrode and on the second lower electrode; the second insulating layer is provided on the first insulating layer and on the conductive layer; the light-emitting element is provided on the second insulating layer, the first insulating layer has a first opening overlapping the first lower electrode and a second opening overlapping the second lower electrode; the second insulating layer has a third opening overlapping the conductive layer and a fourth opening overlapping the conductive layer; the first vertical transistor has a region located within the first opening and a region located within the second opening; the second vertical transistor has a region located within the third opening; the third vertical transistor has a region located within the fourth opening, The conductive layer functions as a gate electrode of the first vertical transistor, a lower electrode of the second vertical transistor, and a lower electrode of the third vertical transistor. 　 In claim 1, A display device, wherein the thickness of the first insulating layer in the region overlapping with the first lower electrode is equal to or greater than the thickness of the second insulating layer in the region overlapping with the conductive layer. 　 In claim 1, the semiconductor layer of the first vertical transistor and the conductive layer have a region located inside the first opening and a region located inside the second opening, a semiconductor layer of the second vertical transistor and a gate electrode of the second vertical transistor have regions located inside the third opening, The display device, wherein the semiconductor layer of the third vertical transistor and the gate electrode of the third vertical transistor have regions located inside the fourth opening. 　 In claim 1, the third opening has an area overlapping with the first opening, The fourth opening has an area overlapping with the second opening. 　 In claim 1, The display device, wherein the semiconductor layers of the first to third vertical transistors each contain indium. 　 In any one of claims 1 to 5, the pixel includes a fourth vertical transistor and a fifth vertical transistor; the first insulating layer is provided on a lower electrode of the fourth vertical transistor; the second insulating layer is provided on a lower electrode of the fifth vertical transistor; the first insulating layer has a fifth opening overlapping the bottom electrode of the fourth vertical transistor; the second insulating layer has a sixth opening overlapping the bottom electrode of the fifth vertical transistor; the fourth vertical transistor has a region located inside the fifth opening, the fifth vertical transistor has a region located within the sixth opening, the second bottom electrode is electrically connected to a bottom electrode of the fourth vertical transistor; an upper electrode of the third vertical transistor is electrically connected to a lower electrode of the fifth vertical transistor; a display device in which an upper electrode of the fourth vertical transistor is electrically connected to one electrode of the light-emitting element; 　 In claim 6, a semiconductor layer of the fourth vertical transistor and a gate electrode of the fourth vertical transistor have regions located inside the fifth opening, The display device, wherein the semiconductor layer of the fifth vertical transistor and the gate electrode of the fifth vertical transistor have regions located inside the sixth opening. In claim 6, The display device, wherein the semiconductor layer of the fourth vertical transistor and the semiconductor layer of the fifth vertical transistor each contain indium. 　 a pixel, a first insulating layer, and a second insulating layer; the pixel includes a first transistor, a second transistor, a third transistor, and a light-emitting element; the first transistor has a first conductive layer, a second conductive layer, a third conductive layer, a first semiconductor layer, and a third insulating layer; the first insulating layer is provided on the first conductive layer and on the second conductive layer; the first insulating layer has a first opening reaching the first conductive layer and a second opening reaching the second conductive layer; the first semiconductor layer has a region in contact with the first conductive layer, a region in contact with the second conductive layer, a region located inside the first opening, and a region located inside the second opening; the third insulating layer is provided on the first semiconductor layer so as to have a region located inside the first opening and a region located inside the second opening; the third conductive layer is provided on the third insulating layer so as to have a region facing the first semiconductor layer with the third insulating layer sandwiched between the third conductive layer and the first opening and the second opening; the second transistor includes the third conductive layer, a fourth conductive layer, a fifth conductive layer, a second semiconductor layer, and a fourth insulating layer; the third transistor includes the third conductive layer, a sixth conductive layer, a seventh conductive layer, a third semiconductor layer, and the fourth insulating layer; the second insulating layer is provided on the third conductive layer; the fourth conductive layer and the sixth conductive layer are provided on the second insulating layer; the second insulating layer and the fourth conductive layer have a third opening reaching the third conductive layer; the second insulating layer and the sixth conductive layer have a fourth opening reaching the third conductive layer; the second semiconductor layer has a region in contact with the third conductive layer, a region in contact with the fourth conductive layer, and a region located inside the third opening, the third semiconductor layer has a region in contact with the third conductive layer, a region in contact with the sixth conductive layer, and a region located inside the fourth opening, the fourth insulating layer is provided on the second semiconductor layer and the third semiconductor layer so as to have a region located inside the third opening and a region located inside the fourth opening; the fifth conductive layer is provided on the fourth insulating layer inside the third opening so as to have a region facing the second semiconductor layer with the fourth insulating layer therebetween; the seventh conductive layer is provided on the fourth insulating layer inside the fourth opening so as to have a region facing the third semiconductor layer with the fourth insulating layer therebetween; The display device, wherein the light-emitting element is provided on the fifth conductive layer, the seventh conductive layer, and the fourth insulating layer. 　 In claim 9, A display device, wherein the thickness of the first insulating layer in a region overlapping with the first conductive layer is equal to or greater than the thickness of the second insulating layer in a region overlapping with the third conductive layer. 　 In claim 9, the third opening has an area overlapping with the first opening, The fourth opening has an area overlapping with the second opening. 　 In claim 9, The display device, wherein the first to third semiconductor layers each contain indium. 　 In any one of claims 9 to 12, the pixel includes a fourth transistor and a fifth transistor; the fourth transistor has an eighth conductive layer, a ninth conductive layer, a tenth conductive layer, a fourth semiconductor layer, and the third insulating layer; the fifth transistor includes the fifth conductive layer, an eleventh conductive layer, a twelfth conductive layer, a fifth semiconductor layer, and the fourth insulating layer; the first insulating layer is provided on the eighth conductive layer; the ninth conductive layer is provided on the first insulating layer; the first insulating layer and the ninth conductive layer have a fifth opening reaching the eighth conductive layer; the fourth semiconductor layer has a region in contact with the eighth conductive layer and a region in contact with the ninth conductive layer, the fourth semiconductor layer has a region located inside the fifth opening, the third insulating layer is provided on the fourth semiconductor layer so as to have a region located inside the fifth opening; the tenth conductive layer is provided on the third insulating layer inside the fifth opening so as to have a region facing the fourth semiconductor layer with the third insulating layer therebetween; the eleventh conductive layer is provided on the third insulating layer; the second insulating layer is provided on the tenth conductive layer and the eleventh conductive layer; the twelfth conductive layer is provided on the second insulating layer; the second insulating layer and the twelfth conductive layer have a sixth opening reaching the eleventh conductive layer; the fifth semiconductor layer has a region in contact with the eleventh conductive layer, a region in contact with the twelfth conductive layer, and a region located inside the sixth opening, the fourth insulating layer is provided on the fifth semiconductor layer so as to have a region located inside the sixth opening; the fifth conductive layer is provided on the fourth insulating layer in the sixth opening so as to have a region facing the fifth semiconductor layer with the fourth insulating layer therebetween; the second conductive layer is electrically connected to the eighth conductive layer; the sixth conductive layer is electrically connected to the eleventh conductive layer; The ninth conductive layer is electrically connected to one electrode of the light-emitting element. 　 In claim 13, The display device, wherein the fourth semiconductor layer and the fifth semiconductor layer each contain indium.

Images