Memory pooling-based computing resource aggregation method and system

Abstract

The present invention relates to the field of cloud computing resource aggregation, and relates to a memory pooling-based computing resource aggregation method and system. The method comprises: acquiring computing resources of a plurality of computing nodes, the computing resources including memory resources and CPU resources; on the basis of a bus interconnect network protocol, constructing a shared memory resource pool interconnected between the computing nodes; aggregating the memory resources by means of the shared memory resource pool; dividing a management area from the shared memory resource pool; in the management area, constructing a fast channel for data transmission in the pool; on the basis of the fast channel, constructing, by means of interrupt forwarding and affinity scheduling, a shared CPU resource pool interconnected between the computing nodes; and aggregating the CPU resources by means of the shared CPU resource pool. The present invention can significantly expand the specifications of virtual machines, greatly increase virtual resources of virtual machines, and expand content of computing nodes, thereby reducing the complexity of programming modes and the difficulty of programming.

Description

A method and system for aggregating computing resources based on pooled memory Technical Field

[0001] This invention belongs to the field of cloud computing resource aggregation, and in particular relates to a method and system for computing resource aggregation based on pooled memory. Background Technology

[0002] In the current cloud computing environment, virtualization technology is its cornerstone and foundation. Through virtualization, the physical resources of computing nodes can be abstracted into virtual resources with similar performance and complete functionality. Cloud hosts (Virtual Machines, VMs) run on these virtual resources and can be viewed as efficient and isolated replicas of real physical machines. This technology enables data centers to utilize physical resources more efficiently while providing good isolation and security.

[0003] In existing technologies, cloud computing vendors typically use a "one-to-many" approach to abstract a single computing node into multiple cloud hosts in order to make reasonable use of data center computing resources and improve overall utilization.

[0004] Furthermore, with the rise of scenarios such as big data mining, AI model training, and chip simulation, CPU-intensive and memory-intensive applications are increasingly constrained by the specifications of computing nodes and cloud servers. For big data applications, the industry typically uses two methods to expand computing resources: scale-up and scale-out. Scale-up aims to increase the physical resource specifications of a single computing node, while scale-out manages multiple computing nodes in a distributed manner to meet the demands of big data processing.

[0005] In the above technical solutions, the "one-to-many" approach abstracts a single computing node into multiple cloud hosts. However, due to limitations in the physical resources of the computing nodes and the CPU and memory barriers between them, the virtual resources available to each cloud host are limited. Vertical scaling of computing resources leads to bottlenecks in the physical resource specifications of a single computing node. Horizontal scaling of computing resources, using a distributed approach, increases the complexity and difficulty of the programming model. Summary of the Invention

[0006] In view of the shortcomings of the prior art, the purpose of the invention is to provide a computing resource aggregation method and system based on pooled memory. By constructing a shared memory resource pool interconnected between computing nodes based on a bus interconnection network protocol and a shared CPU resource pool interconnected between computing nodes, the cloud host specifications can be significantly increased, the virtual resources of the cloud host can be greatly increased, and the number of virtual resources available to the cloud host can be increased. This is not limited by the physical resources of computing nodes and the CPU and memory barriers between computing nodes. The content of computing nodes can be expanded, avoiding the bottleneck of the physical resource specifications of a single computing node. Furthermore, by using a bus interconnection network protocol, the distributed approach is avoided, reducing the complexity and difficulty of the programming mode.

[0007] A first aspect of the present invention proposes a method for aggregating computing resources based on pooled memory, comprising:

[0008] S1, acquire the computing resources of multiple computing nodes, the computing resources including memory resources and CPU resources;

[0009] S2, based on the bus interconnection network protocol, constructs a shared memory resource pool that interconnects various computing nodes;

[0010] S3, aggregate the memory resources through the shared memory resource pool;

[0011] S4, divide the management area in the shared memory resource pool;

[0012] S5, Construct a fast channel for data transmission within the pool in the management area;

[0013] S6. Based on the fast channel, a shared CPU resource pool interconnected between various computing nodes is constructed through interrupt forwarding and affinity scheduling;

[0014] S7, aggregate the CPU resources through the shared CPU resource pool.

[0015] Furthermore, following S2, the pooled memory-based computing resource aggregation method further includes:

[0016] The shared memory resource pool is used to expand the content of the computing node: alloc_mem = local_mem + remote_mem

[0017] Where alloc_mem represents the total amount of memory accessed, local_mem represents the local memory of the compute node, and remote_mem represents the remote memory of the compute node.

[0018] Furthermore, S3 specifically includes:

[0019] S301, the shared memory resource pool is divided into multiple memory units through a PCIe switch and a memory controller;

[0020] S302, through the PCIe switch and memory controller, each computing node sends a remote memory request to the shared memory resource pool;

[0021] S303, based on the request message of the remote memory request, the memory controller locates the remote memory request to a portion of the memory units in the shared memory resource pool;

[0022] S304, through the Dax device mode, the aforementioned memory units are transparently transmitted to each computing node;

[0023] S305, via memory access instructions, the computing node performs nanosecond-level memory data read and write operations on the remote memory of a portion of the transparent memory units to aggregate the memory resources.

[0024] Furthermore, S6 specifically includes:

[0025] S601, the interrupt forwarding is optimized through the task affinity scheduling;

[0026] S602, accelerate the optimized interrupt forwarding through the fast channel;

[0027] S603, through accelerated interrupt forwarding, the interrupt request of the accelerated interrupt forwarding is transparently forwarded across nodes to the advanced programmable interrupt controller of the CPU of the specified node, so as to build a shared CPU resource pool interconnected by various computing nodes.

[0028] Furthermore, S601 specifically includes:

[0029] S6011, through the affinity scheduling, the virtual CPU resources of each host machine are allocated to different NUMA nodes;

[0030] S6012, Based on the communication distance between the computing nodes, set the distance and penalty term between the NUMA nodes;

[0031] S6013, by setting the penalty item, determine whether the CPU resource utilization pressure in the current NUMA node exceeds the threshold; if so, automatically switch the virtual CPU resource to other NUMA nodes; otherwise, keep the virtual CPU resource running in the current NUMA node.

[0032] Furthermore, S602 specifically includes:

[0033] S6021, the interrupt request for interrupt forwarding is sent to the fast channel;

[0034] S6022, Write the interrupt request into the buffer in the fast channel;

[0035] S6023 sends an interrupt request to the listening process of the target computing node through the fast channel after the interrupt request is written;

[0036] S6024, according to the interrupt request, the target computing node reads the data in the cache to its local machine.

[0037] Furthermore, following S7, the pooled memory-based computing resource aggregation method further includes:

[0038] S8 synchronizes the memory data between the various computing nodes through a memory state transition mechanism and active cache refresh.

[0039] Furthermore, the memory state transition mechanism specifically includes:

[0040] Divide memory pages into initial, shared, modifiable, and invalid states;

[0041] The permissions of the EPT page table for memory pages on each compute node are modified using the initial, shared, modifiable, and invalid states.

[0042] Furthermore, the proactive cache refresh specifically includes:

[0043] When the computing node performs nanosecond-level memory data read / write on the remote memory of a portion of the memory units after the pass-through, it flushes the local CPU cache to the shared memory resource pool.

[0044] After flushing the local CPU cache to the shared memory resource pool, the memory page is removed from the local CPU cache.

[0045] A second aspect of the present invention provides a computing resource aggregation system based on pooled memory, comprising: a memory and one or more processors;

[0046] The memory stores one or more applications, which are adapted to be executed by the one or more processors to implement the above-described pooled memory-based computing resource aggregation method.

[0047] The beneficial effects of this invention are as follows:

[0048] The method and system of this invention significantly increase the specifications of cloud hosts and greatly increase the virtual resources of cloud hosts by constructing a shared memory resource pool interconnected between various computing nodes based on a bus interconnection network protocol and a shared CPU resource pool interconnected between various computing nodes. This allows for a greater number of virtual resources available to cloud hosts, freeing them from limitations on the physical resources of computing nodes and the CPU and memory barriers between computing nodes. It also expands the capacity of computing nodes, avoiding bottlenecks in the physical resource specifications of a single computing node. Furthermore, by using a bus interconnection network protocol, it avoids a distributed approach, reducing the complexity and difficulty of the programming model. Attached Figure Description

[0049] The accompanying drawings are for illustrative purposes only and are not intended to limit the invention. Throughout the drawings, the same reference numerals denote the same parts. It is obvious that the drawings described below are merely some embodiments of the present invention, and those skilled in the art can obtain other drawings based on these drawings.

[0050] Figure 1 is a flowchart illustrating a computing resource aggregation method based on pooled memory provided in an embodiment of the present invention;

[0051] Figure 2 is a schematic diagram of a computing resource aggregation system based on pooled memory provided in an embodiment of the present invention. Detailed Implementation

[0052] To enable those skilled in the art to better understand the technical solutions in the embodiments of the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. It should be understood that these descriptions are merely exemplary and are not intended to limit the scope of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0053] Furthermore, descriptions of well-known structures and techniques are omitted in the following description to avoid unnecessarily obscuring the concepts disclosed in this invention.

[0054] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicating orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings, are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance. The terms "installed," "connected," and "linked" should be interpreted broadly; for example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal communication of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0055] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numerals in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present invention. Rather, they are merely examples of methods and systems consistent with some aspects of the invention as detailed in the appended claims.

[0056] This invention proposes a method and system for aggregating computing resources based on pooled memory. It addresses the limitations of existing technologies that use a "one-to-many" approach, abstracting a single computing node into multiple cloud hosts. These methods are constrained by the physical resources of the computing nodes and the CPU and memory limitations between them, resulting in limited virtual resources available to each cloud host. Vertical scaling of computing resources faces bottlenecks due to the physical resource specifications of a single computing node. Horizontal scaling of computing resources, using a distributed approach, increases the complexity and difficulty of the programming model.

[0057] Method Implementation Examples

[0058] Referring to Figure 1 in the specification, a flowchart of a computing resource aggregation method based on pooled memory provided by an embodiment of the present invention is shown.

[0059] This invention provides a method for aggregating computing resources based on pooled memory, comprising:

[0060] Specifically, the method includes steps S1 to S8.

[0061] S1: Obtain computing resources from multiple computing nodes, including memory and CPU resources.

[0062] S2, based on the bus interconnection network protocol, constructs a shared memory resource pool that interconnects various computing nodes.

[0063] It should be noted that the key to the memory resource pooling function is the bus interconnect network protocol.

[0064] Optionally, the bus interconnect network protocols include CXL and UB.

[0065] CXL (Compute Express Link) is a high-speed interconnect technology designed to provide efficient data communication between CPU, memory, and accelerator devices. It combines PCI Express and memory interfaces, supporting high-bandwidth, low-latency data transfer, making it suitable for data centers and high-performance computing applications. It facilitates the integration of heterogeneous computing accelerators and optimizes data flow.

[0066] PCI Express (PCIe) is a high-speed serial computer expansion bus standard used to connect the motherboard to various external hardware devices, such as graphics cards, solid-state drives, and network interface cards. Compared to traditional parallel buses, PCIe offers higher bandwidth, lower latency, and greater scalability, providing efficient data transmission through point-to-point bidirectional links, thereby significantly improving the overall performance and scalability of computer systems.

[0067] Unified Bus (UB) is an integrated circuit design concept designed to integrate the communication needs of multiple functional modules into a shared bus architecture. Through the unified bus, different functional modules such as processors, memory, and input / output devices can share data and control signals, thereby improving the overall efficiency and performance of the system. Unified bus technology is widely used in computer architecture to simplify hardware design, reduce costs, and optimize data flow and resource utilization.

[0068] Specifically, based on this type of bus interconnection network protocol, data centers can build a shared memory resource pool that interconnects various computing nodes.

[0069] Furthermore, by using a shared memory resource pool, different computing nodes can directly access the same memory units on the memory resource pool, achieving cross-node memory sharing and interconnection, thus avoiding data copying and network transmission problems caused by distributed shared memory.

[0070] In this invention, the CXL protocol combines PCIe and memory interfaces to provide high-bandwidth, low-latency data transmission. Through this high-speed interconnect technology, different computing nodes can efficiently share and access memory resources, thereby improving the overall system performance. By using a shared memory resource pool, computing nodes can directly access the same portion of data in shared memory, avoiding the frequent data copying and network transmissions required in traditional distributed shared memory systems, thus reducing communication overhead and latency. High-speed interconnect protocols such as PCIe and CXL allow for easy addition of computing nodes and memory resources, enabling horizontal scaling of the system. This is particularly important for data centers requiring large-scale computing and high performance.

[0071] In one possible implementation, after S2, the following is also included:

[0072] The content of the compute node is expanded by using a shared memory resource pool: alloc_mem = local_mem + remote_mem

[0073] Where alloc_mem represents the total amount of memory accessed, local_mem represents the local memory of the compute node, and remote_mem represents the remote memory of the compute node.

[0074] Specifically, the total amount of memory accessed by a compute node is determined by two parts: the compute node's local memory and the remote memory. The maximum range of the remote memory capacity is equivalent to the capacity of the shared memory resource pool.

[0075] Furthermore, the memory resource pool is shared across nodes. The reading and writing of data in the memory resource pool by the compute nodes is actively perceived by other nodes in order to synchronize the memory data across nodes.

[0076] In this invention, by combining local memory and remote memory, compute nodes can utilize remote memory from a shared memory resource pool to expand their total accessible memory. This approach overcomes the limitations of a single node's physical memory, providing greater memory space to meet the needs of applications with high memory requirements. The shared memory resource pool enables dynamic allocation and sharing of memory resources among multiple compute nodes, avoiding memory waste. For example, when a node's local memory is insufficient, it can utilize remote memory from the shared memory pool, thereby improving the overall system's resource utilization. Through cross-node memory sharing via the memory resource pool, compute nodes are proactively aware of data reads and writes to the memory resource pool, ensuring data consistency and synchronization across different nodes. This avoids computational errors caused by data inconsistency and improves system reliability.

[0077] S3 aggregates memory resources through a shared memory resource pool.

[0078] In one possible implementation, S3 specifically includes sub-steps S301 to S305:

[0079] The S301 divides the shared memory resource pool into multiple memory units through a PCIe switch and a memory controller.

[0080] Specifically, through the PCIe switch and memory controller, the shared memory resource pool is divided into multiple memory units, each of which is mapped to different compute nodes as the DAX devices of the compute nodes and the virtual memory of the cloud hosts.

[0081] DAX (Direct Access) devices are special devices that allow applications to directly access device memory via Direct Memory Access (DMA) without going through the operating system's buffers. This direct access method significantly improves data transfer efficiency and performance, making it particularly suitable for applications requiring high-speed data read / write and low latency, such as high-performance computing and data center applications.

[0082] S302, through the PCIe switch and memory controller, each compute node sends a remote memory request to the shared memory resource pool.

[0083] Optionally, the remote memory request includes the memory resource pool ID, the starting memory unit address, and the requested memory length.

[0084] S303, based on the request message of the remote memory request, the memory controller locates the remote memory request to a portion of the memory unit in the shared memory resource pool.

[0085] S304, through the Dax device mode, passes a portion of memory units to each compute node.

[0086] S305 uses memory access instructions to enable compute nodes to perform nanosecond-level memory data read and write operations on remote memory units of the transparently transmitted memory cells, thereby aggregating memory resources.

[0087] Specifically, within the compute node, the operating system and applications perform nanosecond-level memory data read and write operations on the remote memory passed through the memory resource pool via memory access instructions. While ensuring business performance, the memory resource pool greatly increases the memory capacity of the compute node and synchronizes memory data across nodes in a shared manner.

[0088] In this invention, by dividing the shared memory resource pool into multiple memory units and allowing compute nodes to access these memory units via DAX devices, the memory capacity of each compute node can be significantly increased. This method of expanding memory capacity is more flexible and cost-effective than traditional physical memory expansion. Allowing compute nodes to access remote memory within the shared memory resource pool, through nanosecond-level memory data read / write operations, enables compute nodes to achieve fast access to large-capacity memory under high-performance requirements. This approach avoids the data copying and latency inherent in traditional network-based transmission, improving the overall system efficiency and response speed.

[0089] S4 divides the management area in the shared memory resource pool.

[0090] S5 establishes a fast channel for data transmission within the pool in the management area.

[0091] Specifically, the shared memory resource pool is directly accessed by each computing node, and the access latency is in the nanosecond range, resulting in fast access speed. Therefore, a management area is divided in the shared memory resource pool.

[0092] Furthermore, a fast channel for data transmission within the pool is constructed in the management area.

[0093] Furthermore, the interrupt forwarding method across CPU nodes is accelerated through a fast channel.

[0094] In this invention, establishing a fast channel for data transmission within the pool significantly reduces data transmission latency, enabling data access speeds in the shared memory resource pool to reach nanosecond levels. This is crucial for applications requiring real-time response and high throughput, such as high-performance computing and large-scale data processing tasks in data centers. The fast channel accelerates CPU interrupt forwarding across nodes, allowing compute nodes to respond to and process interrupt requests from other nodes more quickly. This efficient data transmission mechanism greatly shortens data processing time, thereby improving the overall system response speed and processing capacity. By accelerating interrupt forwarding through the fast channel, the system can handle a large number of interrupt requests more effectively, supporting horizontal scaling and the addition of more compute nodes. This scalability enables the system to cope with ever-increasing workloads and data processing demands.

[0095] S6, based on the fast path, constructs a shared CPU resource pool interconnected between various computing nodes through interrupt forwarding and affinity scheduling.

[0096] In one possible implementation, S6 specifically includes sub-steps S601 to S603:

[0097] S601 optimizes interrupt forwarding through task affinity scheduling.

[0098] In one possible implementation, S601 specifically includes sub-steps S6011 to S6013:

[0099] S6011 uses task affinity scheduling to allocate virtual CPU resources, which are abstracted from each host machine, to different NUMA nodes.

[0100] NUMA (Non-Uniform Memory Access) nodes are a multiprocessor system architecture design where access latency may vary between different processor cores and memory modules. Each NUMA node contains a set of processor cores and dedicated local memory. This design improves memory access efficiency and system performance, especially in applications handling large amounts of data or requiring high concurrency.

[0101] Task affinity scheduling is a scheduling strategy designed to optimize the execution efficiency of tasks on the processor. By setting the distance between NUMA nodes and the penalty term, it binds tasks (multi-threaded or process-oriented) to the same NUMA node as much as possible, avoiding data communication and non-local memory access between threads or processes across NUMA nodes.

[0102] S6012 sets the distance and penalty terms between NUMA nodes based on the communication distance between each computing node.

[0103] S6013 determines whether the CPU resource utilization pressure within the current NUMA node exceeds a threshold based on the set penalty parameters. If so, the virtual CPU resources are automatically switched to other NUMA nodes. Otherwise, the virtual CPU resources remain running within the current NUMA node.

[0104] Specifically, after allocating the virtual CPU resources of each host machine to different NUMA nodes, the virtual CPU resources run within the same NUMA node. Only when the CPU resource utilization pressure in the current NUMA node is too high will it automatically switch to other NUMA nodes, reducing the frequency of interrupt forwarding between nodes and improving service performance.

[0105] It should be noted that those skilled in the art can set the threshold value according to actual needs, and this invention does not limit it.

[0106] In this invention, task affinity scheduling is used to allocate virtual CPU resources to different NUMA nodes, maximizing the utilization of computing nodes' resources. By affining tasks with physical CPU resources, latency and performance losses caused by cross-NUMA node access are reduced, improving the overall system's computational efficiency and response speed. Setting distances and penalties between NUMA nodes and dynamically adjusting them based on the current CPU resource utilization pressure within each NUMA node reduces the frequency of interrupt forwarding across nodes. This optimization reduces communication overhead and data transmission latency between nodes, contributing to improved efficiency and performance of business processing. By automatically adjusting the distribution of virtual CPU resources among NUMA nodes, the system can better adapt to load changes and the needs of different applications. This flexibility and adaptability enhance the system's scalability, supporting the integration and expansion of more computing nodes.

[0107] S602 accelerates optimized interrupt forwarding via a fast channel.

[0108] In one possible implementation, S602 specifically includes sub-steps S6021 to S6023:

[0109] S6021 sends the interrupt request for interrupt forwarding to the fast channel.

[0110] Specifically, each compute node creates two processes for the memory resource pool: Listen and Forward. When interrupt forwarding is required, the hyper-aggregator host sends the interrupt request to the fast channel within the pool through the Forward process.

[0111] It should be noted that the interrupt request is an IPI interrupt request.

[0112] Inter-Processor Interrupt (IPI) is an interrupt request used to implement inter-processor communication in a multiprocessor system. An IPI interrupt request allows one processor to send an interrupt signal to another processor to coordinate tasks, synchronize data, or notify specific events, thereby improving the system's parallel processing capabilities and efficiency.

[0113] S6022 writes the interrupt request to the buffer in the fast channel.

[0114] S6023 sends an interrupt request to the listening process of the target computing node through the fast channel after the interrupt request is written.

[0115] Specifically, when the data copying in the cache is complete, the fast channel within the pool sends an I / O interrupt to the original compute node, indicating that the requested data has been written. Simultaneously, the fast channel within the pool sends an interrupt request to the listening process of the target compute node.

[0116] S6024, based on the interrupt request, the target compute node reads the data from the cache to its local machine.

[0117] Specifically, the target compute node is notified to read the specified buffer data locally. This implements the process of sending an IPI interrupt from the original compute node to the target compute node.

[0118] In this invention, using a fast channel to accelerate interrupt forwarding significantly reduces the transmission latency and response time of interrupt requests. This is crucial for applications and tasks requiring real-time responses, especially in multiprocessor systems, where rapid transmission of interrupt requests via a fast channel can speed up task scheduling and execution. The rapid transmission and processing of interrupt requests enhances the system's parallel processing capabilities. In multiprocessor systems, rapid communication and coordination between processors can execute tasks more efficiently, improving the overall parallel computing power and efficiency of the system. The optimized interrupt forwarding acceleration reduces the load on system interrupt handling, especially during high-load periods. By processing interrupt requests more quickly, it effectively alleviates the system's burden, maintaining system stability and performance.

[0119] The S603, through accelerated interrupt forwarding, forwards interrupt requests across nodes to the advanced programmable interrupt controller of the specified node CPU, thereby constructing a shared CPU resource pool interconnected by various computing nodes.

[0120] It should be noted that on each computing node, the local physical CPU resources, after being virtualized and abstracted, are called local CPU resources, while the virtual CPUs provided by other computing nodes are called remote CPU resources. In order to make reasonable use of remote CPU resources across nodes, the virtual CPU resources provided by multiple computing nodes are integrated into a single host for user use through interrupt forwarding.

[0121] Specifically, by using interrupt forwarding, IPI interrupts are directly passed across nodes to the specified node CPU via network transmission or a fast path within the pool, enabling process communication between CPUs across nodes and utilization of CPU resources across nodes.

[0122] In this invention, interrupt forwarding technology enables the integration of remote virtual CPU resources provided by multiple computing nodes into a single host for local user use. This effectively expands the system's computing power and resource utilization, fully utilizing virtual CPU resources distributed across different nodes and improving the overall system's computing performance and efficiency. Interrupt forwarding directly transmits IPI interrupts across nodes to the APIC of the designated node, avoiding traditional data copying and network transmission overhead. This optimization reduces latency and bandwidth consumption during cross-node communication, improving data transmission efficiency and real-time performance. Interrupt forwarding technology enables inter-process communication and resource utilization between CPUs on different nodes, allowing for more efficient collaborative processing of complex tasks and distributed computing. Applications and services within the system can achieve rapid data exchange and sharing through this method, further enhancing the system's parallel processing capabilities and overall performance.

[0123] S7 aggregates CPU resources by sharing a CPU resource pool.

[0124] In one possible implementation, after S7, the following is also included:

[0125] S8 synchronizes memory data between various computing nodes through a memory state transition mechanism and active cache refresh.

[0126] The memory state transition mechanism specifically includes:

[0127] Memory pages are divided into initial, shared, modifiable, and invalid states.

[0128] Specifically, memory pages initially exist in an initialized state. Reading or writing to memory pages in this initial state by the hyper-aggregator host will trigger a page fault, trapping the host in KVM and changing the memory page state to either a shared or mutable state. In the shared state, local write operations to the memory page will change its state to mutable. When other remote nodes need to write to the same memory page in the memory resource pool, they must invalidate the local node's memory page state. Therefore, the next local read / write operation will trigger a page permission fault, requesting the latest memory data from the remote node before performing the read / write operation and modifying the permissions of both the local and remote memory pages. If a remote node needs to read memory page data, and the local node's state is mutable, the memory page permissions will be changed to a shared state to prevent the local node from modifying the memory page without notifying the remote node.

[0129] Modify the EPT page table permissions of memory pages on each compute node by using the initial, shared, modifiable, and invalid states.

[0130] Specifically, through the transition between different states, the hyper-aggregator host modifies the EPT page table permissions of each node's memory page, thereby achieving synchronous communication of memory data between nodes.

[0131] Specifically, proactive cache refresh includes:

[0132] When a compute node performs nanosecond-level memory data read / write operations on the remote memory of a portion of the memory units after the pass-through, it flushes the local CPU cache to the shared memory resource pool.

[0133] After flushing the local CPU cache to the shared memory resource pool, the memory pages are removed from the local CPU cache.

[0134] In this invention, a memory state transition mechanism divides memory pages into initial, shared, modifiable, and invalid states, and manages and synchronizes memory data through transitions between these states. This mechanism ensures consistency in read and write operations on memory data within a multi-node shared memory resource pool, avoiding data conflicts and inconsistencies. By dynamically adjusting and managing the memory page states, the memory state transition mechanism minimizes communication overhead between nodes. Data synchronization is triggered only when necessary, such as requesting the latest data from a remote node when a memory page on a local node becomes invalid, avoiding frequent data transfers and thus improving the overall efficiency and performance of the system. Combined with proactive cache refresh, the memory state transition mechanism supports dynamic adjustment and management of data in the memory resource pool by the hyper-aggregated host. This flexibility and scalability enable the system to automatically optimize resource allocation based on different workloads and needs, improving system responsiveness and adaptability.

[0135] In one possible implementation, the resource aggregation method based on pooled memory further includes:

[0136] A hyper-aggregated host is built by sharing a memory resource pool and a CPU resource pool.

[0137] Specifically, the super-aggregated host uses a shared memory pool based on a novel bus interconnect network as its hardware foundation. Multiple computing nodes connect to the same memory block in the memory pool via this new bus interconnect network protocol, enabling the expansion of computing node memory scale and the synchronization of cross-node memory data. Regarding the CPU resources of the computing nodes, the super-aggregated host forms a shared CPU resource pool through interrupt forwarding and employs CPU affinity scheduling to avoid cross-node process scheduling. Combined with new distributed virtualization and kernel technologies, the computing resources of the CPU resource pool and memory pool are abstracted into virtual resources and provided to the super-aggregated host, achieving cross-node resource aggregation and breaking down resource isolation between computing nodes. Inside the super-aggregated host, customers enjoy ultra-large-scale computing resources while avoiding complex distributed synchronization logic, allowing upper-layer business applications to run seamlessly.

[0138] By using a hyper-aggregator host, physical computing resources from multiple computing nodes are aggregated, shielding the underlying computing node topology and data synchronization mechanisms, and abstracting them into a unified hyperscale host in a distributed virtualization manner.

[0139] Furthermore, customers can run their business directly on the hyper-aggregator host without having to consider a distributed framework.

[0140] In this invention, the hyper-aggregated host connects computing nodes to a shared memory resource pool via a novel bus interconnection network protocol, enabling the expansion of memory scale and the synchronization of cross-node memory data. This architecture simplifies system management and deployment complexity, reduces management costs, and improves system maintainability and scalability. The hyper-aggregated host abstracts CPU and memory resources into unified virtual resources through distributed virtualization and kernel technology. This virtualization approach allows customers to flexibly configure and adjust computing resources, dynamically allocating resources according to actual needs, thus improving system responsiveness and adaptability. The hyper-aggregated host avoids cross-node process scheduling through technologies such as CPU affinity scheduling and interrupt forwarding, optimizing system performance and stability. Furthermore, for application scenarios with high data synchronization and security requirements, it provides reliable guarantees, ensuring data consistency and integrity.

[0141] System Implementation Examples

[0142] Referring to Figure 2 in the specification, a schematic diagram of a computing resource aggregation system based on pooled memory provided by an embodiment of the present invention is shown.

[0143] The present invention proposes a computing resource aggregation system 30 based on pooled memory, comprising: a memory 303 and one or more processors 301.

[0144] The memory 303 stores one or more applications, which are adapted to be executed by the one or more processors 301 to implement the pooled memory-based computing resource aggregation method described in the method embodiment.

[0145] The pooled memory-based computing resource aggregation system 30 includes a processor 301 and a memory 303. The processor 301 and the memory 303 are connected, for example, via a bus 302.

[0146] The structure of the pooled memory-based computing resource aggregation system 30 does not constitute a limitation on the embodiments of the present invention.

[0147] Processor 301 may be a CPU, a general-purpose processor, a DSP, an ASIC, an FPGA, or other programmable logic device, transistor logic device, hardware component, or any combination thereof. It may implement or execute the various exemplary logic blocks, modules, and circuits described in connection with this disclosure. Processor 301 may also be a combination that implements computational functions, such as including one or more microprocessor combinations, a combination of a DSP and a microprocessor, etc.

[0148] Bus 302 may include a pathway for transmitting information between the aforementioned components. Bus 302 may be a PCI bus or an EISA bus, etc. Bus 302 may be divided into address bus, data bus, control bus, etc. For ease of illustration, only one thick line is used to represent it in the figure, but this does not mean that there is only one bus or one type of bus.

[0149] The memory 303 may be a ROM or other type of static storage device capable of storing static information and instructions, RAM or other type of dynamic storage device capable of storing information and instructions, or it may be an EEPROM, CD-ROM or other optical disc storage, optical disc storage (including compressed optical discs, laser discs, optical discs, digital universal optical discs, Blu-ray discs, etc.), magnetic disk storage media or other magnetic storage devices, or any other medium capable of carrying or storing desired program code in the form of instructions or data structures and accessible by a computer, but is not limited thereto.

[0150] Computer-readable storage medium embodiments

[0151] The present invention proposes a computer-readable storage medium having a computer program stored thereon, the computer program being loaded and executed by a processor to perform the pooled memory-based computing resource aggregation method described in the first aspect.

[0152] The applicant of this invention has provided a detailed description of the embodiments of the invention in conjunction with the accompanying drawings. However, those skilled in the art should understand that the above embodiments are merely preferred embodiments of the invention. The detailed description is only intended to help readers better understand the spirit of the invention and is not intended to limit the scope of protection of the invention. On the contrary, any improvements or modifications made based on the inventive spirit of the invention should fall within the scope of protection of the invention.

[0153] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the embodiments of the present invention, and are not intended to limit them. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the protection scope of the present invention.

Claims

1. A method for aggregating computing resources based on pooled memory, characterized in that, The method comprises the following steps: S1, obtaining computing resources of a plurality of computing nodes, the computing resources comprising memory resources and CPU resources; S2, constructing a shared memory resource pool interconnected between the computing nodes based on a bus interconnection network protocol; S3, aggregating the memory resources through the shared memory resource pool; S4, dividing a management area in the shared memory resource pool; S5, constructing a fast channel for data transmission in the pool in the management area; S6, constructing a shared CPU resource pool interconnected between the computing nodes based on the fast channel through interrupt forwarding and affinity scheduling; S7, aggregating the CPU resources through the shared CPU resource pool.

2. The method of claim 1, wherein, After the S2, the method further comprises the following steps: expanding the content of the computing nodes through the shared memory resource pool: alloc_mem = local_mem + remote_mem Wherein, alloc_mem represents the total amount of accessed memory, local_mem represents the local memory of the computing node, and remote_mem represents the remote memory of the computing node.

3. The method of claim 1, wherein, The S3 specifically comprises the following steps: S301, dividing the shared memory resource pool into a plurality of memory units through a PCIE switch and a memory controller; S302, each computing node sends a remote memory application request to the shared memory resource pool through the PCIE switch and the memory controller; S303, according to the request message of the remote memory application request, the memory controller locates the remote memory application request to part of the memory units of the shared memory resource pool; S304, the part of the memory units are transparently transmitted to each computing node through the mode of a Dax device; S305, through a memory access instruction, the computing node performs nanosecond-level memory data read and write on the remote memory of the part of the memory units after the transparent transmission, so as to aggregate the memory resources.

4. The method of claim 1, wherein, The S6 specifically comprises the following steps: S601, optimizing the interrupt forwarding through task affinity scheduling; S602, accelerating the optimized interrupt forwarding through the fast channel; S603, through the accelerated interrupt forwarding, transmitting the interrupt request of the accelerated interrupt forwarding to a high-level programmable interrupt controller of a specified node CPU across nodes, so as to construct a shared CPU resource pool interconnected between the computing nodes.

5. The method of claim 3, wherein, The S601 specifically comprises the following steps: S6011, distributing the virtual CPU resources abstracted from each host computer in different NUMA nodes through the affinity scheduling; S6012, setting the distance and penalty term between the NUMA nodes according to the communication distance between the computing nodes; S6013, judging whether the CPU resource utilization pressure in the current NUMA node exceeds a threshold value through the set penalty term; if yes, automatically switching the virtual CPU resources to the remaining NUMA nodes; otherwise, keeping the virtual CPU resources running in the current NUMA node.

6. The method of claim 3, wherein, The S602 specifically comprises the following steps: S6021, sending the interrupt request of the interrupt forwarding to the fast channel; S6022, write the interrupt request into the cache area in the fast channel; S6023, send the interrupt request to the monitoring process of the target computing node through the fast channel after the interrupt request is written; S6024, according to the interrupt request, the target computing node reads the data of the cache area to the local.

7. The method of claim 3, wherein, After the S7, further comprising: S8, synchronize the memory data between the various computing nodes through the memory state transition mechanism and the cache active refresh.

8. The method of claim 6, wherein, The memory state transition mechanism specifically comprises: Divide the memory page into initial, shared, modifiable and invalid states; Modify the EPT page table permissions of the memory page of each computing node through the initial, shared, modifiable and invalid states.

9. The method of claim 6, wherein, The cache active refresh specifically comprises: When the computing node performs nanosecond-level memory data read and write on the remote memory of the part of the memory unit after being transmitted, the local CPU cache is refreshed to the shared memory resource pool; After the local CPU cache is refreshed to the shared memory resource pool, the memory page is removed from the local CPU cache.

10. A pooling memory based computing resource aggregation system, comprising: Comprise: a memory and one or more processors; one or more application programs are stored in the memory, and the one or more application programs are adapted to be executed by the one or more processors to realize the pool-based memory-based computing resource aggregation method in any one of claims 1 to 9.

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