Polar code encoding method and decoding method, and encoding apparatus and decoding apparatus

Abstract

Provided in the present application are a polar code encoding or decoding method, and an encoding apparatus and a decoding apparatus. A set of first bit positions can be determined on the basis of a reliability sequence of a certain length of a polar code, wherein the set of first bit positions is used for indicating frozen bit positions in the reliability sequence, and the set of first bit positions comprises first bit positions belonging to an ith sub-block. In the first bit positions, the number of first bit positions the reliability of which is higher than the reliability of a second bit position of the ith sub-block is less than or equal to a threshold value, and the second bit position refers to a bit position in the ith sub-block that does not belong to the set of first bit positions and has the lowest reliability, wherein i is an integer, and i is greater than or equal to 0 and i is less than L, L being the number of sub-blocks included in the reliability sequence. By means of meeting the requirements, an information bit position set is determined, such that the number of new code patterns generated under rate matching can be reduced, thereby lowering the complexity of hardware implementation.

Description

Encoding method, decoding method, encoding device and decoding device of polar code

[0001] The present application claims priority to the Chinese patent application No. 202411019705.8, filed on July 26, 2024, and entitled "Encoding method, decoding method, encoding device and decoding device of polar code", the whole content of which is incorporated herein by reference. TECHNICAL FIELD

[0002] The present application relates to the field of channel coding and decoding, and more particularly, to an encoding method and a decoding method of polar code, and corresponding encoding device and decoding device. BACKGROUND

[0003] Polar code is a coding scheme that can be strictly proven to achieve the Shannon channel capacity, and has the advantages of good decoding performance and low complexity. The construction process of polar code includes determining the information bit positions of polar code. The mother code obtained through polar encoding has a length of an integer power of 2, but in actual application, the length of polar code is not necessarily an integer power of 2, at this time, some bits need to be selected from the mother code not to be sent, this process is usually called rate matching. The rate matching methods include puncturing, shortening and repetition. In the current standard protocol, when puncturing is used for rate matching, a pre-freezing operation is needed. Specifically, first, the sub-channels corresponding to the bit positions (which can be puncturing positions or more than puncturing positions) that are set in advance are pre-frozen, these bit positions must not be used as information bits, which are called pre-freezing set, and then the information bits are determined in the remaining sub-channels.

[0004] In order to improve the throughput during decoding, the decoding device decodes the sub-blocks with length of 2 n at the same time, for example, when n = 4, the decoding device decodes u 15 , u 16 , …, u 31 , and so on. Therefore, the decoding device needs separate hardware resources to support various code types of 2 n , the code type refers to the set of information bits in the sub-block, in order to reduce the hardware implementation complexity of the decoding device, it is necessary to reduce the code types as much as possible.

[0005] However, when the rate matching method is puncturing, because the pre-freezing order and the reliability order of the sub-blocks with length of 2 n are different, new code types may appear, which increases the hardware implementation complexity. SUMMARY

[0006] The application provides a polar code encoding method and decoding method, and corresponding encoding device and decoding device, which can reduce the new code type possibly generated after puncturing and reduce the complexity of hardware implementation.

[0007] In a first aspect, a polar code encoding method is provided, which can be executed by a communication device or a module (for example, a processor, a chip, a chip system, an integrated circuit, etc., which can also be a logic module, hardware and / or software capable of realizing all or part of the functions of the communication device) applied to the communication device. The communication device can also be referred to as an encoding device, for example, an encoding device or an encoder. The method comprises: obtaining a first bit sequence to be encoded, and determining a first bit position set according to a first reliability sequence of a polar code; wherein the first reliability sequence is used to indicate the reliability of a bit position in the polar code, and the first bit position set is used to indicate the frozen bit positions in the first reliability sequence, the number of first bit positions whose reliability is higher than that of second bit positions in an i-th sub-block is less than or equal to a threshold value, the first bit positions are bit positions belonging to the i-th sub-block in the first bit position set, the second bit positions are bit positions in the i-th sub-block which do not belong to the first bit position set and have the lowest reliability, the i-th sub-block is a set of bit positions whose index values are greater than or equal to i*2 n and less than (i+1)*2 n , n is a positive integer, i is an integer, i is greater than or equal to 0 and less than L, and L is the number of sub-blocks contained in the first reliability sequence; and encoding the first bit sequence according to the first bit position set to obtain an encoded bit sequence.

[0008] It should be noted that the first bit position set is used to indicate the frozen bit positions in the first reliability sequence. Specifically, the first bit position set is determined before the information bit position set is determined, and thus it can also be said that the first bit position is used to indicate the frozen bit positions in the first reliability sequence before or when the information bit position set is determined. Since the bit positions in the first bit position set are frozen before the information bit position set is determined, the bit positions in the first information bit position set can also be referred to as “pre-frozen” bit positions, i.e., pre-frozen bit positions. In other words, the first bit position set is first determined, which includes one or more “pre-frozen” bit positions, and then the information bit position set is determined from the bit positions in the first reliability sequence other than the first bit position set. After the information bit position set is determined, the bit positions in the first reliability sequence that are not determined as information bit positions and the “pre-frozen” bit positions in the first bit position set together constitute the frozen bit positions of the polar code. Therefore, the bit positions in the first bit position set are ultimately part of the frozen bit positions of the polar code.

[0009] In the technical solution of the present application, the first bit position set is determined, which satisfies the condition that the number of first bit positions with a reliability higher than that of the second bit position (non-pre-frozen bit) in the i-th sub-block in the first bit positions (pre-frozen bits) contained in the first bit position set is less than or equal to a threshold value, and the second bit position is the bit position with the lowest reliability in the i-th sub-block that does not belong to the first bit position set. The i-th sub-block is a set of bit positions with an index value within a certain range. Each sub-block satisfies the above condition. The information bit set is determined based on the first bit position set. Since it can be ensured that in a sub-block with a length of 2 n The number of pre-frozen bits with a reliability higher than that of the non-pre-frozen bit with the lowest reliability in a sub-block with a length of 2

[0010] In a second aspect, a method for decoding a polar code is provided, which can be executed by a communication device or a module (e.g., a processor, a chip, a chip system, an integrated circuit, etc., which can also be a logic module, hardware and / or software capable of implementing all or part of the functions of the communication device) applied to the communication device. The communication device can also be referred to as a decoding device, for example, a decoding apparatus or a decoder. The method comprises: obtaining a sequence of received values; determining a first set of bit positions according to a first reliability sequence of the polar code; wherein the first reliability sequence is used to indicate the reliability of bit positions in the polar code, and the first set of bit positions is used to indicate the bit positions that are frozen in the first reliability sequence, and in the first bit positions, the number of first bit positions whose reliability is higher than that of second bit positions in an i-th sub-block is less than or equal to a threshold value, the first bit positions are bit positions in the first set of bit positions that belong to the i-th sub-block, the second bit positions are bit positions in the i-th sub-block that do not belong to the first set of bit positions and have the lowest reliability, and the i-th sub-block is a set of bit positions whose index values are greater than or equal to i*2 n and less than (i+1)*2 n , n is a positive integer, i is an integer, i is greater than or equal to 0 and i is less than L, and L is the number of sub-blocks included in the first reliability sequence; and decoding the sequence of received values according to the first set of bit positions to obtain a sequence of decoded bits.

[0011] In the technical solution of the present application, the first set of bit positions is determined, which satisfies the condition that in the first bit positions (pre-frozen bits) included in the first set of bit positions, the number of first bit positions whose reliability is higher than that of second bit positions (non-pre-frozen bits) in an i-th sub-block is less than or equal to a threshold value, and the second bit positions are bit positions in the i-th sub-block that do not belong to the first set of bit positions and have the lowest reliability. The i-th sub-block is a set of bit positions whose index values are within a certain range. Each sub-block satisfies the above condition. Based on the first set of bit positions, the set of information bits is determined, and since it can be ensured that in a sub-block with a length of 2 n , the number of pre-frozen bits whose reliability is higher than that of the non-pre-frozen bit with the lowest reliability is less than or equal to the threshold value, by controlling the threshold value, the number of new code types generated after rate matching can be controlled. When the threshold value is greater than 0 (for example, the threshold value is 1), the number of new code types that can be generated after puncturing can be reduced; when the threshold value is 0, the reliability of any non-pre-frozen bit is higher than that of any pre-frozen bit, so that no new code type is generated after rate matching, which can reduce the complexity of hardware implementation and improve the decoding efficiency.

[0012] In some implementations of the first aspect or the second aspect, i traverses values in [0, 1, 2, …, L-1].

[0013] In the implementation, i traverses values in [0, 1, 2, …, L-1], and each sub-block included in the first reliability sequence can satisfy that the number of pre-frozen bits with higher reliability than the reliability of the non-pre-frozen bit with the lowest reliability is less than or equal to the threshold value, so that the number of new code types possibly generated after puncturing can be controlled to be the least, and the hardware implementation complexity can be reduced to the greatest extent. Meanwhile, the decoding efficiency can be improved to the greatest extent at the decoding side.

[0014] In some implementations of the first aspect or the second aspect, the number of bit positions belonging to the first set of bit positions in the ithsub-block is 0; or the bit position belonging to the first set of bit positions in the ithsub-block is the 0thbit in ascending order of position index; or the bit positions belonging to the first set of bit positions in the ithsub-block are the 0thto qthbits in ascending order of position index, 1≤q≤2, or 2 n -3≤q≤2 n -1, q is an integer, and n is a positive integer greater than or equal to 2.

[0015] In the implementation, the number of bit positions belonging to the first set of bit positions in the ithsub-block is 0, indicating that no bit position in the ithsub-block is pre-frozen; or the 0thbit in ascending order of position index in the ithsub-block is pre-frozen; or the 0thto qthbits in ascending order of position index in the ithsub-block are pre-frozen. When 1≤q≤2, the two bit positions with the lowest reliability in the ithsub-block are pre-frozen, and in combination with the implementation in which the 0thbit is frozen, the three bit positions with the lowest reliability in the ithsub-block can be pre-frozen, or when 2 n -3≤q≤2 n -1, all bit positions in the ithsub-block are pre-frozen or the three bit positions with the highest reliability in the ithsub-block are not pre-frozen, and in the case of a short code, the performance is more stable.

[0016] In some implementations of the first aspect or the second aspect, determining the first set of bit positions according to the first reliability sequence of the polar code comprises: determining the number F of bit positions in the first set of bit positions according to the code length E and the mother code length N, F being a positive integer multiple of 2 n , and n being a positive integer greater than or equal to 2; and determining, in ascending order of position index, the bit positions with index values greater than or equal to 0 and less than F as the first set of bit positions.

[0017] In the implementation, the number F of bit positions in the first set of bit positions is determined first, that is, the number of pre-frozen bits, and then F bit positions are pre-frozen in natural order of position index from small to large, F being a sub-block length 2n A positive integer multiple of 2. When the threshold is 0, the length is guaranteed to be 2. n The sub-blocks will not produce new code patterns after punching, resulting in stable performance and low hardware implementation complexity.

[0018] In some implementations of the first or second aspect, 2 n =16, F is a positive integer multiple of 16; or, 2 n =8, F is a positive integer multiple of 8.

[0019] In some implementations of the first or second aspect, determining the first set of bit positions based on the first reliability sequence of the polar code includes: determining the number F of bit positions in the first set of bit positions based on the code length E and the length N of the mother code sequence, wherein F is 2^2 / 2^2. n Modulus remainder 2 n -3, where n is a positive integer greater than or equal to 2; the bit positions with index values ​​greater than or equal to 0 and less than F are determined as the first set of bit positions in ascending order of their position indices.

[0020] In this implementation, the number F of bit positions in the first bit position set is first determined, which is also the number of pre-frozen bits. Then, F bit positions are pre-frozen in ascending order of position index, with F pairs of sub-block lengths of 2. n The remainder when modulo 2 is 2 n -3. When the threshold is 0, the length can be guaranteed to be 2. n The sub-blocks will not produce new code patterns after punching, resulting in stable performance and low hardware implementation complexity.

[0021] In some implementations of the first or second aspect, 2 n =16, F modulo 16 leaves a remainder of 13.

[0022] In some implementations of the first or second aspect, determining the first bit position set based on the first reliability sequence of the polar code includes: determining the number F of bit positions in the first bit position set based on the code length E and the mother code length N; and sorting the bits from the 0th bit to the 1st bit position according to the position index in ascending order. position The bit position, and the first bit position The position reached the first The bits are ordered from lowest to highest reliability. The set of n bit positions is determined as the first set of bit positions, where n is a positive integer greater than or equal to 2, and the sign... This indicates rounding down to the nearest integer.

[0023] In this implementation, the number F of bit positions in the first set of bit positions is determined, and pre-freezing is performed in each sub-block in the order of reliability. Specifically, a part can be pre-frozen in the natural order of position index from small to large, for example, for a sub-block with a length of 2 n , the first bit positions are pre-frozen in the natural order, and the remaining bit positions are pre-frozen in the order of reliability from low to high in the last sub-block. Pre-freezing in the order of reliability can ensure that no new code type appears after puncturing for a sub-block with a length of 2 n , and the calculation of the number of pre-frozen bits is simple.

[0024] In some implementations of the first aspect or the second aspect, the threshold is 0, or the threshold is 1.

[0025] In some implementations of the first aspect or the second aspect, the threshold is 1; and determining the first set of bit positions according to the first order of reliability of the polar code comprises: determining the number F of bit positions in the first set of bit positions according to the code length E and the length N of the mother code sequence, F is 12 modulo 16; and determining, in the order of position index from small to large, bit positions with an index value greater than or equal to 0 and less than F as the first set of bit positions.

[0026] In this implementation, the threshold is set to 1, and for each sub-block, the number of pre-frozen bits with a higher reliability than the non-pre-frozen bit with the lowest reliability is controlled to a lower number (not more than the threshold 1), so that no new code type or a small number of new code types can be generated after puncturing, and the hardware complexity is controllable.

[0027] In a third aspect, a communication apparatus is provided, which has the function of implementing the method in the first aspect or any possible implementation of the first aspect; or the function of implementing the method in the second aspect or any possible implementation of the second aspect. The function can be implemented through hardware, or through hardware executing corresponding software. The hardware or software includes one or more units corresponding to the above functions.

[0028] In a fourth aspect, a communication apparatus is provided, which includes at least one processor configured to cause the communication apparatus to perform the method in the first aspect or any possible implementation of the first aspect. Optionally, the at least one processor is coupled with at least one memory for storing computer programs or instructions, and the at least one processor is configured to call and run the computer programs or instructions from the at least one memory, so that the communication apparatus performs the method in the first aspect or any possible implementation of the first aspect.

[0029] In a fifth aspect, a communication apparatus is provided, which comprises at least one processor configured to cause the communication apparatus to perform the method in the second aspect or any possible implementation of the second aspect. Optionally, the at least one processor is coupled with at least one memory for storing computer program or instructions, and the at least one processor is configured to invoke and run the computer program or instructions from the at least one memory, so as to cause the communication apparatus to perform the method in the second aspect or any possible implementation of the second aspect.

[0030] Optionally, in the fourth aspect or the fifth aspect, the at least one processor can be included in the communication apparatus, or can be configured outside the communication apparatus. Optionally, the communication apparatus further comprises the at least one memory. Furthermore, optionally, the communication apparatus further comprises a communication interface coupled with the at least one processor, which can be used to input information and / or data to the at least one processor, or output information and / or data in the at least one processor.

[0031] In a sixth aspect, a communication apparatus is provided, which comprises a communication interface and a circuit. The communication interface is configured to acquire a first bit sequence to be encoded, and send the first bit sequence to the circuit. The circuit is configured to perform the encoding method in the first aspect or any possible implementation of the first aspect, to determine a first bit position set according to a first reliability sequence of a polar code, and encode the first bit sequence according to the first bit position set, to obtain an encoded bit sequence. Optionally, the communication interface is further configured to output the encoded bit sequence. The communication apparatus can be an encoding apparatus. Optionally, the communication apparatus can be a chip.

[0032] In a seventh aspect, a communication apparatus is provided, which comprises a communication interface and a circuit. The communication interface is configured to acquire a received value sequence, and send the received value sequence to the circuit. The circuit is configured to perform the decoding method in the second aspect or any possible implementation of the second aspect, to determine a first bit position set according to a first reliability sequence of a polar code, and decode the received value sequence according to the first bit position set, to obtain a decoded bit sequence. Optionally, the communication interface is further configured to output the decoded bit sequence. The communication apparatus can be a decoding apparatus. Optionally, the communication apparatus can be a chip.

[0033] In an eighth aspect, a computer readable storage medium is provided, which stores computer program codes or instructions, when the computer instructions are run on a computer, so as to cause the method in the first aspect or any possible implementation of the first aspect to be implemented, or so as to cause the method in the second aspect or any possible implementation of the second aspect to be implemented.

[0034] In a ninth aspect, a computer program product is provided, which comprises computer program codes or instructions, which, when run on a computer, cause the method in the first aspect or any possible implementation manner thereof to be implemented, or cause the method in the second aspect or any possible implementation manner thereof to be implemented.

[0035] In a tenth aspect, a wireless communication system is provided, which comprises an encoding device for performing the encoding method in the first aspect or any possible implementation manner thereof, and a decoding device for performing the decoding method in the second aspect or any possible implementation manner thereof. BRIEF DESCRIPTION OF DRAWINGS

[0036] FIG. 1 is an example of a communication system suitable for the technical solution of the present application.

[0037] FIG. 2 is a schematic diagram of a basic flow of wireless communication.

[0038] FIG. 3 is a schematic flowchart of an encoding method or a decoding method of a polar code provided by the present application.

[0039] FIG. 4 is a schematic structural diagram of a communication device 1000 provided by the present application.

[0040] FIG. 5 is a schematic block diagram of another communication device 1100 provided by the present application.

[0041] FIG. 6 is a schematic diagram of a chip (or chip system) provided by the present application. DETAILED DESCRIPTION

[0042] The technical solution in the present application will be described below with reference to the accompanying drawings.

[0043] For the convenience of understanding the solution, the concepts or technologies involved in the embodiments of the present application are briefly introduced.

[0044] 1. Rate matching

[0045] The construction process of a polar code mainly refers to determining the information bits and frozen bits of the polar code. Generally, the reliability of each subchannel is sorted, and K positions with relatively high reliability are set as information bits, and the remaining N-K positions are set as frozen bits. The mother code of a polar code is always an integer power of 2, but in actual application, the length of the polar code required is not necessarily an integer power of 2, at this time, some bits are removed from the mother code and not transmitted, or part of the bits in the mother code are repeatedly transmitted, this processing process is usually called rate matching. Rate matching mainly includes the following three types:

[0046] 1) Puncture: It refers to directly puncturing some positions of the polar code of the mother code length and not transmitting. In this way, the coded bit sequence of the polar code of any length is generated. At the decoding side, since there is no information amount corresponding to the "punctured" position, the log-likelihood ratio (LLR) of the corresponding bit is set to 0.

[0047] 2) Shorten: It is to design the polar code so that some positions in the coded bit sequence are fixed values, so they also do not need to be transmitted. At the decoding side, since the position corresponding to the "shortened" position is equivalent to known (which can usually be set to 0), the LLR of the corresponding bit is set to infinity.

[0048] 3) Repetition: It refers to obtaining a longer polar code coded bit sequence by repeating the transmission of part of the code word bits.

[0049] When rate matching is performed in the puncturing manner, a pre-freezing operation is needed. Generally, first, the sub-channels corresponding to the bit positions set in advance are pre-frozen, which is called a pre-freezing set; then the information bits and frozen bits are determined according to the reliability order of the remaining sub-channels.

[0050] In order to improve the throughput, the decoding side decodes the sub-blocks with a length of 2 n as the granularity, for example, when n = 4, the decoding device first decodes u0,…,u 15 , and then decodes u 16 ,…,u 31 , and so on. The decoder needs separate hardware resources to support various code types of 2 n length. At the construction end (i.e., the encoding end) of the polar code, the code types are reduced as much as possible, which can reduce the hardware implementation complexity. It should be understood that the "code type" can be the distribution (including the number distribution and the respective position distribution) of the information bits and the frozen bits in the sub-block with a length of 2 n , for example, taking a 16-long sub-block as an example, the sub-block [0000000000010111] indicates that 11, 13, 14, and 15 in the sub-block are information bits, and 0, 1, 2, 4, 8, 3, 5, 9, 6, 10, 12, and 7 are frozen bits. This distribution is a code type in which the number of information bits is 4.

[0051] In the rate matching method using the puncturing manner, in addition to the puncturing positions, a part of the bit sub-channels are additionally frozen, which can improve the performance stability of the polar code when the puncturing manner is used for rate matching.

[0052] Generally, the information bits of the polar code are determined in the bit positions other than the pre-freezing set.

[0053] 2. Rate matching based on natural order

[0054] Specifically, bits of the polar code are sequentially punctured or shortened according to the natural order. Taking puncturing as an example, when a polar code with a length of 6 is needed, a polar code with a length of 8 is first constructed, and then the first two bit positions are punctured; when a polar code with a length of 5 is needed, a polar code with a length of 8 is first constructed, and then the first three bit positions are punctured; taking shortening as an example, when a polar code with a length of 7 is needed, u7=0 can be preset, so that x7 in all encoding bit sequences is 0; when a polar code with a length of 6 is needed, u7 and u6 can be preset to 0, so that x7 and x6 in all encoding bit sequences are 0. In the rate matching based on the natural order, the shortening position or the puncturing position is continuous, and the implementation is simple.

[0055] However, the existing construction method of the polar code produces a large number of new code types under rate matching, which increases the complexity of hardware implementation.

[0056] An example is given below to illustrate the reason for producing new code types in the puncturing mode.

[0057] Suppose that the reliability sequence with a length of 16 is [0 1 2 4 8 3 5 6 9 10 12 7 11 13 14 15], and the reliability sequence with a length of 32 is [0 1 2 4 8 16 3 5 6 9 10 17 12 18 20 24 7 11 13 19 14 21 22 25 26 28 15 23 27 29 30 31].

[0058] For a reliability sequence with a length of 32, the remaining bits after the first 12 bits are pre-frozen, and the bits are arranged in order of reliability from low to high, the reliability sequence is [16 17 12 18 20 24 13 19 14 21 22 25 26 28 15 23 27 29 30 31], and the 18 bits with the highest reliability are read as information bits, that is, [12 18 20 24 13 19 14 21 22 25 26 28 15 23 27 29 30 31]. In the 0th subblock with a length of 16, that is, the bits with bit position indexes of 0-15, the information bits are [12 13 14 15]. Compared with the reliability sequence with a length of 16, it can be found that there is a pre-frozen bit 11 with a higher reliability than the non-pre-frozen bit 12 with the lowest reliability. Therefore, when the number of information bits in the bits with bit position indexes of 0-15 is 4 under the mother code length, the information bits are [11 13 14 15], thereby generating a new code type under the puncturing mode.

[0059] To reduce the new code type, an embodiment of the present application proposes that, in a subblock with a length of 2 n , the number of pre-frozen bits with a higher reliability than the non-pre-frozen bit with the lowest reliability is less than or equal to a threshold value. The smaller the threshold value is, the fewer the new code types are. As an example, when the threshold value is 0, no new code type appears after rate matching.

[0060] The technical solution of the embodiment of the present application can be applied to encoding or decoding of a polar code. The technical solution provided by the present application is described in detail below.

[0061] The technical solution of the embodiment of the present application can be applied to various existing communication systems and future communication systems, including but not limited to: a satellite communication system, a 5th generation (5G) system or a new radio (NR) system, a long term evolution (LTE) system, an LTE frequency division duplex (FDD) system, an LTE time division duplex (TDD) system, and a future communication system, etc. In addition, it can also be applied to sidelink (SL) communication, vehicle-to-everything (V2X) communication, machine to machine (M2M) communication, machine type communication (MTC), and an internet of things (IoT) communication system or other communication systems, etc., which are not limited herein.

[0062] FIG. 1 is an example of a communication system to which the embodiments of the present application are applicable. As shown in FIG. 1, the communication system can include one or more transmitting ends and one or more receiving ends. Optionally, one of the transmitting end and the receiving end can be a terminal device, and the other can be a network device. The encoding or decoding method provided by the embodiments of the present application can be applicable to the communication between the network device and the terminal device shown in FIG. 1, i.e., uplink communication or downlink communication. For example, in downlink communication, the transmitting end (or the encoding device) of the embodiments of the present application is a network device, and the receiving end (or the decoding device) is a terminal device; in uplink communication, the transmitting end (or the encoding device) of the embodiments of the present application is a terminal device, and the receiving end (or the decoding device) is a network device.

[0063] Exemplarily, the terminal device can also be referred to as a user equipment (UE), an access terminal, a user unit, a user station, a mobile station, a mobile station, a mobile terminal (MT), a remote station, a remote terminal, a mobile device, a user terminal, a terminal, a wireless communication device, a user agent or a user apparatus. The terminal device in the embodiments of the present application can be a device providing voice and / or data connectivity for a user, and can be used to connect people, things and machines, such as handheld devices with wireless connection function, vehicle-mounted devices, etc. The terminal device in the embodiments of the present application can be a mobile phone, a pad, a notebook computer, a palm computer, a mobile internet device (MID), a wearable device, a virtual reality (VR) device, an augmented reality (AR) device, a wireless terminal in industrial control, a wireless terminal in self-driving, a wireless terminal in remote medical surgery, a wireless terminal in smart grid, a wireless terminal in transportation safety, a wireless terminal in smart city, a wireless terminal in smart home, etc. Optionally, the UE can be used to act as a base station. For example, the UE can act as a scheduling entity, which provides sidelink signals between UEs in V2X or SL, etc.

[0064] In the embodiments of the present application, the apparatus for implementing the functions of the terminal device can be a terminal device, or an apparatus capable of supporting the terminal device to implement the corresponding functions, such as a chip, a chip system, a hardware circuit, a software module, or a combination of hardware circuit and software module. The apparatus can be configured in the terminal device, or used in matching with the terminal device. The chip system can be composed of a chip, or include a chip and other discrete devices. In the embodiments of the present application, only the apparatus for implementing the corresponding functions of the terminal device is taken as an example for description.

[0065] The network device in the embodiments of the present application can include a device for communicating with a terminal device, and the network device can include an access network device or a radio access network device, for example, the network device can be a base station. The access network device in the embodiments of the present application can refer to a radio access network (RAN) node (or device) that accesses a terminal device to a wireless network. The base station can broadly cover the following various names, or be replaced by the following names, for example: Node B (NodeB), evolved Node B (eNB), next generation Node B (gNB), relay station, access point, transmitting and receiving point (TRP), transmitting point (TP), primary station, secondary station, motor slide retainer (MSR) node, home base station, network controller, access node, wireless node, access point (AP), transmission node, transceiver node, baseband unit (BBU), remote radio unit (RRU), active antenna unit (AAU), remote radio head (RRH), central unit (CU), distributed unit (DU), radio unit (RU), positioning node, etc. The base station can be a macro base station, a micro base station, a relay node, a donor node or a combination thereof. The base station can also refer to a communication module, modem or chip used in the aforementioned device or apparatus. The base station can also be a mobile switching center and a device that performs the function of a base station in D2D, V2X, M2M communication, a network device (such as a base station) in a future communication network or a device that performs the function of a network device, etc. The base station can support networks of the same or different access technologies. Optionally, the RAN node can also be a server, a wearable device, a vehicle or a vehicle-mounted device, etc. For example, the access network device in the vehicle to everything (V2X) technology can be a road side unit (RSU). The embodiments of the present application do not limit the specific technology and specific device form of the network device.

[0066] The base station can be fixed or mobile. For example, a helicopter or a drone can be configured to act as a mobile base station, and one or more cells can move according to the location of the mobile base station. In other examples, the helicopter or the drone can be configured to serve as a device that communicates with another base station.

[0067] In some deployments, the network device in the embodiments of the present application can be a device including a CU, or a DU, or a device including a CU and a DU, or a control plane CU node (central unit-control plane, CU-CP) and a user plane CU node (central unit-user plane, CU-UP), and a DU node. For example, the network device can include a gNB-CU-CP, a gNB-CU-UP, and a gNB-DU.

[0068] In some deployments, wireless access is assisted by a plurality of RAN nodes cooperating to assist a terminal, and different RAN nodes respectively implement part of the functions of a base station. For example, the RAN node can be a CU, a DU, a CU-CP, a CU-UP, or an RU, etc. The CU and the DU can be separately arranged, or can also be included in the same network element, such as a BBU. The RU can be included in a radio frequency device or a radio frequency unit, such as an RRU, an AAU, or an RRH.

[0069] In different systems, the CU (or CU-CP and CU-UP), DU, or RU can also have different names, but those skilled in the art can understand their meanings. For example, in an open radio access network (open RAN, ORAN / O-RAN) system, the CU can also be referred to as an open CU (O-CU), and the DU can also be referred to as an open DU (O-DU). The CU-CP can also be referred to as an O-CU-CP, the CU-UP can also be referred to as an O-CU-UP, and the RU can also be referred to as an O-RU. Any one of the CU (or CU-CP, CU-UP), DU, and RU in the embodiments of the present application can be implemented by a software module, a hardware module, or a combination of a software module and a hardware module.

[0070] In the embodiments of the present application, the device for implementing the functions of the network device can be a network device; or can be a device capable of supporting the network device to implement the corresponding functions, such as a chip system, a hardware circuit, a software module, or a combination of a hardware circuit and a software module. The device can be configured in the network device or used in combination with the network device. In the embodiments of the present application, only the device for implementing the corresponding functions of the network device is taken as an example for description.

[0071] FIG. 2 is a schematic diagram of a basic flow of wireless communication. As shown in FIG. 2, at the sending end of a signal, a signal source is sequentially subjected to source encoding, channel encoding, and digital modulation, and then is sent out. At the receiving end of the signal, the received signal is sequentially subjected to digital demodulation, channel decoding, and source decoding, and then a signal sink is output. Among them, channel encoding and decoding is one of the core technologies in the field of wireless communication.

[0072] The encoding method or decoding method provided by the present application, i.e., the channel encoding or channel decoding scheme, can be applied to a special network device or a general network device, and can be applied to the various network devices (e.g., base stations) described above, and can also be applied to the various terminal devices described above. Specifically, the channel encoding scheme is mainly implemented by a channel encoding unit (e.g., an encoder) in these devices; and the channel decoding scheme is mainly implemented by a channel decoding unit (e.g., a decoder) in these devices.

[0073] FIG. 3 is a schematic flowchart of the method 300 of encoding or decoding provided by the present application. Steps 310-330 and optional step 340 in the method 300 can be performed by an encoding device, or by an apparatus (e.g., a chip, a chip system, or a circuit, etc.) applied to the encoding device. Correspondingly, steps 350-370 and optional step 380 can be performed by a decoding device, or by an apparatus (e.g., a chip, a chip system, or a circuit, etc.) applied to the decoding device. In the following embodiments, the encoding device or the decoding device is taken as an example.

[0074] In addition, in the following embodiments, “information bit” can be replaced by “information bit”, “frozen bit” can be replaced by “frozen bit”, “pre-frozen bit” can be replaced by “pre-frozen bit”; other expressions can also be similarly replaced, for example, “pre-frozen bit set” can be replaced by “pre-frozen bit set”, “information bit set” can be replaced by “information bit set”, and the like, which will not be listed one by one.

[0075] 310、The encoding device obtains a first bit sequence to be encoded.

[0076] The first bit sequence includes K bits, and K is an integer greater than 1.

[0077] As some examples, the first bit sequence can include information bits, cyclic redundancy check (CRC) bits, and parity check (PC) bits; or the first bit sequence includes information bits and CRC bits; or the first bit sequence includes information bits and parity check bits; or the first bit sequence includes information bits only. K can be the length of the first bit sequence. For example, K can be the sum of the number of information bits, the number of CRC bits, and the number of parity check bits included in the first bit sequence. Alternatively, K can be the sum of the number of information bits and the number of CRC bits included in the first bit sequence. Alternatively, K can be the sum of the number of information bits and the number of PC bits included in the first bit sequence, or K can be the number of information bits included in the first bit sequence.

[0078] 320、The encoding device determines a first bit position set according to the first reliability sequence of the polar code.

[0079] In the embodiments of the present application, the first bit position set is used to indicate the bit positions in the first reliability sequence that are frozen when determining the information bit position set. As described above, when the rate matching specifically adopts the puncturing manner, the pre-frozen bits are determined before the information bit set and the frozen bit set are determined. The first bit position herein can be alternatively described as the pre-frozen bit position set. Alternatively, the bit positions in the first bit position set are the pre-frozen bit positions.

[0080] Optionally, the bit positions in the first reliability sequence can be arranged in an order from low to high reliability of the polarization sub-channels, or in an order from high to low reliability.

[0081] For the i-th sub-block (which can also be referred to as a sub-sequence), i is an integer, in other words, the index value of the sub-block starts from 0. It should be noted that in the embodiments of the present application, the sub-block is described by taking the index value starting from 0 as an example, and the index value of the sub-block can also start from 1. Based on the content disclosed in the present application, those skilled in the art can know the implementation when the index value starts from 1, which is not described herein. i is an integer, i is greater than or equal to 0 and i is less than L, L is the number of sub-blocks contained in the first reliability sequence.

[0082] In the method of the first aspect, the i-th sub-block refers to a set of bit positions with index values within a certain range. For the i-th sub-block, it refers to a set of bit positions with index values greater than or equal to i*2 n and less than (i+1)*2 n , n is a positive integer. As an example, if the length of the sub-block is 16, the 0-th sub-block refers to a set of 16 bit positions with index values of 0-15; the 1-st sub-block refers to another set of 16 bit positions with index values of 16-31, and so on.

[0083] The first bit position set includes a first bit position, and the first bit position is a bit position belonging to the i-th sub-block. The i-th sub-block is a set of bit positions with index values greater than or equal to i*2 n and less than (i+1)*2 na set of bit positions, n is a positive integer, i is an integer, i is greater than or equal to 0 and i is less than L. Thus, it can be understood that for a sub-block of a certain length, when i is a specific value, the first bit position in the set of bit positions includes the bit positions belonging to the i-th sub-block, and can also include the bit positions of other sub-blocks other than the i-th sub-block. As an example, for a sub-block of length 16 or length 8, for the 0-th sub-block, the first bit position refers to the bit positions belonging to the 0-th sub-block in the first set of bit positions; for the 1-th sub-block, the first bit position refers to the bit positions belonging to the 1-th sub-block in the first set of bit positions. In the first bit position, the number of first bit positions whose reliability is higher than that of the second bit position in the i-th sub-block is less than or equal to a threshold; wherein the second bit position refers to the bit position in the i-th sub-block that does not belong to the first set of bit positions and has the lowest reliability.

[0084] As described above, the first set of bit positions actually refers to a set of pre-frozen bit positions, and thus all the first set of bit positions are pre-frozen bit positions, and these pre-frozen bit positions can include bit positions belonging to the i-th sub-block. The i-th sub-block includes bit positions with index values in a certain range, some of which are pre-frozen bits and some of which are non-pre-frozen bits, and any one of the non-pre-frozen bits does not belong to the first set of bit positions. In the non-pre-frozen bits, each non-pre-frozen bit corresponds to a reliability, and there is a non-pre-frozen bit with the lowest reliability in the non-pre-frozen bits, which is the second bit position in the i-th sub-block as described in the embodiments of the present application. In other words, the second bit position is the non-pre-frozen bit with the lowest reliability in the i-th sub-block. In the embodiments of the present application, in the first bit positions included in the first set of bit positions, the number of first bit positions whose reliability is higher than that of the second bit position is less than or equal to a threshold, so as to ensure that as few new code types as possible are generated after rate matching. As an example, when the threshold is 0, no new code type is generated after rate matching; when the threshold is an integer greater than 0, the smaller the threshold, the fewer new code types generated after rate matching, thereby reducing the complexity of hardware implementation of the decoding device.

[0085] Optionally, as an example, i traverses values in [0, 1, 2, …, L-1].

[0086] It should be understood that when i traverses values in [0, 1, 2, …, L-1], it means that each sub-block included in the first reliability sequence satisfies the above characteristics. At this time, the number of new code types generated after puncturing will be reduced to the greatest extent, thereby reducing the complexity of hardware implementation to the greatest extent. In addition, for the decoding side, the highest decoding efficiency will also be achieved.

[0087] 330、The encoding device encodes the first bit sequence according to the first bit position set to obtain an encoded bit sequence.

[0088] Specifically, the encoding device determines the information bit set according to the first bit position set. Further, the first bit sequence to be encoded is encoded according to the information bit set to obtain the encoded bit sequence.

[0089] Optionally, the method 300 further includes step 340.

[0090] 340、The encoding device outputs the encoded bit sequence.

[0091] Correspondingly, the decoding process of the decoding device can include steps 350-370 and optional step 380.

[0092] 350、The decoding device obtains the received value sequence.

[0093] 360、The decoding device determines the first bit position set according to the first reliability sequence of the polar code.

[0094] Step 360 can refer to the description in step 320, and will not be repeated here.

[0095] 370、The decoding device decodes the received value sequence according to the first bit position set to obtain a decoded bit sequence.

[0096] 380、The decoding device outputs the decoded bit sequence.

[0097] To sum up, in the embodiments of the present application, by limiting: in a sub-block with a length of 2 n , the number of pre-frozen bits with a higher reliability than the non-pre-frozen bit with the lowest reliability is less than or equal to a threshold value, the generation of new code types after rate matching can be reduced, the hardware implementation can be simplified, and the hardware implementation complexity can be reduced.

[0098] The technical solutions of the present application will be illustrated by several examples.

[0099] Example 1

[0100] The threshold value is 0, the first reliability sequence adopts a corresponding length reliability sequence in new radio (NR), the sub-block length is 2 n , and the bit positions with index values greater than or equal to 0 and less than F in the first reliability sequence are pre-frozen in the natural order of the position index (i.e., in the order of the position index from small to large), and the F bit positions that are pre-frozen constitute the first bit position set, that is, the pre-frozen bit position set. F is a positive integer multiple of 2 n .

[0101] As an example, the sub-block length is 16, F can be divided by 16 (i.e. F is a positive integer multiple of 16).

[0102] In the setting of example 1, the encoding process can be as follows:

[0103] 1. Determine the mother code length N.

[0104] Suppose the number of information bits is K, the length after rate matching (i.e. the length of the encoding block) is E, and R = K / E is the code rate. Here, N is calculated as the smallest power of 2 greater than or equal to E as the mother code length, for example: E = 252, N = 256; for E = 5, N = 8.

[0105] 2. Select the rate matching method.

[0106] According to K / E, determine the rate matching method and the rate matching position set Q.

[0107] 1) Determine the rate matching method. As an example, if K / E ≤ 7 / 16, select the rate matching method as puncturing; otherwise, select the rate matching method as shortening.

[0108] 2) Determine the rate matching position set Q. As an example, when puncturing is used, puncture the first N-E positions, and the punctured positions are referred to as set Q; when shortening is used, shorten the last N-E positions, and the shortened positions are referred to as set Q. Since the bit positions in set Q do not correspond to bits that are transmitted, any code length can be matched.

[0109] 3. Polar code construction.

[0110] If puncturing is used, two information bit sets are obtained according to a first reliability sequence (hereinafter referred to as reliability sequence S), and the union of the two information bit sets is determined as the information bit set for polar encoding.

[0111] As an example, the length of the reliability sequence S is 64, and the reliability sequence in NR is used.

[0112] For example, N = 64, and the reliability sequence S = [0 1 2 4 8 16 32 35 9 6 17 10 18 12 33 20 34 24 36 7 11 40 19 13 48 14 21 35 26 37 25 22 38 41 28 42 49 44 50 15 52 23 56 27 39 29 43 30 45 51 46 53 54 57 58 60 31 47 55 59 61 62 63].

[0113] The first bit position set is determined, i.e., the pre-frozen bit set is determined, to ensure that the number of pre-frozen bits with higher reliability than the non-pre-frozen bit with the lowest reliability in the sub-block with a length of 2 n is less than or equal to a threshold value. As an example, the threshold value is 0. The process of determining the first bit position set can specifically include the following processes:

[0114] 1) Determine the first pre-frozen bit set according to E and N

[0115] As an example, when N is less than or equal to 256, the number of frozen bits (or frozen bits) is F, When N is greater than 256, the number of frozen bits is After determining the number of frozen bits F, the first F bits are frozen in natural order. If the position index starts from 0, the bit positions with position indexes greater than or equal to 0 and less than F in the reliability sequence S are pre-frozen. In example 1, the number of pre-frozen bits F can be an integer multiple of 16.

[0116] 2) Obtain the first information bit set from the reliability sequence S and the first pre-frozen bit set

[0117] As an example, from the reliability sequence S, the position indexes in the first pre-frozen bit set are removed to obtain the reliability sequence S1. The reliability sequence S1 is used to determine the first information bit set

[0118] For example, taking N=64 and E=42 as an example, the reliability sequence S is [0 1 2 4 8 16 32 3 5 9 6 17 10 18 12 33 20 34 24 36 7 11 40 19 13 48 14 21 35 26 37 25 22 38 41 28 42 49 44 50 15 52 23 56 27 39 29 43 30 45 51 46 53 54 57 58 60 31 47 55 59 61 62 63];

[0119] ​According to the values of E and N, the number of frozen bits F = 32 can be calculated, and according to the pre-freezing rule given in Example 1, the first 32 bits are pre-frozen in order of the position index from small to large, thereby obtaining a reliability sequence S1 = [32 33 34 36 40 48 35 37 38 41 42 49 44 50 52 56 39 43 45 51 46 53 54 57 58 60 47 55 59 61 62 63], and the length of the reliability sequence S1 is 32.

[0120] a) When puncturing is used, parameter Z is determined according to E / N i , i = {0, 1}. As an example, the value of Z i is between [0, 1]. It should be noted that Z i here is only an example with 2 values (Z0 and Z1), and Z i essentially is a segment, and there can be more segments. In an example, Z0 = 3 / 4, and Z1 = 5 / 8.

[0121] b) If puncturing is used, T is determined according to K, E, and N. As an example, one method is to determine the threshold T according to the relationship between K, E / N, and Z i . This can be shown in Table 1:

[0122] Table 1

[0123] c) The first information bit set is determined according to the reliability sequence S1

[0124] As an example, one implementation can be that T bits are read from the reliability sequence S1 from back to front as information bits (that is, the indexes of the T bit positions are read in order of reliability from high to low). For example, K = 18, T = 15,

[0125] d) The second pre-frozen bit set is determined according to E and N

[0126] As an example, the first N / 2 bits are pre-frozen. For example, when N = 64, E = 42,

[0127] e) The second information bit set is obtained according to the reliability sequence S and the second pre-frozen bit set

[0128] ​As an example, one implementation can be: from the reliability sequence S, remove the indices in the second pre-frozen bit set The reliability sequence S2 is used to determine the second information bit set of the polar code. For example, taking N = 64, E = 42 as an example, the reliability sequence S2 = [32 33 34 36 40 48 35 37 38 41 42 49 44 50 52 56 39 43 45 51 46 53 54 57 58 60 47 55 59 61 62 63], with a length of 32.

[0129] f) determining the second information bit set according to the reliability sequence S2

[0130] As an example, one implementation can be: from the reliability sequence S2, read out the K-T bit positions not in the first information bit set from back to front (i.e. in the order of reliability from high to low) as information bits. For example, K = 18, T = 15, the first information bit set and the second information bit set constitute the information bit set For example, when K = 18, T = 15,

[0131] As can be seen from the above process, the process of determining the information bit set by the encoding device can be realized in two steps: first, determine the first pre-frozen bit set, and determine the first information bit set according to the first pre-frozen bit set; second, determine the second pre-frozen bit set, and determine the second information bit set according to the second pre-frozen bit set. Finally, the union of the first information bit set and the second information bit set is the information bit set when polar encoding is performed.

[0132] 4. Polar encoding and rate matching.

[0133] The encoding device performs polar encoding according to the information bit set to obtain a coded bit sequence. Then, rate matching is performed on the coded bit sequence to obtain E bits. The encoding device transmits the E bits. The E bits are the E bits obtained after rate matching of the coded bit sequence with a length of N.

[0134] In Example 1, since the threshold value is 0, the reliability of any one non-pre-frozen bit in the 16-long sub-block is higher than the reliability of any one pre-frozen bit, which can ensure that the 16-long sub-block will not appear a new code type after rate matching, and the performance is stable.

[0135] Example 2

[0136] Threshold value is 0, the first reliability sequence can adopt a different reliability sequence from the corresponding length reliability sequence in NR, and the sub-block length is 2 n , the F bit positions with index values greater than or equal to 0 and less than F in the first reliability sequence are pre-frozen in the natural order of the position index (i.e., in the order of the position index from small to large). F is the number of pre-frozen bits. F is 2 n modulus remainder is 2 n -3.

[0137] As an example, the sub-block length is 16, and the modulus remainder of F mod 16 is 13.

[0138] In the setting of Example 2, the encoding process can be as follows:

[0139] 1. Determine the mother code length N.

[0140] Assuming the number of information bits is K, the length after rate matching (i.e., the length of the encoding block) is E, and R = K / E is the code rate. Wherein, calculate N as the smallest power of 2 greater than or equal to E as the mother code length, for example: E = 252, N = 256; for E = 5, N = 8.

[0141] 2. Select the rate matching mode.

[0142] According to K / E, determine the rate matching mode and the rate matching position set Q.

[0143] 1) Determine the rate matching mode. As an example, if K / E ≤ 7 / 16, select the rate matching mode as puncturing; otherwise, select the rate matching mode as shortening.

[0144] 2) Determine the rate matching position set Q. As an example, when puncturing is used, the first N-E positions are punctured, and the punctured positions are referred to as set Q; when shortening is used, the last N-E positions are shortened, and the shortened positions are set Q. Since the positions in set Q correspond to bits that are not transmitted, any code length can be matched.

[0145] 3. Polar code construction.

[0146] If puncturing is used, two information bit sets are obtained according to the first reliability sequence (referred to as reliability sequence S), and the union of the two information bit sets is determined as the information bit set for polar encoding.

[0147] As an example, the reliability sequence S can satisfy that each sub-block with length 16 has the same reliability order, that is, the reliability order of the i-th sub-block with length 16, that is, the reliability order of the i*16-th to (i+1)*16-1 bit positions, minus i*16, i being an integer greater than or equal to 0.

[0148] For example, N=64, the reliability sequence S=[0 1 2 4 8 16 32 3 5 6 9 10 17 12 18 33 20 34 24 7 36 11 40 13 48 19 14 21 35 22 25 37 26 38 28 41 15 42 49 44 50 23 52 27 56 39 29 30 43 45 51 46 53 54 57 31 58 60 47 55 59 61 62 63]; the reliability order of the 0-th sub-block with length 16, 0~15, is [0 1 2 4 8 3 5 6 9 10 12 7 11 13 14 15], the reliability order of the 1-st sub-block with length 16, 16~31, is [16 17 18 20 24 19 21 22 25 26 28 23 27 29 30 31], the reliability order of the 1-st sub-block with length 16, 16~31, minus 16 is [0 1 2 4 8 3 5 6 9 10 12 7 11 13 14 15], which is the same as the reliability order of the 0-th sub-block.

[0149] First, a first set of bit positions, that is, a first set of pre-frozen bits, is determined to ensure that in a sub-block with length 2 n , the number of pre-frozen bits with higher reliability than the non-pre-frozen bit with the lowest reliability is less than or equal to a threshold value. As an example, the threshold value is 0.

[0150] The first F bits are taken as the first set of pre-frozen bits F is determined by E and N, and the value of F modulo 16 is 13. As an example, one method is that when N is less than or equal to 256, the first is taken as the first set of pre-frozen bits; when N is greater than 256, the first is taken as the first set of pre-frozen bits.

[0151] A first set of information bits is determined according to the reliability sequence S and the first set of pre-frozen bits

[0152] As an example, one method can be that from the reliability sequence S, the first set of pre-frozen bits ​remove the position index from the reliability sequence S to obtain a reliability sequence S1. The reliability sequence S1 is used to determine a first information bit set of the polar code

[0153] For example, N = 64, E = 42, the reliability sequence S = [0 1 2 4 8 16 32 3 5 6 9 10 17 12 18 33 20 34 24 7 36 11 40 13 48 19 14 21 35 22 25 37 26 38 28 41 15 42 49 44 50 23 52 27 56 39 29 30 43 45 51 46 53 54 57 31 58 60 47 55 59 61 62 63].

[0154] According to the values of E and N, the number of frozen bits F = 29 is calculated, according to the frozen rule in Example 2, the first 29 bits before freezing are the first frozen bit set, that is, remove the index values 0-28 from the reliability sequence S to obtain the reliability sequence S1; then S1 = [32 33 34 36 40 48 35 37 38 41 42 49 44 50 52 56 39 29 30 43 45 51 46 53 54 57 31 58 60 47 55 59 61 62 63], the length of the reliability sequence S1 is 35.

[0155] a) When puncturing is used, determine the parameter Z according to E / N i , i = {0, 1}. For the description of Z i , see Example 1, which will not be repeated here.

[0156] b) If puncturing is used, determine T according to K, E, N. As an example, a method is to determine the threshold T according to the relationship between K, E / N and Z i , which can be shown in Table 1.

[0157] c) Determine the first information bit set of the polar code according to the reliability sequence S1

[0158] As an example, from the reliability sequence S1, read out T subchannel indexes as information bits from back to front in order of reliability from high to low. For example, K = 18, T = 15,

[0159] d) Determine the second pre-frozen bit set according to E and N

[0160] As an example, the first N / 2 bits are used as the pre-freeze bits. For instance, when N = 64 and E = 42, the second set of frozen bits is the sub-channel index from index 0 to 31.

[0161] e) Based on the reliability sequence S and the second pre-frozen bit set Obtain the second set of information bits

[0162] As an example, a specific method could be: based on the reliability sequence S, remove the set of the second pre-frozen bits. The reliability sequence S2 is obtained by using the index in the code. The reliability sequence S2 is used to determine the set of the second information bits of the polar code. For example, with N=64 and E=42, the reliability sequence S2 = [32 33 34 36 40 48 35 37 38 41 42 49 44 50 52 56 39 43 45 51 46 53 54 57 58 60 47 55 59 61 62 63]; the length of the reliability sequence S2 is 32.

[0163] f) Determine the second information bit set of the polar code based on the reliability sequence S2.

[0164] As an example, read from the reliability sequence S2 backwards the information that is not in the first information bit set. The sub-channel index is the information bit. For example, K=18, T=15. First information bit set With the second set of information bits Constitutes a set of information bits For example, when K = 18 and T = 15,

[0165] 4. Polar coding and rate matching.

[0166] The encoding device performs polar coding based on the information bit set to obtain an encoded bit sequence. Then, it performs rate matching on the encoded bit sequence to obtain E bits. The encoding device then transmits these E bits.

[0167] In Example 2, since the 16-length sub-blocks are either all pre-frozen or not pre-frozen, it can be guaranteed that no new code patterns will appear in the 16-length sub-blocks under punching. The three most reliable positions in the 16-length sub-blocks are not pre-frozen, resulting in more stable performance under short codes.

[0168] Example 3

[0169] The threshold is 0, the first reliability sequence can be different from the corresponding length reliability sequence in NR, and the sub-block length is 2 n The F bit positions in the first reliability sequence with index values greater than or equal to 0 and less than F are pre-frozen in the natural order of the position index (that is, in the order of the position index from small to large), and F is the number of pre-frozen bits. F is a positive integer multiple of 2 n .

[0170] The difference between Example 3 and Example 1 can be that the first reliability sequence in Example 3 is different from the corresponding length reliability sequence in NR used in Example 1. For example, the first reliability sequence in Example 3 can be obtained by re-searching, which is not limited.

[0171] As an example, the sub-block length is 16, and F is a positive integer multiple of 16 (that is, F modulo 16 is 0).

[0172] Under the setting of Example 3, the encoding process can be as follows:

[0173] 1. Determine the mother code length N.

[0174] 2. Select the rate matching method.

[0175] The above two processes can refer to the description in Example 1 or Example 2, and will not be repeated here.

[0176] 3. Polar code construction.

[0177] If puncturing is used, two information bit sets are obtained according to the reliability sequence S, and the union of the two information bit sets is determined as the information bit set for polar encoding.

[0178] As an example, the reliability sequence S can satisfy that each sub-block with a length of 16 has the same reliability order, in other words, the reliability order of the i-th sub-block with a length of 16, that is, the reliability order of the i*16 to (i+1)*16-1 bit positions minus i*16, i is an integer greater than or equal to 0.

[0179] For example, N=64, the reliability sequence S=[0 1 2 4 8 16 32 3 5 6 9 10 17 12 18 33 20 34 24 7 36 11 40 13 48 19 14 21 35 22 25 37 26 38 28 41 15 42 49 44 50 23 52 27 56 39 29 30 43 45 51 46 53 54 57 31 58 60 47 55 59 61 62 63]; for the 0th subblock with length 16, the reliability order of the subchannel indexes 0~15 is [0 1 2 4 8 3 5 6 9 10 12 7 11 13 14 15], for the 1st subblock with length 16, the reliability order of the subchannel indexes 16~31 is [16 17 18 20 24 19 21 22 25 26 28 23 27 29 30 31], the reliability of the subchannel indexes 16~31 of the 1st subblock minus 16 is [0 1 2 4 8 3 5 6 9 10 12 7 11 13 14 15], which is the same as the reliability order of the subchannel indexes of the 0th subblock.

[0180] The first bit position set, i.e., the pre-frozen bit set, is determined to ensure that the number of pre-frozen bits with higher reliability than the non-pre-frozen bit with the lowest reliability in a subblock with length 2 n is less than or equal to a threshold value. As an example, the threshold value is 0.

[0181] The first F bits are taken as the first pre-frozen bit set F is determined by E and N, and the value of F modulo 16 is 0. As an example, one method is to take the first as the first pre-frozen bit set when N is less than or equal to 256; and take the first as the first pre-frozen bit set when N is greater than 256.

[0182] The first information bit set is determined according to the reliability sequence S and the first pre-frozen bit set

[0183] As an example, one method is to remove the position indexes in the first pre-frozen bit set from the reliability sequence S to obtain a reliability sequence S1. The reliability sequence S1 is used to determine the first information bit set

[0184] ​For example, taking N = 64, E = 42 as an example, the reliability sequence S = [0 1 2 4 8 16 32 3 5 6 9 10 17 12 18 33 20 34 24 7 36 11 40 13 48 19 14 21 35 22 25 37 26 38 28 41 15 42 49 44 50 23 52 27 56 39 29 30 43 45 51 46 53 54 57 31 58 60 47 55 59 61 62 63];

[0185] According to the values of E and N, the number of frozen bits F = 32 is calculated, and according to the pre-freezing rule in Example 3, the first 32 bits before freezing are taken as the first frozen bit set, that is, the first frozen bit set is a set composed of subchannel indexes 0-31, so that the reliability sequence S1 = [32 33 34 36 40 48 35 37 38 41 42 49 44 50 52 56 39 43 45 51 46 53 54 57 58 60 47 55 59 61 62 63] is obtained, and the length of the reliability sequence S1 is 32.

[0186] a) When puncturing is used, parameter Z is determined according to E / N i , i = {0, 1}. For the description of Z i , see Example 1, which will not be repeated here.

[0187] b) If puncturing is used, T is determined according to K, E, and N, as an example, a method is as follows: the threshold T is determined according to the relationship between K, E / N, and Z i , which can be shown in Table 1.

[0188] c) The first information bit set for the polar code is determined according to the reliability sequence S1

[0189] As an example, a method is as follows: T subchannel indexes are read out from the reliability sequence S1 from back to front in the order of reliability from high to low as information bits. For example, K = 18, T = 15,

[0190] d) The second pre-frozen bit set is determined according to E and N

[0191] As an example, the first N / 2 is taken as the pre-frozen bit. For example, when N = 64, E = 42,

[0192] e) Based on the reliability sequence S and the second pre-frozen bit set Obtain the second set of information bits

[0193] As an example, remove the second pre-frozen bit set from the reliability sequence S. The reliability sequence S2 is obtained by using the index in the code. The reliability sequence S2 is used to determine the second information bit set of the polar code. For example, when N=64 and E=42, the reliability sequence S2=[32 33 34 36 40 48 35 37 38 41 42 49 44 50 52 56 39 43 45 51 46 53 54 57 58 60 47 55 59 61 62 63], and the length of the reliability sequence S2 is 32.

[0194] f) Determine the second information bit set of the polar code based on the reliability sequence S2.

[0195] As an example, the specific method is to read from the reliability sequence S2 backwards the information that is not in the first information bit set. The sub-channel index is used as the information bit. For example, K=18, T=15, First information bit set With the second set of information bits Constitutes a set of information bits For example, when K = 18 and T = 15,

[0196] 4. Polar coding and rate matching.

[0197] The encoding device performs polar coding based on the information bit set to obtain an encoded bit sequence. Then, it performs rate matching on the encoded bit sequence to obtain E bits. The encoding device then transmits these E bits.

[0198] In Example 3, since the reliability of any non-pre-frozen bit in a 16-length sub-block is higher than that of any pre-frozen bit, it can be guaranteed that no new code pattern will appear in the 16-length sub-block under punching. The number of pre-frozen bits F is divisible by 16 (that is, the number of pre-frozen bits F modulo 16 leaves a remainder of 0), making the configuration simple.

[0199] Example 4

[0200] The threshold is 0, the first reliability sequence can be different from the reliability sequence of the corresponding length in NR, and the sub-block length is 2. n, the F bit positions in the first reliability sequence are pre-frozen according to the natural order of the position indexes (i.e. according to the order of the position indexes from small to large), F is the number of pre-frozen bits. F is a positive integer multiple of 2 n .

[0201] As an example, the sub-block length is 8, F is 0 modulo 8, or in other words, F is a positive integer multiple of 8.

[0202] Example 4 can differ from Example 1 and Example 3 in that the sub-block length is different. In Example 4, the sub-block length is 8; in Example 1 or Example 3, the sub-block length is 16.

[0203] Under the setting of Example 4, the encoding process can be as follows:

[0204] 1. Determine the mother code length N.

[0205] 2. Select the rate matching method.

[0206] The above two processes can refer to the description in Example 1 or Example 2, and will not be repeated here.

[0207] 3. Polar code construction.

[0208] If puncturing is used, two information bit sets are obtained according to the reliability sequence S, and the union of the two information bit sets is determined as the information bit set for polar encoding.

[0209] As an example, the reliability sequence S can satisfy that each sub-block with a length of 8 has the same reliability order, that is, the reliability order of the i-th sub-block with a length of 8, that is, the reliability order of the i*8 to (i+1)*8-1 bit positions, is the same minus i*8, i is an integer greater than or equal to 0.

[0210] For example, N=64, the reliability sequence S=[0 1 2 4 8 16 32 35 6 9 10 17 12 18 33 20 34 24 7 36 11 40 13 48 19 14 21 35 22 25 37 26 38 28 41 15 42 49 44 50 23 52 27 56 39 29 30 43 45 51 46 53 54 57 31 58 60 47 55 59 61 62 63]; for the 0th subblock with length 8, the reliability order of subchannel indexes 0~7 is [0 1 2 4 3 5 6 7], for the 1st subblock with length 8, the reliability order of subchannel indexes 8~15 is [8 9 10 12 11 13 14 15], the reliability order of subchannel indexes 8~15 of the 1st subblock minus 8 is [0 1 2 4 3 5 6 7], which is the same as the reliability order of subchannel indexes of the 0th subblock.

[0211] The first bit position set, i.e., the pre-frozen bit set, is determined to ensure that in a subblock with length 2 n , the number of pre-frozen bits with higher reliability than the non-pre-frozen bit with the lowest reliability is less than or equal to a threshold value. As an example, the threshold value is 0.

[0212] The first F bits are taken as the first pre-frozen bit set F is determined by E and N, and the value of F modulo 8 is 0. As an example, one method is to take the first as the first pre-frozen bit set when N is less than or equal to 256; and to take the first as the first pre-frozen bit set when N is greater than 256.

[0213] The first information bit set is obtained according to the reliability sequence S and the first pre-frozen bit set

[0214] As an example, one method can be to remove the position indexes in the first pre-frozen bit set from the reliability sequence S to obtain a reliability sequence S1. The reliability sequence S1 is used to determine the first information bit set

[0215] ​For example, when N = 64 and E = 42, the reliability sequence S = [0 1 2 4 8 16 32 3 5 6 9 10 17 12 18 33 20 34 24 7 36 11 40 13 48 19 14 21 35 22 25 37 26 38 28 41 15 42 49 44 50 23 52 27 56 39 29 30 43 45 51 46 53 54 57 31 58 60 47 55 59 61 62 63];

[0216] According to the values of E and N, the number of frozen bits F = 32 is calculated, and according to the freezing rule in Example 4, the first 32 bits before freezing are taken as the first frozen bit set, that is, the first frozen bit set is a set composed of subchannel indexes 0-31, so that the reliability sequence S1 = [32 33 34 36 40 48 35 37 38 41 42 49 44 50 52 56 39 43 45 51 46 53 54 57 58 60 47 55 59 61 62 63] is obtained; the length of the reliability sequence S1 is 32.

[0217] a) When puncturing is used, the parameter Z is determined according to E / N i , i = {0, 1}. For the description of Z i , see Example 1, which will not be repeated here.

[0218] b) If puncturing is used, T is determined according to K, E, and N. As an example, one method is to determine the threshold T according to the relationship between K, E / N, and Z i , which can be shown in Table 1.

[0219] c) The first information bit set for the polar code is determined according to the reliability sequence S1

[0220] As an example, one method is to read out T subchannel indexes from the back to the front from the reliability sequence S1 as information bits. For example, K = 18, T = 15,

[0221] d) The second pre-frozen bit set is determined according to E and N

[0222] As an example, the first N / 2 is taken as the pre-frozen bit. For example, when N = 64 and E = 42,

[0223] e) The second pre-frozen bit set is determined according to the reliability sequence S and the second pre-frozen bit set obtaining a second set of information bits

[0224] For example, with N=64, E=42, the reliability sequence S2=[32 33 34 36 40 48 35 37 38 41 42 49 44 50 52 56 39 43 45 51 46 53 54 57 58 60 47 55 59 61 62 63]; length is 32.

[0225] f) determining a second set of information bits of the polar code according to the reliability sequence S2

[0226] As an example, the specific method is to read out the subchannel indexes not in the first set of information bits from the back to the front in the reliability sequence S2 as information bits. For example, K=18, T=15, the first set of information bits and the second set of information bits constitute a set of information bits For example, when K=18, T=15,

[0227] 4. Polar encoding and rate matching.

[0228] The encoding device polar encodes according to the set of information bits to obtain a sequence of encoded bits. The sequence of encoded bits is then rate matched to obtain E bits. The encoding device transmits the E bits.

[0229] In example 4, because of the subblock of length 8 or all pre-frozen or no pre-frozen, it is guaranteed that the subblock of length 8 does not appear new code types under puncturing. The number of pre-frozen bits can be divisible by 8, and the configuration is simple.

[0230] Example 5

[0231] The threshold is 0, the first reliability sequence can be different from the reliability sequence of the corresponding length in NR, and the subblock length is 2 n , pre-freezing is performed according to the reliability of the position index within each subblock. The number of pre-frozen bits in the first reliability sequence is F. As an example, the subblock length is 16. The first bits of the bit positions from the 0th to the bit to the bit are pre-frozen according to the reliability from low to high. ​​

[0232] In the setup of example 5, the encoding process can be as follows:

[0233] 1. Determine the mother code length N.

[0234] 2. Choose the rate matching method.

[0235] The above two processes can refer to the description in example 1 or example 2, and will not be repeated here.

[0236] 3. Polar code construction.

[0237] If puncturing is adopted, two information bit sets are obtained according to the reliability sequence S and the union of the two information bit sets is determined as the information bit set in polar encoding.

[0238] As an example, the reliability sequence S can satisfy that each sub-block with a length of 16 has the same reliability order, in other words, the reliability order of the i-th sub-block with a length of 16, that is, the reliability order of the i*16 to (i+1)*16-1 bit positions, is subtracted by i*16, i is an integer greater than or equal to 0.

[0239] For example, N=64, the reliability sequence S=[0 1 2 4 8 16 32 3 5 6 9 10 17 12 18 33 20 34 24 7 36 11 40 13 48 19 14 21 35 22 25 37 26 38 28 41 15 42 49 44 50 23 52 27 56 39 29 30 43 45 51 46 53 54 57 31 58 60 47 55 59 61 62 63]; for the 0-th sub-block with a length of 16, the reliability order of the sub-channel index 0~15 is [0 1 2 4 8 3 5 6 9 10 12 7 11 13 14 15], for the 1-st sub-block with a length of 16, the reliability order of the sub-channel index 16~31 is [16 17 18 20 24 19 21 22 25 26 28 23 27 29 30 31]; the reliability order of the sub-channel index 16~31 of the 1-st sub-block is subtracted by 16, which is [0 1 2 4 8 3 5 6 9 10 12 7 11 13 14 15], which is the same as the reliability order of the 0-th sub-block.

[0240] Determine the first bit position set, that is, the pre-frozen bit set, to ensure that the length of the information bit set is 2 nthe number of pre-frozen bits in the sub-blocks of the sub-chunk is less than or equal to a threshold value. As an example, the threshold value is 0.

[0241] determining the first pre-frozen bit set according to the code length E and the mother code length N

[0242] As an example, when N is less than or equal to 256, the number of pre-frozen bits is When N is greater than 256, the number of pre-frozen bits is before pre-frozen bits, and the bits are frozen in order of reliability from low to high of the bit positions in the sub-chunk.

[0243] determining the first information bit set according to the reliability sequence S and the first pre-frozen bit set

[0244] As an example, from the reliability sequence S, the position indexes in the first pre-frozen bit set are removed to obtain a reliability sequence S1. The reliability sequence S1 is used to determine the first information bit set

[0245] For example, N = 64, E = 42, and the reliability sequence S = [0 1 2 4 8 16 32 3 5 6 9 10 17 12 18 33 20 34 24 7 36 11 40 13 48 19 14 21 35 22 25 37 26 38 28 41 15 42 49 44 50 23 52 27 56 39 29 30 43 45 51 46 53 54 57 31 58 60 47 55 59 61 62 63];

[0246] According to E and N, the number of pre-frozen bits F = 27 is calculated, according to the pre-frozen rule in Example 5, the first 16 bits are pre-frozen, and the 11 positions in 16 to 31 are frozen in order of reliability from low to high, that is, [16 17 18 20 24 19 21 22 25 26 28], so as to obtain the reliability sequence S1, S1 = [32 33 34 36 40 48 35 37 38 41 42 49 44 50 23 52 27 56 39 29 30 43 45 51 46 53 54 57 31 58 60 47 55 59 61 62 63], and the length of the reliability sequence S1 is 37. ​

[0247] a) Determine parameter Z according to E / N i , i = {0, 1}. For the description of Z i , see Example 1, which will not be repeated here.

[0248] b) If puncturing is used, determine T according to K, E, N. As an example, one method is to determine threshold T according to the relationship between K, E / N and Z i , which can be shown in Table 1.

[0249] c) Determine the first information bit set of the polar code according to reliability sequence S1

[0250] As an example, one method is to read out the subchannel index i from the back to the front from reliability sequence S1 as information bits. For example, K = 18, T = 15,

[0251] d) Determine the second pre-frozen bit set according to E and N

[0252] As an example, the first N / 2 are taken as pre-frozen bits. For example, when N = 64, E = 42,

[0253] e) Obtain the second information bit set according to the reliability sequence S and the second pre-frozen bit set

[0254] As an example, the specific method can be: remove the indexes in the second pre-frozen bit set from the reliability sequence S to obtain the reliability sequence S2. The reliability sequence S2 is used to determine the second information bit set of the polar code. For example, N = 64, E = 42, the reliability sequence S2 = [32 33 34 36 40 48 35 37 38 41 42 49 44 50 52 56 39 43 45 51 46 53 54 57 58 60 47 55 59 61 62 63], the length of the reliability sequence S2 is 32.

[0255] f) Determine the second information bit set of the polar code according to the reliability sequence S2

[0256] As an example, one method is to read out the subchannel index i from the back to the front from reliability sequence S2 as information bits which are not in the first information bit set ​The subchannel index in the middle as an information bit. For example, K = 18, T = 15, The first set of information bits The second set of information bits The set of information bits For example, when K = 18, T = 15,

[0257] 4. Polar encoding and rate matching.

[0258] In Example 5, pre-freezing according to reliability within each subblock can ensure that a 16-length subblock does not appear new code types under puncturing, and the hardware configuration is simple.

[0259] Example 6

[0260] The threshold is 1, the first reliability sequence can be different from the corresponding length reliability sequence in NR, and the subblock length is 2 n In each subblock, the F bit positions with index values greater than or equal to 0 and less than F in the first reliability sequence are pre-frozen in the natural order of the position index (that is, in the order of the position index from small to large), and F is the number of pre-frozen bits.

[0261] As an example, the subblock length is 16, and the remainder of F modulo 16 is 12.

[0262] Under the setting of Example 6, the encoding process can be as follows:

[0263] 1. Determine the mother code length N.

[0264] 2. Select the rate matching method.

[0265] The above two processes can refer to the description in Example 1 or Example 2, and will not be repeated here.

[0266] 3. Polar code construction.

[0267] If puncturing is used, two sets of information bits are obtained according to the reliability sequence S, and the union of the two sets of information bits is determined as the set of information bits for polar encoding.

[0268] As an example, the reliability sequence S can satisfy that each 16-length subblock has the same reliability order, in other words, the reliability order of the i-th 16-length subblock, that is, the reliability order of the i*16 to the (i+1)*16-1 bit position minus i*16, i is an integer greater than or equal to 0.

[0269] For example, N=64, reliability sequence S=[0 1 2 4 8 16 32 3 5 6 9 10 17 12 18 33 20 34 24 7 36 11 40 13 48 19 14 21 35 22 25 37 26 38 28 41 15 42 49 44 50 23 52 27 56 39 29 30 43 45 51 46 53 54 57 31 58 60 47 55 59 61 62 63]; the 0th subblock with length 16, the reliability order of subchannel indexes 0~15 is [0 1 2 4 8 3 5 6 9 10 12 7 11 13 14 15], the 1st subblock with length 16, the reliability order of subchannel indexes 16~31 is [16 17 18 20 24 19 21 22 25 26 28 23 27 29 30 31]; the reliability order of subchannel indexes 16~31 of the 1st subblock is subtracted by 16, which is [0 1 2 4 8 3 5 6 9 10 12 7 11 13 14 15], same as the reliability order of the 0th subblock.

[0270] A first bit position set, i.e., a pre-frozen bit set, is determined to ensure that in a subblock with length 2 n , the number of pre-frozen bits with higher reliability than the non-pre-frozen bit with the lowest reliability is less than or equal to a threshold value. As an example, the threshold value is 1.

[0271] The first F bits are taken as the first pre-frozen bit set F is determined by E and N, and the value of F modulo 16 is 12. As an example, one method is: when N is less than or equal to 256, the first position indexes are taken as the first pre-frozen bit set; when N is greater than 256, the first position indexes are taken as the first pre-frozen bit set.

[0272] A first information bit set is determined according to the reliability sequence S and the first pre-frozen bit set

[0273] As an example, from the reliability sequence S, the position indexes in the first pre-frozen bit set are removed to obtain a reliability sequence S1, and the length of S1 is less than or equal to E. The reliability sequence S1 is used to determine the first information bit set of the polar code

[0274] ​For example, N = 64, E = 42, the reliability sequence S = [0 1 2 4 8 16 32 3 5 6 9 10 17 12 18 33 20 34 24 7 36 11 40 13 48 19 14 21 35 22 25 37 26 38 28 41 15 42 49 44 50 23 52 27 56 39 29 30 43 45 51 46 53 54 57 31 58 60 47 55 59 61 62 63];

[0275] According to E and N, the number of pre-frozen bits F = 28 can be calculated, and then S1 = [32 33 34 36 40 48 35 37 38 28 41 42 49 44 50 52 56 39 29 30 43 45 51 46 53 54 57 31 58 60 47 55 59 61 62 63], the length of the reliability sequence S1 is 35.

[0276] a) Determine parameter Z according to E / N i , i = {0, 1}. For the description of Z i , see Example 1, which will not be repeated here.

[0277] b) If puncturing is used, determine T according to K, E, N, as an example, a method is to determine the threshold T according to the relationship between K, E / N and Z i , which can be shown in Table 1.

[0278] c) Determine the first information bit set for the polar code according to the reliability sequence S1

[0279] As an example, a method is to read out T sub-channel indexes from the back to the front from the reliability sequence S1 as information bits. For example, K = 18, T = 15,

[0280] d) Determine the second pre-frozen bit set according to E and N

[0281] As an example, the first N / 2 is taken as a pre-frozen bit. For example, when N = 64, E = 42,

[0282] e) Obtain the second information bit set according to the reliability sequence S and the second pre-frozen bit set

[0283] ​As an example, a method can be: removing the position indexes in the second pre-frozen bit set from the reliability sequence S, to obtain a reliability sequence S2. The reliability sequence S2 is used to determine a second information bit set of the polar code. For example, N = 64, E = 42, the reliability sequence S2 = [32 33 34 36 40 48 35 37 38 41 42 49 44 50 52 56 39 43 45 51 46 53 54 57 58 60 47 55 59 61 62 63], and the length of the reliability sequence S2 is 32.

[0284] f) determining a second information bit set of the polar code according to the reliability sequence S2

[0285] As an example, a method is to read out the subchannel indexes not in the first information bit set from the back to the front in the reliability sequence S2 as information bits. For example, K = 18, T = 15, the first information bit set and the second information bit set constitute an information bit set For example, when K = 18, T = 15,

[0286] 4. Polar encoding and rate matching.

[0287] In example 6, within each subblock, pre-freezing is performed in a natural order, and the number of pre-frozen bits whose reliability is higher than that of the non-pre-frozen bit with the lowest reliability is less than or equal to a threshold 1 in a subblock with a length of 2 n The number of pre-frozen bits whose reliability is higher than that of the non-pre-frozen bit with the lowest reliability is less than or equal to a threshold 1 in a subblock with a length of 2 n The code pattern of the subblock with a length of 2

[0288] The technical scheme provided by the embodiments of the present application determines a first bit position set, which satisfies the condition that the number of first bit positions whose reliability is higher than that of the second bit position in the i-th subblock is less than or equal to a threshold in the first bit positions contained in the first bit position set, wherein the second bit position is the bit position with the lowest reliability in the i-th subblock and not belonging to the first bit position set, and determines an information bit set based on the first bit position set, which can reduce the new code pattern generated under the puncturing mode of rate matching and can reduce the hardware implementation complexity.

[0289] ​​The above is a detailed description of the method for encoding or decoding the polar code provided in the present application. Next, a communication device provided in the present application is introduced.

[0290] FIG. 4 is a schematic structural diagram of the communication device 1000 provided in the present application. The communication device 1000 can be an encoding device, or a device applied to an encoding device and capable of realizing the corresponding functions of the encoding device in the method embodiments of the present application, such as a chip, a chip system, or a circuit, etc. Alternatively, the communication device 1000 can be a decoding device, or a device applied to a decoding device and capable of realizing the corresponding functions of the decoding device in the method embodiments of the present application, such as a chip, a chip system, or a circuit, etc.

[0291] Optionally, the communication device 1000 comprises a processing module 1001, which can be a processor, a processing board, a processing unit, or a processing device, etc. In the case where the communication device 1000 is an encoding device or a device applied to an encoding device, the processing module 1001 is configured to perform encoding based on the first set of bit positions. The specific process can refer to the detailed description of the corresponding steps in the method embodiments, which will not be repeated here. In the case where the communication device 1000 is a decoding device or a device applied to a decoding device, the processing module 1001 is configured to perform decoding based on the first set of bit positions. The specific process can refer to the detailed description of the corresponding steps in the method embodiments, which will not be repeated here.

[0292] Optionally, the communication device 1000 further comprises a communication module 1002, which can also be referred to as a transceiver module, a transceiver, a transceiver device, or the like, configured to perform receiving (or inputting) and / or transmitting (or outputting) operations. For example, in the case where the communication device 1000 is an encoding device or a device applied to an encoding device, the communication module 1002 can be configured to obtain the first bit sequence to be encoded, and send the first bit sequence to the processing module 1001 for encoding. Optionally, the communication module 1002 can also be configured to output the encoded bit sequence obtained by the processing module 1001 by encoding the first bit sequence. Similarly, in the case where the communication device 1000 is a decoding device or a device applied to a decoding device, the communication module 1002 can be configured to obtain the encoded bit sequence, and send the encoded bit sequence to the processing module 1001 for decoding. Optionally, the communication module 1002 can also be configured to output the decoded bit sequence estimated by the processing module 1001.

[0293] It should be noted that the communication module and / or processing module described above can be implemented by a virtual module, for example, the processing module can be implemented by a software function unit or a virtual device, and the communication module can be implemented by a software function or a virtual device. Alternatively, the processing module or the communication module can also be implemented by an entity device, for example, if the device is implemented by a chip / circuit (for example, an integrated circuit or a logic circuit, etc.). The communication module can be an input / output circuit and / or a communication interface, which performs an input operation (corresponding to the receiving operation described above) and an output operation (corresponding to the sending operation described above); and the processing module is an integrated processor or a microprocessor or a circuit (for example, an integrated circuit, a logic circuit, etc.).

[0294] The division of the modules in the present application is illustrative, and is only a logical function division. In actual implementation, another division manner can be used. In addition, each function module in each example in the present application can be integrated in one processor, or can be a separate physical entity, or two or more modules can be integrated in one module. The integrated module can be implemented in the form of hardware or in the form of a software function module.

[0295] FIG. 5 is a schematic block diagram of another communication device 1100 provided by the present application. As shown in the figure, the communication device 1100 includes at least one processor 1110, which implements the functions of the encoding device or the decoding device described in the foregoing method embodiments.

[0296] Optionally, the processor 1110 is coupled with a memory. The memory can be located in the communication device, or the memory can be integrated with the processor, or the memory can be located outside the communication device. The communication device 1100 can further include at least one memory 1120. The memory 1120 stores computer programs, instructions or data necessary for implementing any one of the foregoing method embodiments. The processor 1110 can execute the computer programs, instructions or data stored in the memory 1120 to complete the encoding method or the decoding method in any one of the foregoing method embodiments.

[0297] Optionally, the communication device 1100 can further include a communication interface 1130. The communication device 1100 can exchange information with other devices through the communication interface 1130. For example, the communication interface 1130 can be a transceiver, a circuit, a bus, a module, a pin or other types of interfaces.

[0298] The coupling in the present application is an indirect coupling or communication connection between devices, units or modules, which can be electrical, mechanical or other forms, for information interaction between devices, units or modules. The processor 1110 can operate in conjunction with the memory 1120 and the communication interface 1130. The specific connection medium between the processor 1110, the memory 1120 and the communication interface 1130 is not limited in the present application.

[0299] Fig. 6 is a schematic diagram of a chip (or chip system) provided by the present application. The chip (or chip system) 30 can include a circuit 31 and an input / output interface 32. The circuit 31 can be a logic circuit, an integrated circuit, etc., and the input / output interface 32 can also be an input / output circuit or an interface circuit, which can input (or receive) information and output (or send) information. Alternatively, the chip system can be composed of a chip, or can include a chip and other discrete devices. The chip 30 can be used to perform the encoding method performed by the encoding device or the decoding method performed by the decoding device in the embodiments of the present application.

[0300] In addition, the present application also provides a computer readable storage medium, which stores computer instructions, when the computer instructions are run on a computer, the operations and / or processes performed by the encoding device or the decoding device in the method embodiments of the present application are performed.

[0301] The present application also provides a computer program product, which includes computer program codes or instructions, when the computer program codes or instructions are run on a computer, the operations and / or processes performed by the encoding device or the decoding device in the method embodiments of the present application are performed.

[0302] In addition, the present application also provides a chip, which includes a processor. A memory for storing computer programs is provided independently of the chip, and the processor is used to execute the computer programs stored in the memory, so that the operations and / or processes performed by the encoding device or the decoding device in any one of the method embodiments are performed.

[0303] Further, the chip can also include a communication interface. The communication interface can be an input / output interface, or an interface circuit, etc. Further, the chip can also include a memory.

[0304] The present application provides a communication system, which includes the encoding device and the decoding device in the method embodiments.

[0305] The processor in the embodiments of the present application has signal processing capability, and can be a central processing unit (CPU), and can also be a general processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, a discrete gate or transistor logic device, a discrete hardware component, and can implement or execute the disclosed methods, steps and logic block diagrams in the present application. The general processor can be a microprocessor or any conventional processor. The steps of the method disclosed in the present application can be directly embodied as hardware processor execution, or executed by a combination of hardware and software modules in the processor. The software module can be located in a mature storage medium in the field, such as random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, register, etc. The storage medium is located in the memory, and the processor reads the information in the memory, and combines the hardware to complete the steps of the above method.

[0306] The memory can be a non-volatile memory, such as a hard disk drive (HDD) or a solid-state drive (SSD), and can also be a volatile memory, such as a random access memory (RAM). The memory can be any other medium capable of carrying or storing desired program code in the form of instructions or data structures and capable of being accessed by a computer, but is not limited to this. The memory in the present application can also be a circuit or any other device capable of realizing the storage function, used for storing program instructions and / or data.

[0307] The technical solutions provided in the present application can be realized by software, hardware, firmware or any combination thereof, in whole or in part. When realized by software, the technical solutions can be realized in the form of a computer program product in whole or in part. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the processes or functions described in the present application are generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, a terminal device, an access network device or other programmable devices. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions can be transmitted from one website, computer, server or data center to another website, computer, server or data center through a wired (such as coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (such as infrared, wireless, microwave, etc.) manner. The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server, data center, etc. that includes one or more available media sets. The available media can be a magnetic medium (such as a floppy disk, a hard disk, a magnetic tape), an optical medium (such as a digital video disc (DVD)), or a semiconductor medium, etc.

[0308] In the present application, the examples can be referred to each other without logical contradiction, for example, the methods and / or terms of the method embodiments can be referred to each other, for example, the functions and / or terms of the device embodiments can be referred to each other, for example, the functions and / or terms of the device examples and the method examples can be referred to each other.

[0309] Those skilled in the art can realize that the units and algorithm steps of the examples described in combination with the embodiments disclosed herein can be realized by electronic hardware or a combination of computer software and electronic hardware. Whether the functions are realized in hardware or software depends on the specific application and design constraints of the technical solutions. Those skilled in the art can use different methods to realize the described functions for each specific application, but such implementation should not be considered beyond the scope of the present application.

[0310] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the above-described system, device and unit can refer to the corresponding processes in the foregoing method embodiments, which will not be described here.

[0311] In several embodiments provided in the present application, it should be understood that the disclosed system, device and method can be implemented in other manners. For example, the described device embodiments are merely schematic. The division of the units is merely logical function division. There can be other division manners in actual implementation. For example, a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the displayed or discussed mutual couplings or direct couplings or communication connections can be indirect couplings or communication connections through some interfaces, devices or units, and can be in electrical, mechanical or other forms.

[0312] The units described as separate components can or can not be physically separate, and the components shown as units can or can not be physical units, i.e., can be located in one place, or can be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the embodiment.

[0313] In addition, each functional unit in the various embodiments of the present application can be integrated into a processing unit, or each unit can be a physically independent unit, or two or more units can be integrated into a unit.

[0314] If the functions are realized in the form of software function units and sold or used as independent products, they can be stored in a computer readable storage medium. Based on this understanding, the technical solutions of the present application can be embodied in the form of a software product, and the computer software product is stored in a storage medium, and includes a number of instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present application. The aforementioned storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, and various media that can store program codes.

[0315] The above description is merely a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art can easily think of changes or replacements within the technical scope disclosed in the present application, which should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A method of encoding a polar code, the method comprising: The method comprises: obtaining a first bit sequence to be encoded; determining a first bit position set according to a first reliability sequence of a polar code; wherein the first reliability sequence is used to indicate reliabilities of bit positions in the polar code, the first bit position set is used to indicate frozen bit positions in the first reliability sequence, a number of first bit positions in which a reliability is higher than a reliability of a second bit position in an i-th sub-block is less than or equal to a threshold value, the first bit position is a bit position belonging to the i-th sub-block in the first bit position set, the second bit position is a bit position with a lowest reliability in the i-th sub-block and not belonging to the first bit position set, the i-th sub-block is a set of bit positions with an index value greater than or equal to i*2 n and less than (i+1)*2 n , n is a positive integer, i is an integer, i is greater than or equal to 0 and i is less than L, L is a number of sub-blocks contained in the first reliability sequence; and, encoding the first bit sequence according to the first bit position set to obtain an encoded bit sequence.

2. A decoding method of a polar code, characterized by, The method comprises: obtaining a received value sequence; determining a first bit position set according to a first reliability sequence of the polar code, wherein the first reliability sequence is used to indicate reliabilities of bit positions in the polar code, and the first bit position set is used to indicate frozen bit positions in the first reliability sequence, a number of first bit positions in which the reliabilities are higher than reliabilities of second bit positions in an ith sub-block is less than or equal to a threshold value, the first bit positions are bit positions belonging to the ith sub-block in the first bit position set, the second bit positions are bit positions in the ith sub-block which do not belong to the first bit position set and have the lowest reliabilities, and the ith sub-block is a set of bit positions with an index value greater than or equal to i*2 n and less than (i+1)*2 n , n is a positive integer, i is an integer, i is greater than or equal to 0 and i is less than L, and L is a number of sub-blocks included in the first reliability sequence. and decoding the received value sequence according to the first bit position set to obtain a decoded bit sequence.

3. The method according to claim 1 or 2, characterized in that, i traverses values in [0, 1, 2, …, L-1].

4. The method according to any one of claims 1 to 3, characterized in that, The number of bit positions belonging to the first bit position set in the ith sub-block is 0; or, The bit position belonging to the first bit position set in the ith sub-block is the 0th bit in ascending order of position index; or The bit positions belonging to the first set of bit positions in the ith sub-block are the 0th bit to the qth bit in ascending order of position index, 1≤q≤2, or 2 n -3≤q≤2 n -1, q is an integer, and n is a positive integer greater than or equal to 2.

5. The method according to any one of claims 1 to 3, characterized in that, The method further comprises: According to the code length E and the mother code length N, a number F of bit positions in the first set of bit positions is determined, F being a positive integer multiple of 2 n n being a positive integer greater than or equal to 2. determining the first bit position set according to the first reliability sequence of the polar code, comprising:

6. The method of claim 5, wherein, 2 n = 16, F is a positive integer multiple of 16; or, n = 8, F is a positive integer multiple of 8.

7. The method according to any one of claims 1 to 3, characterized in that, determining, in ascending order of position index, bit positions with index values greater than or equal to 0 and less than F as the first bit position set. According to the code length E and the length N of the mother code sequence, a number F of bit positions in the first set of bit positions is determined, F being even n Modulo 2 n - 3, n being a positive integer greater than or equal to 2. The method further comprises:

8. The method of claim 7, wherein, 2 n = 16, F mod 16 = 13.

9. The method according to any one of claims 1 to 3, characterized in that, determining the first bit position set according to the first reliability sequence of the polar code, comprising: determining, in ascending order of position index, bit positions with index values greater than or equal to 0 and less than F as the first bit position set. According to the order of the position index from small to large, the 0th to the 3rd are selected as the first to the fourth position indexes, respectively. bits a bit position, and a first bit to the first bits in order of reliability from low to high a bit position determined as the first bit position set, n is a positive integer greater than or equal to 2, symbol The method further comprises:

10. The method according to any one of claims 1 to 9, characterized in that, determining the number F of bit positions in the first bit position set according to the code length E and the mother code length N; 11. The method according to any one of claims 1 to 3, characterized in that, represents rounding down. The threshold value is 0, or the threshold value is 1. The threshold value is 1; the method further comprises:

12. An encoding apparatus, comprising: determining the number F of bit positions in the first bit position set according to the code length E and the length N of the mother code sequence, F modulo 16 is 12; determining, in ascending order of position index, bit positions with index values greater than or equal to 0 and less than F as the first bit position set. The method comprises: determining a first bit position set according to a first reliability sequence of the polar code, wherein the first reliability sequence is used to indicate reliabilities of bit positions in the polar code, and the first bit position set is used to indicate frozen bit positions in the first reliability sequence, a number of first bit positions in which the reliabilities are higher than reliabilities of second bit positions in an ith sub-block is less than or equal to a threshold value, the first bit positions are bit positions belonging to the ith sub-block in the first bit position set, the second bit positions are bit positions in the ith sub-block which do not belong to the first bit position set and have the lowest reliabilities, the ith sub-block is a set of bit positions whose index values are greater than or equal to i*2 n and less than (i+1)*2 n , n is a positive integer, i is an integer, i is greater than or equal to 0 and i is less than L, L is a number of sub-blocks included in the first reliability sequence; and, a communication module configured to obtain a first bit sequence to be encoded; 13. A decoding device, comprising: a processing module configured to: encode the first bit sequence according to the first bit position set to obtain an encoded bit sequence. The method comprises: determining a first bit position set according to a first reliability sequence of the polar code, wherein the first reliability sequence is used to indicate reliabilities of bit positions in the polar code, and the first bit position set is used to indicate frozen bit positions in the first reliability sequence, a number of first bit positions in which the reliabilities are higher than reliabilities of second bit positions in an ith sub-block is less than or equal to a threshold value, the first bit positions are bit positions belonging to the ith sub-block in the first bit position set, the second bit positions are bit positions in the ith sub-block which do not belong to the first bit position set and have the lowest reliabilities, the ith sub-block is a set of bit positions whose index values are greater than or equal to i*2 n and less than (i+1)*2 n , n is a positive integer, i is an integer, i is greater than or equal to 0 and i is less than L, and L is a number of sub-blocks included in the first reliability sequence. a communication module configured to obtain a received value sequence; a processing module configured to:

14. An encoding apparatus, comprising: and 15. A decoding device, comprising: decode the received value sequence according to the first bit position set to obtain a decoded bit sequence.

16. An encoding apparatus, comprising: The method comprises a communication interface and a circuit, the communication interface is configured to obtain a first bit sequence to be encoded, and send the first bit sequence to the circuit; the circuit is configured to determine a first bit position set according to a first reliability sequence of a polar code, and encode the first bit sequence according to the first bit position set to obtain an encoded bit sequence. The method comprises a communication interface and a circuit, the communication interface is configured to obtain a received value sequence, and send the received value sequence to the circuit; the circuit is configured to determine a first bit position set according to a first reliability sequence of a polar code, and decode the received value sequence according to the first bit position set to obtain a decoded bit sequence. The method comprises a module or unit for performing the method of any one of claims 1, 3-11.

17. A decoding device, comprising: comprising a module or unit for performing the method of any of claims 2-11.

18. An encoding apparatus, comprising: comprising a processor coupled with a memory, the processor configured to execute computer programs or instructions stored in the memory to cause the encoding apparatus to perform the method of any of claims 1, 3-11.

19. A decoding device, comprising: comprising a processor coupled with a memory, the processor configured to execute computer programs or instructions stored in the memory to cause the encoding apparatus to perform the method of any of claims 2-11.

20. A computer-readable storage medium, characterized in that, The computer readable storage medium stores computer instructions, when the computer instructions run on a computer, the method of any of claims 1-11 is realized.

21. A computer program product, characterised in that, The computer program product comprises computer program codes or instructions, when the computer program codes or instructions run on a computer, the method of any of claims 1-11 is realized.

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