Chip having a plurality of network nodes

Abstract

The invention relates to a chip (100) having a plurality of nodes (110). The chip (100) comprises a first node (110A), a second node (110B) and a third node (110C). The chip (100) comprises a first data line (120A) for data packets of the first and second nodes. The chip (100) comprises a demultiplexer (330B) which is designed to distribute the data packets of the first and second node from the first data line (120A) to a first demultiplexer output (332A) for data packets of the first node (110A) and to a second demultiplexer output (332B) for data packets of the second node (110B). The chip (100) comprises a switch (130B), which is connected to the third node (110C) via a second data line (120C) for data packets of the third node (110C) and which is connected to the first demultiplexer output (332A) and to the second demultiplexer output (332B). The switch (130B) is designed to receive data packets from the third node (110C) via the second data line (120C), to receive data packets from the first node (110A) via the first demultiplexer output (332A), to receive data packets from the second node (110B) via the second demultiplexer output (332A), and to forward the received data packets to a destination (140) via a third data line (120F).

Description

[0001] CHIP WITH A MULTIPLE NETWORK NODES

[0002] Technical field

[0003] The present disclosure relates, for example, to semiconductor chips with a multiple of processor cores (many-core chip design) and in particular to a switch architecture for bandwidth balancing for Network-on-Chip (NoC).

[0004] background

[0005] A many-core chip design with a 2D mesh network-on-chip (NoC) is an architecture for high-performance processors in which many cores are connected in a two-dimensional mesh arrangement. This architecture can be used to optimize communication between the cores and improve overall system performance.

[0006] A many-core chip can contain a large number of processor cores (often dozens or hundreds) that can operate in parallel. This enables high parallel processing capacity and is suitable for compute-intensive applications. In a 2D mesh NoC, the cores can be arranged in a rectangular grid, similar to a chessboard. Each core is directly connected to its neighbors (above, below, left, right), enabling efficient communication. The NoC is an on-chip communication network that manages data transmission between the cores. It replaces traditional bus systems, which become inefficient with many cores, with a scalable and high-performance network. The 2D mesh architecture is easily scalable. It is simple to add additional cores by expanding the grid. This allows for adjusting the computing capacity as needed.The 2D mesh NoC reduces latency (delay) in communication between cores because data can be transferred via short and direct paths. This increases the overall throughput of the system. The mesh topology enables even load distribution, as data traffic and computational tasks can be efficiently distributed across the entire network. This prevents bottlenecks and improves overall performance. Since each core can have multiple connections to neighboring cores, the network can continue to function even if individual connections or cores fail, increasing reliability.

[0007] In a many-core chip design with a 2D mesh network-on-chip (NoC), it is important that all cores have an equal amount of bandwidth available to memory. This prevents imbalances in program execution and ensures efficient use of computing resources.

[0008] If some cores have more memory bandwidth than others, the cores with less bandwidth can experience bottlenecks and delays. This can negatively impact the overall system performance. A more even distribution of memory bandwidth allows for better load balancing across the cores. Each core can perform its tasks more efficiently without having to wait for data. When all cores have the same amount of memory bandwidth, the available memory bandwidth is used optimally. This improves the overall performance and efficiency of the system. Equal access to memory reduces latency that can result from unevenly distributed bandwidth. This is especially important for applications that require fast data processing. Equal access to memory is also crucial for system scalability.When new cores are added, it's crucial to ensure they also receive sufficient bandwidth to memory to perform their tasks efficiently. Uneven bandwidth distribution can lead to imbalances where some cores are overloaded while others remain underutilized. This can negatively impact the overall performance and efficiency of the system.

[0009] Besides processor cores, other network nodes may also be meant, so that the present disclosure is not limited to processor cores, but includes any data endpoints in the NoC.

[0010] Accordingly, one of the tasks of the present disclosure is to provide all data endpoints or nodes with as much bandwidth as possible.

[0011] Summary

[0012] This problem is solved by devices and methods according to the attached patent claims.

[0013] According to a first aspect of the present disclosure, a chip with a plurality of nodes is proposed. The chip comprises a first node, a second node, and a third node. The nodes can include data endpoints, such as semiconductor memory and / or processing units (CPUs). The chip includes a first data line for data packets of the first and second nodes. That is, the first and second nodes can share the first data line. The chip includes a demultiplexer configured to distribute the data packets of the first and second nodes from the first data line to a first demultiplexer output for data packets of the first node and to a second demultiplexer output for data packets of the second node. The chip includes a switch.A multiplexer is connected to the third node via a second data line for data packets from the third node, and is connected to the first and second demultiplexer outputs. The switch / multiplexer is configured to receive data packets from the third node via the second data line, receive data packets from the first node via the first demultiplexer output, receive data packets from the second node via the second demultiplexer output, and forward the received data packets to a destination via a third data line.

[0014] The present disclosure relates to a chip design with multiple network nodes. A node can be, for example, a CPU or memory. The chip has a data line that carries data from two nodes. A demultiplexer distributes this data to two outputs. A switch / multiplexer connects a third node to these outputs and receives data from all three nodes. It then forwards the data to a destination. One advantage of this design is that it enables a fair distribution of data streams. This ensures that no nodes are overloaded and that all nodes can cooperate efficiently. It is therefore proposed to place a demultiplexer upstream of the switch. Within the switch, there can be a device that performs arbitration to one or more output channels. It is understood that the demultiplexer can also be considered part of the switch and does not need to be implemented separately.

[0015] In some implementations, the switch / multiplexer is configured to forward data packets from the first, second, and third nodes to the destination using a round-robin procedure. This means that the switch can forward the data packets from the three nodes sequentially in a fixed order. This method is called round-robin. One advantage of this method is that all nodes are treated equally. This ensures that no node is favored or neglected.

[0016] In some embodiments, the switch / multiplexer is configured to sort the data packets from the first, second, and third nodes according to priority and forward them to the destination. This means that the switch can sort the data packets from the three nodes according to their importance and then forward them. One advantage of this method is that important data can be processed more quickly. This can improve system performance, especially when some tasks are more urgent than others. In some embodiments, the demultiplexer is configured to distribute the data packets from the first and second nodes to the demultiplexer outputs based on a load-balancing algorithm. This means that the demultiplexer can distribute the data packets from the first and second nodes in such a way that the utilization of the connections is balanced. One advantage of this method is that no connection is overloaded.This ensures consistent and efficient data transmission.

[0017] According to some embodiments, the chip further comprises another demultiplexer configured to distribute the data packets of the second and third nodes from the third data line to a first demultiplexer output, and the data packets of the first node from the third data line to a second demultiplexer output of the second demultiplexer. The chip includes a fourth node and another switch / multiplexer, which is connected to the fourth node via a fourth data line for data packets of the fourth node. The second switch / multiplexer is also connected to the first demultiplexer output of the second demultiplexer.The additional switch / multiplexer is configured to receive data packets from the fourth node via the fourth data line, receive data packets from the first node via the first demultiplexer output of the additional demultiplexer, and forward the received data packets to the destination via a fifth data line. This means that the chip can include an additional demultiplexer. This demultiplexer can distribute the data from the second and third nodes to one output and the data from the first node to another. The chip can also include a fourth node and another switch / multiplexer. This switch / multiplexer connects the fourth node via a data line and receives data from the additional demultiplexer. The switch / multiplexer then forwards the received data to the destination via a fifth data line. One advantage of this arrangement is that more nodes can communicate efficiently with each other.This can improve data distribution and processing on the chip.

[0018] In some embodiments, the additional switch / multiplexer is configured to forward the data packets from the first and fourth nodes to the destination using a round-robin procedure. This means that the additional switch can forward the data packets from the first and fourth nodes alternately in a fixed order to the destination. An advantage of this method is that both nodes can be treated equally. This ensures that neither node is favored or neglected. In some embodiments, the additional switch / multiplexer is configured to sort and forward the data packets from the first and fourth nodes according to priority. This means that the additional switch can sort the data packets from the first and fourth nodes according to their importance and then forward them. An advantage of this method is that important data can be processed more quickly.This can improve the efficiency and performance of the system.

[0019] In some embodiments, the secondary demultiplexer is configured to distribute the data packets from the first, second, and third nodes to the demultiplexer outputs based on a load balancing algorithm. This secondary demultiplexer can thus distribute the data packets from the first, second, and third nodes in such a way that the load is evenly distributed across the outputs. An advantage of this method is that no connection is overloaded. This ensures efficient and stable data transmission.

[0020] In some implementations, the data lines are part of a Network-on-Chip (NoC). A NoC is a network used within a chip to connect different parts (nodes) of the chip. One advantage is that a NoC enables fast and efficient communication between the parts of the chip. This improves the overall performance of the chip.

[0021] In some embodiments, the majority of nodes are arranged in a two-dimensional grid structure on the chip. The nodes can thus be arranged in rows and columns, like a grid. One advantage is that this arrangement facilitates the connection and communication between the nodes. This can improve the efficiency and performance of the chip.

[0022] In some implementations, each node comprises processing units (cores, DSPs, CPUs, GPUs, etc.). This allows each node to perform calculations, increasing the chip's computing power and efficiency.

[0023] In some examples, the goal includes, for instance, a semiconductor memory. A semiconductor memory is a memory chip that can store data. One advantage is that data can be stored and retrieved quickly and reliably. This can improve the overall performance of the system.

[0024] In some implementations, the data lines are bidirectional to transport data packets in both directions. One advantage is that communication can be more flexible and faster. Data can be sent and received simultaneously, which can increase efficiency.

[0025] According to another aspect of the present disclosure, a communication method for a chip with a plurality of data endpoints is proposed. The communication method comprises transporting data packets from a first and second data endpoint of the chip over a first data line. The communication method comprises distributing, by means of a demultiplexer, the data packets from the first and second data endpoints from the first data line to a first demultiplexer output for data packets from the first data endpoint and to a second demultiplexer output for data packets from the second data endpoint. The communication method comprises receiving, by means of a switch / multiplexer, data packets from a third data endpoint over a second data line.The communication procedure includes receiving, via the switch, the data packets of the first data endpoint through the first demultiplexer output. The communication procedure includes receiving, via the switch, the data packets of the second data endpoint through the second demultiplexer output. The communication procedure further includes forwarding, via the switch, the received data packets to a destination.

[0026] Character description

[0027] Some examples of devices and / or methods are explained in more detail below with reference to the accompanying figures. These show:

[0028] Fig. 1 shows a Network-on-Chip (NoC) with four CPUs according to one embodiment;

[0029] Fig. 2 shows a conventional switch in the NoC;

[0030] Fig. 3 shows a switch with demultiplexer functionality according to one embodiment;

[0031] Fig. 4 shows a switch with demultiplexer and multiplexer functionality according to one embodiment; and

[0032] Fig. 5 shows a 2D mesh network-on-chip (NoC) with a 4x4 matrix of CPUs according to one embodiment. Description

[0033] Some examples are now described in more detail with reference to the accompanying figures. However, other possible examples are not limited to the features of these detailed embodiments. These may include modifications of the features, as well as equivalents and alternatives to the features. Furthermore, the terminology used herein to describe certain examples should not be considered restrictive for other possible examples.

[0034] Identical or similar reference symbols throughout the description of the figures refer to identical or similar elements or features, which may be implemented in an identical or modified form, while providing the same or a similar function. Furthermore, the thickness of lines, layers, and / or areas in the figures may be exaggerated for clarity.

[0035] When two elements A and B are combined using "or," this is to be understood as revealing all possible combinations, i.e., only A, only B, and A and B, unless explicitly defined otherwise in a specific case. As an alternative formulation for the same combinations, "at least one of A and B" or "A and / or B" can be used. This applies equivalently to combinations of more than two elements.

[0036] When a singular form, e.g., "ein, eine" and "der, die, das," is used, and the use of only a single element is neither explicitly nor implicitly defined as mandatory, further examples may also use multiple elements to implement the same function. If a function is subsequently described as being implemented using multiple elements, further examples may implement the same function using a single element or a single processing entity.It is further understood that the terms "include", "comprehensive", "exhibit" and / or "exhibit" when used describe the presence of the specified features, integers, steps, operations, processes, elements, components and / or a group thereof, but do not exclude the presence or addition of one or more other features, integers, steps, operations, processes, elements, components and / or a group thereof.

[0037] Fig. 1 schematically shows a simple architecture of a NoC 100 chip with, for example, four processing units or processor cores 110A, 11OB, 11C, and 110D. The processor cores 110A, 110B, 110C, and 110D are arranged in a row. It is understood that the chip 100 can have further rows of processor cores, so that the chip 100 can, for example, comprise a 4x4, 8x8, or 16x16 matrix of processor cores.

[0038] A processor core (also called a CPU core) is an independent processing unit within a processor (CPU) capable of executing instructions and processing tasks. Modern processors often consist of multiple cores, known as multi-core or many-core processors. Each core can independently execute programs and tasks, increasing the overall performance and efficiency of the processor. A processor core can contain all the necessary components to execute instructions, including its own registers, an arithmetic logic unit (ALU), and a control unit. Multiple cores in a processor allow for the simultaneous execution of tasks, increasing the capability for parallel processing. This is particularly useful for multithreading and multitasking applications.Multiple cores can operate at lower clock speeds to achieve the same or even better performance than a single, faster core. This can improve the processor's energy efficiency and heat dissipation. Each core typically has its own dedicated cache memory (L1 cache) and can share larger cache memories (L2, L3) with other cores for fast access to frequently used data and instructions. Processor architectures can be made scalable by adding more cores. This allows computing power to be tailored to different needs, from mobile devices to high-performance servers.

[0039] The processor cores 110A–110D are connected to a destination 140 via data lines 120A–120G and switches 130A–130C. In NoC architectures, the data lines 120 connect the various processor cores 110 and / or other components on the chip 100 to ensure data transmission and communication. A switch, or network switch 130, is a device used in computer networks to route data packets between different network nodes. The switch 130 receives data packets from a network node (such as a processor core, memory, etc.) and forwards these packets to the appropriate destination node, for example, based on MAC addresses. In a Network-on-Chip (NoC), the switch 130 is an integrated switching element that controls communication between different processor cores 110 and other components within the chip 100.Switch 130 forwards data packets between cores 110 and other components on chip 100, based on routing algorithms. NoC switches can be organized in a specific topology, such as a 2D mesh topology, where they are arranged in a grid pattern and connect the cores. The number of ports on a switch determines how many devices or cores can be connected. A switch can be considered a multiplexer in some respects, as both devices aim to route data from multiple input sources to one or more output locations. The destination 140, for example, could be external or internal semiconductor memory (e.g., L2, L3 cache) or other components inside or outside of chip 100.

[0040] Processor core 110A is connected to switch 130A via data line 120A. Processor core 110B is connected to switch 130A via data line 120B. Switch 130A is connected to switch 130B via data line 120E. Processor core 110C is connected to switch 130B via data line 120C. Switch 130B is connected to switch 130C via data line 120F. Processor core 110D is connected to switch 130C via data line 120D. Switch 130C is connected to target 140 via data line 120G. This architecture allows processor cores 110A, 11OB, 110C, and 110D to communicate with each other and simultaneously access target 140, thus enabling data transfer and load balancing.

[0041] In a many-core chip design with a 2D mesh network-on-chip, it can be important that all processor cores 110A, 11OB, 110C, and 110D have an equal amount of bandwidth available to and / or from target 140 to prevent imbalances during program execution. In most cases, the slowest execution unit determines the overall program runtime.

[0042] If, for example, four processor cores 110A, 110B, 110C, and 110D, via switches 130A, 130B, and 130C, each place a packet on their respective data line 120 NoC in every network clock cycle (NoC), then, with a naive implementation of the switch architecture, the bandwidth for processor cores 110A and 110B is halved. A clock cycle is currently the basic unit a processor or network needs to perform a fundamental operation, such as transmitting a data packet, executing an instruction, or transitioning between states. A clock cycle is the time interval between two consecutive clock pulses of the system clock. In modern processors and networks, many operations are performed synchronously with the clock.

[0043] In this example, four processor cores, 110A, 110B, 110C, and 110D, send a packet to the NoC in each clock cycle. This means that in each time unit defined by a clock cycle, each of these processor cores attempts to send data across the network. With a naive implementation of the switch architecture, bottlenecks can occur. If all processor cores send data simultaneously, switches 130A, 130B, and 130C must forward this data. If switches 130A, 130B, and 130C are unable to distribute the data efficiently, the effective bandwidth for the cores furthest from the target 140 (in this case, 110A and 110B) can be halved because the switches might forward the data sequentially instead of in parallel.

[0044] This is illustrated in Fig. 2 for Switch 130B. Switch 130B receives data packets p2 and p3 from processor cores 110B and 110A via data line 120E from Switch 130A. Switch 130A can then alternately distribute the data packets p2 and p3 from processor cores 110B and 110A onto data line 120E. Switch 130B receives data packets p1 from processor core 110C via data line 120C. Based on a round-robin procedure between data lines 120C and 120E, switch 130B would now send a data packet p1 from processor core 110C to data line 120F in the first clock cycle, a data packet p2 from processor core 11 OB in the second clock cycle, another data packet p1 from processor core 110C in the third clock cycle, and a data packet p3 from processor core 110A in the fourth clock cycle, and so on. This results in a halving of the effective bandwidth for processor cores 110B and 110A compared to processor core 110C.

[0045] The present disclosure proposes a concept that reduces or avoids the halving of the effective bandwidth for processor cores 11 OB and 110A. The proposed concept is explained below with reference to Fig. 3.

[0046] Fig. 3 shows a demultiplexer 330B upstream of the switch or multiplexer 130B. Data line 120E forms one input of the demultiplexer 330B. A first demultiplexer output 332A forms a first input for switch 130B. A second demultiplexer output 332B forms a second input for switch 130B. The data line 120C from processor core 110C forms a third input for switch 130B. The demultiplexer 330B is configured to distribute the data packets p2 and p3 of processor cores 110B and 110A from the input data line 120E to the first demultiplexer output 332A for data packets p3 of the first processor core 110A and to the second demultiplexer output 332B for data packets p2 of the second processor core 11 OB.Switch 130B is configured to receive data packets p1 from the third processor core 110C via data line 120C, to receive data packets p3 from the first processor core 110A via the first demultiplexer output 332A, to receive data packets from the second processor core 11 OB via the second demultiplexer output 332B, and to forward the received data packets to destination 140 via data line 120F. Demultiplexer 330B receives data packets p2 and p3 from processor cores 11 OB and 110A via data line 120E from switch 130A. Switch 130B receives data packets p1 from processor core 110C via data line 120C and data packets p2 and p3 from processor cores 11 OB and 110A via demultiplexer outputs 332A and 332B. In the first clock cycle, Switch 130B can send a data packet p1 from processor core 110C to data line 120F.In a second clock cycle, demultiplexer 330B can send a data packet p2 from processor core 11 OB to demultiplexer output 332B, and switch 130B can send the data packet p2 from processor core 11 OB to data line 120F. In a third clock cycle, demultiplexer 330B can send a data packet p3 from processor core 110A to demultiplexer output 332A, and switch 130B can send the data packet p3 from processor core 110A to data line 120F. In a fourth clock cycle, switch 130B can send another data packet p1 from processor core 110C to data line 120F. In a fifth clock cycle, demultiplexer 330B outputs another data packet p2 from processor core 110B to demultiplexer output 332B, and switch 130B outputs the next data packet p2 from processor core 110B to data line 120F, and so on. Thus, processor cores 110B and 110A have the same effective bandwidth as processor core 110C.Switch / multiplexer 130B and demultiplexer 330B can be configured separately or integrated into a single component. Within the switch 130B, there can be a device that performs arbitration to one or more output channels.

[0047] Arbitration, also known as "arbitration," is a process that determines which of several competing data or communication requests takes precedence. This is particularly important in systems where multiple components or devices simultaneously need access to a shared resource, such as a data bus, memory, or network channel. Arbitration ensures that only one request has access to the resource at any given time, preventing data collisions and conflicts. It allows requests to be prioritized based on predefined criteria such as priority, order of arrival, or specific rules. In a network-on-a-chip (NoC), multiple processor cores may need to access the same communication channel concurrently. The switch or a dedicated arbitration device determines which core has priority.

[0048] With static prioritization, each request is assigned a fixed priority, and the request with the highest priority wins. In round-robin prioritization, access rights are distributed cyclically among requesters to ensure fairness. With dynamic prioritization, priorities can change based on specific conditions or rules, such as the urgency of the request or the waiting time. Within the 130B switch, an arbitration device can decide which data request from the inputs (e.g., data packets p1, p2, p3) is routed to which output channel. This is necessary when multiple data streams need to pass through the switch simultaneously and conflicts must be avoided.

[0049] According to some embodiments, the switch / multiplexer 130B is configured to forward the data packets from the processor cores 110 to the destination 140 using a round-robin procedure. This means that the switch 130B can forward the data packets from the three processor cores 110A, 110B, and 110C sequentially in a fixed order. Alternatively, the switch / multiplexer 130B can be configured to sort the data packets from processor cores 110A, 110B, and 110C according to priority and forward them to the destination 140. This means that the switch / multiplexer 130B can sort the data packets from processor cores 110A, 110B, and 110C according to their importance and then forward them. Alternatively, the switch / multiplexer can forward the data packets from processor cores 110A, 110B and 110C to the destination 140 based on a load-balancing algorithm.

[0050] According to the present disclosure, a demultiplexer 330B can be placed upstream of the switch 130B, so that three separate input lines 120C, 332A, and 332B are available for the packets of the three processor cores 110A, 11OB, and 110C at the output arbiter in switch 130B, thus enabling fair arbitration. This ensures that all cores receive the same bandwidth. This effect can be further enhanced by round-robin arbitration between the input lines. The number of cores used here is merely an example; this can be extended to any number of cores.

[0051] If there is only one link (data line) from switch 130C to target 140 (e.g., memory), the same methodology can be applied again. However, if there are multiple links—for example, two—it makes sense to assign a fixed number of processor cores to data lines. This simplifies arbitration, thus preventing congestion, and reduces the number of AXI IDs (Advanced Extensible Interface Identifiers) required, as all processor cores always use the same target link when communicating with target 140.

[0052] Fig. 4 shows an embodiment of Switch 130C, which includes a demultiplexer 430C and a multiplexer 435C. The demultiplexer 430C is configured to distribute the data packets p1 and p3 from processor cores 110C and 110A from the input data line 120F to a first output data line 420A, and the data packets p2 from processor core 11OB from the input data line 120F to a second output data line 420B of the demultiplexer 430C. In a first clock cycle, the demultiplexer 430C can output a data packet p1 from processor core 110C from the input data line 120F to the output data line 420A. In a second clock cycle, demultiplexer 430C can transfer a data packet p2 from processor core 11 OB from input data line 120F to output data line 420B. In a third clock cycle, demultiplexer 430C can transfer a data packet p3 from processor core 110A from input data line 120F to output data line 420A, and so on.

[0053] Switch 130C also includes a multiplexer 435C, which is connected to the fourth processor core 110D via data line 120D for data packets from processor core 110D, and to the second output data line 420B of demultiplexer 430C. Multiplexer 435C is configured to receive data packets pO from the fourth processor core 110D via data line 120D, to receive data packets p2 from processor core 11 OB via the second output data line 420B of demultiplexer 430C, and to forward the received data packets pO and p2 to the destination via output data line 420C. In the first clock cycle, multiplexer 435C can transfer a data packet pO from processor core 110D from input data line 120D to output data line 420C. In a second clock cycle, multiplexer 435C can transfer a data packet p2 of the processor core 110B from the input data line 420B to the output data line 420C.In a third clock cycle, multiplexer 435C can transfer a data packet p1 from processor core 110D from input data line 120D to output data line 420B, and so on. The data packets p1 and p3 from processor cores 110A and 110C can then be forwarded to destination 140 via the first output data line 420A.

[0054] According to some embodiments, the multiplexer 435C is configured to forward the data packets pO, p2 to the destination 140 using a round-robin procedure. This means that the multiplexer 435C can forward the data packets from processor cores 110D, 110B sequentially in a fixed order. Alternatively, the multiplexer 435C can be configured to sort the data packets pO, p2 from processor cores 110D, 110B according to priority and forward them to the destination 140. Alternatively, the multiplexer 435C can forward the data packets pO, p2 from processor cores 110D, 110B to the destination 140 based on a load-balancing algorithm.

[0055] The architecture of the Switch 130C shown in Fig. 4 allows, in a 4x4 mesh, the use of only two columns with maximum bandwidth, or three or four columns where all processor cores have exactly the same bandwidth available. This enables highly flexible use of only the number of resources / cores on a chip that represent the best balance between compute performance and bandwidth for a given application or application class. All other resources can be deactivated to achieve the best possible energy efficiency.

[0056] Fig. 5 shows a 2-D Mesh Network-on-Chip (NoC) 100 with a 4x4 matrix of CPUs 110. The CPUs 110 are interconnected via data lines 120 and switches 130. The switches 130 can incorporate the demultiplexer and / or multiplexer functionality proposed herein.

[0057] Even distribution of memory bandwidth is crucial to prevent bottlenecks and imbalances and to improve overall system performance. An upstream demultiplexer can distribute data packets from processor cores evenly across the inputs of a switch, thus ensuring fair bandwidth allocation. The switch is then able to efficiently receive and forward data packets from different cores.

[0058] The proposed chip comprises multiple nodes (processor cores or memory) interconnected via data lines and switches. A demultiplexer distributes the data from two nodes to separate outputs leading to a switch. The switch receives data packets from various nodes and forwards them to a destination. Within the switch, an arbitration device can determine which data stream receives priority, based on priority or round-robin procedures.

[0059] A chip with multiple nodes arranged in a 2D mesh enables efficient data distribution and load balancing. The use of demultiplexers and switches improves data transmission efficiency and prevents bottlenecks. The chip can also include additional demultiplexers and switches to further distribute data streams from multiple nodes.

[0060] The aspects and features described in connection with one of the previous examples can also be combined with one or more of the further examples to replace an identical or similar feature of that further example or to additionally introduce the feature into the further example.

[0061] Examples can also include a (computer) program with program code for executing one or more of the above procedures, or refer to such a program when executed on a computer, processor, or other programmable hardware component. Steps, operations, or processes of various procedures described above can therefore also be executed by programmed computers, processors, or other programmable hardware components. Examples can also include program storage devices, such as digital data storage media, that are machine-, processor-, or computer-readable and encode or contain machine-executable, processor-executable, or computer-executable programs and instructions. The program storage devices can, for example,Digital storage devices include or may include magnetic storage media such as magnetic disks and magnetic tapes, hard disk drives, or optically readable digital data storage media. Further examples may also include computers, processors, control units, field-programmable logic arrays ((F)PLAs), field-programmable gate arrays ((F)PGAs), graphics processing units (GPUs), application-specific integrated circuits (ASICs), integrated circuits (ICs), or system-on-a-chip (SoCs) programmed to perform the steps of the procedures described above.

[0062] It is further understood that the disclosure of several steps, processes, operations, or functions disclosed in the description or claims should not be interpreted as necessarily occurring in the described sequence, unless explicitly stated in a specific case or required for technical reasons. Therefore, the preceding description does not restrict the execution of multiple steps or functions to a specific sequence. Furthermore, in other examples, a single step, function, process, or operation may include and / or be broken down into multiple sub-steps, functions, processes, or operations.

[0063] If certain aspects described in the preceding sections relate to a device or system, these aspects are also to be understood as a description of the corresponding method. For example, a block, device, or functional aspect of the device or system may correspond to a feature, such as a process step, of the corresponding method. Similarly, aspects described in relation to a method are also to be understood as a description of a corresponding block, element, property, or functional feature of a corresponding device or system. The following claims are hereby incorporated into the detailed description, each claim being a separate example that can stand alone.Furthermore, it should be noted that—although a dependent claim may refer in the claims to a specific combination with one or more other claims—other examples may also include a combination of the dependent claim with the subject matter of any other dependent or independent claim. Such combinations are hereby explicitly proposed unless it is stated in a specific case that a particular combination is not intended. Furthermore, features of a claim for any other independent claim are also to be included, even if that claim is not directly defined as dependent on that other independent claim.

Claims

Patent claims 1. A chip (100) with a plurality of nodes (110), comprising a first node (110A); a second node (11OB); a third node (110C); a first data line (120A) for data packets of the first and second nodes; a demultiplexer (330B) configured to distribute the data packets of the first and second nodes from the first data line (120A) to a first demultiplexer output (332A) for data packets of the first node (110A) and to a second demultiplexer output (332B) for data packets of the second node (110B);a switch (130B) which is connected to the third node (110C) via a second data line (120C) for data packets of the third node (110C), and which is connected to the first demultiplexer output (332A) and to the second demultiplexer output (332B), wherein the switch (130B) is configured to receive data packets from the third node (110C) via the second data line (120C), to receive data packets from the first node (110A) via the first demultiplexer output (332A), to receive data packets from the second node (11 OB) via the second demultiplexer output (332A), and to forward the received data packets to a destination (140) via a third data line (120F).

2. Chip (100) according to claim 1, wherein the switch (130B) is configured to forward the data packets from the first, second and third nodes to the destination (140) according to a round-robin procedure.

3. Chip (100) according to claim 1, wherein the switch (130B) is configured to sort the data packets from the first, second and third nodes according to priority and forward them to the destination (140).

4. Chip (100) according to one of the preceding claims, wherein the demultiplexer (330B) is configured to distribute the data packets of the first and second nodes to the demultiplexer outputs (332A; 332B) based on a load balancing algorithm.

5. Chip (100) according to any of the preceding claims, further comprising a further demultiplexer (430C) configured to distribute the data packets of the second and third nodes (11 OB; 110C) from the third data line (120F) to a first demultiplexer output (420A) and the data packets of the first node (120A) from the third data line (120F) to a second demultiplexer output (420B) of the further demultiplexer (430C); a fourth node (110D);a multiplexer (435C) which is connected to the fourth node (110D) via a fourth data line (120D) for data packets of the fourth node (110D), and which is connected to the second demultiplexer output (420B) of the further demultiplexer (430C), wherein the multiplexer (435C) is configured to receive data packets from the fourth node (110D) via the fourth data line (120D), to receive data packets from the first node (120A) via the second demultiplexer output (420B) of the further demultiplexer (430C), and to forward the received data packets to the destination (140) via a fifth data line (420C).

6. Chip (100) according to claim 5, wherein the multiplexer (435C) is configured to forward the data packets from the first and fourth nodes to the destination according to a round-robin procedure.

7. Chip (100) according to claim 5, wherein the multiplexer (435C) is configured to sort and forward the data packets from the first and fourth nodes according to priority.

8. Chip (100) according to one of claims 5 to 7, wherein the further demultiplexer (430C) is configured to distribute the data packets of the first, second and third node to the demultiplexer outputs based on a load balancing algorithm.

9. Chip (100) according to any of the preceding claims, wherein the data lines (120) are part of a Network-on-Chip, NoC.

10. Chip (100) according to one of the preceding claims, wherein the plurality of nodes (110) are arranged in a two-dimensional lattice structure on the chip (100).

11. Chip (100) according to any of the preceding claims, wherein the nodes (110) each comprise computing units.

12. Chip according to any of the preceding claims, wherein the target (140) comprises a semiconductor memory.

13. Chip (100) according to any of the preceding claims, wherein the data lines are bidirectional to transport data packets in both directions.

14. Communication method for a chip (100) with a plurality of data endpoints (110), comprising Transporting data packets from the first and second data endpoints of the chip via a first data line; Distribute, by means of a demultiplexer, the data packets of the first and second data endpoints from the first data line to a first demultiplexer output for data packets of the first data endpoint and to a second demultiplexer output for data packets of the second data endpoint; and Receiving, by means of a switch, data packets from a third data endpoint via a second data line; Receiving, via the switch, the data packets of the first data endpoint via the first demultiplexer output, Receiving, via the switch, the data packets of the second data endpoint via the second demultiplexer output; Forwarding, using the switch, the received data packets to a destination.

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