Error correction device

Abstract

One aspect of the present invention is an error correction device comprising a control unit that performs error correction on encoded information that is encoded by using a turbo product code transmitted from a transmission source, wherein the control unit optimizes a hyper-parameter α and a hyper-parameter β in encoding using a turbo product code so as to minimize cross entropy of the encoded information in the error correction.

Description

Error Correction Device

[0001] The present invention relates to an error correction device.

[0002] The growing use of cloud services that process large volumes of content is driving demand for even greater capacity in optical transport networks. High-capacity optical transmission systems are realized through high-speed digital signal processing, and highly power-efficient soft-decision (SD) forward error correction (FEC) technology is essential for achieving high-capacity, long-distance transmission.

[0003] In recent years, turbo product code (TPC) has attracted attention as a highly power-efficient method (see Non-Patent Documents 1 and 2), and has been adopted as a power-saving SD-FEC in Open ROADM MSA and Open ZR+MSA (see Non-Patent Documents 3 and 4).

[0004] R. Pyndiah, "Near-optimum decoding of product codes: block turbo codes," IEEE Transactions on Communications, vol. 46, no. 8, pp. 1003 1010, 1998. H. Mukhtar, et al., "Turbo product codes: applications, challenges, and future directions," IEEE Communications Surveys & Tutorials, vol. 18, no. 4, pp. 3052 3069, 2016.Open ROADM MSA 3.01 W-Port Digital SpecificationOpen ZR+ MSA Technical Specification

[0005] It is known that TPC exhibits relatively good correction performance in the region of small overhead (OH), but in the region of large OH, in order to obtain a high coding gain (NCG), it is necessary to increase the inter-code distance and OH. However, since the amount of calculation in each iteration in the iterative decoding process increases exponentially with the inter-code distance, the number of iterations that can be performed is limited, and this limits the performance.

[0006] In view of the above circumstances, an object of the present invention is to provide a technique for improving the performance of error correction.

[0007] One aspect of the present invention is an error correction device that includes a control unit that performs error correction on encoded information, which is information encoded using a turbo product code sent from a transmission source, and in the error correction, the control unit optimizes hyperparameters α and β in encoding using the turbo product code so as to minimize the cross-entropy of the encoded information.

[0008] The present invention makes it possible to improve the performance of error correction.

[0009] 1 is an explanatory diagram for explaining a communication system according to an embodiment. 2 is an explanatory diagram for explaining an example of a result of encoding using a TPC code according to an embodiment. 3 is a diagram showing an example of the hardware configuration of a receiving device according to an embodiment. 4 is a flowchart showing an example of a flow of processing executed in a communication system according to an embodiment. 5 is a diagram showing an example of a result of an experiment according to an embodiment. 6 is a diagram showing values ​​of hyperparameters α and β in an experiment according to an embodiment. 7 is a diagram showing a first example of a result of encoding using a TPC code according to a modified example. 8 is a diagram showing a second example of a result of encoding using a TPC code according to a modified example.

[0010] (Embodiment) Fig. 1 is an explanatory diagram illustrating a communication system 100 according to an embodiment. The communication system 100 includes a transmitting device 1 and a receiving device 2. The receiving device 2 is an example of an error correction device. The transmitting device 1 transmits information coded using a turbo product code (hereinafter referred to as "coded information"). Therefore, the transmitting device 1 is an example of a source of coded information.

[0011] The receiving device 2 receives the encoded information transmitted by the transmitting device 1. The receiving device 2 includes a control unit 21 including a processor 91, such as a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), or an NPU (Neural Network Processing Unit), and a memory 92, which are connected via a bus.

[0012] The control unit 21 decodes the received encoded information. In the decoding process, the control unit 21 performs error correction on the encoded information. In the error correction, the control unit 21 executes a hyperparameter optimization process. The hyperparameter optimization process is a process of optimizing hyperparameters α and β in a turbo product code so as to minimize the cross entropy of the encoded information. The hyperparameters α and β may be optimized by, for example, the steepest descent method.

[0013] <Effects of Hyperparameter Optimization Processing> The effects of the hyperparameter optimization processing will be described. In the case of turbo product codes, in order to obtain a high coding gain in a region where overhead (OH) is large, it is necessary to increase the OH. To increase the OH, the code length can be shortened. This is because shortening the code length effectively increases the OH while maintaining the inter-code distance.

[0014] Although shortening the code length results in a degradation of performance, the amount of calculation in each iteration is reduced, making it possible to increase the number of iterations accordingly. Increasing the number of iterations improves the performance of error correction. In this case, the more optimized the hyperparameters α and β used in each iteration are, the greater the improvement in performance that occurs with increasing the number of iterations. Therefore, by performing the hyperparameter optimization process, it is possible to improve the performance of error correction.

[0015] <Example of Hyperparameter Optimization Process> In error correction, the hyperparameters α and β may be optimized by an iterative process in which unit processes are repeated. The unit process is a process for updating the hyperparameters α and β. In the iterative process, the hyperparameters α and β updated by the lth unit process (l is an integer equal to or greater than 1) are further updated by the (l+1)th unit process.

[0016] <<Unit Processing>> In the lth unit processing, a log-likelihood ratio update process and a process of updating the hyperparameters α and β so as to minimize the cross-entropy of the encoded information based on the log-likelihood ratios updated by the log-likelihood ratio update process are executed.

[0017] <<<Turbo Product Code Conditions>>> Before explaining the log-likelihood ratio update process, the results of encoding using turbo product codes will be explained. More specifically, the conditions that the results of encoding using turbo product codes must satisfy (hereinafter referred to as "turbo product code conditions") will be explained.

[0018] The turbo product code condition includes a first sub-condition. The first sub-condition is a condition that the result of encoding information to be encoded using a turbo product code is a bit string to which parity bits representing the information to be encoded are added, and each information bit in the bit string is added with information on its position in two-dimensional space, which information is determined according to an arrangement rule. Note that the arrangement rule is a predetermined rule regarding the position of each information bit in two-dimensional space.

[0019] The turbo product code condition also includes a second sub-condition, which states that a parity bit exists on each first axis, which is an axis parallel to a predetermined direction in the two-dimensional space and on which at least one information bit exists, and also exists on each second axis, which is an axis perpendicular to the predetermined direction in the two-dimensional space and on which at least one information bit exists.

[0020] The turbo product code conditions also include a third sub-condition, which states that the value of each parity bit is determined based on the information bit sequence present on the axis on which the parity bit exists.

[0021] The fact that this turbo product code condition encompasses the results of the turbo product codes described in Non-Patent Document 1 and Non-Patent Document 2 will be explained again after the explanation of Fig. 2. Here, we return to the explanation of the log-likelihood ratio update process.

[0022] The log-likelihood ratio update process in the lth unit process is a process in which the log-likelihood ratio of the received signal is updated based on the log-likelihood ratio of each information bit and parity bit on all or part of one or more target axes calculated based on the hyperparameter α and hyperparameter β obtained in the (l-1)th unit process.

[0023] An example of the log-likelihood ratio is the following equation (2): The equation (2) indicates that the log-likelihood ratio of the normalized i-th bit after the l-th update is the product of the hyperparameter α in the turbo product code, which is optimized in the l-th unit process, and the extrinsic LLR for the i-th bit, and the log-likelihood ratio r of the i-th bit of the received signal normalized by the square root σ of the noise power of the received signal. ｉ It means that it is the sum of and.

[0024] The axis of symmetry is the first axis when the unit process is an odd-numbered unit process, and is the second axis when the unit process is an even-numbered unit process.

[0025] <> Here, a more specific example of the hyperparameter optimization processing including the repetition of unit processing will be described using mathematical expressions. Note that, in decoding information encoded using turbo product codes, a process of updating the logarithm likelihood ratio (LLR) of each bit of information bits and parity bits is repeated. This LLR update is mathematically expressed by the following equations (1) to (4).

[0026] Equations (1) to (4) are mathematical expressions that represent the l-th LLR update process. Note that the bits to be updated in the LLR update process (hereinafter referred to as "LLR update process") are bits that are predetermined according to the number of LLR update processes. Therefore, the same bits are not updated in all LLR update processes.

[0027]

[0028]

[0029]

[0030]

[0031] α in Equation (2) （ｌ） is a value used in the l-th LLR update process of the hyperparameter α in the turbo product code. （ｌ－１） is a value used in the l-th LLR update process of the hyperparameter β in the turbo product code.

[0032] In equations (1) to (4), the symbol in equation (5) below represents the LLR of the ith bit (i is an integer equal to or greater than 1) obtained by the lth LLR update process.

[0033]

[0034] The i-th bit refers to the i-th bit of a bit string to be subjected to error correction and to which a parity bit has been added. The bit string to be subjected to error correction includes an information bit and a parity bit. The encoded information received by the receiving device 2 is an example of such a target for error correction.

[0035] In formulas (1) to (4), r ｉ represents the LLR of the i-th bit of the received signal normalized by σ. The received signal is the target of error correction, for example, the coded information received by the receiving device 2. σ is the square root of the power of the noise contained in the received signal.

[0036] In equations (1) to (4), the symbol in equation (6) below means the normalized LLR of the i-th bit after the l-th update.

[0037]

[0038] In equations (1) to (4), the symbol in equation (7) below means the extrinsic LLR for the i-th bit. Note that the extrinsic LLR here means an LLR calculated from information other than the received signal.

[0039]

[0040] In equations (1) to (4), the symbol in the following equation (8) means j-th bit information in a nearest neighbor codeword bit string determined based on the LLR of the normalized i-th bit after the (l-1)th update and the element code. Here, the element code is an error correction code for assigning a parity bit to each information bit on each axis, and for example, a BCH code or an extended BCH code is used as the element code. Note that the value of the bit information represented by the symbol in equation (8) is, for example, -1 or 1.

[0041]

[0042] In equations (1) to (4), the symbol in equation (9) below means j-th bit information in a suboptimal codeword bit sequence determined based on the LLR of the i-th normalized bit after the (l-1)-th update and the element code. Note that the value of the bit information represented by the symbol in equation (8) is, for example, −1 or 1.

[0043]

[0044] In equations (1) to (4), the symbol in the following equation (10) is a value that is 1 if a next-best codeword bit string determined based on the LLR of the normalized i-th bit after the (l-1)th update and the element code is found in Chase-Pyndiah decoding, and is 0 otherwise.

[0045]

[0046] In the formulas (1) to (4), N represents the code length of the element code.

[0047] The processes expressed by equations (1) to (4) are the processes disclosed in Non-Patent Documents 1 and 2.

[0048] In the hyperparameter optimization process, in addition to the processes disclosed in Non-Patent Documents 1 and 2, the hyperparameters α and β are optimized.

[0049] Here, an example of the rule for updating the hyperparameters α and β will be described using the case where the optimization algorithm is the steepest descent method. Equation (11) is an example of the rule for updating the hyperparameter α. Equation (12) is an example of the rule for updating the hyperparameter β. μ is a step size parameter, and its value is, for example, 1E-4.

[0050]

[0051]

[0052] The iterative process of the steepest descent method for optimizing the hyperparameters α and β is executed up to 10,000 times, for example.

[0053] An image C101 in FIG. 1 is an image showing, in a circuit diagram, an example of the optimization of the hyperparameters α and β according to the rules of Equation (11) and Equation (12). ｏｐｔ （ｌ） is the optimized hyperparameter α （ｌ） represents β ｏｐｔ （ｌ－１） is the optimized hyperparameter β （ｌ－１） It should be noted that the Chase-Pyndiah decoder represents the decoding process described in Non-Patent Document 2. The Chase-Pyndiah decoder is a general decoding process for TPC.

[0054] The optimization of the hyperparameters α and β involves minimizing a cost function. Specifically, the cost function is the cross-entropy of the encoded information. Such cross-entropy is expressed, for example, by the following equation (13):

[0055]

[0056] where M is the number of bits in the known (i.e., predetermined) bit string used to calculate the cost function. ｉ represents the i-th transmitted bit. In the communication system 100, the transmitted bit means a bit corresponding to a codeword encoded by a turbo product code. ｉ The value of is 0 or 1.

[0057] For example, when one known TPC frame is used to calculate the cost function, M = N1 x N2, where N1 is the code length of the horizontal code and N2 is the code length of the vertical code. The horizontal code and the vertical code will be described with reference to Figure 2.

[0058] 2 is an explanatory diagram illustrating an example of the result of encoding using the TPC code in the embodiment. The bit arrangement in FIG. 2 is the same as that used in Non-Patent Documents 1 and 2. In fact, the arrangement in FIG. 2 satisfies the fourth, fifth, and sixth sub-conditions in addition to the turbo product code conditions.

[0059] The fourth subcondition is that the information bits are arranged in a rectangle in two-dimensional space, the fifth subcondition is that the first axis is parallel to one side of the rectangle, and the sixth subcondition is that the result of encoding using the turbo product code further includes a parity bit based on the parity bit present on the first axis and the parity bit present on the second axis.

[0060] Generally, in encoding using a TPC code, parity bits are assigned to a bit string to be encoded, and an identifier represented by a two-dimensional vector (hereinafter referred to as a "vector identifier") is assigned to each of the information bits and the parity bits. Since the vector identifier is represented by a two-dimensional vector, it can be said to indicate the position of each bit to be assigned in two-dimensional space. Therefore, it can be said that the vector identifier indicates the arrangement of the information bits and parity bits of the bit string to be encoded in two-dimensional space.

[0061] FIG. 2 shows an example of this arrangement. In the example of FIG. 2, the two-dimensional space is the XY plane. In the arrangement of the example of FIG. 2, the information bits are arranged in the shape of a square with one side parallel to the X axis. Furthermore, the parity bits are arranged so as to form a square (hereinafter referred to as a "mixed bit square") that contains the square (hereinafter referred to as an "information bit square") and has only one corner that coincides with a corner of the information bit square. Note that the shape of the bit arrangement may be a rectangle instead of a square, but for simplicity of explanation, a square will be used here.

[0062] In the example of Figure 2, the squares in area A101 are example information bit squares, and the squares in area A105 are example mixed bit squares. Area A105 includes areas A101, A102, A103, and A104. Parity bits are arranged in areas A102 and A103. A parity bit of a parity bit is arranged in area A105.

[0063] A horizontal code refers to a row of the mixed-bit square, i.e., a sequence of bits on an axis parallel to the X-axis. A vertical code refers to a column of the mixed-bit square, i.e., a sequence of bits on an axis parallel to the Y-axis.

[0064] In the example of Figure 2, bit string F101 is an example of a horizontal code, and bit string F102 is an example of a vertical code. The bits in area A102 are parity bits of the horizontal code, and the bits in area A103 are parity bits of the vertical code. The parity bit in area A105 is a parity bit between the parity bit of the vertical code and the parity bit of the horizontal code. The value of the parity bit is determined based on the information bit string present on the axis on which the parity bit exists.

[0065] 2, in the decoding process when the hyperparameters α and β are not optimized, the following first decoding sub-process and second decoding sub-process are executed. The first decoding sub-process is a process in which the LLR of each bit of the horizontal codes is updated for all horizontal codes, and then the LLR of each bit of the vertical codes is updated for all vertical codes, and this process is repeated until a predetermined maximum number of iterations is reached.

[0066] The second decoding sub-process is a process of making a hard decision for each bit. Note that the decoding process in the example of FIG. 2 when the hyperparameters α and β are not optimized is the process described in Non-Patent Documents 1 and 2.

[0067] On the other hand, in the hyperparameter optimization process in the example of Fig. 2, the hyperparameters α and β are optimized. The optimization of the hyperparameters α and β is performed every time immediately before the process of updating the LLR of each bit of the horizontal codes is performed for all horizontal codes, and immediately before the process of updating the LLR of each bit of the vertical codes is performed for all vertical codes.

[0068] Therefore, after optimizing the hyperparameters α and β, the LLRs of each bit of the horizontal codes are updated for all horizontal codes, and then the hyperparameters α and β are optimized again. Then, the LLRs of each bit of the vertical codes are updated for all vertical codes. This process is repeated in the hyperparameter optimization process until a predetermined maximum number of iterations is reached.

[0069] <<<Correspondence Between Odd-Numbered Unit Processing and Even-Numbered Unit Processing>> The correspondence between odd-numbered unit processing and even-numbered unit processing will be described. A set of optimization of hyperparameters α and β and processing in which the LLR of each bit of horizontal codes is updated for all horizontal codes is an example of an odd-numbered unit processing. A set of optimization of hyperparameters α and β and processing in which the LLR of each bit of vertical codes is updated for all vertical codes is an example of an even-numbered unit processing.

[0070] Furthermore, in the explanation of the log-likelihood ratio update process, it was explained that the log-likelihood ratios of each information bit and parity bit on all or some of the target axes are updated, but in the example of Figure 2, a process is performed to update the log-likelihood ratios of each information bit and parity bit on all of the target axes.

[0071] <<<<Additional Explanation of Turbo Product Code Conditions>>> The following is a supplementary explanation of the turbo product code conditions. A specific example of the arrangement rule is that the bits are arranged in a rectangular shape such as a square, as shown in the example of Figure 2. Depending on the arrangement rule, there are multiple types of encoding using TPC codes.

[0072] The position information refers to the vector identifier described above. An axis parallel to a predetermined direction in two-dimensional space is an axis parallel to the X-axis in the example of FIG. 2 described below. Since the square in the example of FIG. 2 exists only in a part of the two-dimensional space, there are also axes parallel to the X-axis on which no bits are allocated. Therefore, the definition of the first axis requires that at least one information bit be present.

[0073] When the first axis is an axis parallel to the X axis, in the example of Fig. 2, the axis perpendicular to the one direction is an axis parallel to the Y axis. Since the square in the example of Fig. 2 exists only partially in two-dimensional space, there are also axes parallel to the Y axis on which no bits are allocated. Therefore, the definition of the second axis requires that at least one information bit exists.

[0074] 3 is a diagram showing an example of the hardware configuration of the receiving device 2 in an embodiment. The receiving device 2 includes a control unit 21 including a processor 91 and a memory 92, and executes a program. By executing the program, the receiving device 2 functions as a device including the control unit 21, an interface unit 22, and a storage unit 23.

[0075] More specifically, the processor 91 reads out a program stored in the storage unit 23 and stores the read program in the memory 92. The processor 91 executes the program stored in the memory 92, causing the receiving device 2 to function as a device including the control unit 21, the interface unit 22, and the storage unit 23.

[0076] The control unit 21 controls the operation of each functional unit included in the receiving device 2. The control unit 21, for example, decodes encoded information. Therefore, the control unit 21 performs, for example, error correction processing. In the error correction processing, the control unit 21 performs hyperparameter optimization processing.

[0077] The control unit 21 acquires, for example, information stored in the storage unit 23. The process of acquiring information stored in the storage unit 23 is specifically a read process.

[0078] The interface unit 22 may be configured to include input devices such as a mouse, a keyboard, a touch panel, etc. The interface unit 22 may be configured as an interface that connects these input devices to the receiving device 2. In this way, the input devices of the interface unit 22 accept input of various information to the receiving device 2 via wired or wireless connections. Note that the various information that can be input to the communication interface of the interface unit 22 does not necessarily have to be input to the communication interface of the interface unit 22, and may also be input to the input devices of the interface unit 22.

[0079] The interface unit 22 outputs, for example, various types of information. The interface unit 22 includes, for example, a display device such as a CRT (Cathode Ray Tube) display, a liquid crystal display, or an organic EL (Electro-Luminescence) display, and a speaker. The interface unit 22 may be configured as an interface that connects these display devices or speakers to the receiving device 2. Therefore, the interface unit 22 may output, for example, information input to a communication interface or an input device of the interface unit 22 as an image or sound.

[0080] The storage unit 23 is configured using a computer-readable storage medium device (non-transitory computer-readable recording medium) such as a magnetic hard disk device or a semiconductor storage device. The storage unit 23 stores various information related to the receiving device 2. The storage unit 23 stores various information generated by the operation of the control unit 21, for example. The storage unit 23 may exist on a cloud, for example.

[0081] 4 is a flowchart showing an example of the flow of processing executed in the communication system 100 according to the embodiment. The transmitting device 1 transmits encoded information (step S101). Next, the receiving device 2 receives the encoded information (step S102). Next, the control unit 21 of the receiving device 2 executes decoding processing (step S103). Error correction is executed in this decoding processing, and hyperparameter optimization processing is executed in the error correction.

[0082] <Experimental Results> Examples of the results of experiments to evaluate the performance of error correction will be described with reference to FIGS. 5 and 6. FIG.

[0083] Fig. 5 is a diagram showing an example of the results of an experiment of the embodiment. Fig. 6 is a diagram showing the values ​​of the hyperparameters α and β in the experiment of the embodiment. Fig. 6 is a diagram showing the experimental conditions. More specifically, Fig. 5 is a diagram showing the results of error correction, showing the relationship between Eb / N0 (signal-to-noise ratio per information bit) of the received signal and the bit error rate after error correction.

[0084] The experimental results shown in Fig. 5 are the results of an experiment comparing the results of error correction that involves hyperparameter optimization with the results of error correction that does not involve hyperparameter optimization. In the error correction that does not involve hyperparameter optimization, the typical values ​​described in Non-Patent Document 1 were used for both the hyperparameters α and β.

[0085] In the experiment, the extended BCH (128, 113) code was used as both the vertical and horizontal element codes. The number of test patterns used to search for the nearest neighbor codeword and the next best codeword was 64, and the number of LLR update processes was 16.

[0086] The optimal values ​​and typical values ​​of the hyperparameters α and β in each LLR update process are as shown in FIG. 6. Note that the value in the braces in FIG. 6 indicates the value in the LLR update process executed at an earlier stage, with the value further to the left. Therefore, for example, the α obtained by optimization in the first LLR update process is ｏｐｔ The value of and β ｏｐｔ FIG. 6 indicates that the values ​​of are 0 and 0.197.

[0087] The results in FIG. 5 show that using optimized α, β results in lower bit error rates at lower Eb / N0.

[0088] The receiving device 2 in this embodiment configured as above optimizes the hyperparameters α and β, which can improve the error correction performance as described in <Effects of the hyperparameter optimization process>.

[0089] (Modification) As described above, the example in Fig. 2 is one example of the result of encoding using the TPC code. The result of encoding using the TPC code is not necessarily limited to the example in Fig. 2. In other words, an arrangement that satisfies the turbo product code condition does not necessarily have to also satisfy some or all of the fourth sub-condition, the fifth sub-condition, and the sixth sub-condition, and may be the result in Fig. 7, for example.

[0090] 7 is a diagram showing a first example of the result of encoding using a TPC code in a modified example. In the example of FIG. 7, the bit arrangement in two-dimensional space is in the form of a staircase. This is an example in which an extended BCH (128, 113) code is used as the element code. More specifically, the bit arrangement in the example of FIG. 7 is an arrangement in which 64-bit x 64-bit squares are arranged in a staircase pattern.

[0091] 7, LLR update processing is performed in the column direction and in the row direction, sequentially following a staircase shape. Therefore, for example, for bits in area A201, after being updated by the column-direction LLR update processing executed as the first LLR update processing, they are further updated by the row-direction LLR update processing executed as the second LLR update processing. The row direction is the direction parallel to the X-axis, and the column direction is the direction parallel to the Y-axis.

[0092] As indicated by the arrows in FIG. 7, each bit of a bit string having a bit number of (64 bits×2) is updated in one LLR update process, and this is performed for each of the 64 bit strings.

[0093] The bits in area A202 are updated by a row-wise LLR update process executed as the second LLR update process, and then further updated by a column-wise LLR update process executed as the third LLR update process.

[0094] The bits in area A203 are updated by a column-wise LLR update process executed as the third LLR update process, and then further updated by a row-wise LLR update process executed as the fourth LLR update process.

[0095] The bits in area A204 are updated by a row-wise LLR update process executed as the fourth LLR update process, and then further updated by a column-wise LLR update process executed as the fifth LLR update process.

[0096] Before each LLR update process is performed, the hyperparameters α and β are optimized.

[0097] In the example of Figure 7, the parity bits are 15 bits x 64 bits. However, the number of bits is merely an example and is not necessarily limited to 15 bits or 64 bits. Note that all bits in the first square of the staircase structure may be zero. Note that the first square is a square whose bits are updated by the first LLR update process and does not include parity bits.

[0098] 7, the square in area A200 is the first square, and therefore, no parity bit exists in the square in area A200.

[0099] In the example of FIG. 7, for simplicity, the arrangement of bits in the areas A200 to A204 has been described as being square, but the arrangement may also be rectangular.

[0100] 7, the regions A201 and A203 are named "first type bit blocks," and the regions A201 and A203 are named "second type bit blocks." The hyperparameters α and β may be individually optimized for the bits in the first type bit blocks and the bits in the second type bit blocks. Furthermore, the hyperparameters α and β individually optimized for the bits in the LLR update process may also be used.

[0101] In the example of Fig. 7, when the first axis is parallel to the Y axis, the second axis is parallel to the X axis. When the first axis is parallel to the X axis, the second axis is parallel to the Y axis. In the example of Fig. 7, the bit strings on each first axis are bit strings in which 64 bits + 64 bits - 15 information bits and 15 parity bits are arranged, and the bit strings on each second axis are also bit strings in which 64 bits + 64 bits - 15 information bits and 15 parity bits are arranged.

[0102] 7 is an area where parity bits exist, and no information bits exist within the parity bit block.

[0103] In the description of the log-likelihood ratio updating process in odd-numbered unit processing, it has been described that the log-likelihood ratios of the information bits and parity bits on all or part of the first axes are updated, but in the example of Fig. 7, a process is performed to update the log-likelihood ratios of the information bits and parity bits on part of the first axes. This is because, in the example of Fig. 7, at the timing when the process to update the log-likelihood ratios is performed for bit sequences on axes parallel to the Y axis in areas A200 and A201, the process to update the log-likelihood ratios is not performed for bit sequences on axes parallel to the Y axis in areas A202 and A203.

[0104] In the description of the log-likelihood ratio update process in the even-numbered unit processing, it has been described that the log-likelihood ratios of the information bits and parity bits on all or part of the second axes are updated, but in the example of Fig. 7, a process of updating the log-likelihood ratios of the information bits and parity bits on part of the second axes is performed. This is because, in the example of Fig. 7, for example, at the timing when the process of updating the log-likelihood ratios is performed for bit sequences on axes parallel to the X axis in areas A201 and A202, the process of updating the log-likelihood ratios is not performed for bit sequences on axes parallel to the X axis in areas A203 and A204.

[0105] The arrangement that satisfies the turbo product code condition may be the result of FIG. 8, for example.

[0106] Fig. 8 is a diagram showing a second example of the result of encoding using the TPC code in the modified example. The example in Fig. 8 is an OFEC in which the shape of the bit arrangement in two-dimensional space is described in the following reference 1. The OFEC has a configuration equivalent to the staircase shape in Fig. 7. Therefore, the OFEC can also be optimized by a hyperparameter optimization process.

[0107] Reference 1: W. Wang, et al., "Real-time FPGA investigation of potential FEC schemes for 800G-ZR / ZR+ forward error correction," Journal of Lightwave Technology, vol. 41, no. 3, pp. 926 933, 2023.

[0108] Note that OFEC uses an extended BCH (256, 239) code as an element code, and in all bit blocks, the LLR update for the latter 128 bits of the BCH-coded 256 bits is the lth LLR update, and the LLR update for the first 128 bits is the l+1th LLR update. Therefore, the first 128 bits and the last 128 bits of the BCH-coded 256 bits may be individually optimized for the hyperparameters α and β. Furthermore, when performing the LLR update process, the hyperparameters α and β optimized individually may be used. Note that a bit block refers to an area in which bits are arranged in a rectangular shape, such as a square.

[0109] In the error correction, hard decision is performed after the LLR update process has been performed up to the maximum number of iterations, as in the processes described in Non-Patent Document 1 and Non-Patent Document 2. By performing hard decision, decoding of the coded information is completed.

[0110] The receiving device 2 may be implemented using a plurality of information processing devices connected to each other via a network so as to be able to communicate with each other. In this case, the processes executed by the control unit 21 may be distributed among the plurality of information processing devices.

[0111] Note that all or part of the functions of the communication system 100 and the receiving device 2 may be realized using hardware such as an ASIC (Application Specific Integrated Circuit), a PLD (Programmable Logic Device), or an FPGA (Field Programmable Gate Array). The program may be recorded on a computer-readable recording medium. Examples of computer-readable recording media include portable media such as flexible disks, optical magnetic disks, ROMs, and CD-ROMs, and storage devices such as hard disks built into computer systems. The program may be transmitted via a telecommunications line.

[0112] Although an embodiment of the present invention has been described in detail above with reference to the drawings, the specific configuration is not limited to this embodiment, and includes designs within the scope of the gist of the present invention.

[0113] REFERENCE SIGNS LIST 100: communication system, 1: transmitting device, 2: receiving device, 21: control unit, 22: interface unit, 23: storage unit, 91: processor, 92: memory

Claims

1. An error correction device comprising: a control unit that performs error correction on encoded information that is information encoded using a turbo product code sent from a transmission source, wherein the control unit optimizes hyperparameters α and β in encoding using the turbo product code so as to minimize the cross-entropy of the encoded information during the error correction.

2. The result of encoding using the turbo product code is a bit string to which parity bits representing information to be encoded are assigned, and each information bit in the bit string is assigned information about its position in two-dimensional space, the information being determined according to a predetermined rule regarding the position of each information bit in the two-dimensional space, and the parity bit exists on each first axis, which is an axis parallel to a predetermined direction in the two-dimensional space and on which at least one information bit exists, and also on each second axis, which is an axis perpendicular to the one direction in the two-dimensional space and on which at least one information bit exists, and the value of each parity bit is determined based on the information bit string existing on the first axis or second axis on which the parity bit exists, and in the error correction, the optimization is performed by an iterative process that repeats unit processes, and the unit process is a process of updating the hyperparameter α and the hyperparameter β, 2. The error correction device according to claim 1, wherein in the l-th unit process (l is an integer greater than or equal to 1), the following processes are executed: a log-likelihood ratio update process for updating the log-likelihood ratio of the encoded information based on the log-likelihood ratio of each information bit and parity bit in all or part of one or more target axes calculated based on the hyper-parameter α and the hyper-parameter β obtained in the (l-1)th unit process; and a process for updating the hyper-parameter α and the hyper-parameter β so as to minimize the cross-entropy based on the log-likelihood ratios after updating by the log-likelihood ratio update process, wherein the target axis is the first axis when the unit process is an odd-numbered unit process, and is the second axis when the unit process is an even-numbered unit process.

3. The result of encoding using the turbo product code is a bit string to which parity bits representing information to be encoded are assigned, and each information bit in the bit string is assigned information about its position in two-dimensional space, the information being determined according to a predetermined rule regarding the position of each information bit in the two-dimensional space, and the parity bit exists on each first axis, which is an axis parallel to a predetermined direction in the two-dimensional space and on which at least one information bit exists, and also on each second axis, which is an axis perpendicular to the one direction in the two-dimensional space and on which at least one information bit exists, and the value of each parity bit is determined based on the information bit string existing on the first axis or the second axis on which the parity bit exists, and the information bits are arranged in a rectangle in the two-dimensional space, and the first axis is parallel to one side of the rectangle, and the result of encoding using the turbo product code further has a parity bit based on the parity bit existing on the first axis and the parity bit existing on the second axis, and the error correction is performed by an iterative process that repeats unit processing, 2. The error correction device according to claim 1, wherein the unit process is a process of updating the hyperparameter α and the hyperparameter β, and in an l-th unit process (l is an integer greater than or equal to 1), the following processes are executed: a log-likelihood ratio update process of updating the log-likelihood ratio of the information to be encoded based on the log-likelihood ratio of each information bit and parity bit in all or a part of one or more target axes calculated based on the hyperparameter α and the hyperparameter β obtained in an (l-1)th unit process; and a process of updating the hyperparameter α and the hyperparameter β so as to minimize the cross-entropy based on the log-likelihood ratios after updating by the log-likelihood ratio update process, and the target axis is the first axis when the unit process is an odd-numbered unit process, and is the second axis when the unit process is an even-numbered unit process.

4. The error correction device according to any one of claims 1 to 3, wherein the optimization is performed by a steepest descent method.

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