Magnetic storage element and writing method for magnetic storage device

Abstract

Provided is a magnetic storage element comprising a first stack composed of: a storage layer formed from a ferromagnetic body; a first fixed layer formed from a ferromagnetic body; a first spacer layer that is sandwiched by the storage layer and the first fixed layer, and that causes antiferromagnetic exchange coupling between the storage layer and the first fixed layer; and a tunnel barrier layer that is provided to the opposite-side surface of the storage layer from the first spacer layer and that is formed of a non-magnetic body. The first stack is sandwiched by a first electrode and a second electrode.

Description

Magnetic memory element and method for writing to magnetic memory device

[0001] The present disclosure relates to a magnetic memory element and a method for writing to a magnetic memory device.

[0002] A magnetoresistive random access memory (MRAM) using a magnetic memory element (magnetoresistive effect element) has a magnetic tunnel junction structure in which a tunnel barrier layer is sandwiched between two magnetic layers (a memory layer and a reference layer). The magnetic tunnel junction structure is used for data storage because its resistance changes depending on the relative magnetization angle between the memory layer, whose magnetization direction is variable, and the reference layer, whose magnetization direction is invariable, and therefore exhibits binary resistance depending on whether the relative magnetization direction is parallel or antiparallel. Specifically, in the memory layer, perpendicular magnetic anisotropy (PMA) makes magnetic energy most stable in two directions, up and down, and because there is an energy barrier at the angle between them, non-volatile data retention is possible even when the voltage is turned off.

[0003] When writing to a voltage-driven magnetic storage device (VC-MRAM: Voltage Controlled Magnetic Random Access Memory), an energy barrier is removed by voltage-controlled magnetic anisotropy (VCMA: Voltage Controlled Magnetic Anisotropy) under the application of an in-plane magnetic field, causing the magnetization of the storage layer to begin precessing with the magnetic field direction as the precession axis. Data writing is then completed by cutting off the voltage when the magnetization direction of the storage layer is reversed. In principle, this voltage-driven writing method is capable of high-speed writing, and has the advantage of low power consumption due to voltage driving.

[0004] Japanese Patent Application Laid-Open No. 2016-225633

[0005] In conventional VC-MRAM, it is necessary to apply a pulse voltage with a short pulse width with high precision in order to reverse the magnetization direction of the storage layer. However, applying a pulse voltage with a short pulse width with high precision is difficult, and for example, a complex and large-scale control circuit is required to precisely control the short pulse width. Therefore, it is difficult to keep the write error rate (WER) low in conventional VC-MRAM.

[0006] Therefore, the present disclosure proposes a new and improved magnetic memory element and a method for writing to a magnetic memory device that do not require highly accurate control of the voltage pulse width.

[0007] According to the present disclosure, there is provided a magnetic memory element comprising a first stack including: a memory layer formed from a ferromagnetic material; a first fixed layer formed from a ferromagnetic material; a first spacer layer sandwiched between the memory layer and the first fixed layer and antiferromagnetically exchange coupling the memory layer and the first fixed layer; and a tunnel barrier layer formed from a nonmagnetic material and provided on the surface of the memory layer opposite the first spacer layer, wherein the first stack is sandwiched between a first electrode and a second electrode.

[0008] Furthermore, according to the present disclosure, there is provided a writing method for a magnetic memory device including a plurality of magnetic memory elements and a control circuit unit that writes data in the plurality of magnetic memory elements, wherein each of the plurality of magnetic memory elements includes a first stack including a memory layer formed from a ferromagnetic material, a first fixed layer formed from a ferromagnetic material, a first spacer layer sandwiched between the memory layer and the first fixed layer and antiferromagnetically exchange coupling the memory layer and the first fixed layer, and a tunnel barrier layer formed from a nonmagnetic material and provided on the surface of the memory layer opposite the first spacer layer, the first stack being sandwiched between a first electrode and a second electrode, and the control circuit unit applying a write voltage to the first electrode and the second electrode of the magnetic memory element of interest.

[0009] FIG. 1 is a diagram for explaining an example of a write operation of a VC-MRAM according to the prior art. FIG. 2 is a diagram showing a mathematical expression for the precession period of a VC-MRAM according to the prior art and a graph showing the relationship between the in-plane magnetic field and the precession period. FIG. 3 is a graph showing the relationship between the in-plane magnetic field and the precession period of a VC-MRAM according to the prior art. FIG. 4 is a diagram showing the pulse width dependency of the write error rate under each in-plane magnetic field application condition of a VC-MRAM according to the prior art. FIG. 1 is a diagram (part 1) for explaining an overview of a magnetic memory element according to an embodiment of the present disclosure. FIG. 2 is a diagram (part 3) for explaining an overview of a magnetic memory element according to an embodiment of the present disclosure. FIG. 4 is a diagram showing an overview of a magnetic memory element according to an embodiment of the present disclosure. FIG. 5 is a diagram showing an example configuration of a magnetic memory element according to an embodiment of the present disclosure. FIG. 6 is a diagram showing the configuration of an SAF coupled structure consisting of two SAF-coupled ferromagnetic layers according to an example. FIG. 7 is a diagram showing the hysteresis loop of an SAF coupled structure according to an example. FIG. 8 is a diagram showing the hysteresis loop of an SAF coupled structure under each perpendicular magnetic anisotropy condition obtained by theoretical calculation. 1 is a diagram showing a shift of a hysteresis loop at each applied voltage in an SAF bonded structure according to an example; FIG. 2 is a diagram showing a configuration example of a magnetic memory element according to a first modification of an embodiment of the present disclosure; FIG. 3 is a diagram showing a configuration example of a magnetic memory element according to a second modification of an embodiment of the present disclosure; FIG. 4 is a diagram showing a configuration example of a magnetic memory element 100 according to a third modification of an embodiment of the present disclosure; FIG. 5 is a diagram showing a configuration example of a magnetic memory element 100 according to a fourth modification of an embodiment of the present disclosure; FIG. 6 is a diagram showing a configuration example of a magnetic memory element 100 according to a fifth modification of an embodiment of the present disclosure; FIG. 7 is a diagram showing a configuration example of a storage device according to an embodiment of the present disclosure; FIG. 8 is a diagram showing a configuration example of a memory cell and its periphery according to an embodiment of the present disclosure; FIG. 9 is a flowchart showing an example of a process (without verification) executed when writing data according to an embodiment of the present disclosure; FIG. 10 is a timing chart for a data write process (without verification) according to an embodiment of the present disclosure; FIG. 11 is a flowchart showing an example of a process (with verification) executed when writing data according to an embodiment of the present disclosure; FIG. 12 is a timing chart for a data write process (with verification) according to an embodiment of the present disclosure.1 is a diagram illustrating an application example using a storage device according to an embodiment of the present disclosure. FIG. 2 is a diagram illustrating an example of the configuration of an imaging device according to Application Example 1. FIG. 3 is a diagram illustrating an example of the configuration of an AI chip according to Application Example 3. FIG. 4 is a flowchart (part 1) illustrating an example of processing executed in the AI ​​chip according to Application Example 3. FIG. 5 is a flowchart (part 2) illustrating an example of processing executed in the AI ​​chip according to Application Example 3. FIG. 6 is a diagram illustrating an example of the configuration of an AI chip according to a modified example of Application Example 3. FIG. 7 is a flowchart (part 1) illustrating an example of processing executed in the AI ​​chip according to a modified example of Application Example 3. FIG. 8 is a flowchart (part 2) illustrating an example of processing executed in the AI ​​chip according to a modified example of Application Example 3. FIG. 9 is a diagram illustrating an example of the configuration of an imaging device according to Application Example 4. FIG. 10 is a flowchart (part 1) illustrating an example of processing executed in the imaging device according to Application Example 4. FIG. 11 is a flowchart (part 2) illustrating an example of processing executed in the imaging device according to Application Example 4. FIG. 12 is a flowchart (part 3) illustrating an example of processing executed in the imaging device according to Application Example 4. FIG. 13 is a flowchart (part 3) illustrating an example of processing executed in the imaging device according to Application Example 4. FIG. 14 is a diagram illustrating an example of the configuration of an imaging device according to Application Example 5. 10 is a diagram illustrating an example of the configuration of an imaging device according to a modified example of application example 5. FIG. 11 is a diagram illustrating an example of the schematic configuration of a CPU according to application example 6. FIG. 12 is a diagram illustrating an example of the schematic configuration of a CPU according to a modified example of application example 6.

[0010] Preferred embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. In this specification and the drawings, components having substantially the same functional configurations are designated by the same reference numerals, and redundant description will be omitted. Furthermore, in this specification and the drawings, multiple components having substantially the same or similar functional configurations may be distinguished by adding different letters after the same reference numeral. However, when there is no particular need to distinguish between multiple components having substantially the same or similar functional configurations, only the same reference numerals will be used.

[0011] The drawings referred to in the following description are for explaining and facilitating understanding of one embodiment of the present disclosure, and for the sake of clarity, the shapes, dimensions, etc. shown in the drawings may differ from the actual ones. Furthermore, the design of the devices shown in the drawings can be modified as appropriate, taking into consideration the following description and known technologies.

[0012] The description of specific numerical values ​​in the following description does not necessarily mean the same values ​​as mathematically defined numerical values. In particular, the description of specific numerical values ​​in the following description also includes cases where there are allowable differences (errors and distortions) in magnetic memory elements, memory devices, their manufacturing processes, and their use and operation.

[0013] Furthermore, when describing the magnetization direction and magnetic anisotropy, terms such as "perpendicular direction" (the direction perpendicular to the film surface, or the stacking direction of the stacked structure) and "in-plane direction" (the direction parallel to the film surface, or the direction perpendicular to the stacking direction of the stacked structure) may be used for convenience. However, these terms do not necessarily refer to the strict direction of magnetization. For example, terms such as "the magnetization direction is perpendicular" and "having perpendicular magnetic anisotropy" mean that the perpendicular magnetization is dominant over the in-plane magnetization. Similarly, terms such as "the magnetization direction is in-plane" and "having in-plane magnetic anisotropy" mean that the in-plane magnetization is dominant over the perpendicular magnetization.

[0014] In the following description of circuits (electrical connections), unless otherwise specified, "electrically connected" or "connection" means connecting multiple elements so that electricity (signals) is conducted between them. In addition, "electrically connected" or "connection" in the following description includes not only cases where multiple elements are directly and electrically connected, but also cases where elements are indirectly and electrically connected via other elements.

[0015] The description will be given in the following order: 1. Background 2. Embodiments 2.1 Overview 2.2 Embodiments 2.3 Examples 2.4 Modifications 2.5 Configuration Examples of Storage Devices 2.6 Write Operation Examples 3. Summary 4. Application Examples 4.1 Various Devices 4.2 Application Example 1 4.3 Application Example 2 4.4 Application Example 3 4.5 Application Example 4 4.6 Application Example 5 4.7 Application Example 6 5. Supplementary Information

[0016] <<1. Background>> First, the background that led the inventors to create the embodiments of the present disclosure will be described with reference to Figures 1 to 4. Figure 1 is a diagram for explaining an example of a write operation of a VC-MRAM according to the prior art, and Figure 2 is a diagram showing a mathematical expression for the precession period of a VC-MRAM according to the prior art and a graph showing the relationship between the in-plane magnetic field and the precession period. Also, Figure 3 is a graph showing the relationship between the in-plane magnetic field and the precession period of a VC-MRAM according to the prior art, and Figure 4 is a diagram showing the pulse width dependency of the write error rate under various in-plane magnetic field application conditions of a VC-MRAM according to the prior art.

[0017] An MRAM using a magnetic memory element has a magnetic tunnel junction structure in which a tunnel barrier layer made of magnesium oxide (MgO) or the like is sandwiched between a memory layer and a reference layer made of a material containing at least one element selected from the group consisting of iron (Fe), cobalt (Co), nickel (Ni), and manganese (Mn). The magnetic tunnel junction structure is used for data storage because its resistance changes depending on the relative magnetization angle between the memory layer, whose magnetization direction is variable, and the reference layer, whose magnetization direction is invariable, and therefore it takes on two resistance values ​​(high resistance state, low resistance state) depending on whether the relative magnetization directions are parallel or antiparallel.

[0018] In writing to a voltage-driven magnetic memory device (VC-MRAM), an energy barrier is removed by applying an in-plane magnetic field through voltage modulation of the magnetic anisotropy, causing the magnetization of the storage layer to begin precessing with the magnetic field direction as the precession axis. Data writing is then completed by turning off the voltage when the magnetization of the storage layer reverses direction. This VC-MRAM writing method is, in principle, capable of high-speed writing on the order of sub-nanoseconds, and has the advantage of low power consumption due to voltage driving. However, the VC-MRAM writing method requires the application of an external magnetic field during writing, and due to constraints on the precession period, precise control of the write voltage pulse width on the order of less than a nanosecond is required.

[0019] First, an example of the write operation of a conventional VC-MRAM will be described with reference to Figure 1. The memory layer of a conventional VC-MRAM has perpendicular magnetic anisotropy. As shown in Figure 1, (a) in the standby state, magnetic energy A1 is most stable in two directions, up and down, and there is an energy barrier A2 at the angle between these two directions, so nonvolatile data can be retained even when the voltage is turned off. Also, (b) when a write voltage is applied, an in-plane magnetic field H ｅｘｔ By removing the energy barrier A2 by modulating the magnetic anisotropy under the applied magnetic field, the magnetization of the storage layer starts precessing with the applied magnetic field direction as the precession axis. Furthermore, (c) after writing, the writing is completed by cutting off the voltage when the magnetization faces the reversal direction E.

[0020] In the example of Figure 1, for convenience of explanation, an XYZ coordinate system (with the Y axis perpendicular to the paper surface) is shown. The X-axis and Y-axis directions correspond to the plane directions of the layers of the magnetoresistive element having the aforementioned stacked structure. The X-axis, Y-axis, and XY plane directions may also be referred to as horizontal directions. The Z-axis direction corresponds to the direction perpendicular to the plane direction of the layers of the magnetoresistive element (stacking direction). The Z-axis direction may also be referred to as the vertical direction.

[0021] The reversal time required for writing is determined by the precession period of the magnetization. Therefore, the precession period τ is expressed by the following equation (1).

[0022] In formula (1), α, γ, μ ０ are the damping constant, gyromagnetic ratio, and magnetic permeability, respectively. ｅｘｔ The relationship between the in-plane magnetic field H and the precession period τ is shown in Figure 2. The graph in Figure 2 shows the results for three different values ​​of the damping constant α (α = 0.1, 0.05, 0.01). However, within the realistic range of the damping constant α, the precession period τ is almost independent of the damping constant α, and overlaps under all conditions. Therefore, the reversal time is proportional to the in-plane magnetic field H ｅｘｔ It can be said that the difference is determined only by the size of

[0023] Next, in FIG. 3, the in-plane magnetic field H ｅｘｔ and the precession period τ, and several parameter sets in this relationship.

[0024] However, when a uniform in-plane magnetic field H ｅｘｔ It is difficult to apply a write voltage to a magnetic memory element, and it is expected that a variation of several Oe will occur for each bit. Therefore, when considering a region of approximately 10 ns or less where the pulse width of the write voltage applied to the magnetic memory element can be precisely controlled, it is found that the precession period τ (reversal time) varies greatly with a change of several Oe in the in-plane magnetic field Hext, as shown in Figure 3. In such a case, the write error rate (WER) will not decrease.

[0025] FIG. 4 shows the in-plane magnetic field H obtained by the simulation. ｅｘｔ 4 shows the pulse width dependency of the write error rate (WER) under the application condition of the in-plane magnetic field H ｅｘｔ The in-plane magnetic field H is relatively easy to control with high precision. ｅｘｔ The plot of white triangles shows the calculation results when the in-plane magnetic field H ｅｘｔ The plot of black triangles shows the calculation results when the in-plane magnetic field H ｅｘｔ The plot of white squares shows the calculation results when the in-plane magnetic field H ｅｘｔ The plots of white circles show the calculation results when the in-plane magnetic field H ｅｘｔThe plot of black circles shows the calculation results when the temperature is reduced to 17 Oe.

[0026] As shown in FIG. 4, the in-plane magnetic field H ｅｘｔ In the results of the plot of the white triangles when the precession period τ is set to 100 Oe, the window C1 in which the write error rate (WER) decreases narrows around 1 to 2 ns on the horizontal axis as the precession period τ shortens. Furthermore, it can be seen that the second and third successful write cycles occur around 5 to 6 ns and 9 ns on the horizontal axis. However, as the window C1 in which the write error rate decreases gradually narrows, it becomes difficult to ensure a margin.

[0027] In-plane magnetic field H ｅｘｔ The results of the plot of the white circles for the case of WER=22 Oe show that the window C2 where the write error rate (WER) decreases is wide in the region of 6 to 10 ns on the horizontal axis. The window width at WER=1e-4 is ｅｘｔ Compared to about 1 ns at 100 Oe, it is extended to about 4 ns, four times longer. However, the in-plane magnetic field H ｅｘｔ As shown in the results plotted by black circles when the in-plane magnetic field H ｅｘｔ The WER curve shifts by about 2 ns (see arrow C3) when the in-plane magnetic field H ｅｘｔ A method for precisely controlling this is needed.

[0028] That is, conventional VC-MRAM is attracting attention as a next-generation memory because it is capable of high-speed writing and has low power consumption. However, as mentioned above, conventional VC-MRAM requires the application of a relatively small magnetic field uniformly and precisely from the outside during writing, and requires precise control of the pulse width of the write voltage on the order of less than a nanosecond. Therefore, the narrow control margin makes it difficult to implement, and this is a hurdle to its practical application as a next-generation memory.

[0029] In view of this situation, the present inventors have created a novel magnetic memory element having two magnetic layers (a storage layer and a fixed layer) that are SAF (Synthetic Antiferromagnetic) exchange-coupled (antiferromagnetic exchange-coupled), as described below, and a tunnel barrier layer for modulating the perpendicular magnetic anisotropy of the storage layer by an applied voltage. The magnetic memory element according to this embodiment can perform writing by applying a write voltage to change (modulate) the value of the exchange coupling magnetic field Hex, which transitions the magnetization directions of the two SAF-coupled magnetic layers (a storage layer and a fixed layer) from an antiparallel state to a parallel state. For example, the magnetic memory element according to this embodiment can reverse the magnetization direction of the storage layer by simply changing the polarity of the applied voltage during writing, without applying a uniform and precise magnetic field from an external source, thereby enabling binary writing.

[0030] Therefore, the magnetic memory element according to this embodiment, like the conventional VC-MRAM, is capable of high-speed writing and consumes low power due to voltage driving. Furthermore, unlike the conventional VC-MRAM, the magnetic memory element according to this embodiment does not require precise control of the pulse width of the write voltage on the order of less than a nanosecond, since the reversal of the magnetization direction of the storage layer does not depend on the pulse width of the write voltage, and the write error rate (WER) can be kept low. Furthermore, the magnetic memory element according to this embodiment does not require initial reading, since the data written to the storage layer 106 depends on the write voltage and is non-toggle, independent of the state before writing. Details of the embodiments of the present disclosure created by the present inventors will be described below.

[0031] <<2. Embodiment>> <2.1 Overview> First, an overview of a writing method for a magnetic memory element (magnetic memory element) 100 according to this embodiment will be described with reference to Fig. 5 to Fig. 8. Fig. 5 to Fig. 8 are diagrams for explaining an overview of the magnetic memory element 100 according to the embodiment of the present disclosure, and in detail, the structure of the magnetic memory element 100 according to this embodiment is shown on the right side of the diagram, and a hysteresis loop is shown on the left side of the diagram.

[0032] 5, the magnetic memory element 100 has a laminated structure laminated on a substrate 130 and sandwiched between a lower electrode 122 and an upper electrode 120. The laminated structure is made up of a fixed layer 102 made of a ferromagnetic material, a memory layer 106 also made of a ferromagnetic material, a spacer layer 104 made of a nonmagnetic metal sandwiched between the fixed layer 102 and the memory layer 106, and a tunnel barrier layer 108 made of a nonmagnetic material. Note that the word "layer" may be interpreted as meaning a film, and the terms "layer" and "film" may be interpreted interchangeably as long as there is no contradiction.

[0033] In detail, the fixed layer 102 is a layer that has magnetic anisotropy and an invariable magnetization direction, and the storage layer 106 is a layer that has magnetic anisotropy and an invariable magnetization direction. The states in which the magnetization direction of the storage layer 106 is the same as the magnetization direction of the fixed layer 102 and the states in which it is different are called the parallel state and the antiparallel state, respectively, and data is written by entering these two states.

[0034] Furthermore, in this embodiment, a spacer layer 104 is provided so as to be sandwiched between the fixed layer 102 and the memory layer 106. Then, the fixed layer 102 and the memory layer 106 are SAF-coupled by the RKKY interaction of the spacer layer 104, and the magnetization directions of the fixed layer 102 and the memory layer 106 become opposite (antiparallel state), thereby stabilizing them.

[0035] Furthermore, similar to conventional VC-MRAM, the perpendicular magnetic anisotropy of the storage layer 106 can be modulated by an applied voltage at the interface between the ferromagnet (storage layer 106) and the insulator (tunnel barrier layer 108) (VCMA effect).

[0036] A schematic diagram of a hysteresis loop showing the external perpendicular magnetic field dependence of the magnetization direction in such a magnetic memory element 100 is shown on the left side of Fig. 5. In the hysteresis loop shown on the left side of Fig. 5, the horizontal axis represents the external perpendicular applied magnetic field, the vertical axis represents the perpendicular magnetization component, and the magnetization directions of the memory layer 106 and the fixed layer 102 in each region of the hysteresis loop are indicated by arrows. Note that in Fig. 5, the applied voltage V applied to the magnetic memory element 100 is assumed to be 0 V.

[0037] In the central region of the hysteresis loop, the fixed layer 102 and the storage layer 106 are SAF-coupled due to the RKKY interaction of the spacer layer 104, and the magnetization directions of the fixed layer 102 and the storage layer 106 are opposite (antiparallel state). However, when the external perpendicularly applied magnetic field exceeds a threshold, a step appears in the hysteresis loop. This step indicates that the SAF coupling is overwhelmed by the external perpendicularly applied magnetic field, and the magnetization directions of the fixed layer 102 and the storage layer 106 become the same (parallel state). Here, the magnitude of the magnetic field when transitioning from the antiparallel state to the parallel state is referred to as the exchange coupling magnetic field Hex. The exchange coupling magnetic field Hex is a value reflecting the magnitude of the coupling energy Jex of the SAF coupling between the fixed layer 102 and the storage layer 106. Furthermore, magnetization reversal, in which the SAF coupling between the fixed layer 102 and the storage layer 106 is overwhelmed by the external perpendicularly applied magnetic field and the fixed layer 102 and the storage layer 106 become parallel, occurs in both positive and negative magnetic fields, resulting in a hysteresis loop such as that shown in FIG. 5.

[0038] In this case, in a zero magnetic field, the magnetization direction of the memory layer 106 is in two different states, and therefore, binary storage is possible in the memory layer 106. However, in order to transition the memory layer 106 from one state to the other, the magnetization direction of the fixed layer 102 must also be reversed, but it is difficult to control such reversal by voltage.

[0039] Next, as an example of this embodiment, the right side of FIG. 6 shows a magnetic memory element 100 further including a reference layer 112 and an exchange bias layer 110 necessary for generating a magnetoresistance change in the magnetic memory element 100 and reading the magnetoresistance change. A schematic diagram of a hysteresis loop showing the dependence of the magnetization direction of such a magnetic memory element 100 on an external perpendicular magnetic field is shown on the left side of FIG. 6. In the hysteresis loop shown on the left side of FIG. 6, the horizontal axis represents the external perpendicularly applied magnetic field, the vertical axis represents the perpendicular magnetization component, and the magnetization directions of the storage layer 106 and the fixed layer 102 in each region of the hysteresis loop are indicated by arrows. Note that, in FIG. 6 as well, the applied voltage V applied to the magnetic memory element 100 is assumed to be 0 V. Here, for simplicity, the magnetization curve of the reference layer 112 is omitted, and the effect of the leakage magnetic field of the reference layer 112 and the effective magnetic field of the exchange bias layer 110 described later (in Figure 6, the reference layer 112 and the exchange bias layer 110 are shown as an example of the "additional magnetic field layer" described later) on shifting the hysteresis loop of the magnetic memory element 100 is shown.

[0040] The exchange bias layer 110 can apply an effective magnetic field called an exchange bias to the adjacent ferromagnetic material. Therefore, as shown on the left side of FIG. 6 , the hysteresis loop exhibits a change that appears to be shifted in one direction due to the leakage magnetic field from the reference layer 112 and the effective magnetic field of the exchange bias layer 110 (in other words, due to the additional magnetic field layer). Therefore, if the leakage magnetic field from the reference layer 112 and / or the effective magnetic field of the exchange bias layer 110 are set to be approximately equal to the exchange coupling magnetic field Hex, the loop indicating magnetization reversal crosses a zero magnetic field, as shown on the left side of FIG. 6 . Therefore, in a zero magnetic field, the magnetization direction of the storage layer 106 can be set to the same state (parallel state) or different state (antiparallel state) from the magnetization direction of the fixed layer 102, making it possible to write binary data to the storage layer 106.

[0041] A schematic diagram of a hysteresis loop showing the external perpendicular magnetic field dependence of the magnetization direction when a voltage is applied to such a magnetic memory element 100 is shown on the left side of Fig. 7. In the hysteresis loop shown on the left side of Fig. 7, the horizontal axis represents the external perpendicular applied magnetic field, the vertical axis represents the perpendicular magnetization component, and the magnetization directions of the storage layer 106 and the fixed layer 102 in each region of the hysteresis loop are indicated by arrows. Note that in the diagram on the left side of Fig. 7, a thick solid line indicates when the applied voltage V is 0, a dashed line indicates when the applied voltage V is a positive finite value (+V), and a dashed-dotted line indicates when the applied voltage V is a negative finite value (-V).

[0042] 7, the magnitude of the exchange coupling magnetic field Hex is modulated by the applied voltage. In this embodiment, the magnetization direction of the storage layer 106 is reversed by modulating the magnitude of the exchange coupling magnetic field Hex by the applied voltage.

[0043] Fig. 8 shows a minor loop focusing only on the reversal of the magnetization direction of the storage layer 106. In the hysteresis loop shown in Fig. 8, the horizontal axis represents the external perpendicularly applied magnetic field, the vertical axis represents the perpendicular magnetization component, and the arrows indicate the magnetization direction of the storage layer 106 in each region of the hysteresis loop. In Fig. 8, a thick solid line indicates when the applied voltage V is 0, a dashed line indicates when the applied voltage V is a positive finite value (+V), and a dashed line indicates when the applied voltage V is a negative finite value (-V).

[0044] As shown in Figure 8, when the applied voltage V is 0, the minor loop crosses the zero magnetic field, and the magnetization direction of the memory layer 106 is different at two points indicated by black triangles at zero magnetic field (no magnetic field). In detail, at the point indicated by the upper black triangle, the magnetization direction of the memory layer 106 points upward, and at the point indicated by the lower black triangle, the magnetization direction of the memory layer 106 points downward. Therefore, it can be seen that the memory layer 106 achieves a binary state in the absence of a magnetic field (zero magnetic field). In other words, the magnetic memory element 100 according to this embodiment functions as a nonvolatile memory element that stores binary information.

[0045] When a positive voltage (V+) is applied during writing, the minor loop shifts to the left, and therefore the only possible magnetization direction of the storage layer 106 in zero magnetic field (no magnetic field) is upward. On the other hand, when a negative voltage (V-) is applied during writing, the minor loop shifts to the right, and therefore the only possible magnetization direction of the storage layer 106 in zero magnetic field (no magnetic field) is downward. In other words, the magnetization direction of the storage layer 106 can be controlled solely by the polarity of the applied voltage, and further, the magnetization direction at that time is maintained when the applied voltage (when the voltage is 0) is turned off. Therefore, the magnetic memory element 100 according to this embodiment can be used as a nonvolatile memory element.

[0046] That is, the magnetic memory element 100 according to this embodiment can reverse the magnetization direction of the memory layer 106 simply by changing the polarity of the applied voltage during writing, without applying a uniform and precise magnetic field from the outside, thereby enabling binary writing. Furthermore, the magnetic memory element according to this embodiment does not require initial reading because the write data in the memory layer 106 is non-toggle dependent, i.e., dependent on the write voltage and not dependent on the state before writing.

[0047] As described above, in the magnetic memory element 100 according to this embodiment, unlike the conventional VC-MRAM, the reversal of the magnetization direction of the storage layer 106 does not depend on precession. That is, in the magnetic memory element 100 according to this embodiment, the reversal of the magnetization direction of the storage layer 106 depends on the write voltage, but not on the pulse width of the write voltage, so there is no need for precise control of the pulse width of the write voltage on the order of less than a nanosecond. Therefore, according to this embodiment, the write error rate (WER) can be kept low. In addition, like the conventional VC-MRAM, the magnetic memory element 100 according to this embodiment performs writing by applying a voltage, so high-speed writing is possible, and low power consumption is achieved due to voltage driving.

[0048] 2.2 Embodiment Next, a detailed configuration of a magnetic memory element (magnetic memory element) 100 according to an embodiment of the present disclosure will be described with reference to Fig. 9. Fig. 9 is a diagram showing an example of the configuration of the magnetic memory element 100 according to an embodiment of the present disclosure, and specifically corresponds to a cross-sectional view of the magnetic memory element 100 cut along the stacking direction of the magnetic memory element 100.

[0049] In this embodiment, as shown in FIG. 9 , the magnetic memory element 100 has a laminated structure (first laminated layer) laminated on a substrate 130 and sandwiched between a lower electrode (first electrode) 122 and an upper electrode (second electrode) 120. The laminated structure includes a fixed layer (first fixed layer) 102 made of a ferromagnetic material, a memory layer 106 also made of a ferromagnetic material, a spacer layer (first spacer layer) 104 made of a nonmagnetic metal sandwiched between the fixed layer 102 and the memory layer 106, and a tunnel barrier layer 108 made of a nonmagnetic material. Specifically, the spacer layer 104 sandwiched between the fixed layer 102 and the memory layer 106 provides SAF coupling between the fixed layer 102 and the memory layer 106 through RKKY interaction. Therefore, in this embodiment, the magnetization directions of the fixed layer 102 and the memory layer 106 are stabilized in an antiparallel state. The tunnel barrier layer 108 is provided on the surface of the memory layer 106 opposite to the spacer layer 104. Furthermore, a write voltage is applied to the upper electrode 120 and the lower electrode 122 to modulate the value Hex of the exchange coupling magnetic field that transitions the magnetization directions of the SAF-coupled memory layer 106 and fixed layer 102 from an antiparallel state to a parallel state.

[0050] Furthermore, the stacked structure may have, as an example of an additional magnetic field layer, a layer that applies an additional magnetic field in a direction perpendicular to the film surface of the magnetic memory element 100 to shift the hysteresis loop of the above-mentioned storage layer 106. Here, the additional magnetic field has, for example, the same absolute value as the value Hex of the exchange coupling magnetic field when the write voltage is 0 V, and has a magnetization direction opposite to that of the exchange coupling magnetic field Hex. In this embodiment, by applying such an additional magnetic field to the storage layer 106, the hysteresis loop of the storage layer 106 is shifted so that the loop indicating magnetization reversal crosses over zero magnetic field (no magnetic field).

[0051] For example, the stacked structure may include, as at least a part of the additional magnetic field layer, a reference layer (first reference layer) 112 made of a ferromagnetic material and provided on the surface of the tunnel barrier 108 opposite to the storage layer 106. Furthermore, for example, the stacked structure may include, as at least a part of the additional magnetic field layer, an exchange bias layer 110 made of an antiferromagnetic material and provided on the surface of the fixed layer 102 opposite to the spacer layer 104. The reference layer 112 can apply a fringing magnetic field to the storage layer 106, and the exchange bias layer 110 can apply an effective magnetic field to the storage layer 106. In this embodiment, by doing so, the hysteresis loop can be shifted in one direction by the effective magnetic field and / or the fringing magnetic field.

[0052] Furthermore, in this embodiment, for example, a hard bias layer that generates a leakage magnetic field may be added to the stacked structure, or an external magnetic field may be applied from outside the stacked structure. Alternatively, in this embodiment, the hysteresis loop may be shifted by the iDMI (interlayer Dzyaloshinskii-Moriya Interaction) effect by introducing a structural symmetry break between the SAF-coupled storage layer 106 and the fixed layer 102.

[0053] Furthermore, in this embodiment, an external magnetic field application unit that applies an additional magnetic field that shifts the hysteresis loop of the storage layer 106 described above may be provided outside the magnetic memory element 100 .

[0054] Furthermore, in this embodiment, the upper electrode 120 and the lower electrode 122 are made of a conductor, and a write voltage is applied to the stacked structure of the magnetic memory element 100. As described above, the write voltage is a voltage that modulates the value Hex of the exchange coupling magnetic field that transitions the magnetization directions of the SAF-coupled storage layer 106 and fixed layer 102 from an antiparallel state to a parallel state. Furthermore, in this embodiment, when an additional magnetic field is applied to the storage layer 106 to shift the hysteresis loop of the storage layer 106 so that the loop indicating magnetization reversal crosses a zero magnetic field (no magnetic field), the value written to the storage layer 106 can be switched between two values ​​by switching the polarity of the write voltage to positive or negative.

[0055] Furthermore, the stack may further include a voltage modulation enhancement layer 114 sandwiched between the tunnel barrier layer 108 and the storage layer 106. The voltage modulation enhancement layer 114 can enhance the VCMA effect that modulates the value of the exchange coupling magnetic field Hex due to the write voltage applied to the upper electrode 120 and the lower electrode 122, and this layer enables low-voltage driving.

[0056] In this embodiment, the cross-sectional structure when the magnetic memory element 100 is cut along the stacking direction is not particularly limited, and may be, for example, a rectangular shape, a trapezoidal shape (tapered hair shape / reverse tapered shape), a stepped shape, etc. Furthermore, in this embodiment, the cross-sectional structure when the magnetic memory element 100 is cut perpendicular to the stacking direction is also not particularly limited, and may be, for example, a circular shape, an elliptical shape, a polygonal shape, etc.

[0057] The fixed layer 102 is a ferromagnetic layer having a fixed magnetization direction. The magnetization direction of the fixed layer 102 is controlled by magnetic anisotropy to be perpendicular to the film surface, and the magnetization direction of the fixed layer 102 is antiparallel to the magnetization direction of the reference layer 112. Therefore, the fixed layer 102 has the function of canceling out the leakage magnetic field applied from the reference layer 112 to the storage layer 106.

[0058] The fixed layer 102 contains, for example, one or more elements selected from the group consisting of iron (Fe), cobalt (Co), nickel (Ni), manganese (Mn), platinum (Pt), and palladium (Pd), and at least a portion thereof is alloyed or composed of an artificial lattice of Co / Pt, Co / Ni, or Co / Pd.

[0059] The spacer layer 104 contains, for example, one or more elements selected from the group consisting of ruthenium (Ru), iridium (Ir), rhodium (Rh), rhenium (Re), vanadium (V), chromium (Cr), copper (Cu), niobium (Nb), molybdenum (Mo), tantalum (Ta), tungsten (W), iron (Fe), cobalt (Co), nickel (Ni), manganese (Mn), and magnesium (Mg). The spacer layer 104 may also be formed from an oxide containing at least one element selected from the group consisting of Cr, Fe, Co, Ni, Mn, and Mg. As described above, the spacer layer 104 couples the fixed layer 102 and the memory layer 106 to each other through the RKKY interaction. Therefore, in this embodiment, the magnetization directions of the fixed layer 102 and the memory layer 106 are opposite (antiparallel).

[0060] In this embodiment, the magnetization direction of at least a part of the memory layer 106 changes, for example, by application of a voltage. For example, the memory layer 106 has a thickness of 0.26 nm or more and 3 nm or less. By setting the thickness to this value, the magnetization direction becomes perpendicular to the film surface due to interfacial magnetic anisotropy during standby of the magnetic memory element 100. Furthermore, the thickness of the memory layer 106 is preferably 1.5 nm or less in order to increase the VCMA effect due to voltage and improve controllability during writing.

[0061] The storage layer 106 is made of a ferromagnetic material and contains, for example, one or more elements selected from the group consisting of Fe, Co, Ni, and Mn. Furthermore, one or more elements selected from the group consisting of hafnium (Hf), zirconium (Zr), titanium (Ti), tantalum (Ta), tungsten (W), gold (Au), molybdenum (Mo), ruthenium (Ru), palladium (Pd), yttrium (Y), vanadium (V), scandium (Sc), gadolinium (Gd), terbium (Tb), lanthanum (La), magnesium (Mg), aluminum (Al), silver (Ag), copper (Cu), chromium (Cr), boron (B), carbon (C), silicon (Si), gallium (Ga), and germanium (Ge) may be added to the storage layer 106 in order to increase VCMA efficiency, control interface magnetic anisotropy energy, adjust saturation magnetization, control magnetocrystalline anisotropy energy, and adjust crystal grain size and inter-crystal grain bonding.

[0062] In this embodiment, the perpendicular magnetic anisotropy of the storage layer 106 can be modulated by an applied voltage at the interface between the storage layer 106 and the tunnel barrier layer 108 (VCMA effect).

[0063] The tunnel barrier layer 108 may contain at least one of an oxide, a nitride, or a fluoride containing one or more elements selected from the group consisting of magnesium oxide (MgO), magnesium (Mg), calcium (Ca), lithium (Li), silicon (Si), aluminum (Al), strontium (Sr), zirconium (Zr), hafnium (Hf), titanium (Ti), zinc (Zn), scandium (Sc), lanthanum (La), tantalum (Ta), europium (Eu), copper (Cu), barium (Ba), molybdenum (Mo), tungsten (W), vanadium (V), yttrium (Y), nickel (Ni), cobalt (Co), manganese (Mn), chromium (Cr), iron (Fe), boron (B), and carbon (C), or may be formed using a stacked structure thereof. Furthermore, since the magnetic memory element 100 according to this embodiment is voltage-driven, the sheet resistance of the tunnel barrier layer 108 is 10 Ωμm 2 It is preferable that this is equal to or greater than this.

[0064] The magnetization direction of the reference layer 112 is controlled to be perpendicular to the film surface and does not substantially change, for example, when a voltage is applied. The electrical resistance of the stacked structure of the magnetic memory element 100 according to this embodiment changes before and after the voltage application. This change in electrical resistance is due to, for example, a change in the relative relationship between the magnetization direction of the reference layer 112 and the magnetization direction of at least a part of the storage layer 106. In this embodiment, the data stored in the storage layer 106 can be read by reading the resistance state (high resistance state (high resistance value) or low resistance state (low resistance value)) of the magnetic memory element 100.

[0065] Furthermore, the reference layer 112 can apply a fringing magnetic field Hstray to the storage layer 106, thereby shifting the hysteresis loop in one direction.

[0066] The reference layer 112 is made of a ferromagnetic material and contains, for example, one or more elements selected from the group consisting of iron (Fe), cobalt (Co), nickel (Ni), and manganese (Mn). Furthermore, the reference layer 112 may contain, for example, one or more elements selected from the group consisting of boron (B), carbon (C), magnesium (Mg), yttrium (Y), silicon (Si), aluminum (Al), tantalum (Ta), zirconium (Zr), hafnium (Hf), platinum (Pt), palladium (Pd), and rare earth elements in order to adjust saturation magnetization, control magnetocrystalline anisotropy energy, and adjust crystal grain size and inter-crystal grain bonding.

[0067] The exchange bias layer 110 is preferably an antiferromagnetic alloy, and the magnetization direction is controlled to be perpendicular to the film surface. The exchange bias layer 110 is made of an alloy containing one or more elements selected from the group consisting of chromium (Cr), manganese (Mn), iron (Fe), cobalt (Co), and nickel (Ni), and one or more elements selected from the group consisting of ruthenium (Ru), rhodium (Rh), palladium (Pd), silver (Ag), osmium (Os), iridium (Ir), platinum (Pt), and gold (Au). More specifically, the exchange bias layer 110 may be made of, for example, a Pt—Mn alloy, an Ir—Mn alloy, or an Fe—Mn alloy. Furthermore, Co—O, Ir—Mn, Fe—Mn, or Cr—O may be used as an antiferromagnetic layer for generating perpendicular exchange bias.

[0068] As explained above, the exchange bias layer 110 can apply an effective magnetic field HEB to the storage layer 106 and shift the hysteresis loop in one direction. Therefore, in this embodiment, the exchange bias layer 110 is designed to have an effective magnetic field HEB such that the center of the hysteresis loop (minor loop) of the storage layer 106 is near zero magnetic field. In other words, the exchange bias layer 110 is designed so that the effective magnetic field HEB of the exchange bias layer 110 is approximately equal to the exchange coupling magnetic field Hex. In this way, the magnetic memory element 100 can store binary values ​​in a nonvolatile manner, and the magnetization direction of the storage layer 106 can be controlled only by the polarity of the applied voltage.

[0069] Furthermore, as explained above, the reference layer 112 can apply a fringing magnetic field Hstray to the storage layer 106, and can shift the hysteresis loop in one direction. Therefore, in this embodiment, for example, when combining the effective magnetic field HEB of the exchange bias layer 110 and the fringing magnetic field Hstray of the reference layer 112, the exchange bias layer 110 and the reference layer 112 are designed so that the sum or difference of the effective magnetic field HEB of the exchange bias layer 110 and the fringing magnetic field Hstray of the reference layer 112 is approximately equal to the exchange coupling magnetic field Hex. Note that whether it is the sum or difference depends on the relative relationship between the magnetization direction of the exchange bias layer 110 and the magnetization direction of the reference layer 112.

[0070] In this embodiment, the method for shifting the hysteresis loop of the storage layer 106 is not limited to the above-described means. In this embodiment, for example, a hard bias layer that generates a leakage magnetic field may be added to the stacked structure. Alternatively, in this embodiment, the hysteresis loop may be shifted by the iDMI effect by introducing a structural symmetry break between the SAF-coupled storage layer 106 and the fixed layer 102. Furthermore, in this embodiment, the combination of an in-plane bias magnetic field and the iDMI effect for the storage layer 106 and the fixed layer 102 whose magnetization directions are perpendicular to the surface can produce the effect of shifting the hysteresis loop.

[0071] The voltage modulation enhancement layer 114 is provided for the purposes of increasing VCMA efficiency and controlling the interface magnetic anisotropy energy and damping constant. The voltage modulation enhancement layer 114 contains one or more elements selected from the group consisting of iridium (Ir), osmium (Os), platinum (Pt), rhodium (Rh), tantalum (Ta), titanium (Ti), tungsten (W), rhenium (Re), gold (Au), molybdenum (Mo), ruthenium (Ru), palladium (Pd), vanadium (V), chromium (Cr), and magnesium (Mg). Furthermore, the VCMA efficiency is enhanced by setting the thickness of the voltage modulation enhancement layer 140 to 0.5 nm or less. From the viewpoint of VCMA efficiency enhancement, the thickness of the voltage modulation enhancement layer 114 is preferably 0.3 nm or less. Furthermore, since the voltage modulation enhancement layer 114 enhances the damping constant of the storage layer 106, thereby enabling high-speed magnetization reversal, it is desirable to select a material that enhances the damping constant of the storage layer 106 from the above material group.

[0072] Furthermore, the stacked structure of the magnetic memory element 100 is not limited to the stacked structure of FIG. 9 and can be modified in various ways, such as the various modified examples described below. Furthermore, the stacked structure of the magnetic memory element 100 may have an underlayer 132 ( FIG. 9 ) inserted between the lower electrode 122 and the fixed layer 102. The underlayer 132 can be formed using, for example, a noble metal such as chromium (Cr), tantalum (Ta), ruthenium (Ru), gold (Au), silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), vanadium (V), molybdenum (Mo), zirconium (Zr), hafnium (Hf), rhenium (Re), tungsten (W), platinum (Pt), palladium (Pd), iridium (Ir), or rhodium (Rh), an alloy containing these, a layer made of a transition metal element, or a stacked structure thereof.

[0073] 2.3 Examples Below, examples that confirmed the effects of embodiments of the present disclosure will be described with reference to Fig. 10 to Fig. 13. Fig. 10 is a diagram showing the configuration of an SAF structure consisting of two SAF-coupled ferromagnetic layers according to an example, and Fig. 11 is a diagram showing the hysteresis loop of the SAF structure according to an example. Fig. 12 is a diagram showing the hysteresis loop of the SAF structure under various perpendicular magnetic anisotropy conditions obtained by theoretical calculation, and Fig. 13 is a diagram showing the shift of the hysteresis loop at various applied voltages in the SAF structure according to an example.

[0074] Here, verification was performed using a magnetic memory element 100 having a stacked structure as shown in FIG. 10 . In this example, the magnetic memory element 100 is stacked on a substrate 130 and has a stacked structure sandwiched between a lower electrode 122 consisting of a stack of Ta (5 nm thick) / Ru (10 nm thick) / Ta (5 nm thick) and an upper electrode 120 consisting of indium tin oxide (ITO) (20 nm thick). Furthermore, the stacked structure includes a fixed layer 102 consisting of Co (1.1 nm thick), a memory layer 106 consisting of Co (1.1 nm thick), a spacer layer 104 consisting of Ru (0.1 nm to 0.4 nm thick) that bonds the fixed layer 102 and the memory layer 106 via an SAF, and a tunnel barrier layer 108 consisting of a stack of MgO (2 nm thick) / HfOx (5 nm thick). The HfOx layer of the tunnel barrier layer 108 is stacked to increase the dielectric constant of the MgO layer. Furthermore, in this embodiment, a voltage modulation enhancement layer 114 is inserted between the memory layer 106 and the tunnel barrier layer 108, and the voltage modulation enhancement layer 114 is made of Ir (thickness: 0.1 nm). Also, in this example, an underlayer 132 is inserted between the lower electrode 122 and the fixed layer 102, and the underlayer 132 is made of Pt (thickness: 4 nm). Furthermore, in this example, each layer is formed at room temperature, and the magnetic memory element 100 is post-annealed at 250° C. for 1 hour.

[0075] The results of the hysteresis loop showing the dependency of the magnetization direction on the external perpendicular magnetic field obtained in the example are shown in the upper part of Fig. 11. In the hysteresis loop shown in the upper part of Fig. 11, the horizontal axis represents the external perpendicularly applied magnetic field, the vertical axis represents the perpendicular magnetization component, and the magnetization directions of the storage layer 106 and the fixed layer 102 in each region of the hysteresis loop are indicated by arrows. Note that the upper arrow indicates the magnetization direction of the storage layer 106, and the lower arrow indicates the magnetization direction of the fixed layer 102. The results shown in Fig. 11 are obtained when the applied voltage V is 0V.

[0076] 11, a step appears when the external perpendicular magnetic field exceeds ±10 kOe, indicating that the SAF coupling is defeated by the external perpendicular magnetic field, and the magnetization directions of the fixed layer 102 and the storage layer 106 become the same (parallel state). The magnitude of the magnetic field at this time is the exchange coupling magnetic field Hex described above.

[0077] Furthermore, the results of the hysteresis loop when a voltage (V = ±1.2 V) is applied to the magnetic memory element 100 according to the example are shown in the lower part of FIG. 11. The diagram in the lower part of FIG. 11 corresponds to the upper right region of the diagram in the upper part of FIG. 11, i.e., the vicinity of the exchange coupling magnetic field Hex. Therefore, in the hysteresis loop shown in the lower part of FIG. 11, the horizontal axis represents the external perpendicularly applied magnetic field, the vertical axis represents the perpendicular magnetization component, and the arrows indicate the magnetization directions of the memory layer 106 and the fixed layer 102 in each region of the hysteresis loop. The upper arrow indicates the magnetization direction of the memory layer 106, and the lower arrow indicates the magnetization direction of the fixed layer 102.

[0078] From the lower graph in FIG. 11, it is clear that the exchange coupling magnetic field Hex changes depending on the applied voltage.

[0079] Furthermore, the voltage modulation of the exchange coupling magnetic field Hex can be explained by the VCMA effect at the interface between the ferromagnet (storage layer 106) and the insulator (tunnel barrier layer 108). Therefore, the results of theoretical calculations performed on the magnetic memory element 100 shown in FIG. 12 are shown. Specifically, FIG. 12 shows the perpendicular magnetic anisotropy k1 at the interface between the ferromagnet (storage layer 106) and the insulator (tunnel barrier layer 108), which is modulated by voltage due to the VCMA effect, at 0.22 MJ / m. ３ ,0.135MJ / m ３ 12, the horizontal axis represents the external perpendicular applied magnetic field, and the vertical axis represents the amount of change in the Kerr rotation angle, i.e., the magnetization direction. In addition, in FIG. 12, the perpendicular magnetic anisotropy k1 is 0.22 MJ / m ３ The solid line indicates the perpendicular magnetic anisotropy k1 is 0.135 MJ / m ３ The dashed line indicates when

[0080] As shown in FIG. 12, the perpendicular magnetic anisotropy k1 of the interface between the storage layer 106 and the tunnel barrier layer 108 is set to 0.22 MJ / m ３ ,0.135MJ / m ３ 12, the exchange coupling magnetic field Hex is approximately 11.4 kOe and 10.3 kOe, respectively. That is, from the result of Figure 12, it can be seen that the exchange coupling magnetic field Hex changes due to the change in the perpendicular magnetic anisotropy k1 at the interface between the storage layer 106 and the tunnel barrier layer 108, which can be modulated by voltage due to the VCMA effect. Therefore, it was confirmed that the voltage modulation of the exchange coupling magnetic field Hex can be explained by assuming that the perpendicular magnetic anisotropy is modulated by the VCMA effect when a voltage is applied.

[0081] Next, the results of an experiment demonstrating magnetization reversal using voltage modulation of the exchange coupling magnetic field Hex are shown in Figure 13. Under the condition of an applied voltage V of 0 V, a magnetic memory element 100 with an exchange coupling magnetic field Hex of approximately 11 kOe was used. The results of a voltage sweep under application of an external perpendicular magnetic field (9 kOe, 11 kOe, 13 kOe) are shown in the upper part of Figure 13. In the upper part of Figure 13, the horizontal axis represents the sweep voltage, and the vertical axis represents the change in the Kerr rotation angle, i.e., the magnetization direction. In the upper part of Figure 13, the thick solid line represents the external perpendicular magnetic field H of 13 kOe, the dotted line represents the external perpendicular magnetic field H of 11 kOe, and the thin solid line represents the external perpendicular magnetic field H of 9 kOe.

[0082] From the results shown in the upper part of FIG. 13, it was found that only when the external perpendicular magnetic field was 11 kOe did the magnetization direction change due to the application of voltage, and that magnetization reversal occurred due to the application of voltage.

[0083] The above results will be considered using the hysteresis loop results under applied voltage (V = ±3.0 V) shown in the lower part of Figure 13. In the hysteresis loop shown in the lower part of Figure 13, the horizontal axis represents the external perpendicularly applied magnetic field, and the vertical axis represents the change in the Kerr rotation angle, i.e., the magnetization direction. Furthermore, in the lower part of Figure 13, the dashed line represents when the applied voltage V is +3 V, and the solid line represents when the applied voltage V is -3 V. In addition, in the lower part of Figure 13, the dashed and solid arrows connect the results for the applied magnetic fields of 9 kOe, 11 kOe, and 13 kOe in the upper part of Figure 13 to indicate where in the hysteresis loop they correspond.

[0084] In the lower part of Figure 13, the magnetization direction is constant regardless of the applied voltage in the cases of an applied magnetic field of 9 kOe and an applied magnetic field of 13 kOe, which is consistent with the fact that in the upper part of Figure 13, the magnetization direction did not change even when the voltage was swept in the range of ±3.0 V.

[0085] In contrast, in the lower part of FIG. 13 , the magnetization direction changes depending on the applied voltage for an applied magnetic field of 11 kOe. Specifically, for an applied magnetic field of 11 kOe, the results for an applied voltage V of −3 V show a Kerr rotation angle near 0, while the results for an applied voltage V of +3 V show a Kerr rotation angle near −0.07, indicating that the magnetization direction changes depending on the applied voltage. This is consistent with the change in the magnetization direction in the voltage range of ±3.0 V shown in the upper part of FIG. 13 . In other words, the results of FIG. 13 reveal that magnetization reversal occurs due to voltage modulation of the exchange coupling magnetic field Hex. Note that, although an additional magnetic field is applied from outside the magnetic memory element 100 here, in this embodiment, additional magnetic field application can be achieved by the exchange bias layer 110 or the like. In order to shift the hysteresis loop of the storage layer 106 so that it crosses the zero magnetic field, it may be preferable to use not only the effective magnetic field HEB from the exchange bias layer 110 but also the fringing magnetic field Hstray from the reference layer 112 or other layers, or to use the fringing magnetic field Hstray together with the effective magnetic field HEB from the exchange bias layer 110.

[0086] <2.4 Modifications> As described above, in this embodiment, the magnetic memory element 100 is not limited to the form shown in FIG. 9, but can be modified into various forms.

[0087] (Variation 1) First, a detailed configuration of a magnetic memory element 100a according to Variation 1 of the present embodiment will be described with reference to Fig. 14. Fig. 14 is a diagram showing an example of the configuration of a magnetic memory element 100a according to Variation 1 of the embodiment of the present disclosure, and more specifically corresponds to a cross-sectional view of the magnetic memory element 100a cut along the stacking direction of the magnetic memory element 100a.

[0088] The magnetic memory element 100a according to this modification has a basic structure that allows voltage modulation of the exchange coupling magnetic field Hex of the SAF coupling between the fixed layer 102 and the memory layer 106. That is, in this modification as well, the memory layer 106 and the fixed layer 102 are SAF coupled via the spacer layer 104. In this modification, when a voltage is applied in a direction perpendicular to the film surface of the magnetic memory element 100a, the perpendicular magnetic anisotropy is modulated by the VCMA effect at the interface between the tunnel barrier layer 108 and the memory layer 106, and the exchange coupling magnetic field Hex is modulated.

[0089] In this modified example, an external magnetic field may be applied from outside the stacked structure, or the hysteresis loop may be shifted by the iDMI effect by introducing a structural symmetry break between the SAF-coupled storage layer 106 and the fixed layer 102.

[0090] 14, the magnetic memory element 100a has a laminated structure (first laminated layer) laminated on a substrate 130 and sandwiched between a lower electrode 122 and an upper electrode 120. The laminated structure is made up of a fixed layer 102 made of a ferromagnetic material, a memory layer 106 also made of a ferromagnetic material, a spacer layer 104 made of a nonmagnetic metal sandwiched between the fixed layer 102 and the memory layer 106, and a tunnel barrier layer 108 made of a nonmagnetic material.

[0091] (Variation 2) First, a detailed configuration of a magnetic memory element 100b according to Variation 2 of the present embodiment will be described with reference to Fig. 15. Fig. 15 is a diagram showing a configuration example of a magnetic memory element 100b according to Variation 2 of the embodiment of the present disclosure, and more specifically, corresponds to a cross-sectional view of the magnetic memory element 100b cut along the stacking direction of the magnetic memory element 100b.

[0092] The magnetic memory element 100b according to this modification is obtained by inserting a voltage modulation enhancement layer 114 between the tunnel barrier layer 108 and the memory layer 106 in addition to the stacking of the magnetic memory element 100a according to the first modification described above. The voltage modulation enhancement layer 114 can enhance the voltage modulation effect (VCMA effect) that modulates the value of the exchange coupling magnetic field Hex due to the write voltage applied to the upper electrode 120 and the lower electrode 122. By inserting such a voltage modulation enhancement layer 114, the magnetic memory element 100b becomes capable of writing at a low voltage (more specifically, a small absolute value of the applied voltage).

[0093] (Variation 3) First, a detailed configuration of a magnetic memory element 100c according to Variation 3 of the present embodiment will be described with reference to Fig. 16. Fig. 16 is a diagram showing a configuration example of a magnetic memory element 100c according to Variation 3 of the embodiment of the present disclosure, and more specifically corresponds to a cross-sectional view of the magnetic memory element 100c cut along the stacking direction of the magnetic memory element 100c.

[0094] The magnetic memory element 100c according to this modification is the same as the magnetic memory element 100b according to the second modification, except that a reference layer (second reference layer) 112 is provided on the tunnel barrier layer 108. By providing the reference layer 112, it becomes possible to detect a change in the electrical resistance of the laminated structure due to a change in the relative relationship between the magnetization direction of the reference layer 112 and the magnetization direction of at least a part of the storage layer 106 before and after voltage application. Furthermore, the reference layer 112 applies a leakage magnetic field Hstray to the storage layer 106, which can shift the hysteresis loop in one direction.

[0095] (Variation 4) First, a detailed configuration of a magnetic memory element 100d according to Variation 4 of this embodiment will be described with reference to Fig. 17. Fig. 17 is a diagram showing a configuration example of a magnetic memory element 100d according to Variation 3 of the embodiment of the present disclosure, and more specifically, corresponds to a cross-sectional view of the magnetic memory element 100d cut along the stacking direction of the magnetic memory element 100d.

[0096] The magnetic memory element 100d according to this modification is obtained by providing a spacer layer (second spacer layer) 116 and a fixed layer (second fixed layer) 118 on the reference layer 112, in addition to the stack of the magnetic memory element 100c according to the above-described modification 3. In other words, it can also be said that the magnetic memory element 100d according to this modification is obtained by providing, on the tunnel barrier layer 108, a stacked structure (second stacked layer) including the reference layer 112 formed from a ferromagnetic material, the fixed layer 118 formed from a ferromagnetic material, and the spacer layer 116 sandwiched between the reference layer 112 and the fixed layer 118 and SAF-coupling the reference layer 112 and the fixed layer 118.

[0097] The fixed layer 118 is a ferromagnetic layer having a fixed magnetization direction. The magnetization direction of the fixed layer 118 is controlled by magnetic anisotropy in a direction perpendicular to the film surface, and the magnetization direction of the fixed layer 118 is antiparallel to the magnetization direction of the reference layer 112. Therefore, the fixed layer 118 can cancel out the leakage magnetic field applied from the reference layer 112 to the memory layer 106 and stabilize the magnitude of the additional magnetic field applied to the memory layer 106. Therefore, in this modification, the shift amount of the hysteresis loop of the memory layer 106 can be controlled with high precision.

[0098] The fixed layer 118 contains, for example, one or more elements selected from the group consisting of iron (Fe), cobalt (Co), nickel (Ni), manganese (Mn), platinum (Pt), and palladium (Pd), and at least a portion thereof is alloyed or composed of an artificial lattice of Co / Pt, Co / Ni, and Co / Pd.

[0099] The spacer layer 116 includes, for example, one or more elements selected from the group consisting of ruthenium (Ru), iridium (Ir), rhodium (Rh), rhenium (Re), vanadium (V), chromium (Cr), copper (Cu), niobium (Nb), molybdenum (Mo), tantalum (Ta), tungsten (W), iron (Fe), cobalt (Co), nickel (Ni), manganese (Mn), and magnesium (Mg). Alternatively, the spacer layer 116 may be formed of, for example, an oxide containing at least one element selected from the group consisting of Cr, Fe, Co, Ni, Mn, and Mg. As described above, the spacer layer 116 couples the fixed layer 118 and the reference layer 112 to each other via the RKKY interaction. Therefore, in this modification, the magnetization directions of the fixed layer 118 and the reference layer 112 are opposite (antiparallel).

[0100] (Variation 5) First, a detailed configuration of a magnetic memory element 100e according to Variation 5 of this embodiment will be described with reference to Fig. 18. Fig. 18 is a diagram showing a configuration example of a magnetic memory element 100e according to Variation 3 of the embodiment of the present disclosure, and more specifically, corresponds to a cross-sectional view of the magnetic memory element 100e cut along the stacking direction of the magnetic memory element 100e.

[0101] The magnetic memory element 100e according to this modification has the stacking order reversed upside down in the magnetic memory element 100d according to the above-described modification 4. In this modification, even when the stacking order is reversed, it is possible to make it function in the same way as modification 4, so it is preferable to select whether or not to reverse the stacking order depending on the combination of the film formation process and the element characteristics and circuit characteristics. Note that in the above-described embodiments and modifications of the present disclosure, the illustrated stacking order can also be reversed upside down.

[0102] In these modified examples, the magnetic memory element 100 is not limited to the forms shown in FIGS. 15 to 18, but can be further modified in various ways.

[0103] 2.5 Configuration Example of Storage Device The magnetic memory element 100 according to an embodiment of the present disclosure can be used, for example, as a component of a storage device (magnetic storage device) 200. Hereinafter, a configuration example of the storage device 200 according to an embodiment of the present disclosure will be described with reference to Fig. 19. Fig. 19 is a diagram showing a configuration example of the storage device 200 according to an embodiment of the present disclosure.

[0104] As shown in FIG. 19 , the memory device 200 has a memory cell array 70 including a plurality of memory cells 10 arranged two-dimensionally. Furthermore, the memory cell array 70 includes a magnetic memory element 100 according to an embodiment of the present disclosure and a selection transistor 8. The memory device 200 also has bit lines BL, source lines SL, and word lines WL as signal lines / control lines for accessing the memory cells 10 for data reading and writing, etc. The word lines WL, the bit lines BL, and the source lines SL extend so as to intersect (e.g., perpendicular to) each other. Each memory cell 10 is connected to the bit lines BL, the source lines SL (also called sense lines), and the word lines WL.

[0105] The memory cell 10 is a unit for reading and writing data, and in this sense can be regarded as the same as the magnetic memory element 100. Within the scope of no contradiction, the memory cell 10 and the magnetic memory element 100 may be interpreted as appropriate.

[0106] In this embodiment, the memory device 200 also includes various peripheral circuits / elements provided around the memory cell array 70. As shown in FIG. 19 , the peripheral circuits / elements include an I / O (Input / Output) 730, a control circuit (control circuit section) 731, a voltage generation circuit 732, a write circuit 733, a read circuit 734, a bit / source line address decoder 735, a bit / source line control circuit 736, a word line address decoder 737, a word line control circuit 738, and a sense amplifier 739. The bit / source line control circuit 736 is connected to the bit lines BL and source lines SL. The word line control circuit 738 is connected to the word lines WL. The sense amplifier 739 is connected to the bit lines BL and source lines SL.

[0107] Commands relating to data write and data read, addresses of memory cells 10 to be accessed, write data, read data, etc. are exchanged between elements external to the storage device 200 and a control circuit 731 of the storage device 200 via the I / O 730. An example of an element external to the storage device 200 is a host computer such as a CPU (Central Processing Unit).

[0108] The control circuit 731 controls other peripheral circuits / elements in response to commands. It can be said that the entire storage device 200 except for the I / O 730 is substantially controlled by the control circuit 731. The control by the control circuit 731 includes control of writing data to the magnetic memory element 100, control of reading data from the magnetic memory element 100, etc. The control circuit 731 is configured to include, for example, a state machine, etc.

[0109] The voltage generating circuit 732 generates a pulse voltage (write voltage) used for writing data and a voltage (read voltage) used for reading data. Voltages required for circuit operation may be supplied separately.

[0110] The write circuit 733 uses the voltage generated by the voltage generating circuit 732 to control the pulse of the write voltage.

[0111] The read circuit 734 uses the voltage generated by the voltage generating circuit 732 to control the pulse of the read voltage.

[0112] The bit / source line address decoder 735 obtains the addresses of the bit lines BL and source lines SL corresponding to the addresses received at the I / O 730 described above.

[0113] The bit / source line control circuit 736 selects and controls the bit line BL and source line SL corresponding to the address of the word line address decoder 737. Writing of data to the memory cell 71 using a data write voltage generated by the voltage generation circuit 732 and pulse-controlled by the read circuit 734 is performed via the bit / source line control circuit 736, etc. Furthermore, reading of data from the memory cell 71 using a data read voltage generated by the voltage generation circuit 732 and pulse-controlled by the read circuit 734 is performed via the bit / source line control circuit 736, etc.

[0114] The word line address decoder 737 obtains the address of the word line WL corresponding to the address received at the I / O 730 described above.

[0115] The word line control circuit 738 selects and controls the word line WL corresponding to the address of the word line address decoder 737 .

[0116] The sense amplifier 739 detects the data read from the memory cell 10 , specifically the resistance value of the magnetic memory element 100 .

[0117] The above-described control circuit 731 to sense amplifier 739 control writing of data to the magnetic memory element 100 and reading of data from the magnetic memory element 100. Unless otherwise specified, it may be understood that the control unit is the control circuit 731.

[0118] The memory cell 10 will now be described again. The magnetic memory element 100 of the memory cell 10 is electrically connected between a bit line BL and a source line SL. In this example, one end of the magnetic memory element 100 is connected to the bit line BL, and the other end is connected to the source line SL via the selection transistor 8.

[0119] The selection transistor 8 is an example of a selection element for selecting a memory cell 10 from which data is to be written and read from among the multiple memory cells 10, and more specifically, is a FET switch. The function of the selection transistor 8 can also be called a selector function. The FET (Field Effect Transistor) constituting the selection transistor 8 may be a MOS (Metal-Oxide-Semiconductor) FET, and the MOSFET may be an N-type MOSFET or a P-type MOSFET. Here, the FET is assumed to be an N-type MOSFET.

[0120] The selection transistor 8 switches between a state that enables data access (data reading and writing) to the corresponding magnetic memory element 100 and a state that prevents data access. Specifically, in the example shown in FIG. 24 , one of the source and drain of the selection transistor 8 is connected to the magnetic memory element 100, and the other is connected to a source line SL. The gate of the selection transistor 8 is connected to a word line WL. When the selection transistor 8 is turned on (conductive state), data access to the magnetic memory element 100 to which the selection transistor 8 is connected becomes possible. When the selection transistor 8 is turned off (non-conductive state), data access to the magnetic memory element 100 to which the selection transistor 8 is connected is prevented.

[0121] A voltage corresponding to the potential difference between the bit line BL and the source line SL is applied to the magnetic memory element 100 in the memory cell 10, and this voltage corresponds to the write voltage V described above. In this embodiment, for example, one of a positive voltage (voltage V>0) and a negative voltage (voltage V<0) is applied to the magnetic memory element 100 so that the magnetic memory element 100 has one of a low resistance value and a high resistance value. Also, in this embodiment, the other of a positive voltage and a negative voltage is applied to the magnetic memory element 100 so that the magnetic memory element 100 has the other of a low resistance value and a high resistance value. In the example shown in FIG. 24 , the voltage V applied to the magnetic memory element 100 is represented by the potential of the bit line BL when the source line SL is used as the reference potential. When the potential of the bit line BL is higher than the potential of the source line SL, a positive voltage (V>0) is applied to the magnetic memory element 100. Furthermore, when the potential of the source line SL is higher than the potential of the bit line BL, in other words, when the potential of the bit line BL is lower than the potential of the source line SL, a negative voltage (V<0) is applied to the magnetic memory element 1 .

[0122] The absolute values ​​(|V|) of the positive and negative voltages may be the same or different. By making one voltage smaller than the other, the possibility of reducing power consumption is further increased.

[0123] The configuration of the storage device 200 is not limited to the configuration shown in Fig. 24 described above. Storage devices having various known configurations may be used as the storage device 200 within the scope to which the magnetic memory element 100 is applicable.

[0124] 19 has been described with reference to an example in which one source line SL is commonly connected to two memory cells 10 (two magnetic memory elements 100). However, in this embodiment, one source line SL may be connected to one memory cell 10 (one magnetic memory element 100), and a memory array with a cross-point structure may also be used. Furthermore, in this embodiment, an error correction function may be added depending on the error rate of the magnetic memory element 100 and system requirements.

[0125] Next, a configuration example of a memory cell 10 according to an embodiment of the present disclosure will be described with reference to Fig. 20. Fig. 20 is a diagram showing a configuration example of a memory cell 10 according to an embodiment of the present disclosure and its periphery. As shown in Fig. 20, the memory cell 10 includes, in addition to a magnetic memory element 100 and a select transistor 8 included in the memory cell 10, a contact layer 91, a semiconductor substrate 92, a bit line BL, a word line WL, and a source line SL, for example.

[0126] The select transistor 8 includes a source region 81, a drain region 82, and a gate electrode. The source region 81 and the drain region 82 are formed in a semiconductor substrate 92. In this example, the gate electrode is a word line WL.

[0127] The contact layer 91 is a layer that electrically connects several elements and is configured to include, for example, vias. 25 illustrates three contact layers 91: a contact layer 91 that connects the magnetic memory element 100 and the bit line BL, a contact layer 91 that connects the magnetic memory element 100 and the source region 81 of the select transistor 8, and a contact layer 91 that connects the drain region 82 of the select transistor 8 and the source line SL.

[0128] Furthermore, as described above, the storage device 200 according to this embodiment may have an external magnetic field application unit (not shown) that applies an additional magnetic field from outside the magnetic memory element 100 to shift the hysteresis loop of the storage layer 106. In detail, the external magnetic field application unit (not shown) applies a magnetic field in a direction perpendicular to the magnetic memory element 100. The additional magnetic field has, for example, the same absolute value as the value Hex of the exchange coupling magnetic field when the write voltage is 0 V, and has a magnetization direction opposite to that of the exchange coupling magnetic field Hex.

[0129] 21A and 21B, an example of the operation when writing data in the storage device 200 will be described. Fig. 21A is a flowchart showing an example of processing (without verification) executed when writing data according to this embodiment, and Fig. 21B is a timing chart for the data writing processing (without verification) according to this embodiment.

[0130] 21A is controlled by, for example, a state machine included in the control circuit 731 (FIG. 19), and is started in response to input of a write command and write data. It is assumed that the memory cell 10 including the magnetic memory element 100 to which data is to be written has been selected, and the corresponding selection transistor 8 is turned on.

[0131] When the magnetic memory element 100 is to have a high resistance value (step S1: Yes), the source line SL of the bit line BL and the source line SL is set to a high potential (step S2), and a voltage is set that makes the resistance value of the magnetic memory element 100 a high resistance value (step S3). For example, the voltage applied to the magnetic memory element 100 is set to a negative voltage (voltage V<0).

[0132] On the other hand, if the magnetic memory element 100 is to have a low resistance value (step S1: No), the bit line BL of the bit line BL and the source line SL is set to a high potential (step S4), and a voltage that reduces the resistance value of the magnetic memory element 100 is set (step S5). For example, the voltage applied to the magnetic memory element 100 is set to a positive voltage (voltage V>0).

[0133] After setting step S3 or step S5, a pulse voltage (write voltage) having the set voltage is applied (step S6). The magnetic memory element 100 comes to have a low resistance value or a high resistance value. Here, as described above, the write voltage is a voltage that modulates the value Hex of the exchange coupling magnetic field that transitions the magnetization directions of the SAF-coupled storage layer 106 and fixed layer 102 from an antiparallel state to a parallel state. The write voltage is applied to the upper electrode 120 and the lower electrode 122 of the magnetic memory element 100.

[0134] FIG. 21B shows an example of a timing chart for writing data. Note that FIG. 21B schematically illustrates the voltage changes over time of the write start signal, write direction control signal, word line voltage, bit line voltage, and source line voltage, and the actual voltages are not limited to those shown. The write start signal is generated, for example, by the control circuit 731 (FIG. 19). The write direction control signal controls the polarity of the write voltage V to control whether the data stored in the magnetic memory element 100 is one of two values ​​(high resistance value, low resistance value). The word line voltage, bit line voltage, and source line voltage refer to voltages applied to the word line WL, bit line BL, and source line SL. The bit line BL, source line SL, and word line WL are selected by the bit / source line address decoder 735 and word line address decoder 737, and the word line voltage, bit line voltage, and source line voltage are generated by the bit / source line control circuit 736 and word line control circuit 738. The bit line voltage and source line voltage are detected by the sense amplifier 739.

[0135] 21B shows a timing chart in the case where a positive voltage (V>0) is applied to the magnetic memory element 100. The lower part of Fig. 21B shows a timing chart in the case where a negative voltage (V<0) is applied to the magnetic memory element 100.

[0136] In detail, a word line voltage is applied in response to a write start signal. At the same time, when a positive voltage (V>0) is applied, the bit line voltage is controlled to be higher than the source line voltage, as shown in the upper part of FIG. 21B. When a negative voltage (V<0) is applied, the source line voltage is controlled to be higher than the bit line voltage, as shown in the lower part of FIG. 21B. This causes one of two values ​​(high resistance value, low resistance value) to be written to the memory layer 106 of the magnetic memory element 100.

[0137] 21B shows the word line voltage, bit line voltage, and source line voltage as having the same pulse width, but the pulse widths of these voltages may be different. For example, it is also possible to control the voltages so that the word line voltage rises first, then the bit line voltage or source line voltage rises, and then the word line voltage falls after the bit line voltage or source line voltage falls.

[0138] Furthermore, in this embodiment, a verify read may be performed during a write. The verify read is a read performed after a write to compare the read value (resistance value, bit value, etc.) with an expected value, which is the value to be written. If the read value does not match the expected value during the verify read, the write voltage is applied again. An example of the operation during data write in the storage device 200 with such a verify read will be described with reference to FIGS. 22A and 22B. FIG. 22A is a flowchart showing an example of a process (with verify) executed during data write according to this embodiment, and FIG. 22B is a timing chart during a data write process (with verify) according to this embodiment.

[0139] 22A is a flowchart showing an example of a process (data write method) executed when writing data. After steps S1 to S6 described above with reference to FIG. 21A are completed, a verify read is performed (step S7), and it is determined whether the read value matches the expected value (step S8). If the read value matches the expected value (step S8: Yes), the process of the flowchart ends. If the read value does not match the expected value (step S8: No), the process returns to step S6, where a pulse voltage is applied again.

[0140] By repeatedly applying a pulse voltage until the resistance value of the magnetic memory element 100 matches the expected value, data can be reliably written to the magnetic memory element 100. Note that a maximum value may be set for the number of times the processes of steps S6 to S8 are repeated. If the number of times the processes are repeated exceeds the maximum value, the process of the flowchart ends.

[0141] 22B shows an example of a timing chart when writing data. The comparison result signal indicates whether the value read by the verify read matches the expected value (match or mismatch), and is generated by, for example, the sense amplifier 739 or a separately provided verify circuit (not shown). In the example shown in FIG. 22B, the comparison result signal goes high when the read value matches the expected value.

[0142] As in the previously described FIG. 21B, a word line voltage is applied in response to a write start signal. At the same time, when a positive voltage (V>0) is applied to the magnetic memory element 100, the bit line voltage is controlled to be higher than the source line voltage, as shown in the upper part of FIG. 22B. When a negative voltage (V<0) is applied, the source line voltage is controlled to be higher than the bit line voltage, as shown in the lower part of FIG. 22B. This results in one of two values ​​(high resistance value, low resistance value) being written to the memory layer 106 of the magnetic memory element 100. However, here, it is assumed that this first data write attempt was unsuccessful, and the resistance value of the magnetic memory element 100 is not the expected value.

[0143] Then, a verify read is performed. In response to a read start signal, a word line voltage is applied, and in this example, the bit line voltage is controlled so as to apply the same voltage as the read voltage. Furthermore, the sense amplifier 739 is enabled, and it is determined whether the resistance value of the magnetic memory element 100 is a high resistance value or a low resistance value. It is determined whether the resistance value indicated in the determination result, i.e., the read value, matches the expected value.

[0144] In FIG. 22B, the read value does not match the expected value (mismatch), and writing to the magnetic memory element 100 is performed again. In response to the second write start signal, the word line voltage is applied, and one of the bit line voltage and the source line voltage is controlled so that it is higher than the other. Here, it is assumed that this second data write is successful, and the resistance value of the magnetic memory element 100 is the expected value. Thereafter, a verify read is performed, and it is determined that the read value matches the expected value (match). Writing data to the magnetic memory element 100 is completed.

[0145] If the read value does not match the expected value even in the second verify read, further data writing and verify read are performed. As described above, the maximum number of repetitions may be set.

[0146] In this way, by adding the verify read, a write error is detected by the verify read and writing is performed again, thereby reducing the write error rate.

[0147] As described above, the magnetic memory element 100 according to this embodiment does not require initial reading because, as explained above, the write data in the memory layer 106 depends on the write voltage and is non-toggle, i.e., does not depend on the state before writing.

[0148] 22B shows the word line voltage, bit line voltage, and source line voltage as having the same pulse width, but the pulse widths of these voltages may be different. For example, it is also possible to control the voltages so that the word line voltage rises first, then the bit line voltage or source line voltage rises, and then the word line voltage falls after the bit line voltage or source line voltage falls.

[0149] Various methods may also be used for reading data. The flowchart and timing chart for reading data can be explained as part of Figures 22A and 22B, and therefore detailed explanations will be omitted.

[0150] <<3. Summary>> As described above, in the magnetic memory element 100 according to the embodiment of the present disclosure, the reversal of the magnetization direction of the memory layer 106 depends on the write voltage but does not depend on the pulse width of the write voltage, and therefore precise control of the pulse width of the write voltage on the order of less than a nanosecond is not required. Therefore, according to this embodiment, the write error rate (WER) can be kept low. In addition, since the magnetic memory element 100 according to this embodiment performs writing by applying a voltage, it is capable of high-speed writing and consumes low power due to voltage driving. Furthermore, in the magnetic memory element 100 according to this embodiment, the write data in the memory layer 106 depends on the write voltage and is non-toggle, i.e., does not depend on the state before writing, and therefore does not require initial reading.

[0151] Furthermore, the magnetic memory element 100 according to the embodiment of the present disclosure can be manufactured using manufacturing methods, devices, and conditions that are used in the manufacture of general semiconductor devices.

[0152] Examples of the above-mentioned method include a PVD (Physical Vapor Deposition) method, a CVD (Chemical Vapor Deposition) method, and an ALD (Atomic Layer Deposition) method. Examples of PVD methods include vacuum deposition, EB (electron beam) deposition, various sputtering methods (magnetron sputtering, RF (radio frequency)-DC (direct current) combined bias sputtering, ECR (electron cyclotron resonance) sputtering, facing target sputtering, high frequency sputtering, etc.), ion plating, laser ablation, molecular beam epitaxy (MBE), and laser transfer. Examples of CVD methods include plasma CVD, thermal CVD, metal organic (MO) CVD, and photo CVD. Other methods include electroplating, electroless plating, spin coating, dipping, casting, microcontact printing, drop casting, various printing methods such as screen printing, inkjet printing, offset printing, gravure printing, and flexographic printing, stamping, spraying, and various coating methods such as air doctor coater, blade coater, rod coater, knife coater, squeeze coater, reverse roll coater, transfer roll coater, gravure coater, kiss coater, cast coater, spray coater, slit orifice coater, and calendar coater. Furthermore, patterning methods include chemical etching such as shadow mask, laser transfer, and photolithography, and physical etching using ultraviolet light or laser. Additionally, planarization techniques include CMP (Chemical Mechanical Polishing), laser planarization, and reflow.

[0153] <4. Application Examples> <4.1 Various Devices> An application example of the storage device 200 according to the embodiment of the present disclosure described above will be described with reference to Fig. 23. Fig. 23 is a diagram showing an application example using the storage device 200 according to the embodiment of the present disclosure.

[0154] The storage device 200 according to the embodiment of the present disclosure described above can be used in various cases for sensing light such as visible light, infrared light, ultraviolet light, and X-rays, for example, as follows. For example, as shown in FIG. 23 , the storage device 200 according to the embodiment of the present disclosure is used in "devices for capturing images for viewing, such as digital cameras and mobile devices with camera functions," "devices for traffic use, such as in-vehicle sensors for capturing images of the front, rear, surroundings, and interior of a vehicle for safe driving such as automatic stopping and for recognizing the driver's state, surveillance cameras for monitoring moving vehicles and roads, and distance measurement sensors for measuring distances between vehicles, etc.," "devices for home appliances such as TVs, refrigerators, and air conditioners for capturing images of user gestures and operating the device in accordance with the gestures," "devices for medical and healthcare use, such as endoscopes and devices for capturing blood vessel images by receiving infrared light," "devices for security use, such as surveillance cameras for crime prevention and cameras for person authentication," "devices for beauty use, such as skin measuring devices for capturing images of the skin and microscopes for capturing images of the scalp," "devices for sports use, such as action cameras and wearable cameras for sports use, etc.," and "devices for agriculture, such as cameras for monitoring the condition of fields and crops."

[0155] The technology according to the present disclosure can be applied to various products. For example, the technology according to the present disclosure may be realized as an electronic device mounted on any type of moving body, such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, personal mobility, an airplane, a drone, a ship, a robot, construction machinery, or agricultural machinery (tractor). Furthermore, for example, the technology according to the present disclosure may be realized as an electronic device mounted on an endoscopic surgery system, a microsurgery system, or the like.

[0156] 4.2 Application Example 1 An imaging device 300 according to Application Example 1 will be described with reference to Fig. 24. Fig. 24 is a diagram illustrating an example configuration of the imaging device 300 according to Application Example 1. The imaging device 300 is an example of an electronic device to which the storage device 200 according to an embodiment of the present disclosure is applied. Examples of the imaging device 300 include electronic devices such as digital still cameras, video cameras, smartphones and mobile phones with imaging functions.

[0157] 24, the imaging device 300 includes an optical system 301, a shutter device 302, an imaging element 303, a control circuit 304, a signal processing circuit 305, a monitor 306, and a memory 307. The imaging device 300 can capture still images and moving images.

[0158] The optical system 301 includes one or more lenses. The optical system 301 guides light from a subject (incident light) to the image sensor 303, and forms an image on the light receiving surface of the image sensor 303.

[0159] The shutter device 302 is disposed between the optical system 301 and the image sensor 303. The shutter device 302 controls the light irradiation period and the light blocking period for the image sensor 303 under the control of the control circuit 304.

[0160] The image sensor 303 accumulates signal charges for a certain period of time in response to light that is imaged on the light receiving surface via the optical system 301 and the shutter device 302. The signal charges accumulated in the image sensor 303 are transferred in accordance with a drive signal (timing signal) supplied from the control circuit 304. The image sensor 303 may be, for example, a solid-state image sensor.

[0161] The control circuit 304 outputs a drive signal that controls the transfer operation of the image sensor 303 and the shutter operation of the shutter device 302 , thereby driving the image sensor 303 and the shutter device 302 .

[0162] The signal processing circuit 305 performs various signal processing on the signal charges output from the image sensor 303. The image (image data) obtained by the signal processing performed by the signal processing circuit 305 is supplied to a monitor 306 and further to a memory 307.

[0163] The monitor 306 displays a moving image or a still image captured by the image sensor 303 based on the image data supplied from the signal processing circuit 305. As the monitor 306, for example, a panel-type display device such as a liquid crystal panel or an organic EL (Electro Luminescence) panel can be used.

[0164] The memory 307 stores image data supplied from the signal processing circuit 305, i.e., image data of moving images or still images captured by the image sensor 303. As the memory 307, for example, the storage device 200 according to the embodiment of the present disclosure described above can be used.

[0165] 4.3 Application Example 2 A distance measuring device 400 according to Application Example 2 will be described with reference to Fig. 25. Fig. 25 is a diagram illustrating an example configuration of the distance measuring device 400 according to Application Example 2. The distance measuring device 400 is an example of an electronic device to which the storage device 200 according to an embodiment of the present disclosure is applied.

[0166] 25 , distance measuring device 400 includes a light source unit 401, an optical system 402, an image sensor 403, a control circuit 404, a signal processing circuit 405, a monitor 406, and a memory 407. Distance measuring device 400 projects light from light source unit 401 toward a subject and receives light (modulated light or pulsed light) reflected from the surface of the subject, thereby obtaining a distance image corresponding to the distance to the subject.

[0167] The light source unit 401 projects light toward the subject. For example, a vertical cavity surface emitting laser (VCSEL) array that emits laser light as a surface light source, or a laser diode array in which laser diodes are arranged in a line, is used as the light source unit 401. The laser diode array is supported by a predetermined drive unit (not shown) and scanned in a direction perpendicular to the direction in which the laser diodes are arranged.

[0168] The optical system 402 includes one or more lenses. The optical system 402 guides light (incident light) from a subject to the image sensor 403, and forms an image on the light receiving surface (sensor portion) of the image sensor 403.

[0169] The imaging element 403 accumulates signal charges in response to light that is imaged on the light receiving surface via the optical system 402. A distance signal indicating a distance determined from a light receiving signal output from the imaging element 403 is supplied to a signal processing circuit 405. The imaging element 403 may be, for example, a solid-state imaging element such as an image sensor.

[0170] The control circuit 404 outputs a drive signal (control signal) that controls the operation of the light source unit 401, the image sensor 403, etc., and drives the light source unit 401, the image sensor 403, etc.

[0171] The signal processing circuit 405 performs various types of signal processing on the distance signal supplied from the image sensor 403. For example, the signal processing circuit 405 performs image processing (e.g., histogram processing, peak detection processing, etc.) to construct a distance image based on the distance signal. The image (image data) obtained by the signal processing performed by the signal processing circuit 405 is supplied to a monitor 406 and further to a memory 407.

[0172] The monitor 406 displays the distance image captured by the image sensor 403 based on the image data supplied from the signal processing circuit 405. The monitor 406 may be, for example, a panel display device such as a liquid crystal panel or an organic EL panel.

[0173] The memory 407 stores image data supplied from the signal processing circuit 405, i.e., image data of the distance image captured by the image sensor 403. As the memory 407, for example, the storage device 200 according to the embodiment of the present disclosure can be used.

[0174] As described above, the storage device 200 according to the embodiment of the present disclosure can be implemented in various electronic devices. For example, the storage device 200 according to the embodiment of the present disclosure may be installed in various electronic devices, such as an HDD (hard disk drive), a notebook PC (personal computer), a mobile device (e.g., a smartphone, a tablet PC, etc.), a PDA (personal digital assistant), a wearable device, a game device, a music device, etc., in addition to the imaging device 300 and the ranging device 400. For example, the storage device 200 may be used as various types of memory, such as storage. Furthermore, details of an example of an electronic device to which the storage device 200 according to the embodiment of the present disclosure is applied will be described.

[0175] 4.4 Application Example 3 An AI (Artificial Intelligence) chip 500 according to Application Example 3 will be described with reference to FIG. 26. FIG. 26 is a diagram showing an example configuration of the AI ​​chip 500 according to Application Example 3. The storage device 200 according to an embodiment of the present disclosure can be incorporated into the AI ​​chip 500 for use. The AI ​​chip 500 is, for example, a semiconductor chip configured to include a silicon semiconductor or the like, and includes an AI processing circuit 511 and a memory area 512 as shown in FIG.

[0176] The AI ​​processing circuit 511 executes various types of AI processing. Examples of AI processing include recognition processing, inference processing, etc. Examples of processing targets include, but are not limited to, text, images, videos, audio, music, etc.

[0177] The memory area 512 stores data used by the AI ​​chip 500. The storage device 200 according to an embodiment of the present disclosure can be applied to the memory area 512. Specifically, the memory area 512 includes a long-term retention area 621 and a short-term retention area 622. Furthermore, the long-term retention area 621 and the short-term retention area 622 each have a memory block 508a, 508b including a plurality of magnetic memory elements 100 according to an embodiment of the present disclosure.

[0178] In application example 3, learning data is stored in the long-term storage area 621. Because the learning data is updated infrequently, long-term data storage is required in the long-term storage area 621. Calculated values ​​are stored in the short-term storage area 622. Because the calculated values ​​are frequently updated (overwritten, etc.), the short-term storage area 622 only needs to store data for a short period of time, but is required to take a short time to write, i.e., have low latency.

[0179] Next, an example of processing executed in the AI ​​chip 500 according to Application Example 3 will be described with reference to Fig. 27 and Fig. 28. Fig. 27 and Fig. 28 are flowcharts showing an example of processing executed in the AI ​​chip 500 according to Application Example 3.

[0180] 27 shows a flow for updating learning data. When learning data is input (step S31), the data is stored in the long-term storage area 621 (step S32). Specifically, bit data is written to the magnetic memory element 100 in the memory block 508a included in the long-term storage area 621. The learning data may be generated and updated by the AI ​​processing circuit 511.

[0181] FIG. 28 shows a flow chart of AI processing. When data to be processed by AI is input (step S41), learning data is read from the long-term storage area 621 (step S42), and AI processing is executed (step S43). For example, the AI ​​processing circuit 511 executes a multiply-and-accumulate operation on the input data and learning data. The calculation value used in this operation is stored in the short-term storage area 622 (step S44). In other words, the intermediate calculation results are temporarily stored. Depending on the components of the AI ​​processing circuit 511, such as the number of networks and the number of layers, calculations using the learning data and intermediate calculation results are repeatedly executed a predetermined number of times (step S45: No, steps S42 to S44). When the predetermined number of times is reached (step S45: Yes), the AI ​​processing circuit 511 terminates the calculation and outputs the results (step S46).

[0182] Data writing to the long-term retention area 621 and data writing to the short-term retention area 622 may use techniques similar to those of the embodiments of the present disclosure described above. For example, writing data to the long-term retention area 621, i.e., updating learning data, does not require processing as fast as AI processing, so verify read may be performed to sufficiently reduce the write error rate. The flowchart and timing chart may be similar to those of Figures 26 and 27 described above. When writing data to the short-term retention area 622, i.e., updating the calculation value, verify read may not be performed from the perspective of low-latency access.

[0183] As described above, the storage device 200 according to the embodiment of the present disclosure can be incorporated into the AI ​​chip 500. The same application is possible for chips, devices, etc. configured to execute various known processes, not limited to AI processing. In this sense, the AI ​​chip 500 can be appropriately interpreted as a chip, device, etc. that is not limited to AI processing.

[0184] Furthermore, several modified examples of Application Example 3 will be described. Since the long-term storage area 621 stores learning data for a long period of time, there is a possibility that the error rate will increase over time. To address this, error correction technology may be applied to the long-term storage area 621. Storing error-correction-coded data improves error tolerance. In the following modified example, error correction is performed only on the long-term storage area 621 out of the long-term storage area 621 and the short-term storage area 622. This modified example will be described with reference to FIG. 29. FIG. 29 is a diagram showing an example of the configuration of an AI chip 500 relating to a modified example of Application Example 3.

[0185] In this modified example, the AI ​​chip 500 has an error correction function only for the long-term storage area 621 out of the long-term storage area 621 and the short-term storage area 622. Specifically, as shown in Figure 29, the AI ​​chip 500 includes an error correction circuit 513. The error correction circuit 513 performs error correction encoding on the learning data stored in the long-term storage area 621, and error correction decoding on the learning data read out from the long-term storage area 621.

[0186] Next, an example of processing executed in the AI ​​chip 500 according to this modified example will be described with reference to Fig. 30 to Fig. 32. Fig. 30 to Fig. 32 are flowcharts showing an example of processing executed in the AI ​​chip 500 according to this modified example.

[0187] Figure 30 shows a flow for updating learning data. This flow differs from the previously described flow of Figure 31 in that it includes step S33 between steps S31 and S32. When learning data is input (step S31), the data is error-correction coded (step S33) and stored in long-term storage area 621 (step S32).

[0188] Figure 31 shows a flow for AI processing. This flow differs from the previously described flow of Figure 28 in that it includes step S47 between step S42 and step S43. When data to be subjected to AI processing is input (step S41), learning data is read from the long-term storage area 621 (step S42) and error correction decoded (step S47). The subsequent processing of steps S44 to S46 is as previously described.

[0189] The error correction function described above may also be used to refresh the data in the long-term storage area 621. This will be described with reference to FIG.

[0190] FIG. 32 is a flowchart showing an example of processing executed by the AI ​​chip 500. This flow is initiated in response to receipt of a refresh command. Upon receipt of a refresh command, learning data is read from the long-term storage area 621 (step S51), and error detection is performed (step S52). Then, a determination is made as to whether or not there is a detected error (step S53). If there is no error (step S53: No), the processing of the flowchart ends. On the other hand, if there is an error (step S53: Yes), a determination is made as to whether or not the error can be corrected (step S54). If the error can be corrected (step S54: Yes), the error is corrected (step S55), and the corrected learning data is stored in the long-term storage area 621 (step S56), and the processing of the flowchart ends. If the error cannot be corrected (step S54: No), a notification is sent to the system (step S57), and the processing of the flowchart ends. The system may be, for example, a system operating on a device or the like equipped with the AI ​​chip 500.

[0191] By using the error correction function as described above, it is possible to further improve the error tolerance of data, particularly data related to long-term storage such as learning data.

[0192] Furthermore, in this modification, error correction technology may also be applied to the short-term retention area 622. In addition, the long-term retention area 621 and the short-term retention area 622 may be designed so that the correction capabilities of the error correction codes are different. From the viewpoint of low-latency readout, for example, a Hamming code or a 2-bit correction BCH code may be used for the short-term retention area 622. Since the long-term retention area 621 is more tolerant of low latency than the short-term retention area 622, a correction code with higher performance than the short-term retention area 622 may be used for the long-term retention area 621. In this way, the error tolerance of both the long-term retention area 621 and the short-term retention area 622 can be improved.

[0193] 4.5 Application Example 4 Next, an imaging device 514 according to Application Example 4 will be described with reference to FIG. 33. FIG. 33 is a diagram illustrating an example configuration of the imaging device 514 according to Application Example 4. The storage device 200 according to an embodiment of the present disclosure can be incorporated into the imaging device 514. As illustrated in FIG. 33, the imaging device 514 mainly includes an ADC (Analog-to-Digital Converter) 641, a frame memory control unit 642, a logic unit 643, a memory control unit 644, an I / F (Interface) 645, and a memory area 646.

[0194] The memory area 646 stores data used by the imaging device 514. Typical memory functions related to data processing by the imaging device 514 include a frame memory that stores image data for one frame, an image processing memory that stores data related to image processing, and a non-volatile memory for storing setting values ​​for image processing and data transmission, and the storage device 200 according to an embodiment of the present disclosure can be applied to some or all of these. Specifically, the memory area 646 includes short-term storage areas 647b and 647c and a long-term storage area 648.

[0195] Image data is stored in the short-term storage areas 647b and 647c. The short-term storage areas 647b and 647c include the memory blocks 508b and 508c. The short-term storage areas 647b and 647c are required to store data for a short period of time, but are required to have a short writing time, i.e., low latency.

[0196] The long-term storage area 648 stores program data, operation setting values, etc. The program data is, for example, a control program for controlling the entire imaging device 514. The operation setting values ​​are, for example, parameters for defining the image processing in the imaging device 514, the operation of the I / F 645, etc. The long-term storage area 648 includes the memory block 508a. The long-term storage area 648 is required to store data for a long period of time.

[0197] The ADC 641 converts analog pixel signals obtained from a pixel array unit (not shown) into digital signals. The frame memory control unit 642 stores one frame's worth of image data in a short-term holding area 647b of the memory area 646. The logic unit 643 performs image processing based on one frame's worth of image data. The image processing may include, for example, image correction processing, but is not limited to this in this application example, and various other known image processing may be performed. The memory control unit 644 stores the image data after logic processing in a short-term holding area 647c of the memory area 646. The I / F 645 outputs the image data to the outside.

[0198] The short-term storage area 647b stores one frame of image data after AD conversion and functions as a frame memory. The short-term storage area 647c stores image data after image processing and before being output by the I / F 645, and may also be called a buffer, a subsequent memory, or a main memory.

[0199] Next, an example of processing executed in the imaging device 514 according to this application example will be described with reference to Fig. 34 to Fig. 36. Fig. 34 to Fig. 36 are flowcharts showing an example of processing executed in the imaging device 514 according to this application example.

[0200] 34 shows the flow at startup. Operational setting values ​​are read from the long-term storage area 648 (step S61). By using the internal non-volatile memory, there is no need to load data from an external flash memory, for example, and startup speed can be increased accordingly.

[0201] A flow for updating program data is shown in Figure 35. When program data is input (step S71), the data is stored in the long-term storage area 648 (step S72).

[0202] 36 shows the flow of image data processing. Pixel signals are AD converted (step S81), and the resulting image data is stored in the short-term holding area 647b (step S82). The image data is read from the short-term holding area 647b (step S83), image processing is performed, and the image data is stored in the short-term holding area 647c (step S84). The image data is read from the short-term holding area 647b and output from the I / F 645 (step S85).

[0203] The same techniques as those described above may be used for writing data to the long-term retention area 648 and the short-term retention areas 647b and 647c. For example, writing data to the long-term retention area 648, i.e., updating program data, does not require the same high-speed processing as image processing, so a verify read may be performed to sufficiently reduce the write error rate. The flowcharts and timing charts may be the same as those shown in Figures 21A, 21B, 22A, and 22B described above. When writing data to the short-term retention areas 647b and 647c, i.e., updating image data, a verify read may not be performed from the perspective of low-latency access.

[0204] Furthermore, several modified examples of Application Example 4 will be described. In this application example, as in Application Example 3, error correction code technology may be applied. In this case, the imaging device 514 may include, for example, a circuit similar to the error correction circuit 513 of FIG. 34 described above. For example, the error correction circuit 513 may be provided only for the long-term retention area 648 out of the short-term retention areas 647b and 647c and the long-term retention area 648 of the memory area 646. In this way, it is possible to improve the error tolerance of data related to long-term data retention.

[0205] Furthermore, error correction technology may also be applied to the short-term retention areas 647b and 647c. Additionally, the long-term retention area 648 and the short-term retention areas 647b and 647c may be designed so that their error correction capabilities are different. Details are similar to those of the long-term retention area 621 and short-term retention area 622 ( FIG. 29 ) described above, and therefore will not be described here. This improves the error tolerance of both the long-term retention area 648 and the short-term retention areas 647b and 647c.

[0206] 4.6 Application Example 5 The imaging device 514 described above may have a stacked structure in which multiple chips are stacked. Therefore, the imaging device 514 according to Application Example 5 will be described with reference to FIG. 37 . FIG. 37 is a diagram showing an example configuration of the imaging device 514 according to Application Example 5. The imaging device 514 includes multiple chips and has a stacked structure in which the chips are stacked. Examples of the multiple chips include chip CH1 and chip CH2. When stacked, chip CH1 and chip CH2 function as the imaging device 514. FIG. 37 shows chip CH1 and chip CH2 exploded in the stacking direction.

[0207] The chip CH1 is a pixel chip, and is provided with, for example, a plurality of pixels (pixel array portion) arranged in a two-dimensional array, a pixel circuit including transistors used for driving the pixels, and the like.

[0208] Chip CH2 is an image processing chip for processing pixel signals. In the example shown in Fig. 38 , chip CH2 includes a logic region R1 and a memory region R2. The logic region R1 is provided with the ADC 641, frame memory control unit 642, logic unit 643, memory control unit 644, I / F 645, and the like, which are previously described and shown in Fig. 33 . The memory region R2 is provided with the memory region 646, which was previously described, and the storage device 200 according to the embodiment of the present disclosure is applied to memory region 462.

[0209] Next, a modified example of Application Example 5 will be described. Fig. 38 is a diagram showing a configuration example of an imaging device 514 according to a modified example of Application Example 5. In this modified example, as shown in Fig. 38 , an SRAM 515 is provided in a region of chip CH2 separate from the logic region R1 and the memory region R2. In this modified example as well, the memory device 200 according to the embodiment of the present disclosure is applied to the memory region 462.

[0210] 4.7 Application Example 6 Next, a CPU 516 according to Application Example 6 will be described with reference to FIG. 39 . FIG. 39 is a diagram illustrating an example of a schematic configuration of the CPU 516 according to Application Example 6. The storage device 200 according to an embodiment of the present disclosure is incorporated into the CPU 516 for use. The CPU 516 includes a CPU core 660, a primary cache 661, and a secondary cache 662.

[0211] The CPU core 660 executes various arithmetic processes while using a primary cache 661 and a secondary cache 662 .

[0212] The primary cache 661 includes a storage device 200 according to an embodiment of the present disclosure and an error correction circuit 513. The error correction circuit 513 is as described above. Although the error correction circuit 513 is shown as an element separate from the storage device 200 in FIG. 39 , the error correction circuit 513 may be included in the storage device 200 as a component of the storage device 200. Similarly to the primary cache 661, the secondary cache 662 also includes a storage device 200 and an error correction circuit 513.

[0213] The CPU 516 described above can be suitably used in systems requiring large-scale caches and high-speed processing, such as processors installed in servers in communication networks. Since SRAMs have large areas and large leakage currents, increasing the size of the cache poses a problem of increased memory power consumption. However, by using the magnetic memory element 100 according to an embodiment of the present disclosure, the increase in power consumption can be suppressed compared to SRAMs.

[0214] In this application example, it is also possible to configure the device without the error correction circuit 513. If the error correction circuit 513 is provided, the possibility of reducing the write error rate increases accordingly.

[0215] Furthermore, a modified example of application example 6 will be described. Fig. 40 is a diagram showing an example of a schematic configuration of a CPU 516 according to a modified example of application example 6. In this modified example, as shown in Fig. 40 , the primary cache 661 of the primary cache 661 and secondary cache 662 of the CPU 516 includes an SRAM 515. In this way, a configuration in which the storage device 200 according to the embodiment of the present disclosure and the SRAM 515 are mixed is also possible, and various combinations can be made according to the required specifications, etc.

[0216] <<5. Supplementary Information>> Although preferred embodiments of the present disclosure have been described in detail above with reference to the accompanying drawings, the technical scope of the present disclosure is not limited to such examples. It is clear that a person skilled in the art of the present disclosure can conceive of various modified or altered examples within the scope of the technical idea described in the claims, and it is understood that these also naturally fall within the technical scope of the present disclosure.

[0217] Furthermore, the effects described herein are merely descriptive or exemplary and are not limiting. In other words, the technology according to the present disclosure may achieve other effects that will be apparent to those skilled in the art from the description of this specification, in addition to or in place of the above-described effects.

[0218] Furthermore, the components of each device shown in the figure are conceptual functional components and do not necessarily have to be physically configured as shown in the figure. In other words, the specific form of distribution and integration of each device is not limited to that shown in the figure, and all or part of them can be functionally or physically distributed and integrated in any unit depending on various loads, usage conditions, etc.

[0219] The present technology can also be configured as follows: (1) A magnetic memory element including a first stack including: a memory layer formed from a ferromagnetic material; a first fixed layer formed from a ferromagnetic material; a first spacer layer sandwiched between the memory layer and the first fixed layer and antiferromagnetically exchange-coupling the memory layer and the first fixed layer; and a tunnel barrier layer formed from a nonmagnetic material and provided on a surface of the memory layer opposite to the first spacer layer, wherein the first stack is sandwiched between a first electrode and a second electrode. (2) The magnetic memory element according to (1), wherein a voltage that modulates the magnitude of an exchange coupling magnetic field that transitions the magnetization directions of the memory layer and the first fixed layer from an antiparallel state to a parallel state is applied between the first electrode and the second electrode as a write voltage. (3) The magnetic memory element according to (2), wherein the first stack further includes an additional magnetic field layer that applies an additional magnetic field having the same absolute value as the magnitude of the exchange coupling magnetic field when the write voltage is 0 V and in a direction opposite to the magnetization direction of the exchange coupling magnetic field. (4) The magnetic memory element according to (3), wherein the first stack includes an exchange bias layer formed of an antiferromagnetic material as at least a part of the additional magnetic field layer and that applies an effective magnetic field. (5) The magnetic memory element according to (4), wherein the exchange bias layer is provided on the surface of the first pinned layer opposite to the first spacer layer. (6) The magnetic memory element according to (4) or (5), wherein the exchange bias layer is formed of an alloy. (7) The magnetic memory element according to (6), wherein the exchange bias layer contains at least one element selected from the group consisting of Cr, Mn, Fe, Co, and Ni, and at least one element selected from the group consisting of Ru, Rh, Pd, Ag, Os, Ir, Pt, and Au. (8) The magnetic memory element according to any one of (1) to (7), wherein the first spacer layer contains at least one element selected from the group consisting of Ru, Ir, Rh, Re, V, Cr, Cu, Nb, Mo, Ta, W, Fe, Co, Ni, Mn, and Mg.(9) The magnetic memory element according to (8), wherein the first spacer layer is formed of an oxide containing at least one element selected from the group consisting of Cr, Fe, Co, Ni, Mn, and Mg. (10) The magnetic memory element according to any one of (1) to (9), wherein the first stack further includes a voltage modulation enhancement layer sandwiched between the tunnel barrier layer and the memory layer. (11) The magnetic memory element according to (10), wherein the voltage modulation enhancement layer contains at least one element selected from the group consisting of Ir, Os, Pt, Rh, Ta, Ti, W, Re, Au, Mo, Ru, Pd, V, Cr, and Mg. (12) The magnetic memory element according to (10) or (11), wherein the voltage modulation enhancement layer has a thickness of 0.5 nm or less. (13) The magnetic memory element according to (12), wherein the voltage modulation enhancement layer has a thickness of 0.3 nm or less. (14) The magnetic memory element according to any one of (1) to (13), wherein the first stacked layer further includes a first reference layer made of a ferromagnetic material. (15) The magnetic memory element according to (14), wherein the first reference layer is provided on the surface of the tunnel barrier layer opposite to the memory layer. (16) The magnetic memory element according to any one of (1) to (13), further including a second stacked layer provided on the surface of the tunnel barrier layer opposite to the memory layer, the second stacked layer comprising: a second reference layer made of a ferromagnetic material; a second fixed layer made of a ferromagnetic material; and a second spacer layer sandwiched between the second reference layer and the second fixed layer and exchange-coupling the second reference layer and the second fixed layer. (17) The area resistance of the tunnel barrier layer is 10 Ωμm. 2(18) The magnetic memory element according to any one of (1) to (16) above, wherein the tunnel barrier layer contains at least one of an oxide, a nitride, or a fluoride containing one or more elements selected from the group consisting of Mg, Ca, Li, Si, Al, Sr, Zr, Hf, Ti, Zn, Sc, La, Ta, Eu, Cu, Ba, Mo, W, V, Y, Ni, Co, Mn, Cr, Fe, B, and C. (19) The magnetic memory element according to any one of (1) to (18) above, wherein the thickness of the memory layer is 0.26 nm or more and 3 nm or less. (20) The magnetic memory element according to (19) above, wherein the memory layer contains one or more elements selected from the group consisting of Fe, Co, Ni, and Mn. (21) The magnetic memory element according to any one of (1) to (20) above, wherein the first pinned layer contains one or more elements selected from the group consisting of Fe, Co, Ni, Mn, Pt, and Pd. (22) A writing method for a magnetic memory device including a plurality of magnetic memory elements and a control circuit unit that writes data in the plurality of magnetic memory elements, wherein each of the plurality of magnetic memory elements includes a first stack including: a memory layer formed from a ferromagnetic material; a first fixed layer formed from a ferromagnetic material; a first spacer layer sandwiched between the memory layer and the first fixed layer and antiferromagnetically exchange-coupling the memory layer and the first fixed layer; and a tunnel barrier layer formed from a nonmagnetic material and provided on a surface of the memory layer opposite to the first spacer layer, wherein the first stack is sandwiched between a first electrode and a second electrode, and the control circuit unit applies a write voltage to the first electrode and the second electrode of the magnetic memory element of interest. (23) The method for writing to a magnetic memory device according to (22), wherein the control circuit applies the write voltage to the first electrode and the second electrode of the target magnetic memory element without performing an initial read of data from the magnetic memory element.(24) The method for writing to a magnetic memory device according to (22) or (23), wherein a voltage that modulates the magnitude of an exchange coupling magnetic field that transitions the magnetization direction of the memory layer and the magnetization direction of the first pinned layer from an anti-parallel state to a parallel state is applied between the first electrode and the second electrode as the write voltage. (25) The method for writing to a magnetic memory device according to (24), wherein the first stack further includes an additional magnetic field layer that applies an additional magnetic field that has the same absolute value as the magnitude of the exchange coupling magnetic field when the write voltage is 0 V and is in the opposite direction to the magnetization direction of the exchange coupling magnetic field. (26) The method for writing to a magnetic memory device according to (25), wherein the control circuit applies a voltage having positive or negative polarity to the first electrode and the second electrode as the write voltage that writes one of two values ​​to the memory layer. (27) A magnetic memory device comprising a plurality of magnetic memory elements, wherein each of the plurality of magnetic memory elements comprises a first stack including: a memory layer formed of a ferromagnetic material, a first fixed layer formed of a ferromagnetic material, a first spacer layer sandwiched between the memory layer and the first fixed layer and antiferromagnetically exchange-coupling the memory layer and the first fixed layer, and a tunnel barrier layer formed of a nonmagnetic material and provided on a surface of the memory layer opposite to the first spacer layer, wherein the first stack is sandwiched between a first electrode and a second electrode. (28) The magnetic memory device according to (27), wherein a voltage that modulates the magnitude of an exchange coupling magnetic field that transitions the magnetization direction of the memory layer and the magnetization direction of the first fixed layer from an antiparallel state to a parallel state is applied between the first electrode and the second electrode as a write voltage. (29) The magnetic storage device according to (28) above, further comprising an external magnetic field application unit that applies an additional magnetic field having the same absolute value as the magnitude of the exchange coupling magnetic field when the write voltage is 0 V and in a direction opposite to the magnetization direction of the exchange coupling magnetic field.(30) An electronic device equipped with a magnetic memory device, wherein the magnetic memory device includes a plurality of magnetic memory elements, each of the plurality of magnetic memory elements including a first stack including: a memory layer formed from a ferromagnetic material; a first fixed layer formed from a ferromagnetic material; a first spacer layer sandwiched between the memory layer and the first fixed layer and antiferromagnetically exchange-coupling the memory layer and the first fixed layer; and a tunnel barrier layer formed from a nonmagnetic material and provided on a surface of the memory layer opposite to the first spacer layer, wherein the first stack is sandwiched between a first electrode and a second electrode.

[0220] 8 Select transistor 10, 71 Memory cell 70 Memory cell array 81 Source region 82 Drain region 91 Contact layer 92 Semiconductor substrate 100, 100a, 100b, 100c, 100d, 100e Magnetic memory element 102, 118 Fixed layer 104, 116 Spacer layer 106 Storage layer 108 Tunnel barrier layer 110 Exchange bias layer 112 Reference layer 114 Voltage modulation enhancement layer 120 Upper electrode 122 Lower electrode 130 Substrate 132 Underlayer 140 Voltage modulation enhancement layer 200 Storage device 300, 514 Imaging device 301, 402 Optical system 302 Shutter device 303, 403 Imaging element 304, 404, 731 Control circuit 305, 405 Signal processing circuit 306, 406 Monitor 307, 407 Memory 400 Distance measuring device 401 Light source section 462, 512, 646 Memory area 500 AI chip 508a, 508b, 508c Memory block 511 AI processing circuit 513 Error correction circuit 515 SRAM 516 CPU 621, 648 Long-term storage area 622, 647b, 647c Short-term storage area 641 ADC 642 Frame memory control section 643 Logic section 644 Memory control section 645 I / F 660 CPU core 661 Primary cache 662 Secondary cache 730 I / O 732 Voltage generation circuit 733 Write circuit 734 Read circuit 735 Bit / source line address decoder 736 Bit / source line control circuit 737 Word line address decoder 738 Word line control circuit 739 Sense amplifier

Claims

1. A magnetic memory element comprising a first stack consisting of: a memory layer formed from a ferromagnetic material; a first fixed layer formed from a ferromagnetic material; a first spacer layer sandwiched between the memory layer and the first fixed layer and antiferromagnetically exchange coupling the memory layer and the first fixed layer; and a tunnel barrier layer formed from a non-magnetic material and provided on the surface of the memory layer opposite the first spacer layer, wherein the first stack is sandwiched between a first electrode and a second electrode.

2. The magnetic memory element of claim 1, wherein a voltage that modulates the magnitude of the exchange coupling magnetic field that transitions the magnetization direction of the memory layer and the magnetization direction of the first pinned layer from an antiparallel state to a parallel state is applied between the first electrode and the second electrode as a write voltage.

3. The magnetic memory element of claim 2, wherein the first stack further includes an additional magnetic field layer that applies an additional magnetic field having the same absolute value as the magnitude of the exchange coupling magnetic field when the write voltage is 0 V and in a direction opposite to the magnetization direction of the exchange coupling magnetic field.

4. The magnetic memory element according to claim 3, wherein the first stacked layer has, as at least a part of the additional magnetic field layer, an exchange bias layer made of an antiferromagnetic material and applying an effective magnetic field.

5. The magnetic memory element according to claim 4, wherein the exchange bias layer is provided on the surface of the first pinned layer opposite the first spacer layer.

6. The magnetic memory element of claim 4, wherein the exchange bias layer comprises at least one element selected from the group consisting of Cr, Mn, Fe, Co, and Ni, and at least one element selected from the group consisting of Ru, Rh, Pd, Ag, Os, Ir, Pt, and Au.

7. The magnetic memory element according to claim 1, wherein the first spacer layer contains at least one element selected from the group consisting of Ru, Ir, Rh, Re, V, Cr, Cu, Nb, Mo, Ta, W, Fe, Co, Ni, Mn, and Mg.

8. The magnetic memory element of claim 1, wherein the first stack further comprises a voltage modulation enhancement layer sandwiched between the tunnel barrier layer and the memory layer.

9. The magnetic memory element according to claim 8, wherein the voltage modulation enhancement layer contains at least one element selected from the group consisting of Ir, Os, Pt, Rh, Ta, Ti, W, Re, Au, Mo, Ru, Pd, V, Cr, and Mg.

10. The magnetic memory element according to claim 8, wherein the voltage modulation enhancement layer has a thickness of 0.5 nm or less.

11. The magnetic memory element of claim 1, wherein the first stack further comprises a first reference layer formed from a ferromagnetic material.

12. The magnetic memory element according to claim 11, wherein the first reference layer is provided on the surface of the tunnel barrier layer opposite to the surface of the memory layer.

13. The magnetic memory element according to claim 1, further comprising a second stack provided on the surface of the tunnel barrier layer opposite the memory layer, the second stack consisting of: a second reference layer formed from a ferromagnetic material; a second fixed layer formed from a ferromagnetic material; and a second spacer layer sandwiched between the second reference layer and the second fixed layer and exchange-coupling the second reference layer and the second fixed layer.

14. The sheet resistance of the tunnel barrier layer is 10 Ωμm 2 The magnetic memory element according to claim 1 .

15. The magnetic memory element according to claim 1, wherein the thickness of the memory layer is 0.26 nm or more and 3 nm or less.

16. A writing method for a magnetic memory device comprising a plurality of magnetic memory elements and a control circuit unit that writes data to the plurality of magnetic memory elements, wherein each of the plurality of magnetic memory elements comprises a first stack consisting of: a memory layer formed from a ferromagnetic material; a first fixed layer formed from a ferromagnetic material; a first spacer layer sandwiched between the memory layer and the first fixed layer and antiferromagnetically exchange coupling the memory layer and the first fixed layer; and a tunnel barrier layer formed from a nonmagnetic material and provided on the surface of the memory layer opposite to the first spacer layer, wherein the first stack is sandwiched between a first electrode and a second electrode, and the control circuit unit applies a write voltage to the first electrode and the second electrode of the magnetic memory element being a target.

17. The method for writing to a magnetic memory device according to claim 16, wherein the control circuit applies the write voltage to the first electrode and the second electrode of the target magnetic memory element without performing an initial read to read data from the magnetic memory element.

18. A method for writing to a magnetic storage device as described in claim 17, wherein the write voltage is a voltage that modulates the magnitude of an exchange coupling magnetic field that transitions the magnetization direction of the memory layer and the magnetization direction of the first pinned layer from an antiparallel state to a parallel state, and is applied between the first electrode and the second electrode.

19. A method for writing to a magnetic storage device as described in claim 18, wherein the first stack further has an additional magnetic field layer that applies an additional magnetic field having the same absolute value as the magnitude of the exchange coupling magnetic field when the write voltage is 0 V and in a direction opposite to the magnetization direction of the exchange coupling magnetic field.

20. A method for writing to a magnetic memory device as described in claim 19, wherein the control circuit applies a voltage having a positive or negative polarity to the first electrode and the second electrode as the write voltage for writing one of two values ​​to the memory layer.

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