Semiconductor device

Abstract

The present disclosure relates to a semiconductor device with which it is possible to more suitably improve PID protection capability of a protection element. A semiconductor device according to the present disclosure comprises a protected element formed on the front surface side of a semiconductor substrate, a protection element formed on the semiconductor substrate and electrically connected to the protected element, and a through hole penetrating from the rear surface of the semiconductor substrate to the front surface. Each of the protection element and the protected element has a PN junction, and in a cross-sectional view of the semiconductor substrate, the distance between the PN junction interface of the PN junction of the protection element and the back surface of the semiconductor substrate is smaller than the distance between the PN junction interface of the PN junction of the protected element and the rear surface of the semiconductor substrate. The present disclosure can be applied to, for example, a CMOS image sensor.

Description

Semiconductor Devices

[0001] The present disclosure relates to a semiconductor device, and more particularly to a semiconductor device that can more suitably improve the PID protection capability of a protection element.

[0002] Conventionally, there is a technology that activates a protection element that releases plasma charge using plasma light (especially ultraviolet light) during processing of a semiconductor substrate. This technology reduces plasma induced damage (PID) to the protected element by increasing the leakage current in the protection element only during plasma processing. For example, Patent Document 1 discloses a semiconductor device in which wiring layout restrictions are imposed so that plasma light is more easily irradiated onto the surface of the active region of the antenna protection element.

[0003] Japanese Patent Application Laid-Open No. 2007-299898

[0004] The wiring layout innovation disclosed in Patent Document 1 was unable to improve the PID protection capability of the protection element in the process of forming through holes from the back surface side of the semiconductor substrate.

[0005] The present disclosure has been made in view of the above circumstances, and aims to more suitably improve the PID protection capability of a protection element.

[0006] A semiconductor device according to a first aspect of the present disclosure comprises a protected element formed on the front surface side of a semiconductor substrate, a protecting element formed in the semiconductor substrate and electrically connected to the protected element, and a through hole penetrating the semiconductor substrate from the back surface to the front surface, wherein the protecting element and the protected element each have a PN junction, and in a cross-sectional view of the semiconductor substrate, the distance between the PN junction interface of the PN junction of the protecting element and the back surface of the semiconductor substrate is smaller than the distance between the PN junction interface of the PN junction of the protected element and the back surface of the semiconductor substrate.

[0007] A semiconductor device according to a second aspect of the present disclosure comprises a protected element formed on the front surface side of a semiconductor substrate, a protection element formed in the semiconductor substrate and electrically connected to the protected element, and a through hole penetrating the semiconductor substrate from the back surface to the front surface, wherein the protection element is composed of a diffusion layer formed on the front surface side of the semiconductor substrate and one or more well regions formed in the semiconductor substrate at a position deeper than the diffusion layer, and at least a portion of the PN junction interface of a PN junction formed between the semiconductor substrate and the well region is formed so as to be close to the back surface of the semiconductor substrate.

[0008] In a first aspect of the present disclosure, in a semiconductor device comprising: a protected element formed on the front surface side of a semiconductor substrate; a protecting element formed in the semiconductor substrate and electrically connected to the protected element; and a through hole penetrating from the back surface of the semiconductor substrate to the front surface, the protecting element and the protected element each have a PN junction, and in a cross-sectional view of the semiconductor substrate, the distance between the PN junction interface of the PN junction of the protecting element and the back surface of the semiconductor substrate is smaller than the distance between the PN junction interface of the PN junction of the protected element and the back surface of the semiconductor substrate.

[0009] In a second aspect of the present disclosure, in a semiconductor device comprising: a protected element formed on the front surface side of a semiconductor substrate; a protection element formed in the semiconductor substrate and electrically connected to the protected element; and a through hole penetrating the semiconductor substrate from the back surface to the front surface, the protection element is composed of a diffusion layer formed on the front surface side of the semiconductor substrate and one or more well regions formed in the semiconductor substrate at a position deeper than the diffusion layer, and at least a portion of a PN junction interface of a PN junction formed between the semiconductor substrate and the well region is formed so as to be close to the back surface of the semiconductor substrate.

[0010] FIG. 1 is a cross-sectional view showing a configuration example of a semiconductor device to which the technology according to the present disclosure is applied. FIG. 2 is a view illustrating a manufacturing process of a semiconductor device. FIG. 3 is a view illustrating a manufacturing process of a semiconductor device. FIG. 4 is a view illustrating a manufacturing process of a semiconductor device. FIG. 5 is a view illustrating a manufacturing process of a semiconductor device. FIG. 6 is a view comparing a conventional protective element with a protective element of the present disclosure. FIG. 7 is a cross-sectional view showing another configuration example of a semiconductor device. FIG. 8 is a cross-sectional view showing yet another configuration example of a semiconductor device. FIG. 9 is a cross-sectional view showing yet another configuration example of a semiconductor device. FIG. 10 is a plan view showing yet another configuration example of a semiconductor device. FIG. 11 is a cross-sectional view showing yet another configuration example of a semiconductor device.

[0011] Modes for carrying out the present disclosure (hereinafter referred to as embodiments) will be described below in the following order.

[0012] 1. Prior art and its problems 2. Configuration example of semiconductor device 3. Manufacturing process of semiconductor device 4. Other embodiments 5. Modifications

[0013] <1. Prior Art and Problems> Conventionally, there is a technology that uses plasma light (especially ultraviolet light) during semiconductor substrate processing to activate a protection element that releases plasma charge. This technology suppresses PID to the protected element by increasing the leakage current in the protection element only during plasma processing. For example, Patent Document 1 (Japanese Patent Laid-Open Publication No. 2007-299898) discloses a semiconductor device in which wiring layout restrictions are imposed so that plasma light is more likely to irradiate the surface of the active region of the antenna protection element.

[0014] When plasma processing is performed to form through-holes that penetrate the semiconductor substrate from the backside, the area and aspect ratio of the through-holes become large, which increases the impact of PID on the protected element. In this case, existing protection elements do not have sufficient PID protection capabilities, resulting in significant damage to the protected element.

[0015] Furthermore, when plasma processing is performed from the backside of the semiconductor substrate, the protective element is formed on the front side of the semiconductor substrate using the FEOL (Front-End-Of-Line) method, so activation of the protective element by plasma light cannot be expected compared to when plasma processing is performed from the front side of the semiconductor substrate.In addition, it is expected that the PID protection capability will be reduced compared to conventional methods.

[0016] As described above, the wiring layout innovation disclosed in Patent Document 1 was unable to improve the PID protection capability of the protection element in the process of forming through holes from the back surface side of the semiconductor substrate.

[0017] In contrast, in the semiconductor device of the present disclosure, the PN junction, where plasma charge leakage occurs in the protective element, is formed in a position close to the back surface of the semiconductor substrate so that plasma light from the back surface of the semiconductor substrate improves the PID protection capability of the protective element. This allows plasma light to reach the PN junction of the protective element, increasing the amount of PID charge that can flow through the PN junction, making it possible to suppress damage to the protected element that occurs during plasma processing from the back surface of the semiconductor substrate.

[0018] 2. Configuration Example of Semiconductor Device FIG. 1 is a cross-sectional view showing a configuration example of a semiconductor device 1 to which the technology according to the present disclosure is applied.

[0019] 1 may be a part of a semiconductor device 1 having a three-layer stacked structure, or may be a part of a semiconductor device 1 having a WLCSP (Wafer Level Chip Size Package) structure. The semiconductor device 1 can be applied to various types of devices in which a protected element is formed on a semiconductor substrate. Specifically, the semiconductor device 1 can be applied to semiconductor chips such as photodetectors, such as CMOS (Complementary Metal-Oxide-Semiconductor) image sensors and ToF (Time of Flight) sensors, and CPUs (Central Processing Units).

[0020] The semiconductor device 1 is configured to include a P-type semiconductor substrate (Psub) 10 made of Si, a wiring layer 20 formed on the front surface side (upper side in the figure) of the P-type semiconductor substrate 10, and a dielectric layer 30 formed on the back surface side (lower side in the figure) of the P-type semiconductor substrate 10.

[0021] A protected element 11 and a protecting element 12 are formed on the front surface side of a P-type semiconductor substrate 10 .

[0022] The protected element 11 is configured as an N-type MOS transistor. That is, the protected element 11 is configured with a source layer and a drain layer made of an N-type diffusion layer (N+), a channel layer formed between the source layer and the drain layer, and a gate electrode formed on the channel layer. A PN junction is formed between the N-type diffusion layer (source layer and drain layer) of the protected element 11 and the P-type semiconductor substrate 10.

[0023] The protection element 12 is composed of an N-type diffusion layer (N+) formed on the front surface side of the P-type semiconductor substrate 10, and an N-type well region (NW) formed in the P-type semiconductor substrate 10 at a position deeper than the N-type diffusion layer. A PN junction is formed between the N-type well region of the protection element 12 and the P-type semiconductor substrate 10. In other words, the protection element 12 forms a PN junction diode consisting of the N-type diffusion layer, the N-type well region, and the P-type semiconductor substrate 10.

[0024] Here, in a cross-sectional view of the P-type semiconductor substrate 10, the distance between the PN junction interface of the PN junction portion of the protection element 12 and the back surface of the P-type semiconductor substrate 10 is formed to be smaller than the distance between the PN junction interface of the PN junction portion of the protected element 11 and the back surface of the P-type semiconductor substrate 10.

[0025] That is, in the PN junction diode formed by the protection element 12, at least a part of the PN junction interface of the PN junction portion formed between the P-type semiconductor substrate 10 and the well region of the protection element 12 is formed close to the back surface of the P-type semiconductor substrate 10. More specifically, when the P-type semiconductor substrate 10 is formed so that its film thickness h is about 3 μm, the protection element 12 is formed so that the distance t between the PN junction interface of the PN junction portion and the back surface of the P-type semiconductor substrate 10 is smaller than 0.5 μm.

[0026] In the wiring layer 20, wiring 21 is formed across multiple layers (three layers in the example of FIG. 1 ). The wiring 21 and the protected element 11, and the wiring 21 and the protecting element 12 are electrically connected by contacts 22, respectively. That is, the protected element 11 and the protecting element 12 are electrically connected to each other. The dielectric layer 30 is formed of a material such as SiO or SiN.

[0027] In the P-type semiconductor substrate 10, a through hole 40 is formed that penetrates from the back surface of the P-type semiconductor substrate 10 to the front surface together with the dielectric layer 30. Furthermore, in the P-type semiconductor substrate 10, a through electrode 50 is formed by filling the through hole 40 with a metal material such as Cu. The through hole 40 is formed so as to reach a part of the wiring 21 of the wiring layer 20 from the front surface of the P-type semiconductor substrate 10, so that the through electrode 50 and the wiring 21 are electrically connected to each other. In other words, the protected element 11 and the protecting element 12 are electrically connected to the through electrode 50.

[0028] 2 to 5, a manufacturing process of the semiconductor device 1 after the wiring layer 20 is formed on the front surface side of the P-type semiconductor substrate 10 and the dielectric layer 30 is formed on the back surface side of the P-type semiconductor substrate 10 will be described.

[0029] 2, photoresist 110 is applied onto dielectric layer 30 (lower side in the figure), and then dry etching using plasma is performed in a state where a photomask (not shown) is formed in the region where through-hole 40 is to be formed. As a result, through-hole 40 penetrating P-type semiconductor substrate 10 is formed.

[0030] Next, in step P2 shown in FIG. 3, a TEOS (Tetra Eth Oxy Silane) film 120 is formed as an interlayer insulating film on the dielectric layer 30 and in the through-hole 40 by CVD (Chemical Vapor Deposition).

[0031] Next, in process P3 shown in FIG. 4, a through hole 40 is formed by etching back using plasma so as to reach a part of the wiring 21 of the wiring layer 20 from the front surface of the P-type semiconductor substrate 10.

[0032] At this time, plasma charge (PID current) generated by the plasma processing flows through the wiring 21 exposed from the through-hole 40 into the protected element 11 and the protection element 12 electrically connected to the wiring 21. In particular, in the protection element 12, the plasma charge flows into the N-type diffusion layer (N+) and the N-type well region (NW) through the wiring 21 and the contact 22.

[0033] On the other hand, because the thickness of the Si film between the rear surface of P-type semiconductor substrate 10 and the PN junction interface of the PN junction of protection element 12 is thin, plasma light PL penetrates into the PN junction of protection element 12. This increases the leakage of plasma charge generated at the PN junction of protection element 12, thereby improving the PID protection capability of protection element 12.

[0034] Thereafter, in step P4 shown in FIG. 5, the through-holes 40 are filled with a Cu material 130 to form the through electrodes 50.

[0035] According to the above manufacturing process, in the semiconductor device 1 to which the technology disclosed herein is applied, the PN junction of the protection element is formed in a position close to the back surface of the semiconductor substrate, thereby improving the PID protection capability of the protection element during the process of forming a through hole from the back surface of the semiconductor substrate, thereby making it possible to suppress damage to the protected element that occurs during plasma processing from the back surface of the semiconductor substrate.

[0036] Specifically, a protection element incorporating the technology disclosed herein can reduce the PID current flowing into the protected element to about 1 / 30 of that of a conventional protection element. In particular, the PID protection capability of the protection element during processing depends on the light intensity of the plasma light penetrating the PN junction, and this effect can be more pronounced by reducing the distance between the back surface of the P-type semiconductor substrate 10 and the PN junction interface of the PN junction of the protection element 12 to less than 0.5 μm.

[0037] Furthermore, a protection element to which the technology according to the present disclosure is applied can have a smaller area than a conventional protection element.

[0038] FIG. 6 is a diagram comparing a conventional protection element and a protection element of the present disclosure, both having equivalent PID protection capabilities.

[0039] 6A shows a conventional protective element 12a (N-type diffusion layer) viewed from the top of the wiring layer 20. The protective element 12a is formed to be 10 μm square, and is connected to a through electrode (not shown) and a protected element via a plurality of wirings 21 and contacts 22. As such, the conventional protective element required a large-area diffusion layer to allow plasma charge to escape.

[0040] 6B shows the protective element 12 (N-type diffusion layer) of the present disclosure as viewed from the top surface of the wiring layer 20. The protective element 12 is formed with a square of 1 μm and is connected to a through electrode (not shown) and a protected element via only one wiring 21 and contact 22. In this way, the protective element of the present disclosure can increase the amount of plasma charge leakage at the PN junction in the semiconductor substrate, thereby reducing its area to about 1 / 100 of that of conventional protective elements. As a result, the footprint on the semiconductor substrate can be reduced, enabling the circuit area to be shrunk.

[0041] 4. Other Embodiments The semiconductor device 1 to which the technology according to the present disclosure is applied is not limited to the above-described embodiment, and other embodiments may be adopted. The following description will be given with reference to the cross-sectional configuration when the through-hole 40 is formed by etch-back using plasma, similar to process P3 shown in FIG.

[0042] (Another Example of Polarity of Protection Element) FIG. 7 is a cross-sectional view showing another example of the configuration of the semiconductor device 1. In FIG.

[0043] The semiconductor device 1 in FIG. 7 differs from the semiconductor device 1 in FIG. 1 in the polarity of the protective element 12.

[0044] 7 is composed of a P-type diffusion layer (P+) formed on the front surface side of a P-type semiconductor substrate 10, and an N-type well region (NW) formed in the P-type semiconductor substrate 10 at a position deeper than the P-type diffusion layer. A PN junction is formed between the N-type well region of the protection element 12 and the P-type semiconductor substrate 10. In other words, the protection element 12 forms a PN junction diode consisting of the P-type diffusion layer, the N-type well region, and the P-type semiconductor substrate 10.

[0045] In the PN junction diode formed by the protection element 12, at least a portion of the PN junction interface of the PN junction formed between the P-type semiconductor substrate 10 and the type well region of the protection element 12 is formed so as to be close to the back surface of the P-type semiconductor substrate 10.

[0046] With this structure, plasma charge (PID current) generated by plasma processing flows through the wiring 21 exposed from the through-hole 40 into the protected element 11 and the protection element 12 electrically connected to the wiring 21. In particular, in the protection element 12, the plasma charge flows into the P-type diffusion layer (P+) and the N-type well region (NW) through the wiring 21 and the contact 22.

[0047] On the other hand, because the thickness of the Si film between the rear surface of P-type semiconductor substrate 10 and the PN junction interface of the PN junction of protection element 12 is thin, plasma light PL penetrates into the PN junction of protection element 12. This increases the leakage of plasma charge generated at the PN junction of protection element 12, thereby improving the PID protection capability of protection element 12.

[0048] In the semiconductor device 1 of FIG. 7, the protected element 11 is configured as a P-type MOS transistor and is configured to include an N-type well region (NW) formed at a position deeper than the P-type diffusion layer (P+).

[0049] (Protection Element Having Deep Well Region) FIGS. 8 and 9 are cross-sectional views showing still other configuration examples of the semiconductor device 1. FIG.

[0050] The semiconductor device 1 in FIGS. 8 and 9 differs from the semiconductor device 1 in FIG. 1 in that the protection element 12 is composed of a diffusion layer formed on the front surface side of the semiconductor substrate, a first well region formed in the semiconductor substrate at a position deeper than the diffusion layer, and a second well region formed at a position deeper than the first well region.

[0051] 8 is composed of a P-type diffusion layer (P+) formed on the front surface side of a P-type semiconductor substrate 10, a P-type well region (PW) formed in the P-type semiconductor substrate 10 at a position deeper than the P-type diffusion layer, and an N-type deep well region (DNW) formed at a position deeper than the P-type well region. A PN junction is formed between the N-type deep well region of the protection element 12 and the P-type semiconductor substrate 10. In other words, the protection element 12 forms a PN junction diode consisting of the P-type diffusion layer, the P-type well region, the N-type deep well region, and the P-type semiconductor substrate 10.

[0052] In the PN junction diode formed by the protection element 12, at least a portion of the PN junction interface of the PN junction formed between the P-type semiconductor substrate 10 and the N-type deep well region of the protection element 12 is formed so as to be close to the back surface of the P-type semiconductor substrate 10.

[0053] With this structure, plasma charge (PID current) generated by plasma processing flows through the wiring 21 exposed from the through-hole 40 into the protected element 11 and the protection element 12 electrically connected to the wiring 21. In particular, in the protection element 12, the plasma charge flows into the P-type diffusion layer (P+), N-type well region (NW), and N-type deep well region (DNW) through the wiring 21 and contact 22.

[0054] On the other hand, because the thickness of the Si film between the rear surface of P-type semiconductor substrate 10 and the PN junction interface of the PN junction of protection element 12 is thin, plasma light PL penetrates into the PN junction of protection element 12. This increases the leakage of plasma charge generated at the PN junction of protection element 12, thereby improving the PID protection capability of protection element 12.

[0055] In the semiconductor device 1 of Figure 8, the gate electrode of the protected element 11 (N-type MOS transistor) is electrically connected to the N-type deep well region (DNW), thereby electrically connecting the protected element 11 and the protection element 12.

[0056] 9 is composed of an N-type diffusion layer (N+) formed on the front surface side of a P-type semiconductor substrate 10, an N-type well region (NW) formed in the P-type semiconductor substrate 10 at a position deeper than the P-type diffusion layer, and an N-type deep well region (DNW) formed at a position deeper than the N-type well region. A PN junction is formed between the N-type deep well region of the protection element 12 and the P-type semiconductor substrate 10. In other words, the protection element 12 forms a PN junction diode consisting of the N-type diffusion layer, the N-type well region, the N-type deep well region, and the P-type semiconductor substrate 10.

[0057] In the PN junction diode formed by the protection element 12, at least a portion of the PN junction interface of the PN junction formed between the P-type semiconductor substrate 10 and the N-type deep well region of the protection element 12 is formed so as to be close to the back surface of the P-type semiconductor substrate 10.

[0058] With this structure, plasma charge (PID current) generated by plasma processing flows through the wiring 21 exposed from the through-hole 40 into the protected element 11 and the protection element 12 electrically connected to the wiring 21. In particular, in the protection element 12, the plasma charge flows into the N-type diffusion layer (N+), N-type well region (NW), and N-type deep well region (DNW) through the wiring 21 and contact 22.

[0059] On the other hand, because the thickness of the Si film between the rear surface of P-type semiconductor substrate 10 and the PN junction interface of the PN junction of protection element 12 is thin, plasma light PL penetrates into the PN junction of protection element 12. This increases the leakage of plasma charge generated at the PN junction of protection element 12, thereby improving the PID protection capability of protection element 12.

[0060] In the semiconductor device 1 of Figure 9, the gate electrode of the protected element 11 (N-type MOS transistor) is electrically connected to the N-type deep well region (DNW), thereby electrically connecting the protected element 11 and the protection element 12.

[0061] (Protection Element Formed in a Deep Region of a Semiconductor Substrate) FIG. 10 is a cross-sectional view showing yet another example of the configuration of the semiconductor device 1. In FIG.

[0062] The semiconductor device 1 of FIG. 10 differs from the semiconductor device 1 of FIG. 1 in that the protective element 12 is composed of an impurity region formed in a semiconductor substrate at a position closer to the back surface side of the semiconductor substrate than to the front surface side of the semiconductor substrate.

[0063] The protection element 12 in Fig. 10 is composed of an N-type impurity region formed in a P-type semiconductor substrate 10 at a position closer to the back surface side of the P-type semiconductor substrate 10 than the front surface side. This N-type impurity region is formed by ion implantation into a deep region within the P-type semiconductor substrate 10. Furthermore, in the protection element 12 in Fig. 10, a contact 22 is formed up to the deep region within the P-type semiconductor substrate 10. A PN junction is formed between the N-type impurity region of the protection element 12 and the P-type semiconductor substrate 10. In other words, the protection element 12 forms a PN junction diode consisting of the N-type impurity region and the P-type semiconductor substrate 10.

[0064] In the PN junction diode formed by the protection element 12, at least a portion of the PN junction interface of the PN junction formed between the P-type semiconductor substrate 10 and the N-type impurity region of the protection element 12 is formed so as to be close to the back surface of the P-type semiconductor substrate 10.

[0065] With this structure, plasma charge (PID current) generated by plasma processing flows through the wiring 21 exposed from the through-hole 40 into the protected element 11 and the protecting element 12 electrically connected to the wiring 21. In particular, in the protecting element 12, the plasma charge flows into the N-type impurity region through the wiring 21 and the contact 22.

[0066] On the other hand, because the thickness of the Si film between the rear surface of P-type semiconductor substrate 10 and the PN junction interface of the PN junction of protection element 12 is thin, plasma light PL penetrates into the PN junction of protection element 12. This increases the leakage of plasma charge generated at the PN junction of protection element 12, thereby improving the PID protection capability of protection element 12.

[0067] Furthermore, when forming the N-type impurity region of the protection element 12, ions are not implanted into the surface of the P-type semiconductor substrate 10, so that the footprint of the protection element 12 can be reduced.

[0068] (Protection Element Formed in the Proximity of the Through-Hole) FIG. 11 is a cross-sectional view showing yet another example of the configuration of the semiconductor device 1. In FIG.

[0069] The semiconductor device 1 in FIG. 11 differs from the semiconductor device 1 in FIG. 1 in that the protective element 12 is composed of a diffusion layer formed on the front surface side of the semiconductor substrate and a mold well region formed in the semiconductor substrate at a position deeper than the diffusion layer and in the vicinity of the through hole.

[0070] 11 is composed of an N-type diffusion layer (N+) formed on the front surface side of a P-type semiconductor substrate 10, and an N-type well region (NW) formed in the P-type semiconductor substrate 10 at a position deeper than the N-type diffusion layer and in proximity to the through-hole 40. A PN junction is formed between the N-type well region of the protection element 12 and the P-type semiconductor substrate 10. In other words, the protection element 12 forms a PN junction diode consisting of the N-type diffusion layer, the N-type well region, and the P-type semiconductor substrate 10.

[0071] In the PN junction diode formed by the protection element 12, at least a part of the PN junction interface of the PN junction portion formed between the P-type semiconductor substrate 10 and the N-type well region of the protection element 12 is formed so as to be close to the rear surface of the P-type semiconductor substrate 10 and the through-hole 40. More specifically, as shown in Fig. 12, the protection element 12 is formed so that the distance d between the PN junction interface of the PN junction portion and the through-hole 40 is smaller than 0.5 µm in a plan view of the P-type semiconductor substrate 10.

[0072] With this structure, plasma charge (PID current) generated by plasma processing flows through the wiring 21 exposed from the through-hole 40 into the protected element 11 and the protection element 12 electrically connected to the wiring 21. In particular, in the protection element 12, the plasma charge flows into the N-type diffusion layer (N+) and N-type well region (NW) through the wiring 21 and contact 22.

[0073] On the other hand, because the thickness of the Si film between the back surface of P-type semiconductor substrate 10 and the PN junction interface of the PN junction of protection element 12, and between through-hole 40 and the PN junction interface of the PN junction of protection element 12, is thin, plasma light PL penetrates the PN junction of protection element 12. This further increases the leakage of plasma charge generated at the PN junction, and the PID protection capability of protection element 12 can be further improved.

[0074] (Hole Opened from the Back Side of the Semiconductor Substrate) FIG. 13 is a cross-sectional view showing yet another example of the configuration of the semiconductor device 1. In FIG.

[0075] The semiconductor device 1 of FIG. 13 differs from the semiconductor device 1 of FIG. 1 in that the protective element 12 is composed of a diffusion layer formed on the front surface side of the semiconductor substrate at a position where a hole opening from the back surface side of the semiconductor substrate is provided.

[0076] The protection element 12 in Fig. 13 is composed of an N-type diffusion layer (N+) formed on the front surface side of the P-type semiconductor substrate 10 at a position where a hole 10H opening from the back surface side of the P-type semiconductor substrate 10 is provided. The hole 10H is filled with a dielectric layer 30. A PN junction is formed between the N-type diffusion layer of the protection element 12 and the P-type semiconductor substrate 10. In other words, the protection element 12 forms a PN junction diode consisting of the N-type diffusion layer and the P-type semiconductor substrate 10. Note that the protection element 12 in Fig. 13 may be composed of an N-type diffusion layer and an N-type well region.

[0077] In the PN junction diode formed by the protection element 12, at least a part of the PN junction interface of the PN junction formed between the P-type semiconductor substrate 10 and the N-type diffusion layer of the protection element 12 is formed close to the back surface (hole 10H) of the P-type semiconductor substrate 10. More specifically, the protection element 12 is formed so that the distance t between the PN junction and the back surface (hole 10H) of the P-type semiconductor substrate 10 is smaller than 0.5 μm.

[0078] With this structure, plasma charge (PID current) generated by plasma processing flows through the wiring 21 exposed from the through-hole 40 into the protected element 11 and the protection element 12 electrically connected to the wiring 21. In particular, in the protection element 12, the plasma charge flows into the P-type diffusion layer (P+) through the wiring 21 and the contact 22.

[0079] On the other hand, the thin Si film between the back surface (hole 10H) of P-type semiconductor substrate 10 and the PN junction interface of the PN junction of protection element 12 allows plasma light PL to penetrate into the PN junction of protection element 12. As a result, even if the film thickness of P-type semiconductor substrate 10 is relatively thick, the leakage of plasma charge generated at the PN junction of protection element 12 increases, and the PID protection capability of protection element 12 can be improved.

[0080] 5. Modifications The embodiments described above can be combined as appropriate. In the above-described embodiments, the P-type and N-type conductivity types may all be reversed.

[0081] Furthermore, in the semiconductor device 1 to which the technology according to the present disclosure is applied, the protected element is not limited to a MOS transistor and may be other elements. For example, the protected element may be a metal-insulator-metal (MIM) capacitance element formed three-dimensionally between the wirings 21 of the wiring layer 20.

[0082] The effects described in this specification are merely examples and are not limiting, and other effects may also be present.

[0083] Furthermore, the embodiments to which the technology according to the present disclosure is applied are not limited to the above-described embodiments, and various modifications are possible within the scope that does not deviate from the gist of the technology according to the present disclosure.

[0084] The present disclosure may further be configured as follows: (1) A semiconductor device comprising: a protected element formed on the front surface side of a semiconductor substrate; a protection element formed in the semiconductor substrate and electrically connected to the protected element; and a through hole penetrating the semiconductor substrate from the back surface to the front surface, wherein the protection element and the protected element each have a PN junction, and in a cross-sectional view of the semiconductor substrate, the distance between a PN junction interface of the PN junction of the protection element and the back surface of the semiconductor substrate is smaller than the distance between the PN junction interface of the PN junction of the protected element and the back surface of the semiconductor substrate. (2) The semiconductor device according to (1), further comprising a through electrode formed in the through hole, wherein the protection element and the protected element are electrically connected to the through electrode. (3) The semiconductor device according to (1) or (2), wherein the protection element is composed of a diffusion layer formed on the front surface side of the semiconductor substrate and a well region formed in the semiconductor substrate at a position deeper than the diffusion layer, and the PN junction of the protection element is formed between the semiconductor substrate and the well region. (4) The semiconductor device according to (3), wherein the protection element is composed of the diffusion layer of an opposite conductivity type to the semiconductor substrate and the well region of an opposite conductivity type to the semiconductor substrate. (5) The semiconductor device according to (3), wherein the protection element is composed of the diffusion layer of the same conductivity type as the semiconductor substrate and the well region of an opposite conductivity type to the semiconductor substrate. (6) The semiconductor device according to (1) or (2), wherein the protection element is composed of a diffusion layer formed on the front surface side of the semiconductor substrate, a first well region formed in the semiconductor substrate at a position deeper than the diffusion layer, and a second well region formed at a position deeper than the first well region, and the PN junction of the protection element is formed between the semiconductor substrate and the second well region. (7) The semiconductor device according to (6), wherein the protection element is composed of the diffusion layer of the same conductivity type as the semiconductor substrate, the first well region of the same conductivity type as the semiconductor substrate, and the second well region of an opposite conductivity type to the semiconductor substrate.(8) The semiconductor device according to (6), wherein the protection element is composed of the diffusion layer of an opposite conductivity type to the semiconductor substrate, the first well region of an opposite conductivity type to the semiconductor substrate, and the second well region of an opposite conductivity type to the semiconductor substrate. (9) The semiconductor device according to (1) or (2), wherein the protection element is composed of an impurity region formed in the semiconductor substrate at a position closer to the back surface side of the semiconductor substrate than the front surface side of the semiconductor substrate, and the PN junction of the protection element is formed between the semiconductor substrate and the impurity region. (10) The semiconductor device according to (1) or (2), wherein the protection element is composed of a diffusion layer formed on the front surface side of the semiconductor substrate and a well region formed in the semiconductor substrate at a position deeper than the diffusion layer and close to the through hole, and the PN junction of the protection element is formed between the semiconductor substrate and the well region. (11) The semiconductor device according to (1) or (2), wherein the protection element is composed of a diffusion layer formed on the front surface side of the semiconductor substrate at a position where a hole opening from the back surface side of the semiconductor substrate is provided, and the PN junction of the protection element is formed between the semiconductor substrate and the diffusion layer. (12) The semiconductor device according to any of (1) to (11), wherein a distance between a PN junction interface of the PN junction of the protection element and the back surface of the semiconductor substrate is less than 0.5 μm. (13) The semiconductor device according to any of (1) to (12), wherein the protected element is a MOS (Metal-Oxide-Semiconductor) transistor. (14) A semiconductor device comprising: a protected element formed on a front surface side of a semiconductor substrate; a protection element formed in the semiconductor substrate and electrically connected to the protected element; and a through hole penetrating the semiconductor substrate from a back surface to the front surface, wherein the protection element is composed of a diffusion layer formed on the front surface side of the semiconductor substrate and one or more well regions formed in the semiconductor substrate at a position deeper than the diffusion layer, and at least a part of a PN junction interface of a PN junction portion formed between the semiconductor substrate and the well region is formed so as to be close to the back surface of the semiconductor substrate.

[0085] REFERENCE SIGNS LIST 1 semiconductor device, 10 P-type semiconductor substrate, 11 element to be protected, 12 protection element, 20 wiring layer, 21 wiring, 22 contact, 30 dielectric layer, 40 through hole, 50 through electrode

Claims

1. A semiconductor device comprising: a protected element formed on the front surface side of a semiconductor substrate; a protecting element formed on said semiconductor substrate and electrically connected to said protected element; and a through hole penetrating from the back surface of said semiconductor substrate to the front surface, wherein said protecting element and said protected element each have a PN junction, and in a cross-sectional view of said semiconductor substrate, the distance between the PN junction interface of the PN junction of said protecting element and the back surface of said semiconductor substrate is shorter than the distance between the PN junction interface of the PN junction of said protected element and the back surface of said semiconductor substrate.

2. The semiconductor device according to claim 1, further comprising a through electrode formed in the through hole, wherein the protecting element and the protected element are electrically connected to the through electrode.

3. The semiconductor device according to claim 2, wherein the protection element is composed of a diffusion layer formed on the front surface side of the semiconductor substrate and a well region formed in the semiconductor substrate at a position deeper than the diffusion layer, and the PN junction of the protection element is formed between the semiconductor substrate and the well region.

4. The semiconductor device according to claim 3, wherein the protection element is composed of the diffusion layer of a conductivity type opposite to that of the semiconductor substrate, and the well region of a conductivity type opposite to that of the semiconductor substrate.

5. The semiconductor device according to claim 3, wherein the protection element is composed of the diffusion layer of the same conductivity type as the semiconductor substrate and the well region of the opposite conductivity type to the semiconductor substrate.

6. The semiconductor device according to claim 2, wherein the protection element is composed of a diffusion layer formed on the front surface side of the semiconductor substrate, a first well region formed in the semiconductor substrate at a position deeper than the diffusion layer, and a second well region formed at a position deeper than the first well region, and the PN junction of the protection element is formed between the semiconductor substrate and the second well region.

7. The semiconductor device according to claim 6, wherein the protection element is composed of the diffusion layer of the same conductivity type as the semiconductor substrate, the first well region of the same conductivity type as the semiconductor substrate, and the second well region of the opposite conductivity type to the semiconductor substrate.

8. The semiconductor device according to claim 6, wherein the protection element is composed of the diffusion layer of a conductivity type opposite to that of the semiconductor substrate, the first well region of a conductivity type opposite to that of the semiconductor substrate, and the second well region of a conductivity type opposite to that of the semiconductor substrate.

9. The semiconductor device according to claim 2, wherein the protection element is composed of an impurity region formed in the semiconductor substrate at a position closer to the back surface side of the semiconductor substrate than to the front surface side of the semiconductor substrate, and the PN junction of the protection element is formed between the semiconductor substrate and the impurity region.

10. The semiconductor device according to claim 2, wherein the protection element is composed of a diffusion layer formed on the front surface side of the semiconductor substrate and a well region formed in the semiconductor substrate at a position deeper than the diffusion layer and in the vicinity of the through hole, and the PN junction of the protection element is formed between the semiconductor substrate and the well region.

11. The semiconductor device according to claim 2, wherein the protection element is composed of a diffusion layer formed on the front surface side of the semiconductor substrate at a position where a hole opening from the back surface side of the semiconductor substrate is provided, and the PN junction of the protection element is formed between the semiconductor substrate and the diffusion layer.

12. The semiconductor device according to claim 1, wherein the distance between the PN junction interface of the PN junction portion of the protection element and the rear surface of the semiconductor substrate is less than 0.5 μm.

13. The semiconductor device according to claim 1, wherein the element to be protected is a MOS (Metal-Oxide-Semiconductor) transistor.

14. A semiconductor device comprising: a protected element formed on the front surface side of a semiconductor substrate; a protecting element formed in the semiconductor substrate and electrically connected to the protected element; and a through hole penetrating the semiconductor substrate from the back surface to the front surface, wherein the protecting element is composed of a diffusion layer formed on the front surface side of the semiconductor substrate and one or more well regions formed in the semiconductor substrate at a position deeper than the diffusion layer, and at least a portion of a PN junction interface of a PN junction formed between the semiconductor substrate and the well region is formed so as to be close to the back surface of the semiconductor substrate.

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