Fast table lookup circuit, memory, storage module, chip, and fast table lookup method

Abstract

A fast table lookup circuit, a memory, a storage module, a chip, and a fast table lookup method. The fast table lookup circuit comprises a storage array, a row address decoding circuit, a readout circuit, and a comparison circuit. The storage array is configured to store a plurality of data items, and the data items each comprise index data and second data; first data comprises address data and index comparison data; the address decoding circuit decodes row address data, and selects, from the storage array, all or some of data items stored in a target row; the readout circuit reads out all the selected data items in parallel; and the comparison circuit compares the index comparison data in parallel with index data in all the read-out data items, and only when a target data item having the same comparison result is present, outputs the second data in the target data item as found second data. The fast table lookup circuit can be applied to the memory, the storage module, and the chip.

Description

Fast lookup table circuit, memory, storage module, chip and fast lookup table method

[0001] The present application claims priority to the Chinese patent application No. 2024110533237, filed on August 01, 2024, and entitled "Fast lookup table circuit, memory, storage module, chip and fast lookup table method", the content of which is incorporated herein by reference. TECHNICAL FIELD

[0002] Embodiments of the present disclosure relate to, but are not limited to, the technical field of data processing, and in particular to a fast lookup table circuit, a memory, a storage module, a chip and a fast lookup table method. BACKGROUND

[0003] The lookup table technology is widely used in the scene of fast lookup and matching of data, for example, in network devices (routers and switches), it can realize functions such as fast routing lookup, data packet classification and access control list matching; for another example, in the field of memory, address mapping between different storage units can be realized through lookup table.

[0004] One scheme that can be used for fast lookup table is CAM (Content Addressable Memory) fast lookup table, in which scheme, the input data is compared with all the stored data at the same time, and if a match is successful, the address corresponding to the found data is returned. The hardware structure required by this fast lookup table scheme is relatively complex and the cost is relatively high.

[0005] SUMMARY

[0006] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims. An embodiment of the present disclosure provides a fast lookup table circuit for looking up pre-stored second data according to input first data, the fast lookup table circuit comprising a storage array, an address decoding circuit for lookup table, a readout circuit and a comparison circuit, wherein: the storage array comprises at least one row and multiple columns and is configured to store multiple data items, each of the data items comprising index data and the second data; the first data comprises address data and index comparison data, the address decoding circuit is configured to decode the address data and select all or part of the data items stored in the target row from the storage array; the readout circuit is configured to read out all the data items selected by the address decoding circuit in parallel; the comparison circuit is configured to compare the index comparison data in the first data with the index data in all the readout data items in parallel, and only in the case that there is a target data item with the same comparison result, the second data in the target data item is output as the found second data.

[0007] An embodiment of the present disclosure further provides a memory, comprising a data receiving circuit, an address decoder, a memory cell array, and the fast lookup table circuit according to any one of the embodiments of the present disclosure, wherein: the data receiving circuit is configured to output an access address in a data access instruction to the fast lookup table circuit; the fast lookup table circuit is configured to compare a specified part of the access address as index data of the first data, and compare other parts as address data in the first data; and output the second data found and an indication signal indicating that the second data is found, or output an indication signal indicating that the second data is not found; the address decoder is configured to decode the second data found as a new access address to implement data access in response to the indication signal indicating that the second data is found, or decode the access address to implement data access in response to the indication signal indicating that the second data is not found; wherein the data items in the storage array of the fast lookup table circuit are stored after a corresponding redundant memory cell is allocated for a failed memory cell in the memory cell array; for each failed memory cell, a specified part of the address of the failed memory cell is stored as index data in a data item, and other parts are used to determine the storage position of the data item in the storage array, and the address of the redundant memory cell corresponding to the failed memory cell is stored as second data in the data item.

[0008] An embodiment of the present disclosure further provides a memory module, comprising a control chip and a memory connected with the control chip, and the control chip is provided with a controller and the fast lookup table circuit according to any one of the embodiments of the present disclosure, wherein: the controller is configured to: acquire a redundant memory cell allocated for a failed memory cell in the memory; for each failed memory cell, store a data item in the storage array of the fast lookup table circuit, index data in the data item is a specified part of the address of the failed memory cell, the storage position of the data item in the storage array is determined according to other parts of the address of the failed memory cell, and second data in the data item is the address of the redundant memory cell corresponding to the failed memory cell; the controller is further configured to input a specified part of an access address of the memory as index comparison data of the first data, and input other parts as address data of the first data to the fast lookup table circuit, and access the memory according to the access address in a case where the fast lookup table circuit does not find second data; and access the memory according to the second data found as a new access address in a case where the fast lookup table circuit finds second data.

[0009] An embodiment of the present disclosure further provides a control chip, which is provided with a controller, the fast lookup table circuit according to any one of the embodiments of the present disclosure, and an interface connected with a memory, wherein the controller is configured to: acquire a redundant storage unit allocated for a failed storage unit in the memory; for each failed storage unit, store a data item in a storage array of the fast lookup table circuit, wherein index data in the data item is a specified part of an address of the failed storage unit, and a storage position of the data item in the storage array is determined according to other parts of the address of the failed storage unit, and second data in the data item is an address of a redundant storage unit corresponding to the failed storage unit; and the controller is further configured to: input a specified part of an access address of the memory as index comparison data of first data, and other parts as address data of the first data into the fast lookup table circuit, and access the memory according to the access address in a case where the fast lookup table circuit does not find second data; and access the memory according to the found second data as a new access address in a case where the fast lookup table circuit finds the second data.

[0010] An embodiment of the present disclosure further provides a fast lookup table method for finding second data pre-stored in a storage array according to input first data, wherein the first data comprises address data and index comparison data, the storage array comprises at least one row and multiple columns and is configured to store multiple data items, and each data item comprises index data and the second data, and the method comprises: decoding the address data to select all or part of data items stored in a target row of the storage array; reading out all the selected data items in parallel; comparing the index comparison data with the index data in all the read data items in parallel, and outputting the second data in a target data item as found second data only in a case where there is a target data item with the same comparison result.

[0011] An embodiment of the present disclosure further provides a recovery method of failed storage units, comprising: allocating a corresponding redundant storage unit for each failed storage unit in a memory; storing a data item in a storage array for each failed storage unit, wherein index data in the data item is a specified part of an address of the failed storage unit, a position of the data item in the storage array is determined according to other parts of the address of the failed storage unit, and second data in the data item is an address of the corresponding redundant storage unit of the failed storage unit; when accessing the memory, a specified part of an access address is compared with index data of first data, other parts of the access address are compared with address data of the first data, and the second data is searched by using the fast lookup table method in any embodiment of the present disclosure; in a case where the second data is not found, the memory is accessed according to the access address; in a case where the second data is found, the memory is accessed by using the found second data as a new access address; wherein the specified part refers to k bit data of low bits or high bits, and k≥1.

[0012] An embodiment of the present disclosure further provides a non-transitory computer storage medium, wherein a computer program is stored in the computer readable storage medium, and the computer program is executed by a processor to implement the fast lookup table method in the above embodiment or the recovery method of failed storage units in the above embodiment.

[0013] Other aspects can become apparent after reading and understanding the accompanying drawings and detailed description.

[0014] SUMMARY

[0015] The accompanying drawings are included to provide a further understanding of the present disclosure, and constitute a part of the specification, which together with the embodiments of the present disclosure serve to explain the technical solutions of the present disclosure, and do not constitute a limitation on the technical solutions of the present disclosure.

[0016] FIG. 1 is a schematic diagram of a fast lookup table circuit according to an embodiment of the present disclosure;

[0017] FIG. 2 is a structural schematic diagram of a fast lookup table circuit according to another embodiment of the present disclosure;

[0018] FIG. 3 is a structural schematic diagram of a comparison sub-circuit in a fast lookup table circuit according to an embodiment of the present disclosure;

[0019] FIG. 4 is a structural schematic diagram of a memory according to an embodiment of the present disclosure;

[0020] FIG. 5 is a structural schematic diagram of a storage module according to an embodiment of the present disclosure;

[0021] FIG. 6 is a structural schematic diagram of a control chip according to an embodiment of the present disclosure;

[0022] FIG. 7 is a flowchart of a fast lookup table method according to an embodiment of the present disclosure;

[0023] FIG. 8 is a flowchart of a recovery method of a failed memory cell according to an embodiment of the disclosure.

[0024] DETAILED DESCRIPTION

[0025] Hereinafter, embodiments of the disclosure will be described in detail with reference to the accompanying drawings. In the case where there is no conflict, embodiments of the disclosure and features in the embodiments can be combined with each other.

[0026] Embodiments of the disclosure are not necessarily limited to the sizes shown in the drawings, and the shapes and sizes of the components in the drawings do not reflect true proportions. In addition, the drawings schematically show ideal examples, and embodiments of the disclosure are not limited to the shapes or values shown in the drawings.

[0027] The ordinal numbers "first", "second", and the like in the disclosure are set to avoid confusion of constituent elements, and do not represent any order, number, or importance.

[0028] The disclosure describes a plurality of embodiments, but the description is exemplary, not limiting, and more embodiments and implementation schemes can be possible within the scope encompassed by the embodiments described in the disclosure for those of ordinary skill in the art. Although many possible combinations of features are shown in the drawings and discussed in the detailed description, many other combinations of the disclosed features are possible. Unless specifically limited, any feature or element of any embodiment can be used in combination with or in place of any other feature or element in any other embodiment. This also means that single features can be any one feature or more features.

[0029] The disclosure includes and contemplates combinations of features and elements known to those of ordinary skill in the art. The embodiments, features, and elements disclosed in the disclosure can also be combined with any conventional features or elements to form a solution defined by the claims. Any feature or element of any embodiment can also be combined with features or elements from other disclosed solutions to form another solution defined by the claims. Therefore, it should be understood that any feature shown and discussed in the disclosure can be implemented alone or in any appropriate combination. Therefore, the embodiments are not limited other than as set forth in the claims and their equivalents. In addition, various modifications and changes can be made within the scope of protection of the appended claims.

[0030] Furthermore, in describing representative embodiments, the specification can have presented the method and / or process as a particular sequence of steps. However, to the extent that the method or process depends on the particular order of steps, this description should not be construed as limiting since other steps can be performed in other sequences and / or omitted from the method or process. Therefore, the particular order of steps presented in the specification should not be construed as a limitation on the claims. Furthermore, the claims should not be limited to the steps of the method or process in the specific order presented, but can include other steps not expressly shown or described. Additionally, one of ordinary skill in the art will readily recognize that steps in the methods and processes can be combined, separated, and / or reordered without departing from the disclosure.

[0031] As shown in FIG. 1, the fast table lookup circuit according to the embodiments of the disclosure is configured to look up a pre-stored second data according to an input first data, and the fast table lookup circuit comprises a storage array 110, an address decoding circuit 120 for table lookup, a readout circuit 130, and a comparison circuit 140. The storage array 110 comprises at least one row and multiple columns, and is configured to store multiple data items, each of which comprises index data and second data. The first data comprises address data and index comparison data, and the address decoding circuit 120 is configured to decode the address data and select all or part of the data items stored in a target row in the storage array. The readout circuit 130 is configured to read out all the data items selected by the address decoding circuit in parallel. The comparison circuit 140 is configured to compare the index comparison data in the first data with the index data in all the readout data items in parallel, and output the second data in a target data item as the looked-up second data only when there is a target data item with the same comparison result.

[0032] In an example of the embodiments, the storage array 110 in the fast table lookup circuit can be pre-stored with multiple data items before leaving the factory, and no read / write operation is needed when a user uses a product comprising the fast table lookup circuit. In another example of the embodiments, the fast table lookup circuit can also write data items into the storage array 110 through a write operation during use. In some examples, after writing data items, the storage array 110 can read out data at a corresponding position according to an input access address, like a traditional storage array, in addition to performing a table lookup operation. FIG. 1 only shows the circuits related to table lookup, and does not show the related circuits for reading and writing the storage array 110. In the case that there are related circuits for data access of the storage array 110, the address decoding circuit used for table lookup can also be used for data access, but the two are not necessarily exactly the same. For example, the address decoding circuit used for table lookup can only comprise a row address decoding circuit, while the address decoding circuit used for data access can comprise a row address decoding circuit and a column address decoding circuit. In the absence of a limitation, the address decoding circuit herein refers to the address decoding circuit used for table lookup.

[0033] In the embodiment, each data item in the storage array 110 includes index data and second data, and the first data can be input to the fast table lookup circuit as a screening condition of the data. The address decoding circuit decodes the address data in the first data to obtain the storage location of the data to be looked up in the storage array 110, so as to select all or part of the data items (i.e. the data to be looked up) stored in the target row, and then the readout circuit 130 reads out all the selected data items in parallel, and the index data in all the readout data items is output to the comparison circuit 140. The comparison circuit 140 can compare the index comparison data with the index data in all the readout data items in parallel, and if there is a data item (referred to as a target data item) with the same index data as the index comparison data, the second data in the target data item is output as the second data to be looked up.

[0034] The fast table lookup circuit in the embodiment can look up multiple data items in the storage array in parallel, and realize fast table lookup. Moreover, the embodiment does not compare the input data with each bit of all the stored data as in the CAM, and then convert the compared data into a corresponding address. Instead, the address data in the input is used to select the data item to be compared and read out, and then the index comparison data is compared with the index data in the data item, and the second data to be looked up is directly output when the comparison result is the same. Therefore, the embodiment does not require that each storage unit storing 1-bit data in the storage array is provided with a corresponding comparison circuit and readout circuit, and a general storage array can be used. Moreover, since only part or all of the data items in the target row are read out at a time, the readout circuit and the comparison circuit are relatively simple. The embodiment can directly output the second data to be looked up, without converting the looked-up data into a corresponding address as in the CAM, so as to further simplify the structure of the circuit and reduce the cost.

[0035] In an example embodiment of the disclosure, the address decoding circuit can be a row address decoding circuit, and the address data in the first data can be row address data. The row address decoding circuit is configured to decode the row address data to select all the data items in a target row from the storage array. As shown in FIG. 2, the address decoding circuit for table lookup is a row address decoding circuit 220. Based on the circuit structure of the embodiment, all the data items in a target row in the storage array can be selected when table lookup is performed, without using a column address decoding circuit to select part of the data items in the target row, so that the structure is simpler. However, as described above, the column address decoding circuit for data access can exist in the peripheral circuit of the storage array.

[0036] In another exemplary embodiment of the present disclosure, the address decoding circuit can include a row address decoding circuit and a column address decoding circuit; the address data in the first data can include row address data and column address data; the address decoding circuit is configured to select the partial data item of the target row from the storage array based on decoding the row address data by the row address decoding circuit and decoding the column address data by the column address decoding circuit. This embodiment can add a column address decoding circuit based on the structure of FIG. 2, input the row address data into the row address decoding circuit and input the column address data into the column address decoding circuit. Based on the circuit structure of this embodiment, the row address decoding and the column address decoding can be performed simultaneously when searching the table, and the partial data item of the target row in the storage array is selected. When the storage array is large, the range of the data item to be searched can be reduced, and the structure of the readout circuit and the comparison circuit can be simplified.

[0037] The address decoding circuit (which can be a row address decoding circuit or a column address decoding circuit) in the above embodiments can include a decoding circuit and a driving circuit (for example, the row address decoding circuit can include a row decoding circuit and a row driving circuit), and the driving circuit can include a plurality of selection switches. The switch control signal generated by the decoding circuit after decoding the input address data can control the on-off of the selection switches in the driving circuit, so as to select the corresponding row or column.

[0038] In an exemplary embodiment of the present disclosure, the storage array in the fast table searching circuit can use a one-time programmable memory such as an eFuse (electronic fuse) storage array or an antiFuse (anti-fuse) storage array, or a random memory RAM such as an SRAM (Static Random-Access Memory, static random memory) storage array, but the present disclosure is not limited thereto, and other types of storage arrays can also be used. The cost of eFuse and antiFuse is lower than that of the storage array used by CAM. By setting the address decoding circuit, the readout circuit and the comparison circuit in the peripheral circuit of the storage array such as eFuse, antiFuse or SRAM, fast table searching can be achieved, and the hardware cost is lower.

[0039] In an exemplary embodiment of the present disclosure, the fast table searching circuit is a memory chip. In another exemplary embodiment of the present disclosure, the fast table searching circuit is a subsystem in the chip.

[0040] In an example embodiment of the present disclosure, the index comparison data in the first data is k bit data in the low-order part of the first data, and the address data in the first data is other data in the first data except the index comparison data; in another example embodiment of the present disclosure, the index comparison data in the first data is k bit data in the high-order part of the first data, and the address data in the first data is other data in the first data except the index comparison data; k≥1. In these embodiments, the index comparison data and the address data in the first data are separated, each including one bit or a plurality of bits of data in the first data, which can facilitate wiring, but is not necessarily so.

[0041] Generally, when there is a failed storage unit in a memory (such as a memory chip), a redundant storage unit can be used to replace the failed storage unit to implement reading and writing of data, and the correspondence between the address of the failed storage unit and the address of the corresponding redundant storage unit (i.e., a replacement address table) is recorded, so as to implement recovery of the failed storage unit (i.e., repair of the memory chip). When the repaired memory chip is accessed, the correspondence needs to be looked up to determine whether there is a failed storage unit in the access region, and in the case where there is a failed storage unit, the redundant storage unit is accessed according to the address of the redundant storage unit found. Therefore, the performance of looking up the correspondence is directly related to the performance of the memory chip.

[0042] In an example embodiment of the present disclosure, the fast table lookup circuit can be applied to recovery of a failed storage unit, and can be arranged in a control chip of a memory or in the memory. The first data can be an access address of the memory; in a data item pre-stored in the storage array, the index data is a specified part of the address of a failed storage unit in the memory, the position of the data item in the storage array is determined according to other parts of the address of the failed storage unit, and the second data is the address of a redundant storage unit allocated for the failed storage unit in the memory.

[0043] In an example of the present embodiment, when the fast lookup circuit of the present embodiment is used to record the above correspondence, the k bit in the low-order part of the address of the failed storage unit can be used as the index data in the data item, the address of the corresponding redundant storage unit can be used as the second data in the data item, and the data other than the k bit in the low-order part of the address of the failed storage unit is used to determine the storage position of the data item, which can be a row in the storage array, and the data item can be stored in a free position in the row. The storage position can also be a partial area of a row in the storage array, for example, in the case where a row includes 20 data storage spaces, the determined storage position can be the storage space of the first 10 data items in the row.

[0044] In an example of the embodiment, when the correspondence is looked up using the fast lookup circuit of the embodiment, the k bits of the low bits of the access address are used as the index matching data in the first data, and the other data (one or more bits of the high bits) are used as the address data in the first data. The second data is looked up using the first data with the access address of the memory as the input. If the access address is the address of the failed memory cell, the second data can be found and the second data is the address of the redundant memory cell corresponding to the failed memory cell. If the access address is not the address of the failed memory cell, the second data cannot be found.

[0045] After the fast lookup table circuit of the embodiment receives the input access address, the corresponding address of the redundant memory cell can be quickly found by parallel reading and comparison when the access address is the address of the failed memory cell, so that the recovery of the failed memory cell is realized. The fast lookup table circuit has simple structure and low cost, which helps to improve the performance of the memory or the control chip of the memory and reduce the hardware cost of the memory or the control chip.

[0046] In the example where the row address data is used as the address data in the first data, the bit number (i.e. k) of the row address data can be determined according to the number of rows in the storage array. Assuming that the storage array includes 2n rows, the row address data can include n bits. In this case, if the bit number of the first data is n+k, the k bits of the low bits are used as the index matching data. In the case where the address data in the first data includes the row address data and the column address data, the bit number of the row address data can still be determined according to the number of rows in the storage array, and the bit number of the column address data can be determined according to the ratio of the selected part of the data items in the target row to all the data items in the target row. For example, if a row of the storage array can store 32 data items and 16 data items in the row are selected at a time, 1 bit of the column address data can be used, and if 8 data items in the row are selected at a time, 2 bits of the column address data can be used, and so on.

[0047] In an example embodiment of the present disclosure, the comparison circuit is further configured to output an indication signal indicating that the second data is found in a case where there is a target data item with the same comparison result, and / or output an indication signal indicating that the second data is not found in a case where there is no target data item with the same comparison result. These indication signals can be used for control, for example, in an embodiment where the recovery of invalid storage units is implemented by using the access address of the memory as the first data to look up the table, the indication signals can be used to control a multiplexer including a control terminal and at least two input terminals, the first input terminal can receive the access address, and the second input terminal can receive the second data (the address of the redundant storage unit) output by the fast lookup circuit. When the control terminal of the multiplexer receives the indication signal indicating that the second data is found, the second data received by the second input terminal is output as a new access address to implement data access; if the indication signal indicating that the second data is not found is received, the access address received by the first input terminal is output, i.e., the original access address is used to implement data access. It should be noted that in other applications, the above-mentioned indication signals can not be used, or by judging whether the valid second data is output, a similar effect can also be achieved.

[0048] In an example embodiment of the present disclosure, the storage array includes N rows, each row storing M data items, N≥1, M>1 or M=1; the readout circuit includes M' readout sub-circuits, different readout sub-circuits corresponding to different data items in the column direction, each readout sub-circuit being configured to read out and save a corresponding data item stored in the target row according to a readout instruction; the comparison circuit includes M' comparison sub-circuits corresponding to the M' readout sub-circuits one by one, each comparison sub-circuit being configured to compare the index data in the index comparison data and the data item read out by the corresponding readout sub-circuit, and output a signal indicating that the comparison result is the same to the corresponding readout sub-circuit when the comparison result is the same; the readout sub-circuit is further configured to output the second data in the readout data item as the found second data in response to the signal indicating that the comparison result is the same.

[0049] In an example of the present embodiment, the comparison sub-circuit is further configured to output a signal indicating that the comparison result is different in a case where the index data in the index comparison data and the data item read out by the corresponding readout sub-circuit are different (at least one bit of the index data and the index comparison data is different).

[0050] In one example of the embodiment, M' = M, i.e. the selected target row has all the data items, and the address decoding circuit for the table lookup is the row address decoding circuit 220, as shown in FIG. 2. The fast table lookup circuit shown in FIG. 2 further includes a storage array 210, a readout circuit 230, and a comparison circuit 240. The number of rows and columns of the storage array 210 shown in the figure is only illustrative, and only needs to satisfy N≥1, M>1 or M=1. The readout circuit 230 in FIG. 2 includes M readout sub-circuits 2301, and different readout sub-circuits 2301 correspond to different data items in the column direction, e.g. the first readout sub-circuit corresponds to the first data item in the column direction of the storage array (i.e. the first data item in all rows), the second readout sub-circuit corresponds to the second data item in the column direction of the storage array (i.e. the second data item in all rows), and so on. Each readout sub-circuit 2301 can read out and save a corresponding data item stored in the selected target row according to a readout instruction, e.g. in a flip-flop or register set in the readout circuit. As shown in FIG. 2, the comparison circuit 240 includes M comparison sub-circuits 2401 corresponding to the M readout sub-circuits 2301 one by one, each comparison sub-circuit 2401 compares the index data in the index comparison data and the data item read out by the corresponding readout sub-circuit 231, and when each corresponding bit of the index data and the index comparison data is the same, outputs a signal indicating that the comparison result is the same to the corresponding readout sub-circuit 2301; when at least one corresponding bit of the index data and the index comparison data is different, outputs a signal indicating that the comparison result is different to the corresponding readout sub-circuit 2301.

[0051] The signal output by one comparison sub-circuit 2401 indicating that the comparison result is the same can be used to control the flip-flop or register in the corresponding readout sub-circuit 2301 that saves the second data, so that it outputs the saved second data as the found second data; and the signal output by one comparison sub-circuit 2401 indicating that the comparison result is different can be used to control the flip-flop or register in the corresponding readout sub-circuit 2301 that saves the second data, so that it cannot output the saved second data.

[0052] The embodiment of the disclosure finds at most one second data at a time, and the output ends of the second data of all readout circuits can be connected to a common output line, and the found second data is output from the output line.

[0053] In another example of the embodiment, M'<M, and a part of the data items in a target row are selected in the table lookup. In this case, the address decoder includes a row address decoder and a column address decoder, and the readout sub-circuits and the comparison sub-circuits are still one-to-one correspondingly arranged. Each readout sub-circuit also reads and stores one data item, but the number of the data items is less than the maximum number of the data items that can be stored in a row of the storage array. In this case, the row address decoding circuit and the column address decoding circuit can be used to select M' data items stored in a corresponding region in a target row, so that the M' data items can be read by the M' readout sub-circuits, respectively. The functions of the readout sub-circuits and the comparison sub-circuits, the output of the second data, and the generation of the indication signal in this example can be the same as those in the example of M'=M. In another implementation of this example, M readout sub-circuits are still arranged, and some of the readout sub-circuits are enabled by the decoding result of the column address data by the column address decoding circuit, so that the enabled readout sub-circuits can read the part of the data items in the target row corresponding to the column address data, while the other readout sub-circuits that are not enabled cannot read data. This result is more flexible, and the working mode of selecting all the data items in a row or selecting part of the data items in a row can be selected as needed.

[0054] In yet another example of the embodiment, the storage array is subdivided into multiple sub-arrays, for example, into multiple longitudinal sub-arrays. M readout sub-circuits and M comparison sub-circuits can be arranged for each longitudinal sub-array, in which case M'>M. In the table lookup, a target row can be selected, and the M readout sub-circuits and the M comparison sub-circuits corresponding to the longitudinal sub-array where the target row is located can perform the readout operation and the comparison operation. In this example, the table lookup is performed based on each longitudinal sub-array and the corresponding readout sub-circuits and comparison sub-circuits. When the second data is found in any longitudinal sub-array, an indication signal indicating that the second data is found is output. When the second data is not found in all longitudinal sub-arrays, an indication signal indicating that the second data is not found is output.

[0055] In an example of the embodiment, readout circuits for data access can also be arranged around the storage array. The readout circuits in the fast table lookup circuit of the embodiment can be arranged separately from the readout circuits for data access. The structures of the readout sub-circuits and the readout circuits for data access in the embodiment can be basically the same, and the number of bits of the readout data can be different.

[0056] In an example of the embodiment, the comparison sub-circuit can be implemented by a logic circuit. FIG. 3 shows a possible way to implement the comparison sub-circuit using a logic circuit. In the example shown in the figure, the index data includes 4 index bits and the index comparison data includes 4 comparison bits, and a comparison sub-circuit includes 4 comparison units, each of which compares 1 index bit and 1 comparison bit, and outputs a comparison result signal of different levels when the index bit and the comparison bit are the same and when the index bit and the comparison bit are different. In the example shown in the figure, each comparison unit includes an OR gate, a first NAND gate and a second NAND gate, and the index bit and the comparison bit are input to the OR gate and the first NAND gate respectively, and the output of the OR gate and the first NAND gate is input to the second NAND gate. For example, when the index bit and the comparison bit are both high (i.e. 1), the output of the OR gate is 1, the output of the first NAND gate is 0, and the second NAND gate outputs a bit comparison result signal of "1", indicating that the index bit and the comparison bit are the same; when the index bit and the comparison bit are both low (i.e. 0), the output of the OR gate is 0, the output of the first NAND gate is 1, and the second NAND gate outputs a bit comparison result signal of "1", indicating that the index bit and the comparison bit are the same; when the index bit and the comparison bit are different (i.e. one is 0 and the other is 1), the output of the OR gate is 1, the output of the first NAND gate is 1, and the second NAND gate outputs a bit comparison result signal of "0", indicating that the index bit and the comparison bit are different. As shown in FIG. 3, a comparison sub-circuit can also include an output unit including 4 first switching devices (such as MOS tubes, etc.) connected in series and a second switching device for output control, and the control end of each first switching device is connected to the output (i.e. the output of the second NAND gate) of the corresponding comparison unit. The first end of the second switching device is connected to the power supply VDD, and the second end can be used to output a signal indicating the comparison result of the index data and the index comparison data. The second end is connected to ground through the 4 second switching devices connected in series, and the second switching device can be controlled by the control signal Init connected to the output end, i.e. the second switching device is open when Init is set to a first level during initialization, and the second switching device is turned on when Init is set to a second level different from the first level during comparison. In this way, during comparison, only when all comparison units output a bit comparison result signal of "1" indicating that the index bit and the comparison bit are the same, the second end of the second switching device outputs a low level "0", indicating that the index data and the index comparison data compared by the comparison circuit are the same. If the index data and the index comparison data are different in any corresponding bit, the second end of the second switching device outputs a high level "1", indicating that the index data and the index comparison data compared by the comparison circuit are different.

[0057] Fig. 3 is only schematic, for example, when the index data and the index comparison data include more bits, more comparison units and first switch tubes can be provided; the structures of the comparison units and the output units in the figure are also only schematic, other structures can also be used to compare whether the single bits are the same and output the results.

[0058] The output signals of the comparison sub-circuits shown in Fig. 3 can be connected to corresponding readout sub-circuits, for controlling whether the readout sub-circuits output the second data (such as stored in flip-flops or registers) saved by them. For example, when the levels of the output signals represent that the comparison results are the same (the comparison sub-circuits output signals representing that the comparison results are the same), the corresponding readout sub-circuits can be controlled to output the saved second data; when the levels of the output signals represent that the comparison results are different (the comparison sub-circuits output signals representing that the comparison results are different), the corresponding readout sub-circuits can be controlled not to output the saved second data.

[0059] In an example embodiment of the present disclosure, the comparison circuit further includes an indication signal generation circuit configured to perform an AND operation or an OR operation on the signals output by all the comparison sub-circuits, and output an indication signal representing that the second data is found when any of the comparison sub-circuits outputs a signal representing that the comparison results are the same; output an indication signal representing that the second data is not found when all the comparison sub-circuits output signals representing that the comparison results are different. In an example, the comparison sub-circuits output low level "0" representing that the comparison results are the same, and the signals output by all the comparison sub-circuits can be input to an AND operation circuit (which can be any structure of circuit capable of performing AND operation), the AND operation circuit outputs "0" as the indication signal representing that the second data is found when any of the comparison sub-circuits outputs a low level signal representing that the comparison results are the same; the AND operation circuit outputs "1" as the indication signal representing that the second data is not found when all the comparison sub-circuits output high level signals "1" representing that the comparison results are different. In another example, the comparison sub-circuits output high level "1" representing that the comparison results are the same, and the signals output by all the comparison sub-circuits can be input to an OR operation circuit (which can be any structure of circuit capable of performing OR operation), the OR operation circuit outputs "1" as the indication signal representing that the second data is found when any of the comparison sub-circuits outputs a high level signal representing that the comparison results are the same; the OR operation circuit outputs "0" as the indication signal representing that the second data is not found when all the comparison sub-circuits output low level signals "0" representing that the comparison results are different.

[0060] The timing control of the fast lookup table circuit in the embodiments of the present disclosure can be implemented by a controller. When performing lookup table operation, the controller can output control signals to make the address decoding circuit, the readout circuit and the comparison circuit work in sequence according to the designed timing, thereby completing the whole process of fast lookup table operation.

[0061] When the storage space of the storage array is large, for example, the number of rows is large and / or the length of each row is long, the amount of data read and compared each time is large, which can affect the lookup table performance. To address this phenomenon, the storage array can be divided into multiple sub-arrays.

[0062] In an example of the embodiment, the storage array is divided into multiple longitudinal sub-arrays in the column direction. Assuming that the number of data items that can be stored in a row of the storage array is M, each longitudinal sub-array is provided with a corresponding readout sub-circuit and comparison sub-circuit, for example, M readout sub-circuits and M comparison sub-circuits can be provided for each longitudinal sub-array. The address decoding circuit in the fast lookup table circuit in the example can include a row address decoding circuit (if the row direction is also subdivided, it can include a row address decoding circuit and a column address decoding circuit). A target row can be selected by the row address decoding circuit, and the row address decoding circuit can also output an enable signal to the readout sub-circuit and the comparison sub-circuit corresponding to the longitudinal sub-array where the target row is located. The readout sub-circuit and the comparison sub-circuit corresponding to the longitudinal sub-array where the target row is located perform readout operation and comparison operation, and the readout sub-circuit and the comparison sub-circuit corresponding to other longitudinal sub-arrays that do not receive the enable signal do not perform readout operation and comparison operation. The example helps to alleviate the adverse effect of a large number of rows on the lookup table speed.

[0063] In another example of the embodiment, the storage array is divided into multiple lateral sub-arrays in the row direction, and different lateral sub-arrays can use different row driving circuits. As described above, the row address decoding circuit can include a row decoding circuit and a row driving circuit, and different lateral sub-arrays can use the same row decoding circuit and different row driving circuits, but different lateral sub-arrays can also use different row decoding circuits. The number of data items stored in each row in each lateral sub-array is less than the number M of data items stored in a row of the entire storage array, and when looking up the table, the data items in a row of a lateral sub-array can be selected by the corresponding row driving circuit of the multiple lateral sub-arrays as the data items of the selected target row (equivalent to the partial data items of the selected target row), and one or more bits in the row address data can be used to determine the selected lateral sub-array among the multiple lateral sub-arrays. This example can set one-to-one correspondence between M readout sub-circuits and M comparison sub-circuits to realize the reading and comparison of data items, or one-to-one correspondence between M' readout sub-circuits and M' comparison sub-circuits can be set, where M' is the number of data items that can be stored in a row in a lateral sub-array, and M' < M, and at this time, the M' readout sub-circuits and M' comparison sub-circuits can be controlled according to the decoding result to read data items from the selected lateral sub-array and perform comparison. This embodiment helps to alleviate the adverse effects of long row length on lookup speed.

[0064] The fast lookup circuit of the embodiment of the present disclosure can be arranged in the memory or in the control chip of the memory to realize the function of the failed storage unit of the memory.

[0065] An embodiment of the present disclosure provides a memory, as shown in FIG. 4, which includes a data receiving circuit 410, an address decoder 420, a storage unit array 430, and a fast lookup circuit 440 of any embodiment of the present disclosure, wherein:

[0066] The data receiving circuit 410 is configured to output an access address in a data access instruction to the fast lookup circuit 440; the data receiving circuit 410 can be used to receive a data access instruction;

[0067] The fast lookup circuit 440 is configured to compare a specified part of the access address as an index of first data with data, and other parts as address data in the first data to look up a table; and output the found second data and an indication signal indicating that the second data is found, or output an indication signal indicating that the second data is not found;

[0068] The address decoder 420 is configured to decode the found second data as a new access address to implement data access in response to the indication signal that the second data is found; or decode the access address to implement data access in response to the indication signal that the second data is not found;

[0069] The data item in the storage array of the fast lookup circuit 440 is stored after a corresponding redundant memory cell is allocated for a failed memory cell in the memory cell array 430; for each failed memory cell, a specified part of the address of the failed memory cell is stored as index data in a data item, and the other part is used to determine the storage location of the data item in the storage array, and the address of the redundant memory cell corresponding to the failed memory cell is stored as the second data in the data item.

[0070] The memory of the embodiment can repair the failed memory cells in the memory cell array 430 and realize the reading and writing of data by using redundant memory cells to replace the failed memory cells. After a corresponding redundant memory cell is allocated for a failed memory cell in the memory cell array, the mapping relationship between the address of the failed memory cell and the address of the corresponding redundant memory cell is recorded. However, instead of directly storing the addresses of the failed memory cells and the corresponding redundant memory cells in a mapping table, for each failed memory cell, a specified part of the address of the failed memory cell is stored as index data in a data item, and the other part of the address of the failed memory cell is used to determine the storage location of the data item in the storage array (row, column, subarray, etc.), and the address of the redundant memory cell corresponding to the failed memory cell is stored as the second data in the data item.

[0071] When the memory receives a data access instruction, the data receiving circuit 410 outputs the access address in the data access instruction to the fast lookup circuit 440, a specified part of the access address is used as index data for comparison, and the other part is used as address data. The fast lookup circuit 440 is used to find out whether the second data (i.e. the address of the redundant memory cell) corresponding to the access address is stored in the storage array, and output the corresponding indication signal and the second data according to the finding result. When the access address is the address of a failed memory cell pre-stored in the storage array of the fast lookup circuit, the second data can be found and the indication signal indicating that the second data is found is output; when the access address is not the address of a failed memory cell pre-stored in the storage array of the fast lookup circuit, the indication signal indicating that the second data is not found is output. The address decoder 420 can include a multiplexer. As described above, when the indication signal indicating that the second data is found is received, the multiplexer outputs the received second data as a new access address to realize data access to the memory cell array; when the indication signal indicating that the second data is not found is received, the multiplexer outputs the received access address, i.e. uses the original access address to realize data access to the memory cell array.

[0072] The memory in the embodiment can realize recovery of the failed memory cell, and by using the fast lookup table circuit in the embodiment of the present disclosure, the influence of address lookup on the access speed of the memory can be reduced; compared with the scheme of setting a CAM in the memory to realize recovery of the failed memory cell, the embodiment has a simpler hardware structure and lower hardware cost.

[0073] In an example of the embodiment, the specified part of the address of the failed memory cell is k bit data in the low bits of the address of the failed memory cell, and the specified part of the access address is k bit data in the low bits of the access address; in another example of the embodiment, the specified part of the address of the failed memory cell is k bit data in the high bits of the address of the failed memory cell, and the specified part of the access address is k bit data in the high bits of the access address; where k≥1.

[0074] The embodiment of the present disclosure further provides a storage module, as shown in FIG. 5, which includes a control chip 510 and a memory 520 connected with the control chip, the control chip 510 is provided with a controller 511 and a fast lookup table circuit 512 according to any embodiment of the present disclosure, where: the controller 510 is configured to: acquire a redundant memory cell allocated for a failed memory cell in the memory 520; for each failed memory cell, store a data item in the storage array of the fast lookup table circuit 512, the index data in the data item is a specified part of the address of the failed memory cell, and the storage location of the data item in the storage array is determined according to other parts (parts other than the specified part) of the address of the failed memory cell, and the second data in the data item is the address of the redundant memory cell corresponding to the failed memory cell; the controller 511 is further configured to: take the specified part of the access address of the memory 520 as the index comparison data of the first data, and take the other part as the address data of the first data to input the fast lookup table circuit 512; in the case where the second data is not found in the fast lookup table circuit 512, access the memory 520 according to the access address; in the case where the second data is found in the fast lookup table circuit 512, access the memory 520 according to the found second data as a new access address.

[0075] The storage module of the embodiment stores the mapping relationship between the failed memory cell and the corresponding redundant memory cell in the fast lookup circuit of the control chip, and in the case where the access address of the memory is the address of the stored failed memory cell, the address of the corresponding redundant memory cell can be output to replace the original access address, so as to realize recovery of the failed memory cell. The embodiment can improve the access efficiency of the storage module and reduce the hardware cost.

[0076] In an example of the embodiment, the specified part of the address of the failed storage unit is k bits of low bits of the address of the failed storage unit, and the specified part of the access address is k bits of low bits of the access address; in another example of the embodiment, the specified part of the address of the failed storage unit is k bits of high bits of the address of the failed storage unit, and the specified part of the access address is k bits of high bits of the access address; where k is greater than or equal to 1.

[0077] In an example of the embodiment, the storage module is a CXL memory module.

[0078] As an example of the embodiment, the storage array of the fast lookup table circuit can employ eFuse or antiFuse and be disposed in the control chip. Alternatively, the storage array of the fast lookup table circuit can employ SRAM, and the CXL memory module can further include a flash memory or a memory, etc. After the controller determines the replacement relationship between the redundant storage unit and the failed storage unit in the memory, the address mapping relationship between the two can be recorded in the storage array of the fast lookup table circuit. If SRAM is used, the data items in the storage array can be read out from the non-volatile memory and loaded into the storage array each time the device is powered on, and the data items in the storage array can be saved to the non-volatile memory in the case of power-off or other power-off.

[0079] The embodiment of the disclosure further provides a control chip, as shown in FIG. 6, which is provided with a controller 610, a fast lookup table circuit 620 according to any embodiment of the disclosure, and an interface 630 connected with a memory. The controller 610 is configured to: obtain a redundant storage unit allocated for a failed storage unit in the memory; for each failed storage unit, store a data item in the storage array of the fast lookup table circuit, where the index data in the data item is a specified part of the address of the failed storage unit, the storage location of the data item in the storage array is determined according to other parts (parts other than the specified part) of the address of the failed storage unit, and the second data in the data item is the address of the redundant storage unit corresponding to the failed storage unit; and the controller 610 is further configured to: input the specified part of the access address of the memory as the index comparison data of the first data and the other part as the address data of the first data into the fast lookup table circuit 620, and access the memory according to the access address in the case where the second data is not found in the fast lookup table circuit 620; and access the memory according to the found second data as a new access address in the case where the second data is found in the fast lookup table circuit.

[0080] In an example of the embodiment, the specified part of the address of the failed storage unit is k bit data in the low bits of the address of the failed storage unit, and the specified part of the access address is k bit data in the low bits of the access address; or the specified part of the address of the failed storage unit is k bit data in the high bits of the address of the failed storage unit, and the specified part of the access address is k bit data in the high bits of the access address; where k≥1.

[0081] The control chip of the embodiment of the present disclosure can realize recovery of the failed storage unit in the memory, has little influence on the access speed, and has low hardware cost.

[0082] The embodiment of the present disclosure also provides a fast lookup table method for looking up second data pre-stored in a storage array according to input first data, the first data including address data and index comparison data, the storage array including at least one row and multiple columns and being configured to store multiple data items, the data items each including index data and second data. As shown in FIG. 7, the method includes the following steps.

[0083] Step 710: decode the row address data to select all or part of the data items stored in a target row from the storage array.

[0084] Step 720: read out all the selected data items in parallel.

[0085] Step 730: compare the index comparison data with the index data in all the read data items in parallel, and output the second data in the target data item as the found second data only in the case that there is a target data item with the same comparison result.

[0086] In an example of the embodiment, the fast lookup table method is applied to the fast lookup table circuit as described in any embodiment of the present disclosure.

[0087] In an example of the embodiment, the index comparison data in the first data is k bit data in the low bits or high bits of the first data, and the address data in the first data is other data in the first data except the index comparison data, where k≥1.

[0088] In an example of the embodiment, the method further includes: outputting an indication signal indicating that the second data is found only in the case that there is a target data item with the same comparison result; and outputting an indication signal indicating that the second data is not found only in the case that there is no target data item with the same comparison result.

[0089] The embodiment can read all data items or multiple related data items in a row of the storage array simultaneously based on the address data in the first data, and compare the index data in the read data items with the index comparison data in the first data simultaneously, determine whether there is a target data item to be searched based on the comparison result, and output the second data in the target data item in the case that there is the target data item. The embodiment can improve the table searching speed through parallel reading and comparison of data. The table searching method can also help to simplify the structure of the corresponding table searching circuit and reduce the cost.

[0090] The embodiment of the present disclosure also provides a recovery method of a failed storage unit, as shown in FIG. 8, including the following steps.

[0091] Step 810: allocating a corresponding redundant storage unit for each failed storage unit in the memory.

[0092] Step 820: storing a data item in a storage array for each failed storage unit.

[0093] The index data in the data item is a specified part of the address of the failed storage unit, the second data in the data item is the address of the redundant storage unit corresponding to the failed storage unit, and the storage position of the data item in the storage array is determined according to other parts of the address of the failed storage unit.

[0094] Step 830: when accessing the memory, using the specified part of the access address as the index comparison data of the first data and the other part of the access address as the address data of the first data, and using the fast table searching method of any embodiment of the present disclosure to search for the second data.

[0095] Step 840: in the case that the second data is not found, accessing the memory according to the access address.

[0096] Step 850: in the case that the second data is found, accessing the memory using the found second data as a new access address.

[0097] The specified part of the access address refers to k bit data of the low bits of the access address, and the specified part of the address of the failed storage unit refers to k bit data of the low bits of the address of the failed storage unit; or the specified part of the access address refers to k bit data of the high bits of the access address, and the specified part of the address of the failed storage unit refers to k bit data of the high bits of the address of the failed storage unit, k≥1.

[0098] In the embodiment, when repairing the failed memory cell in the memory, the mapping relationship between the address of the failed memory cell in the memory and the address of the redundant memory cell is recorded in the storage array in the fast lookup table circuit. Through the fast lookup table method, when the access address of the memory is the address of the stored failed memory cell, the address of the corresponding redundant memory cell is output to replace the original access address to access the memory, so that the recovery of the failed memory cell is realized. The method shortens the lookup time, can reduce the influence of the recovery of the failed memory cell on the access speed of the memory, and the used lookup table method is helpful to simplify the structure of the corresponding lookup table circuit and reduce the cost.

[0099] The embodiment of the present disclosure also provides a non-transitory computer storage medium, and the computer readable storage medium stores a computer program. The computer program is executed by a processor to implement the fast lookup table method of any embodiment of the present disclosure or the recovery method of the failed memory cell described in any embodiment of the present disclosure.

[0100] Those skilled in the art can understand that all or some steps in the method disclosed above, and the functions of the functional modules / units in the system and the device can be implemented as software, firmware, hardware or appropriate combination thereof. In the hardware implementation, the division between the functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, one physical component can have multiple functions, or one function or step can be performed by several physical components in cooperation. Some or all of the components can be implemented as software executed by a processor, such as a digital signal processor or a microprocessor, or as hardware, or as an integrated circuit, such as an application specific integrated circuit. Such software can be distributed on a computer readable medium, which can include computer storage media (or non-transitory media) and communication media (or transitory media). As known to those skilled in the art, the term computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information such as computer readable instructions, data structures, program modules or other data. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disk (DVD) or other optical disk storage, magnetic cassettes, magnetic tapes, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and can be accessed by a computer. In addition, as known to those skilled in the art, communication media generally includes computer readable instructions, data structures, program modules or other data in modulated data signals such as carriers or other transmission mechanisms, and can include any information delivery medium.

Claims

1. A fast table lookup circuit for looking up a pre-stored second data according to an input first data, the fast table lookup circuit comprising a storage array, an address decoding circuit for table lookup, a readout circuit, and a comparison circuit, wherein: the storage array comprises at least one row and multiple columns, and is configured to store multiple data items, each of the data items comprising index data and the second data; the first data comprises address data and index comparison data, and the address decoding circuit is configured to decode the address data to select all or part of data items stored in a target row from the storage array; the readout circuit is configured to read out all the selected data items in parallel; and the comparison circuit is configured to compare the index comparison data in the first data with the index data in all the readout data items in parallel, and output the second data in a target data item as the looked-up second data only when there exists the target data item with the same comparison result. 2.The circuit of claim 1, wherein: the address decoding circuit is a row address decoding circuit, and the address data in the first data is row address data; or the address decoding circuit comprises a row address decoding circuit and a column address decoding circuit, and the address data in the first data comprises row address data and column address data; and the address decoding circuit is configured to decode the row address data based on the row address decoding circuit and decode the column address data based on the column address decoding circuit to select part of data items in a target row from the storage array. 3.The circuit of claim 1, wherein: the storage array is an eFuse storage array, or an antiFuse storage array, or an SRAM storage array; and the fast table lookup circuit is a memory chip, or a subsystem in a chip. 4.The circuit of claim 1, wherein: the index comparison data in the first data is k bit data in a lower bit or a higher bit of the first data, and the address data in the first data is other data in the first data except the index comparison data, k≥1. 5.The circuit of claim 1, wherein: the first data comprises an access address of a memory; and in a data item pre-stored in the storage array, the index data is a specified part of an address of a failed storage unit in the memory, and the second data is an address of a redundant storage unit allocated for the failed storage unit in the memory. 6.The circuit of claim 1, wherein: the comparison circuit is further configured to output an indication signal indicating that the second data is looked up when there exists the target data item with the same comparison result, and / or output an indication signal indicating that the second data is not looked up when there is no target data item with the same comparison result. ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ 7.The circuit of claim 1, wherein: the storage array comprises N rows, each row storing M data items, N≥1, M>1 or M=1; the readout circuit comprises M’ readout sub-circuits, different readout sub-circuits corresponding to different data items in the column direction, each readout sub-circuit configured to read out a corresponding data item stored in the target row and store the data item according to a readout instruction; the comparison circuit comprises M’ comparison sub-circuits corresponding to the M’ readout sub-circuits one by one, each comparison sub-circuit configured to compare the index data in the index comparison data and the index data in the data item read out by the corresponding readout sub-circuit, and output a signal indicating the same comparison result to the corresponding readout sub-circuit when the comparison result is the same, M’ being equal to or different from M; the readout sub-circuit is further configured to output the second data in the readout data item as the found second data in response to the signal indicating the same comparison result. 8.The circuit of claim 7, wherein: the comparison sub-circuit is further configured to output a signal indicating a different comparison result when the index data in the index comparison data and the index data in the data item read out by the corresponding readout sub-circuit are different; the comparison circuit further comprises an indication signal generation circuit configured to perform an AND operation or an OR operation on the signals output by all comparison sub-circuits, and output an indication signal indicating that the second data is found when any comparison sub-circuit outputs the signal indicating the same comparison result, or output an indication signal indicating that the second data is not found when all comparison sub-circuits output the signal indicating the different comparison result. 9.The circuit of claim 7, wherein: the storage array is divided into multiple longitudinal sub-arrays in the column direction, each longitudinal sub-array corresponding to M readout sub-circuits and M comparison sub-circuits; and / or, the storage array is divided into multiple transverse sub-arrays in the row direction, different transverse sub-arrays using different row driving circuits. 10.A memory comprising a data receiving circuit, an address decoder, a memory cell array, and the fast table lookup circuit of any one of claims 1 to 9, wherein: the data receiving circuit is configured to output an access address in a data access instruction to the fast table lookup circuit; the fast table lookup circuit is configured to perform table lookup on a specified part of the access address as the index comparison data of the first data, and other parts as address data in the first data; and, output the found second data and an indication signal indicating that the second data is found, or output an indication signal indicating that the second data is not found; the address decoder is configured to decode the found second data as a new access address to implement data access in response to the indication signal indicating that the second data is found, or decode the access address to implement data access in response to the indication signal indicating that the second data is not found; wherein the data items in the storage array of the fast table lookup circuit are stored after corresponding redundant memory cells are allocated to failed memory cells in the memory cell array. ​ For each failed memory cell, a specified part of the address of the failed memory cell is stored as index data in a data item, and other parts are used to determine the storage location of the data item in the storage array, and the address of the redundant memory cell corresponding to the failed memory cell is stored as second data in the data item.

11. The memory of claim 10, wherein: the specified part of the address of the failed memory cell is k bit data in the lower bits of the address of the failed memory cell, and the specified part of the access address is k bit data in the lower bits of the access address; or the specified part of the address of the failed memory cell is k bit data in the higher bits of the address of the failed memory cell, and the specified part of the access address is k bit data in the higher bits of the access address; wherein k ≥ 1.

12. A memory module comprising a control chip and a memory connected to the control chip, wherein the control chip is provided with a controller and the fast lookup table circuit of any one of claims 1 to 9, and wherein: the controller is configured to obtain a redundant memory cell allocated for a failed memory cell in the memory; for each failed memory cell, a data item is stored in the storage array of the fast lookup table circuit, index data in the data item is a specified part of the address of the failed memory cell, and the storage location of the data item in the storage array is determined according to other parts of the address of the failed memory cell, and second data in the data item is the address of the redundant memory cell corresponding to the failed memory cell; the controller is further configured to input a specified part of an access address of the memory as index comparison data of first data, and other parts as address data of the first data to the fast lookup table circuit, and in the case that the fast lookup table circuit does not find second data, access the memory according to the access address; in the case that the fast lookup table circuit finds second data, access the memory using the found second data as a new access address.

13. The memory module of claim 12, wherein: the specified part of the address of the failed memory cell is k bit data in the lower bits of the address of the failed memory cell, and the specified part of the access address is k bit data in the lower bits of the access address; or the specified part of the address of the failed memory cell is k bit data in the higher bits of the address of the failed memory cell, and the specified part of the access address is k bit data in the higher bits of the access address; wherein k ≥ 1.

14. The storage module of claim 12, wherein, the memory module is a CXL memory module.

15. A control chip provided with a controller, the fast lookup table circuit of any one of claims 1 to 9, and an interface connected to a memory, wherein: the controller is configured to obtain a redundant memory cell allocated for a failed memory cell in the memory; For each failed memory cell, a data item is stored in a memory array of the fast lookup circuit, index data in the data item is a specified part of an address of the failed memory cell, a storage location of the data item in the memory array is determined according to other parts of the address of the failed memory cell, and second data in the data item is an address of a redundant memory cell corresponding to the failed memory cell; The controller is further configured to: input, as index comparison data of first data, a specified part of an access address of the memory and, as address data of the first data, other parts of the access address into the fast lookup circuit; and in a case where the second data is not found by the fast lookup circuit, access the memory according to the access address. In a case where the second data is found by the fast lookup circuit, access the memory according to the found second data as a new access address.

16. The control chip according to claim 15, wherein: The specified part of the address of the failed memory cell is k bit data of low bits of the address of the failed memory cell, and the specified part of the access address is k bit data of low bits of the access address; or the specified part of the address of the failed memory cell is k bit data of high bits of the address of the failed memory cell, and the specified part of the access address is k bit data of high bits of the access address; wherein k≥1.

17. A fast lookup method for finding second data pre-stored in a memory array according to input first data, the first data including address data and index comparison data, the memory array including at least one row and multiple columns and being configured to store multiple data items, each of the data items including index data and the second data, the method including: decoding the address data to select all or part of data items stored in a target row from the memory array; reading out all the selected data items in parallel; comparing the index comparison data with the index data in all the read-out data items in parallel, and outputting, in a case where there is a target data item with the same comparison result, the second data in the target data item as the found second data.

18. The fast lookup method according to claim 17, wherein: The method is applied to the fast lookup circuit according to any one of claims 1 to 9; the index comparison data in the first data is k bit data of low bits or high bits of the first data, and the address data in the first data is other data of the first data except the index comparison data, k≥1; The method further includes: in a case where there is a target data item with the same comparison result, outputting an indication signal indicating that the second data is found; and in a case where there is no target data item with the same comparison result, outputting an indication signal indicating that the second data is not found.

19. A method for recovering a failed memory cell, including: allocating a corresponding redundant memory cell for a failed memory cell in a memory; ​ For each failed memory cell, a data item is stored in a memory array, index data in the data item is a specified part of the address of the failed memory cell, the data item is stored in a storage location of the memory array according to other parts of the address of the failed memory cell, and second data in the data item is the address of a redundant memory cell corresponding to the failed memory cell; When accessing the memory, a specified part of the access address is compared as index data of the first data, other parts of the access address are compared as address data of the first data, and the second data is searched by using the fast lookup table method of claim 17 or 18; In a case where the second data is not found, the memory is accessed according to the access address; and in a case where the second data is found, the memory is accessed by using the found second data as a new access address; The specified part of the access address refers to k bit data of low bits in the access address, and the specified part of the address of the failed memory cell refers to k bit data of low bits in the address of the failed memory cell; or the specified part of the access address refers to k bit data of high bits in the access address, and the specified part of the address of the failed memory cell refers to k bit data of high bits in the address of the failed memory cell, k≥1.

20. A computer storage medium having stored thereon a computer program, wherein, The computer program, when executed by a processor, can implement the fast lookup table method of any one of claims 17 to 18, or implement the recovery method of the failed memory cell of claim 19.

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