Shift register, gate drive circuit, display apparatus and gate drive method

Abstract

A shift register, a gate drive circuit, a display apparatus and a gate drive method. The shift register comprises a pull-up node control circuit (10), a pull-down node control circuit (20), an output circuit (30) and a sensing compensation circuit (40), wherein the pull-up node control circuit (10) is configured to control an electrical signal of a pull-up node (QA); the output circuit (30) comprises a gate drive output end, and the output circuit (30) is configured to output a composite signal to the gate drive output end under the control of the electrical signal of the pull-up node (QA); the pull-down node control circuit (20) is configured to at least input a first voltage-end signal into a pull-down node (QB) under the control of the electrical signal of the pull-up node (QA); and the sensing compensation circuit (40) is configured to output a sensing signal under the control of an electrical signal of the pull-down node (QB).

Description

Shift register, gate driving circuit, display device and gate driving method Cross-reference to Related Applications

[0001] This application claims priority to Chinese Patent Application No. 2024110485375, filed on July 31, 2024, the entire contents of which are incorporated herein by reference. TECHNICAL FIELD

[0002] The present disclosure relates to the technical field of display, and in particular, to a shift register, a gate driving circuit, a display device and a gate driving method. BACKGROUND

[0003] In related technologies, most display products adopt GOA (English: Gate Driver On Array, Chinese: Gate Driver on Array) technology to realize row-by-row scanning driving function, thereby saving the use of traditional gate driver (English: Gate Driver IC). However, the threshold voltage and other characteristics of some transistors in GOA drift, which makes it difficult for GOA to accurately output scanning signals. SUMMARY

[0004] The present disclosure provides a shift register, a gate driving circuit, a display device and a gate driving method, aiming to at least partially solve the problem that the threshold voltage and other characteristics of some transistors in GOA drift, which makes it difficult for GOA to accurately output scanning signals.

[0005] In a first aspect of the present disclosure, a shift register is provided, comprising: a pull-up node control circuit configured to control an electrical signal of a pull-up node; an output circuit comprising a gate driving output end, the output circuit being configured to output a composite signal to the gate driving output end under the control of the electrical signal of the pull-up node; a pull-down node control circuit configured to input a first voltage terminal signal to a pull-down node under the control of the electrical signal of the pull-up node; and an induction compensation circuit configured to output an induction signal under the control of the electrical signal of the pull-down node.

[0006] In some embodiments, further comprising: a first stabilization circuit configured to control the electrical signal of the pull-up node under the control of the electrical signal of the pull-down node.

[0007] In some embodiments, the pull-up node control circuit comprises: an input sub-circuit configured to input a first power signal to the pull-up node under the control of a charging input signal; and the pull-down node control circuit is configured to input a second power signal or the first voltage terminal signal to the pull-down node under the control of the electrical signal of the pull-up node.

[0008] In some embodiments, the pull-up node control circuit further comprises: a reset protection sub-circuit configured to control an electrical signal of a pull-up synchronization node under control of an electrical signal of the pull-up node, the pull-up synchronization node being connected to the first stabilization circuit; and the first stabilization circuit is further configured to control the electrical signal of the pull-up synchronization node under control of an electrical signal of the pull-down node.

[0009] In some embodiments, further comprising: a selection compensation circuit configured to charge a pull-up control node under control of a selection compensation control signal, and charge the pull-up node under control of a sub-clock signal.

[0010] In some embodiments, the sensing compensation circuit comprises: a sensing sub-circuit configured to generate the sensing signal based on a first control signal when a level of the pull-down node is higher than a threshold voltage.

[0011] In some embodiments, the sensing sub-circuit comprises: at least one sensing transistor, a control terminal of the sensing transistor being connected to the pull-down node; the sensing transistor is configured to be turned on when the level of the pull-down node is higher than the threshold voltage, so that the first control signal generates the sensing signal through the sensing transistor.

[0012] In some embodiments, the at least one sensing transistor comprises: a first sensing transistor, a first end of the first sensing transistor being connected to the first control signal; a second sensing transistor, a first end of the second sensing transistor being connected to a second end of the first sensing transistor, and the sensing signal being output through a second end of the second sensing transistor.

[0013] In some embodiments, the first control signal and a selection compensation control signal share the same signal line, and the selection compensation control signal is a control signal for compensating the composite signal.

[0014] In some embodiments, the sensing compensation circuit further comprises: an output control sub-circuit configured to output the sensing signal under control of a second control signal.

[0015] In some embodiments, the output control sub-circuit comprises: an output control transistor, a control terminal of the output control transistor being connected to the second control signal, a first end of the output control transistor being connected to the second end of the second sensing transistor, and the sensing signal being output through a second end of the output control transistor.

[0016] In some embodiments, the first control signal is a delayed signal of the second control signal.

[0017] In some embodiments, the sensing compensation circuit further comprises a voltage stabilizing sub-circuit configured to stabilize the level of the pull-down node when the level of the first control signal jumps.

[0018] In some embodiments, the voltage stabilizing sub-circuit comprises a voltage stabilizing capacitor, a first end of the voltage stabilizing capacitor being connected to the pull-down node, and a second end of the voltage stabilizing capacitor being connected to a second voltage terminal signal.

[0019] In some embodiments, the sensing compensation circuit further comprises a voltage adjusting sub-circuit configured to adjust the level of the pull-down node under the control of a third control signal.

[0020] In some embodiments, the voltage adjusting sub-circuit comprises a voltage adjusting transistor, a control end of the voltage adjusting transistor being connected to the third control signal, a first end of the voltage adjusting transistor being connected to the pull-down node, and a second end of the voltage adjusting transistor being connected to a first voltage terminal signal.

[0021] In some embodiments, the shift register further comprises a first stabilizing circuit, the first stabilizing circuit comprising a first noise reduction transistor, a control end of the first noise reduction transistor being connected to the pull-down node, and a first end of the first noise reduction transistor being connected to the pull-up node; and a second noise reduction transistor, a control end of the second noise reduction transistor being connected to the pull-down node, a first end of the second noise reduction transistor being connected to a second end of the first noise reduction transistor, and a second end of the second noise reduction transistor being connected to the first voltage terminal signal.

[0022] In some embodiments, the sensing compensation circuit further comprises a sensing control sub-circuit configured to connect the level of the connection point of the first noise reduction transistor and the second noise reduction transistor to the sensing sub-circuit under the control of a fourth control signal.

[0023] In some embodiments, the sensing control sub-circuit comprises a sensing control transistor, a control end of the sensing control transistor being connected to the fourth control signal, a first end of the sensing control transistor being connected to the second end of the first noise reduction transistor and the first end of the second noise reduction transistor, and a second end of the sensing control transistor being connected to the second end of the first sensing transistor and the first end of the second sensing transistor.

[0024] In some embodiments, the pull-up node control circuit comprises: a first input transistor, a control terminal of the first input transistor being connected to the charging input signal, a first terminal of the first input transistor being connected to a first power supply signal; a second input transistor, a control terminal of the second input transistor being connected to the charging input signal, a first terminal of the second input transistor being connected to the first terminal of the first input transistor, a second terminal of the second input transistor being connected to the pull-up node; an input protection transistor, a control terminal of the input protection transistor being connected to the pull-down node, a first terminal of the input protection transistor being connected to the first power supply signal, a second terminal of the input protection transistor being connected to the second terminal of the first input transistor and the first terminal of the second input transistor; a first reset transistor, a control terminal of the first reset transistor being connected to the display total reset signal, a first terminal of the first reset transistor being connected to the pull-up node; a second reset transistor, a control terminal of the second reset transistor being connected to the display total reset signal, a first terminal of the second reset transistor being connected to the second terminal of the first reset transistor, the second terminal of the first noise reduction transistor, and the first terminal of the second noise reduction transistor, a second terminal of the second reset transistor being connected to a first voltage terminal signal; a first reset protection transistor, a control terminal of the first reset protection transistor being connected to the pull-up node, a first terminal of the first reset protection transistor being connected to the first power supply signal; a second reset protection transistor, a control terminal of the second reset protection transistor being connected to the pull-up node, a first terminal of the second reset protection transistor being connected to the second terminal of the first reset protection transistor, and the second terminal of the first reset transistor and the first terminal of the second reset transistor.

[0025] In some embodiments, the second stabilizing circuit further comprises: a first total reset transistor, a control terminal of the first total reset transistor being connected to a total reset signal, a first terminal of the first total reset transistor being connected to the pull-up node; a second total reset transistor, a control terminal of the second total reset transistor being connected to the total reset signal, a first terminal of the second total reset transistor being connected to the second terminal of the first total reset transistor, the first terminal of the second noise reduction transistor, the second terminal of the first noise reduction transistor, the second terminal of the second reset protection transistor, the second terminal of the first reset transistor, and the first terminal of the second reset transistor, a second terminal of the second total reset transistor being connected to the first power supply terminal signal.

[0026] In some embodiments, the pull-down node control circuit comprises: a first pull-up transistor, a control end of the first pull-up transistor and a first end of the first pull-up transistor being connected to a second power supply signal; a second pull-up transistor, a control end of the second pull-up transistor being connected to the second power supply signal, and a first end of the second pull-up transistor being connected to a second end of the first pull-up transistor; a pull-down transistor, a control end of the pull-down transistor being connected to the pull-up node, a first end of the pull-down transistor being connected to a second end of the second pull-up transistor, and a second end of the pull-down transistor being connected to a second voltage terminal signal; a first inverting transistor, a control end of the first inverting transistor being connected to the second end of the second pull-up transistor and the first end of the pull-down transistor, a first end of the first inverting transistor being connected to the second power supply signal, and a second end of the first inverting transistor being connected to the pull-down node; and a second inverting transistor, a control end of the second inverting transistor being connected to the pull-up node, a first end of the second inverting transistor being connected to the pull-down node, and a second end of the second inverting transistor being connected to a first voltage terminal signal.

[0027] In some embodiments, the connection point of the first sensing transistor and the second sensing transistor is connected to the connection point of the first noise reduction transistor and the second noise reduction transistor.

[0028] In some embodiments, the sensing compensation circuit further comprises: a maintaining sub-circuit configured to maintain the level of the control end of the sensing transistor under the control of a fifth control signal.

[0029] In some embodiments, the maintaining sub-circuit comprises: a first maintaining transistor connected in series between the pull-down node and the second inverting transistor, a control end of the first maintaining transistor being connected to the fifth control signal, a first end of the first maintaining transistor being connected to the pull-down node, and a second end of the first maintaining transistor being connected to a first end of the second inverting transistor.

[0030] In some embodiments, the maintaining sub-circuit further comprises: a second maintaining transistor connected in series between the second pull-up transistor and the pull-down transistor, a control end of the second maintaining transistor being connected to the fifth control signal, a first end of the second maintaining transistor being connected to the second end of the second pull-up transistor, and a second end of the second maintaining transistor being connected to the first end of the pull-down transistor.

[0031] In some embodiments, the maintaining sub-circuit comprises: a third maintaining transistor connected in series between the pull-down node and the control terminal of the sensing transistor; the control terminal of the third maintaining transistor is connected to the fifth control signal, the first terminal of the third maintaining transistor is connected to the pull-down node, and the second terminal of the third maintaining transistor is connected to the control terminal of the sensing transistor; and a fourth maintaining transistor, the control terminal of the fourth maintaining transistor is connected to the first control signal, the first terminal of the fourth maintaining transistor is connected to a sixth control signal, and the second terminal of the fourth maintaining transistor is connected to the second terminal of the third maintaining transistor and the control terminal of the sensing transistor.

[0032] In some embodiments, the sixth control signal and the second power signal share the same signal line.

[0033] In some embodiments, the output circuit comprises at least one output sub-circuit, and the composite signal comprises an output signal of each output sub-circuit in the output circuit; each output sub-circuit comprises: a first output transistor, the control terminal of the first output transistor is connected to the pull-up node, the first terminal of the first output transistor is connected to a clock signal, and the second terminal of the first output transistor outputs the output signal of the output sub-circuit; an output capacitor, the first pole of the output capacitor is connected to the pull-up node and the control terminal of the first output transistor, and the second pole of the output capacitor is connected to the second terminal of the first output transistor; and a second output transistor, the control terminal of the second output transistor is connected to the pull-down node, the first terminal of the second output transistor is connected to the second terminal of the first output transistor, and the second terminal of the second output transistor is connected to a first voltage terminal signal.

[0034] In some embodiments, the pull-down node stabilizing circuit comprises: an initial inverting transistor, the control terminal of the initial inverting transistor is connected to a charging input signal, the first terminal of the initial inverting transistor is connected to the pull-down node, and the second terminal of the initial inverting transistor is connected to the first voltage terminal signal.

[0035] In some embodiments, the selection compensation circuit further includes: a charging sub-circuit including a charging capacitor, a first charging transistor, a second charging transistor, and a third charging transistor; a first pole of the charging capacitor, a control terminal of the first charging transistor, and a control terminal of the second charging transistor are connected to a selection compensation control signal; a second pole of the charging capacitor is connected to a pull-up control node; a first terminal of the first charging transistor is connected to a charging input signal; a first terminal of the second charging transistor is connected to a second terminal of the first charging transistor; a second terminal of the second charging transistor is connected to the pull-up control node; a control terminal of the third charging transistor is connected to the pull-up control node; a first terminal of the third charging transistor is connected to a first power supply signal; and a second terminal of the third charging transistor is connected to the second terminal of the first charging transistor and the first terminal of the second charging transistor.

[0036] In some embodiments, the pull-down node stabilization circuit further includes: a first discharge transistor, a control terminal of the first discharge transistor being connected to the sub-clock signal, and a first terminal of the first discharge transistor being connected to the pull-down node; and a second discharge transistor, a control terminal of the second discharge transistor being connected to the pull-up control node, a first terminal of the second discharge transistor being connected to a second terminal of the first discharge transistor, and a second terminal of the second discharge transistor being connected to the first voltage terminal signal.

[0037] In a second aspect of the present disclosure, a gate drive circuit is provided, which includes at least one first shift register and a plurality of second shift registers cascaded with the first shift register, at least one of the first shift register and the second shift registers being the shift register provided in the first aspect.

[0038] In some embodiments, the sensing signal carries a threshold voltage of a target transistor; when at least one of the first shift register and the second shift register comprises the first stabilizing circuit provided in the first aspect, the target transistor comprises a first noise reduction transistor and a second noise reduction transistor in each of the shift registers; when at least one of the first shift register and the second shift register comprises the output sub-circuit provided in the first aspect, the target transistor comprises a second output transistor in each of the shift registers.

[0039] In a third aspect of the present disclosure, a display device is provided, which comprises the gate driving circuit provided in the second aspect.

[0040] In a fourth aspect of the present disclosure, a gate driving method is provided, which comprises: under the control of a charging input signal, pulling up a level of a pull-up node and adjusting a level of a pull-down node based on the level of the pull-up node, the level of the pull-down node being opposite to the level of the pull-up node; outputting a composite signal based on the level of the pull-up node and the level of the pull-down node; under the control of a display total reset signal, pulling down the level of the pull-up node and adjusting the level of the pull-down node based on the level of the pull-up node; and outputting a sensing signal based on the level of the pull-down node to adjust a driving voltage of a target transistor, the sensing signal carrying a threshold voltage of the target transistor.

[0041] According to the shift register, the gate driving circuit, the display device and the gate driving method provided in one or more embodiments of the present disclosure, by adding the sensing compensation circuit to output a sensing signal under the control of the electrical signal of the pull-down node, the threshold voltage biasing condition of the target transistor can be simulated by the sensing compensation circuit, the threshold voltage of the target transistor is carried in the sensing signal, so that the driving voltage of the target transistor can be adjusted according to the threshold voltage of the target transistor, and the voltage biasing of the target transistor is compensated. In this way, when the threshold voltage of part of the transistors (i.e. the target transistor) in the GOA is positively shifted, the threshold voltage variation of the target transistor can be known by the sensing compensation circuit, and then the driving voltage of the target transistor is dynamically compensated according to the threshold voltage of the target transistor, so that the target transistor can be precisely driven, and finally the precision of the output scan signal of the GOA is improved. BRIEF DESCRIPTION OF DRAWINGS

[0042] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present disclosure, and other drawings can be obtained by those skilled in the art without any creative effort.

[0043] Figure 1 shows a structural diagram of a shift register in one or more embodiments of the present disclosure.

[0044] Figure 2 shows a structural block diagram of various modules in the shift register of Figure 1.

[0045] Figure 3 shows a circuit diagram of various modules in the shift register of Figure 2.

[0046] Figure 4 shows a timing diagram of some signals in the shift register of Figure 3.

[0047] Figure 5 shows a circuit diagram of blanking phase transmission signals of Figure 4.

[0048] Figure 6 shows a circuit diagram of scan first phase transmission signals of Figure 4.

[0049] Figure 7 shows a circuit diagram of scan second phase transmission signals of Figure 4.

[0050] Figure 8 shows a circuit diagram of scan third phase transmission signals of Figure 4.

[0051] Figure 9 shows a timing diagram of inductive compensation circuit related signals of Figure 3.

[0052] Figure 10 shows another timing diagram of inductive compensation circuit related signals of Figure 3.

[0053] Figure 11 shows another structural block diagram of the shift register of Figure 1.

[0054] Figure 12 shows a circuit diagram of the shift register of Figure 11.

[0055] Figure 13 shows a timing diagram of inductive compensation circuit related signals of Figure 12.

[0056] Figure 14 shows yet another structural block diagram of the shift register of Figure 1.

[0057] Figure 15 shows a circuit diagram of the shift register of Figure 14.

[0058] Figure 16 shows a timing diagram of inductive compensation circuit related signals of Figure 15.

[0059] Figure 17 shows another circuit diagram of the shift register of Figure 1.

[0060] Figure 18 shows yet another circuit diagram of the shift register of Figure 1.

[0061] Figure 19 shows yet another circuit diagram of the shift register of Figure 1.

[0062] Figure 20 shows a timing diagram of inductive compensation circuit related signals of Figures 18 and 19.

[0063] Figure 21 shows another circuit diagram of the shift register of Figure 1.

[0064] Figure 22 shows a timing diagram of the signals related to the sensing compensation circuit of Figure 21.

[0065] Figure 23 shows another timing diagram of the signals related to the sensing compensation circuit of Figure 21.

[0066] Figure 24 shows yet another timing diagram of the signals related to the sensing compensation circuit of Figure 21.

[0067] Figure 25 shows a simulation diagram of the partial signals of the shift register of Figure 3.

[0068] Figure 26 shows a structural schematic diagram of a gate driving circuit in one or more embodiments of the present disclosure.

[0069] Figure 27 shows a structural block diagram of a partial first shift register of Figure 26.

[0070] Figure 28 shows a structural block diagram of a partial second shift register of Figure 26.

[0071] Figure 29 shows a circuit diagram of the second shift register of Figure 28.

[0072] Figure 30 shows another circuit diagram of the second shift register of Figure 28.

[0073] Figure 31 shows a flowchart of a gate driving method in one or more embodiments of the present disclosure.

[0074] Legend: 10: pull-up node control circuit; 11: input sub-circuit; 12: reset sub-circuit; 13: input protection sub-circuit; 14: reset protection sub-circuit; 20: pull-down node control circuit; 21: first inverting sub-circuit; 22: second inverting sub-circuit; 30: output circuit; 31: output sub-circuit; 40: sensing compensation circuit; 41: sensing sub-circuit; 42: output control sub-circuit; 43: voltage stabilizing sub-circuit; 44: voltage regulating sub-circuit; 45: sensing control sub-circuit; 46: maintaining sub-circuit; 50: first stabilizing circuit; 60: second stabilizing circuit; 70: pull-down node stabilizing circuit; 80: selection compensation circuit; 81: charging sub-circuit; 82: storage sub-circuit; 83: isolation sub-circuit; 84: discharging sub-circuit; 100: first shift register; 200: second shift register. DETAILED DESCRIPTION

[0075] In order to make the skilled in the art to which the present disclosure belongs more clearly understand the present disclosure, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those of ordinary skill in the art without creative labor fall within the scope of protection of the present disclosure.

[0076] AMOLED (Active-matrix organic light-emitting diode) products have the advantages of high contrast, wide viewing angle and fast response speed, and are expected to replace liquid crystal displays as the mainstream choice of the next generation of displays. In the pixel circuit of the AMOLED product, considering the limitation of the process, all N-type TFTs (Thin Film Transistors) are designed. Since the AMOLED product needs EL (electroluminescent) devices to emit light, the light-emitting current required by the EL device is provided by the Drive TFT, so in order to ensure the uniformity of the light emission of the AMOLED product, the consistency of the EL device characteristics needs to be increased, and the GOA is usually used to externally compensate. However, in the GOA of the related art, some transistors will be subjected to long-term PBTS (Positive Bias Temperature Stress), causing the threshold voltage of the transistor to positively drift, making it difficult for the GOA to accurately output the scanning signal.

[0077] FIG. 1 is a structural schematic diagram of a shift register in one or more embodiments of the present disclosure. Referring to FIG. 1, the first aspect embodiment of the present disclosure provides a shift register, which includes a pull-up node control circuit 10, a pull-down node control circuit 20, an output circuit 30 and a sensing compensation circuit 40. The pull-up node control circuit 10 is configured to control the electrical signal of the pull-up node QA. The output circuit 30 includes a gate driving output end, and the output circuit 30 is configured to output a composite signal to the gate driving output end under the control of the electrical signal of the pull-up node QA. The pull-down node control circuit 20 is configured to input a first voltage end signal VGL1 to the pull-down node QB under the control of the electrical signal of the pull-up node QA. The sensing compensation circuit 40 is configured to output a sensing signal Se under the control of the electrical signal of the pull-down node QB.

[0078] Exemplarily, the pull-up node control circuit 10 controls the electrical signal of the pull-up node QA to pull the electrical level of the pull-up node QA to high under the control of the charging input signal STU, or to pull the electrical level of the pull-up node QA to low under the control of the display total reset signal STD. The pull-down node control circuit 20 is configured to adjust the electrical level of the pull-down node QB based on the electrical level of the pull-up node QA (the electrical level of the pull-down node QB is opposite to the electrical level of the pull-up node QA), which can include but is not limited to inputting the first voltage terminal signal VGL1 to the pull-down node QB under the control of the electrical signal of the pull-up node QA, and inputting the second power supply signal GVDD2 to the pull-down node QB under the control of the electrical signal of the pull-up node QA, i.e. inputting the second power supply signal GVDD2 or the first voltage terminal signal VGL1 to the pull-down node QB under the control of the electrical signal of the pull-up node QA. The output circuit 30 is configured to output the composite signal based on the electrical level of the pull-up node QA and the electrical level of the pull-down node QB, which can include but is not limited to outputting the composite signal to the gate driving output terminal under the control of the electrical signal of the pull-up node QA. The induction compensation circuit 40 can simulate the threshold voltage bias condition of the target transistor, carry the threshold voltage of the target transistor in the induction signal Se, and then adjust the driving voltage of the target transistor according to the induction signal Se to compensate for the voltage bias of the target transistor.

[0079] Exemplarily, the electrical level of the pull-down node QB opposite to the electrical level of the pull-up node QA means that when the electrical level of the pull-up node QA is high, the electrical level of the pull-down node QB is low, and when the electrical level of the pull-up node QA is low, the electrical level of the pull-down node QB is high.

[0080] The shift register includes a pull-up node control circuit 10, a pull-down node control circuit 20, an output circuit 30, and a sensing compensation circuit 40. The pull-up node control circuit 10 pulls the level of the pull-up node QA high under the control of the charging input signal STU or pulls the level of the pull-up node QA low under the control of the display total reset signal STD. The pull-down node control circuit 20 adjusts the level of the pull-down node QB based on the level of the pull-up node QA, and the level of the pull-down node QB is opposite to the level of the pull-up node QA. The output circuit 30 outputs a composite signal based on the level of the pull-up node QA and the level of the pull-down node QB. Thus, the cascade of the shift register can realize the row-by-row scan driving function of the GOA, can reduce the manufacturing cost and simplify the process, and can make the frame of the display panel narrower. Moreover, the sensing compensation circuit 40 outputs a sensing signal Se under the control of the electrical signal of the pull-down node QB. The sensing compensation circuit 40 simulates the threshold voltage bias condition of a target transistor, carries the threshold voltage of the target transistor in the sensing signal Se, and thus can adjust the driving voltage of the target transistor according to the threshold voltage of the target transistor, compensate for the voltage bias of the target transistor. Thus, when the threshold voltage of the target transistor is positively shifted, the sensing compensation circuit 40 can learn the threshold voltage variation of the target transistor, and then dynamically compensate for the driving voltage of the target transistor according to the threshold voltage of the target transistor, accurately drive the target transistor, and finally improve the accuracy of the GOA output scan signal.

[0081] FIG. 2 is a structural block diagram of each module in the shift register of FIG. 1. As shown in FIG. 2, in some embodiments, the pull-up node control circuit 10 can include an input sub-circuit 11 and a reset sub-circuit 12. The input sub-circuit 11 is configured to pull the level of the pull-up node QA high under the control of the charging input signal STU, for example, by inputting the first power supply signal GVDD1 to the pull-up node QA under the control of the charging input signal STU. The reset sub-circuit 12 is configured to pull the level of the pull-up node QA low under the control of the display total reset signal STD.

[0082] For example, the input sub-circuit 11 can include at least one input transistor, and the control end of the input transistor is connected to the charging input signal STU. The input transistor is configured to be turned on when the level of the charging input signal STU is higher than the threshold voltage, so as to write the first power supply signal GVDD1 to the pull-up node QA.

[0083] FIG. 3 is a circuit diagram of each module in the shift register of FIG. 2. As shown in FIG. 3, the at least one input transistor can include a first input transistor T1 and a second input transistor T2. The first end of the first input transistor T1 is connected to the first power supply signal GVDD1, and the first end of the second input transistor T2 is connected to the first end of the first input transistor T1. The second end of the second input transistor T2 is connected to the pull-up node QA.

[0084] Referring to FIG. 2, the pull-up node control circuit 10 can further include an input protection sub-circuit 13. The input protection sub-circuit 13 is configured to write the first power supply signal GVDD1 to the connection point of the first input transistor T1 and the second input transistor T2 when the level of the pull-down node QB is higher than the threshold voltage.

[0085] Since the level of the pull-down node QB is opposite to that of the pull-up node QA, when the level of the pull-down node QB is higher than the threshold voltage, the level of the pull-up node QA is lower than the threshold voltage, at this time, although the first input transistor T1 and the second input transistor T2 are in the off state, the access end of the first power supply signal GVDD1 can leak to the pull-up node QA through the first input transistor T1 and the second input transistor T2. Here, the input protection sub-circuit 13 writes the first power supply signal GVDD1 to the connection point of the first input transistor T1 and the second input transistor T2 when the level of the pull-down node QB is higher than the threshold voltage, the first end and the second end of the first input transistor T1 are both accessed to the first power supply signal GVDD1, the first end and the second end of the first input transistor T1 have the same voltage, so that the first power supply signal GVDD1 cannot leak to the pull-up node QA through the first input transistor T1 and the second input transistor T2, significantly reducing the leakage current of the shift register at this stage.

[0086] Referring to FIG. 3, the input protection sub-circuit 13 can include an input protection transistor T3, the control end of the input protection transistor T3 is connected with the pull-down node QB. The input protection transistor T3 is configured to write the first power supply signal GVDD1 to the connection point of the first input transistor T1 and the second input transistor T2 when the level of the pull-down node QB is higher than the threshold voltage.

[0087] The first end of the input protection transistor T3 is accessed to the first power supply signal GVDD1, and the second end of the input protection transistor T3 is connected with the second end of the first input transistor T1 and the first end of the second input transistor T2.

[0088] For example, the reset sub-circuit 12 can include at least one reset transistor, the control end of the reset transistor is accessed to the display total reset signal STD. The reset transistor is configured to be turned on when the level of the display total reset signal STD is higher than the threshold voltage, so as to write the first voltage end signal VGL1 to the pull-up node QA.

[0089] Referring to FIG. 3, the at least one reset transistor can include a first reset transistor T4 and a second reset transistor T5, the first end of the first reset transistor T4 is connected with the pull-up node QA, the first end of the second reset transistor T5 is connected with the second end of the first reset transistor T4, and the second end of the second reset transistor T5 is accessed to the first voltage end signal VGL1.

[0090] Referring to FIG. 2, the pull-up node control circuit 10 can further include a reset protection sub-circuit 14. The reset protection sub-circuit 14 is configured to control the electrical signal of the pull-up synchronization node Q3 under the control of the electrical signal of the pull-up node QA, such as writing the first power signal GVDD1 to the connection point of the first reset transistor T4 and the second reset transistor T5 (i.e., the pull-up synchronization node Q3) when the level of the pull-up node QA is higher than the threshold voltage.

[0091] Since the level of the pull-down node QB is opposite to that of the pull-up node QA, when the level of the pull-up node QA is higher than the threshold voltage, the level of the pull-down node QB is at the threshold voltage, at this time, although the first reset transistor T4 and the second reset transistor T5 are in the off state, the pull-up node QA can leak to the access end of the first voltage end signal VGL through the first reset transistor T4 and the second reset transistor T5. Here, the reset protection sub-circuit 14 writes the first power signal GVDD1 to the connection point of the first reset transistor T4 and the second reset transistor T5 when the level of the pull-up node QA is higher than the threshold voltage, the first end and the second end of the first reset transistor T4 are both connected to the first power signal GVDD1, the voltage of the first end and the second end of the first reset transistor T4 is the same, so that the pull-up node QA cannot leak to the access end of the first voltage end signal VGL through the first reset transistor T4 and the second reset transistor T5, significantly reducing the leakage current of the shift register at this stage.

[0092] The reset protection sub-circuit 14 can include at least one reset protection transistor, the control end of the reset protection transistor is connected with the pull-up node QA. The reset protection transistor is configured to be turned on when the level of the pull-up node QA is higher than the threshold voltage, so that the first power signal GVDD1 is written to the connection point of the first reset transistor T4 and the second reset transistor T5.

[0093] Referring to FIG. 3, the at least one reset protection transistor can include a first reset protection transistor T6 and a second reset protection transistor T7, the first end of the first reset protection transistor T6 is connected to the first power signal GVDD1, the first end of the second reset protection transistor T7 is connected with the second end of the first reset protection transistor T6, and the second end of the second reset protection transistor T7 is connected with the second end of the first reset transistor T4 and the first end of the second reset transistor T5. The reset protection sub-circuit 14 is realized by two reset protection transistors in series, which can improve the reliability of the reset protection sub-circuit 14.

[0094] In some embodiments, referring to FIG. 2, the shift register can further include a first stabilizing circuit 50 configured to electrically control the pull-up node QA under the electrical signal control of the pull-down node QB, such as pulling down the level of the pull-up node QA when the level of the pull-down node QB is higher than a threshold voltage. By adding the first stabilizing circuit 50 to pull down the level of the pull-up node QA when the level of the pull-down node QB is higher than the threshold voltage, the pull-down of the level of the pull-up node QA can be ensured in cooperation with the reset sub-circuit 13.

[0095] Exemplarily, the first stabilizing circuit 50 can be connected with the pull-up synchronization node Q3 and further configured to electrically control the pull-up synchronization node Q3 under the electrical signal control of the pull-down node QB.

[0096] Exemplarily, the first stabilizing circuit 50 can include at least one noise reduction transistor, and a control end of the noise reduction transistor is connected with the pull-down node QB. The noise reduction transistor is configured to be turned on when the level of the pull-down node QB is higher than the threshold voltage, so as to write the first voltage end signal VGL1 into the pull-up node QA.

[0097] Referring to FIG. 3, the at least one noise reduction transistor can include a first noise reduction transistor T8 and a second noise reduction transistor T9. The first end of the first noise reduction transistor T8 is connected with the pull-up node QA, the first end of the second noise reduction transistor T9 is connected with the second end of the first noise reduction transistor T8, the second end of the second reset transistor T7, the second end of the first reset transistor T4, and the first end of the second reset transistor T5, and the second end of the second noise reduction transistor T9 is connected with the first voltage end signal VGL1. By connecting the two noise reduction transistors in series to realize the first stabilizing circuit 50, the reliability of the first stabilizing circuit 50 can be improved.

[0098] Exemplarily, when the shift register includes the first stabilizing circuit 50, the target transistor can include each noise reduction transistor in the first stabilizing circuit 50.

[0099] In some embodiments, referring to FIG. 2, the shift register can further include a second stabilizing circuit 60 configured to pull down the level of the pull-up node QA under the control of the total reset signal TRS. The second stabilizing circuit 60 and the reset sub-circuit 13 can reset at different stages. The reset sub-circuit 13 can reset only the shift register after the scanning of one row of pixel sub-circuits is completed, and the second stabilizing circuit 60 can reset all shift registers after the scanning of one frame of image is completed.

[0100] Exemplarily, the second stabilizing circuit 60 can include at least one total reset transistor, a control terminal of the total reset transistor being connected to a total reset signal TRS. The total reset transistor is configured to write the first voltage terminal signal VGL1 to the pull-up node QA under the control of the total reset signal TRS.

[0101] Referring to FIG. 3, the at least one total reset transistor can include a first total reset transistor T10 and a second total reset transistor T11. A first terminal of the first total reset transistor T10 is connected to the pull-up node QA, and a first terminal of the second total reset transistor T11 is connected to a second terminal of the first total reset transistor T10, a first terminal of the second noise reduction transistor T9, a second terminal of the first noise reduction transistor T8, a second terminal of the second reset protection transistor T7, a second terminal of the first reset transistor T4, and a first terminal of the second reset transistor T5. A second terminal of the second total reset transistor T11 is connected to the first voltage terminal signal VGL1. The second stabilizing circuit 60 is implemented by two total reset transistors in series, which can improve the reliability of the second stabilizing circuit 60.

[0102] In some embodiments, referring to FIG. 2, the pull-down node control circuit 20 can include a first inverting sub-circuit 21 and a second inverting sub-circuit 22. The first inverting sub-circuit 21 is configured to adjust the level of the first node Q1 based on the level of the pull-up node QA, the level of the first node Q1 being opposite to the level of the pull-up node QA. The second inverting sub-circuit 22 is configured to adjust the level of the pull-down node QB based on the level of the first node Q1 and the level of the pull-up node QA.

[0103] Exemplarily, the level of the first node Q1 being opposite to the level of the pull-up node QA means that when the level of the pull-up node QA is high, the level of the first node Q1 is low, and when the level of the pull-up node QA is low, the level of the first node Q1 is high.

[0104] By first adjusting the level of the first node Q1 based on the level of the pull-up node QA, the level of the first node Q1 being opposite to the level of the pull-up node QA, and then adjusting the level of the pull-down node QB based on the level of the first node Q1 and the level of the pull-up node QA, it can be ensured that the level of the pull-down node QB is opposite to the level of the pull-up node QA.

[0105] Exemplarily, the first inverting sub-circuit 21 can include at least one pull-up transistor and a pull-down transistor. A control terminal of the pull-up transistor is connected to the second power supply signal GVDD2, and the pull-up transistor is configured to write the second power supply signal GVDD2 to the first node Q1. A control terminal of the pull-down transistor is connected to the pull-up node QA, and the pull-down transistor is configured to write the second voltage terminal signal VGL2 to the first node Q1 when the level of the pull-up node QA is higher than a threshold voltage.

[0106] Referring to FIG. 3, the at least one pull-up transistor can include a first pull-up transistor T12 and a second pull-up transistor T13, a first end of the first pull-up transistor T12 is connected to the second power supply signal GVDD2, a first end of the second pull-up transistor T13 is connected to a second end of the first pull-up transistor T12, and a second end of the second pull-up transistor T13 is connected to the first node Q1. A first end of a pull-down transistor T14 is connected to the first node Q1, and a second end of the pull-down transistor T14 is connected to the second voltage terminal signal VGL2. The first inverting sub-circuit 21 is implemented by connecting the two pull-up transistors in series, which can improve the reliability of the first inverting sub-circuit 21.

[0107] Exemplarily, the second inverting sub-circuit 22 can include a first inverting transistor and a second inverting transistor. The first inverting transistor is configured to write the second voltage terminal signal VGL2 to the pull-down node QB when a level of the first node Q1 is higher than a threshold voltage. The second inverting transistor is configured to write the first voltage terminal signal VGL1 to the pull-down node QB when a level of the pull-up node QA is higher than the threshold voltage.

[0108] Referring to FIG. 3, a control end of the first inverting transistor T15 is connected to the first node Q1, a first end of the first inverting transistor T15 is connected to the second power supply signal GVDD2, and a second end of the first inverting transistor T15 is connected to the pull-down node QB. A control end of the second inverting transistor T16 is connected to the pull-up node QA, a first end of the second inverting transistor T16 is connected to the pull-down node QB, and a second end of the second inverting transistor T16 is connected to the first voltage terminal signal VGL1.

[0109] Exemplarily, the voltage of the second power supply signal GVDD2 can be adjusted according to the threshold voltage of the target transistor, and the level of the pull-down node QB changes accordingly, thereby compensating the driving voltage of the target transistor (such as the first noise reduction transistor T8 and the second noise reduction transistor T9).

[0110] In some embodiments, referring to FIG. 2, the shift register can further include a pull-down node stabilizing circuit 70. The pull-down node stabilizing circuit 70 is configured to write the first voltage terminal signal VGL1 to the pull-down node QB under the control of the charging input signal STU. Since the input sub-circuit 11 writes the first power supply signal GVDD1 to the pull-up node QA under the control of the charging input signal STU, by additionally providing the pull-down node stabilizing circuit 70 to write the first voltage terminal signal VGL1 to the pull-down node QB under the control of the charging input signal STU, the pull-down node stabilizing circuit 70 can cooperate with the pull-down node control circuit 20 to ensure that the pull-down node QB is low when the pull-up node QA is high.

[0111] Exemplarily, the pull-down node stabilization circuit 70 can include an initial inverter transistor, a control terminal of the initial inverter transistor being connected to the charging input signal STU. The initial inverter transistor is configured to be turned on when the level of the charging input signal STU is higher than a threshold voltage, so as to write the first voltage terminal signal VGL1 to the pull-down node QB.

[0112] Referring to FIG. 3, a first terminal of the initial inverter transistor T17 is connected to the pull-down node QB, and a second terminal of the initial inverter transistor T17 is connected to the first voltage terminal signal VGL1.

[0113] In some embodiments, referring to FIG. 2, the output circuit 30 can include at least one output sub-circuit 31, and the composite signal includes output signals OUT of each output sub-circuit 31 in the output circuit 30. The output sub-circuit 31 is configured to generate the output signal OUT based on the level of the pull-up node QA and the level of the pull-down node QB, and output the output signal OUT based on the clock signal CLKD.

[0114] Exemplarily, the clock signals CLKD connected to the output sub-circuits 31 can be different from each other. Accordingly, the output signals OUT of the output sub-circuits 31 can be different from each other.

[0115] When the shift register is a driving GOA, the output circuit 30 of the shift register can include a plurality of output sub-circuits 31, and the composite signal OUT output by one output sub-circuit 31 serves as the charging input signal STU and / or the display total reset signal STD of other shift registers cascaded with the shift register, and the composite signals OUT output by other output sub-circuits 31 serve as scan signals of at least one row of pixel sub-circuits, and the composite signals OUT output by different output sub-circuits 31 serve as scan signals of different rows of pixel sub-circuits.

[0116] When the shift register is a dummy GOA, the output circuit 30 of the shift register can include only one output sub-circuit 31, and the composite signal OUT output by the output sub-circuit 31 serves as the charging input signal STU and / or the display total reset signal STD of other shift registers cascaded with the shift register. The output circuit 30 of the shift register can also include a plurality of output sub-circuits 31, and the composite signal OUT output by one output sub-circuit 31 serves as the charging input signal STU and / or the display total reset signal STD of other shift registers cascaded with the shift register, and the composite signals OUT output by other output sub-circuits 31 do not serve as scan signals of pixel sub-circuits.

[0117] Exemplarily, the shift register can be a dummy GOA.

[0118] The output sub-circuit 31 can include a first output transistor, an output capacitor and a second output transistor. The control terminal of the first output transistor is connected with the pull-up node QA and is configured to be turned on when the level of the pull-up node QA is higher than the threshold voltage, to output the composite signal OUT. The output capacitor is configured to further pull up the level of the pull-up node QA, so that the level of the pull-up node QA is higher than the threshold voltage. The control terminal of the second output transistor is connected with the pull-down node QB and is configured to be turned on when the level of the pull-down node QB is higher than the threshold voltage, to reset the composite signal OUT.

[0119] Referring to FIG. 3, the first terminal of the first output transistor T18 is connected with the clock signal CLKD, and the composite signal OUT is output through the second terminal of the first output transistor. The first pole of the output capacitor C1 is connected with the pull-up node QA and the control terminal of the first output transistor T18, and the second pole of the output capacitor C1 is connected with the second terminal of the first output transistor T18. The first terminal of the second output transistor T19 is connected with the second terminal of the first output transistor T18, and the second terminal of the second output transistor T19 is connected with the first voltage terminal signal VGL1.

[0120] Exemplarily, when the output circuit 30 includes at least one output sub-circuit 31, the target transistor can include the second output transistor T19 in each output sub-circuit 31.

[0121] FIG. 4 is a timing diagram of part of the signals in the shift register of FIG. 3, FIG. 5 is a circuit diagram of the blanking stage transmission signal of FIG. 4, FIG. 6 is a circuit diagram of the scanning first stage transmission signal of FIG. 4, FIG. 7 is a circuit diagram of the scanning second stage transmission signal of FIG. 4, and FIG. 8 is a circuit diagram of the scanning third stage transmission signal of FIG. 4. In FIGS. 5-8, the direction of the transmission signal of each stage is indicated by an arrow, and the turned-on transistor is indicated by a solid line, and the turned-off transistor is indicated by a dashed line. Next, the working process of the shift register will be briefly introduced in combination with FIGS. 4-8.

[0122] Referring to FIG. 4 and FIG. 5, in the blanking stage, the charging input signal STU is at a low level, the first input transistor T1 and the second input transistor T2 are turned off, and the initial inverter transistor T17 is turned off. The display total reset signal STD is at a low level, and the first reset transistor T4 and the second reset transistor T5 are turned off.

[0123] The total reset signal TRS is at a high level, the first total reset transistor T10 and the second total reset transistor T11 are turned on, and the first voltage terminal signal VGL1 is written into the pull-up node QA at a low level.

[0124] The pull-up node QA is at low level, the first reset protection transistor T6 and the second reset protection transistor T7 are turned off, the pull-down transistor T14 and the second inverter transistor T16 are turned off. The first pull-up transistor T12 and the second pull-up transistor T13 are turned on, the second power supply signal GVDD2 is written into the first node Q1, and the first node Q1 is at high level. The first node Q1 is at high level, the first inverter transistor T15 is turned on, and the second power supply signal GVDD2 is written into the pull-down node QB, and the pull-down node QB is at high level.

[0125] The pull-down node QB is at high level, the input protection transistor T3 is turned on, the first power supply signal GVDD1 is written into the second node Q2 (i.e. the connection point of the first input transistor T1 and the second input transistor T2), and the second node Q2 is at high level. The first end and the second end of the first input transistor T1 are connected to the first power supply signal GVDD1, and the voltages at the first end and the second end of the first input transistor T1 are the same, which can prevent the first input transistor T1 from leaking current and affecting the pull-up node QA to be at low level, and further affecting the pull-down node QB to be at high level.

[0126] The pull-down node QB is at high level, the first noise reduction transistor T8 and the second noise reduction transistor T9 are turned on, the first voltage end signal VGL1 is written into the pull-up node QA, and the pull-up node QA is at low level.

[0127] The pull-up node QA is at low level, the first output transistor T18 is turned off. The pull-down node QB is at high level, the second output transistor T19 is turned on, and the first voltage end signal VGL1 is output. Therefore, the composite signal OUT is at low level.

[0128] Please refer to FIG. 4 and FIG. 6, in the first stage of scanning, the charging input signal STU is at high level, the first input transistor T1 and the second input transistor T2 are turned on, the first power supply signal GVDD1 is written into the pull-up node QA, and the pull-up node QA is at high level. Moreover, the initial inverter transistor T17 is turned on, the first voltage end signal VGL1 is written into the pull-down node QB, and the pull-down node QB is at low level. The pull-down node QB is at low level, and the input protection transistor T3 is turned off.

[0129] The display total reset signal STD is at low level, the first reset transistor T4 and the second reset transistor T5 are turned off. The pull-up node QA is at high level, the first reset protection transistor T6 and the second reset protection transistor T7 are turned on, the first power supply signal GVDD1 is written into the pull-up synchronization node Q3 (i.e. the connection point of the first reset transistor T4 and the second reset transistor T5), and the pull-up synchronization node Q3 is at high level. The first end and the second end of the first reset transistor T4 are connected to the first power supply signal GVDD1, and the voltages at the first end and the second end of the first reset transistor T4 are the same, which can prevent the first reset transistor T4 from leaking current and affecting the pull-up node QA to be at high level.

[0130] The first pull-up transistor T12 and the second pull-up transistor T13 are turned on, and the second power signal GVDD2 is written into the first node Q1. At the same time, the pull-up node QA is at a high level, the pull-down transistor T14 is turned on, and the second voltage terminal signal VGL2 is written into the first node Q1. Therefore, the level of the first node Q1 is lower than the threshold voltage, and the first inverter transistor T15 is turned off. The pull-up node QA is at a high level, the second inverter transistor T16 is turned on, the first voltage terminal signal VGL1 is written into the pull-down node QB, and the pull-down node QB is at a low level.

[0131] The pull-down node QB is at a low level, and the first noise reduction transistor T8 and the second noise reduction transistor T9 are turned off. In addition, the total reset signal TRS is at a low level, and the first total reset transistor T10 and the second total reset transistor T11 are turned off.

[0132] The pull-up node QA is at a high level, but does not reach the threshold voltage of the first output transistor T18, and the first output transistor T18 is turned off. The pull-down node QB is at a low level, and the second output transistor T19 is turned off. Therefore, the composite signal OUT is at a low level.

[0133] Please refer to FIG. 4 and FIG. 7, in the second stage of scanning, the charging input signal STU is at a low level, the first input transistor T1 and the second input transistor T2 are turned off, and the pull-up node QA remains at a high level. Moreover, the initial inverter transistor T17 is turned off, and the pull-down node QB remains at a low level. The pull-down node QB is at a low level, and the input protection transistor T3 is turned off.

[0134] The display total reset signal STD is at a low level, and the first reset transistor T4 and the second reset transistor T5 are turned off. The pull-up node QA is at a high level, the first reset protection transistor T6 and the second reset protection transistor T7 are turned on, the first power signal GVDD1 is written into the pull-up synchronization node Q3, and the pull-up synchronization node Q3 is at a high level. The first end and the second end of the first reset transistor T4 are connected to the first power signal GVDD1, and the voltages of the first end and the second end of the first reset transistor T4 are the same, which can prevent the first reset transistor T4 from leaking electricity.

[0135] The first pull-up transistor T12 and the second pull-up transistor T13 are turned on, and the second power signal GVDD2 is written into the first node Q1. At the same time, the pull-up node QA is at a high level, the pull-down transistor T14 is turned on, and the second voltage terminal signal VGL2 is written into the first node Q1. Therefore, the level of the first node Q1 is lower than the threshold voltage, and the first inverter transistor T15 is turned off. The pull-up node QA is at a high level, the second inverter transistor T16 is turned on, the first voltage terminal signal VGL1 is written into the pull-down node QB, and the pull-down node QB is at a low level.

[0136] The pull-down node QB is low, and the first noise reduction transistor T8 and the second noise reduction transistor T9 are turned off. In addition, the total reset signal TRS is low, and the first total reset transistor T10 and the second total reset transistor T11 are turned off.

[0137] The clock signal CLKD is high, and the output capacitor further pulls up the level of the pull-up node QA. The level of the pull-up node QA is higher than the threshold voltage of the first output transistor T18, the first output transistor T18 is turned on, and the clock signal CLKD is output. Therefore, the composite signal OUT is high.

[0138] Please refer to FIG. 4 and FIG. 8. In the third scanning stage, the charging input signal STU is low, the first input transistor T1 and the second input transistor T2 are turned off, and the initial inverter T17 is turned off.

[0139] The display total reset signal STD is high, the first reset transistor T4 and the second reset transistor T5 are turned on, the first voltage terminal signal VGL1 is written into the pull-up synchronization node Q3 and the pull-up node QA, and the pull-up synchronization node Q3 and the pull-up node QA are low. The pull-up node QA is low, and the first reset protection transistor T6 and the second reset protection transistor T7 are turned off.

[0140] The pull-up node QA is low, and the pull-down transistor T14 and the second inverter T16 are turned off. The first pull-up transistor T12 and the second pull-up transistor T13 are turned on, the second power supply signal GVDD2 is written into the first node Q1, and the first node Q1 is high. The first node Q1 is high, the first inverter T15 is turned on, the second power supply signal GVDD2 is written into the pull-down node QB, and the pull-down node QB is high.

[0141] The pull-down node QB is high, the input protection transistor T3 is turned on, the first power supply signal GVDD1 is written into the second node Q2, and the second node Q2 is high. The first end and the second end of the first input transistor T1 are connected to the first power supply signal GVDD1, and the voltages of the first end and the second end of the first input transistor T1 are the same, which can prevent the first input transistor T1 from leaking.

[0142] The pull-down node QB is high, the first noise reduction transistor T8 and the second noise reduction transistor T9 are turned on, the first voltage terminal signal VGL1 is written into the pull-up node QA, and the pull-up node QA is low. In addition, the total reset signal TRS is low, and the first total reset transistor T10 and the second total reset transistor T11 are turned off.

[0143] The pull-up node QA is low, and the first output transistor T18 is turned off. The pull-down node QB is high, the second output transistor T19 is turned on, and the first voltage terminal signal VGL1 is output. Therefore, the composite signal OUT is low.

[0144] Based on the above, the first noise reduction transistor T8, the second noise reduction transistor T9, and the second output transistor T19 are subjected to the PBTS for a long time, which can cause the threshold voltage to be positively shifted, and the shift register can not accurately output the composite signal OUT.

[0145] In some embodiments, referring to FIG. 2, the sensing compensation circuit 40 can include a sensing sub-circuit 41. The sensing sub-circuit 41 is configured to generate a sensing signal Se based on the first control signal DCLK1 when the level of the pull-down node QB is higher than the threshold voltage.

[0146] The first noise reduction transistor T8, the second noise reduction transistor T9, and the second output transistor T19 are turned on when the level of the pull-down node QB is higher than the threshold voltage, and the sensing sub-circuit 41 is configured to generate the sensing signal Se based on the first control signal DCLK1 when the level of the pull-down node QB is higher than the threshold voltage. The threshold voltage of the first noise reduction transistor T8, the second noise reduction transistor T9, and the second output transistor T19 (i.e., the threshold voltage of the target transistor) can be carried in the sensing signal Se, and the driving voltage of the first noise reduction transistor T8, the second noise reduction transistor T9, and the second output transistor T19 (i.e., the voltage of the second power supply signal GVDD2) can be adjusted to compensate for the positively shifted threshold voltage of the first noise reduction transistor T8, the second noise reduction transistor T9, and the second output transistor T19, so that the shift register can accurately output the composite signal OUT.

[0147] Exemplarily, the sensing sub-circuit 41 can include at least one sensing transistor, and the control end of the sensing transistor is connected with the pull-down node QB. The sensing transistor is configured to be turned on when the level of the pull-down node QB is higher than the threshold voltage, so that the first control signal DCLK1 passes through the sensing transistor to generate the sensing signal Se.

[0148] The sensing sub-circuit 41 includes at least one sensing transistor, and the control end of the sensing transistor is connected with the pull-down node QB. The sensing transistor is configured to be turned on when the level of the pull-down node QB is higher than the threshold voltage, which is the same as the first noise reduction transistor T8, the second noise reduction transistor T9, and the second output transistor T19. Therefore, the threshold voltage change of the first noise reduction transistor T8, the second noise reduction transistor T9, and the second output transistor T19 can be reflected through the threshold voltage change of the sensing transistor, and the driving voltage of the first noise reduction transistor T8, the second noise reduction transistor T9, and the second output transistor T19 can be adjusted to compensate for the positively shifted threshold voltage of the first noise reduction transistor T8, the second noise reduction transistor T9, and the second output transistor T19, so that the shift register can accurately output the composite signal.

[0149] Referring to FIG. 3, the at least one sensing transistor can include a first sensing transistor T20 and a second sensing transistor T21, a first end of the first sensing transistor T20 is connected to the first control signal DCLK1, a first end of the second sensing transistor T21 is connected to a second end of the first sensing transistor T20, and the sensing signal Se is output through a second end of the second sensing transistor T21.

[0150] The first sensing transistor T20 and the second sensing transistor T21 are connected in series in the same way as the first noise reduction transistor T8 and the second noise reduction transistor T9, and the threshold voltage change of the sensing transistor can more truly reflect the threshold voltage change of the first noise reduction transistor T8, the second noise reduction transistor T9 and the second output transistor T19, and then more accurately adjust the driving voltage of the first noise reduction transistor T8, the second noise reduction transistor T9 and the second output transistor T19, so as to better compensate for the threshold voltage of the first noise reduction transistor T8, the second noise reduction transistor T9 and the second output transistor T19 that occurs in the forward direction, so that the shift register can accurately output the composite signal.

[0151] Exemplarily, referring to FIG. 2, the sensing compensation circuit 40 can further include an output control sub-circuit 42. The output control sub-circuit 42 is configured to output the sensing signal Se under the control of the second control signal DCLK2.

[0152] By adding the output control sub-circuit 42 to output the sensing signal Se under the control of the second control signal DCLK2, the output of the sensing signal Se can be controlled, and the sensing signal Se is only output in the blanking stage, without affecting the level of each node in the scanning stage, thereby avoiding interference with the normal operation of the circuit (such as outputting the composite signal).

[0153] Referring to FIG. 3, the output control sub-circuit 42 can include an output control transistor T22, a control end of the output control transistor T22 is connected to the second control signal DCLK2, a first end of the output control transistor T22 is connected to a second end of the second sensing transistor T21, and the sensing signal Se is output through a second end of the output control transistor T22.

[0154] The control end of the output control transistor T22 is connected to the second control signal DCLK2, the first end of the output control transistor T22 is connected to the second end of the second sensing transistor T21, and the sensing signal Se is output through the second end of the output control transistor T22, so that the output control transistor T22 is turned on when the level of the second control signal DCLK2 is higher than the threshold voltage, so as to output the sensing signal Se.

[0155] FIG. 9 is a timing diagram of the related signals of the sensing compensation circuit of FIG. 3. Referring to FIG. 9, exemplarily, the first control signal DCLK1 can be a delayed signal of the second control signal DCLK2.

[0156] The second control signal DCLK2 is high first, and the output control transistor T22 is turned on. At this time, the first control signal DCLK1 is low, and the sensing signal Se is low to reset the sensing signal Se. The first control signal DCLK1 is low and then high, and the sensing signal Se is high to carry the threshold voltage of the sensing transistor.

[0157] The voltage of the second power signal GVDD2 is less than 10V, so the voltage of the pull-down node QB is less than 10V. The high level of the first control signal DCLK1 is 20V-24V, so the sensing transistor works in the saturation region. As the voltage of the sensing signal Se gradually rises to the voltage of the pull-down node QB minus the threshold voltage of the sensing transistor, the sensing transistor is cut off, thereby obtaining the threshold voltage of the sensing transistor.

[0158] FIG. 10 is another timing diagram of the sensing compensation circuit related signals of FIG. 3. Referring to FIG. 10, the first control signal DCLK1 and the selection compensation control signal OE can share the same signal line. The selection compensation control signal OE is the control signal for compensating the composite signal.

[0159] By sharing the same signal line with the selection compensation control signal OE, the first control signal DCLK1 does not need to add a signal line, and the number of signal lines can be reduced.

[0160] In a possible embodiment, referring to FIG. 2, the sensing compensation circuit 40 can further include a voltage stabilizing sub-circuit 43. The voltage stabilizing sub-circuit 43 is configured to stabilize the level of the pull-down node QB when the level of the first control signal DCLK1 jumps.

[0161] By adding the voltage stabilizing sub-circuit 43 to stabilize the level of the pull-down node QB when the level of the first control signal DCLK1 jumps, the level of the first control signal DCLK1 can be prevented from affecting the level of the pull-up node QA, and the compensation accuracy can be ensured.

[0162] Referring to FIG. 3, the voltage stabilizing sub-circuit 43 can include a voltage stabilizing capacitor C2. The first end of the voltage stabilizing capacitor C2 is connected to the pull-down node QB, and the second end of the voltage stabilizing capacitor C2 is connected to the second voltage terminal signal VGL2.

[0163] The first end of the voltage stabilizing capacitor C2 is connected to the pull-down node QB, and the second end of the voltage stabilizing capacitor C2 is connected to the second voltage terminal signal VGL2, which can stabilize the level of the pull-down node QB when the level of the first control signal DCLK1 jumps.

[0164] Fig. 11 is another structural block diagram of the shift register of Fig. 1. Referring to Fig. 11, in another possible embodiment, the sensing compensation circuit 40 can further include a voltage regulating sub-circuit 44. The voltage regulating sub-circuit 44 is configured to adjust the level of the pull-down node QB under the control of a third control signal DCLK3.

[0165] By adding the voltage regulating sub-circuit 44 to adjust the level of the pull-down node QB under the control of the third control signal DCLK3, the voltage range of the sensing signal Se can be controlled, and the accuracy of the sensing signal Se can be ensured.

[0166] Fig. 12 is a circuit diagram of the shift register of Fig. 11. Referring to Fig. 12, exemplarily, the voltage regulating sub-circuit 44 can include a voltage regulating transistor T23. The control terminal of the voltage regulating transistor T23 is connected to the third control signal DCLK3. The first terminal of the voltage regulating transistor T23 is connected to the pull-down node QB. The second terminal of the voltage regulating transistor T23 is connected to the first voltage terminal signal VGL1.

[0167] The first terminal of the voltage regulating transistor T23 is connected to the pull-down node QB. The second terminal of the voltage regulating transistor T23 is connected to the first voltage terminal signal VGL1. The voltage regulating transistor T23 can be turned on under the control of the third control signal DCLK3. The first voltage terminal signal VGL1 is written to the pull-down node QB. At this time, the first inverter transistor T15 is also turned on, and the second power supply signal GVDD2 is also written to the pull-down node QB. The first inverter transistor T15 and the voltage regulating transistor T23 perform voltage division, and thus the level of the pull-down node QB can be adjusted.

[0168] Fig. 13 is a timing diagram of the related signals of the sensing compensation circuit of Fig. 12. Referring to Fig. 13, the third control signal DCLK3 can be the same as the first control signal DCLK1.

[0169] Exemplarily, the third control signal DCLK3 and the first control signal DCLK1 can share the same signal line, and the number of signal lines can be reduced.

[0170] Fig. 14 is another structural block diagram of the shift register of Fig. 1. Referring to Fig. 14, in another possible embodiment, the sensing compensation circuit 40 can further include a sensing control sub-circuit 45. The sensing control sub-circuit 45 is configured to connect the level of the connection point of the first noise reduction transistor T8 and the second noise reduction transistor T9 to the sensing sub-circuit 41 under the control of a fourth control signal DCLK4.

[0171] The level of the connection point of the first noise reduction transistor T8 and the second noise reduction transistor T9 is connected to the induction sub-circuit 41 under the control of the fourth control signal DCLK4 by adding the induction control sub-circuit 45. The level of the connection point of the first noise reduction transistor T8 and the second noise reduction transistor T9 can be aligned on the basis of the overall change of the first noise reduction transistor T8 and the second noise reduction transistor T9. Therefore, the threshold voltage change of the first noise reduction transistor T8 and the second noise reduction transistor T9 can be better simulated, the threshold voltage change of the first noise reduction transistor T8 and the second noise reduction transistor T9 can be more truly reflected, and the driving voltage of the first noise reduction transistor T8, the second noise reduction transistor T9, and the second output transistor T19 can be more accurately adjusted to better compensate for the threshold voltage of the first noise reduction transistor T8, the second noise reduction transistor T9, and the second output transistor T19 that occurs in a positive direction, so that the shift register can accurately output the composite signal OUT.

[0172] FIG. 15 is a circuit diagram of the shift register of FIG. 14. Referring to FIG. 15, the induction control sub-circuit 45 may, for example, include an induction control transistor T24. The control end of the induction control transistor T24 is connected to the fourth control signal DCLK4. The first end of the induction control transistor T24 is connected to the second end of the first noise reduction transistor T8 and the first end of the second noise reduction transistor T9. The second end of the induction control transistor T24 is connected to the second end of the first induction transistor T20 and the first end of the second induction transistor T21.

[0173] The control end of the induction control transistor T24 is connected to the fourth control signal DCLK4. The first end of the induction control transistor T24 is connected to the second end of the first noise reduction transistor T8 and the first end of the second noise reduction transistor T9. The second end of the induction control transistor T24 is connected to the second end of the first induction transistor T20 and the first end of the second induction transistor T21. The level of the connection point of the first induction transistor T20 and the second induction transistor T21 can be aligned with the level of the connection point of the first noise reduction transistor T8 and the second noise reduction transistor T9 under the control of the fourth control signal DCLK4. Therefore, the threshold voltage change of the first noise reduction transistor T8 and the second noise reduction transistor T9 can be better simulated through the threshold voltage change of the first induction transistor T20 and the second induction transistor T21. The driving voltage of the first noise reduction transistor T8, the second noise reduction transistor T9, and the second output transistor T19 can be more accurately adjusted to better compensate for the threshold voltage of the first noise reduction transistor T8, the second noise reduction transistor T9, and the second output transistor T19 that occurs in a positive direction, so that the shift register can accurately output the composite signal OUT.

[0174] Fig. 16 is a timing diagram of the signals related to the sensing compensation circuit of Fig. 15. Referring to Fig. 16, the fourth control signal DCLK4 is high during the scanning phase to align the level of the connection point of the first sensing transistor T20 and the second sensing transistor T21 with the level of the connection point of the first noise reduction transistor T8 and the second noise reduction transistor T9. The fourth control signal DCLK4 is low first and high last during the blanking phase to avoid the influence of the sensing signal Se on the level of the connection point of the first sensing transistor T20 and the second sensing transistor T21.

[0175] In the above embodiment, the connection point of the first sensing transistor T20 and the second sensing transistor T21 is not connected to the connection point of the first noise reduction transistor T8 and the second noise reduction transistor T9, which can avoid the level of the connection point of the first noise reduction transistor T8 and the second noise reduction transistor T9 from interfering with the threshold voltage of the target transistor of the sensing signal Se.

[0176] Fig. 17 is another circuit diagram of the shift register of Fig. 1. Referring to Fig. 17, in some embodiments, the connection point of the first sensing transistor T20 and the second sensing transistor T21 can be connected to the connection point of the first noise reduction transistor T8 and the second noise reduction transistor T9, i.e., the sensing compensation circuit 40 is connected to the pull-up synchronization node Q3.

[0177] By connecting the connection point of the first sensing transistor T20 and the second sensing transistor T21 to the connection point of the first noise reduction transistor T8 and the second noise reduction transistor T9, the level of the connection point of the first sensing transistor T20 and the second sensing transistor T21 can be aligned with the level of the connection point of the first noise reduction transistor T8 and the second noise reduction transistor T9, so that the threshold voltage variation of the first noise reduction transistor T8 and the second noise reduction transistor T9 can be better simulated by the threshold voltage variation of the first sensing transistor T20 and the second sensing transistor T21, and the driving voltage of the first noise reduction transistor T8, the second noise reduction transistor T9 and the second output transistor T19 can be more accurately adjusted to better compensate for the threshold voltage of the first noise reduction transistor T8, the second noise reduction transistor T9 and the second output transistor T19 that is positively shifted, so that the shift register can accurately output the composite signal.

[0178] Fig. 18 is yet another circuit diagram of the shift register of Fig. 1. Referring to Fig. 18, the sensing compensation circuit 40 can further include a maintaining sub-circuit 46, for example. The maintaining sub-circuit 46 is configured to maintain the level of the control end of the sensing transistor under the control of a fifth control signal DCLK5.

[0179] The maintenance sub-circuit 46 is added to maintain the level of the control terminal of the sensing transistor under the control of the fifth control signal DCLK5, so as to improve the accuracy of the sensing sub-circuit 41 in detecting the threshold voltage of the target transistor.

[0180] Referring to FIG. 18, in a possible embodiment, the maintenance sub-circuit 46 can include a first maintenance transistor T25 connected in series between the pull-down node QB and the second inverter transistor T16. The control terminal of the first maintenance transistor T25 is connected to the fifth control signal DCLK5, the first end of the first maintenance transistor T25 is connected to the pull-down node QB, and the second end of the first maintenance transistor T25 is connected to the first end of the second inverter transistor T16.

[0181] The control terminal of the first maintenance transistor T25 is connected to the fifth control signal DCLK5, the first end of the first maintenance transistor T25 is connected to the pull-down node QB, and the second end of the first maintenance transistor T25 is connected to the first end of the second inverter transistor T16, so as to isolate the pull-down node QB from the second inverter transistor T16 under the control of the fifth control signal DCLK5, avoid the second inverter transistor T16 affecting the level of the pull-down node QB, thereby maintaining the level of the control terminal of the sensing transistor, and improving the accuracy of the sensing sub-circuit 41 in detecting the threshold voltage of the target transistor.

[0182] FIG. 19 is another circuit diagram of the shift register of FIG. 1. Referring to FIG. 19, the maintenance sub-circuit 46 can also include a second maintenance transistor T26 connected in series between the second pull-up transistor T13 and the pull-down transistor T14. The control terminal of the second maintenance transistor T26 is connected to the fifth control signal DCLK5, the first end of the second maintenance transistor T26 is connected to the second end of the second pull-up transistor T13, and the second end of the second maintenance transistor T26 is connected to the first end of the pull-down transistor T14.

[0183] The control terminal of the second maintenance transistor T26 is connected to the fifth control signal DCLK5, the first end of the second maintenance transistor T26 is connected to the second end of the second pull-up transistor T13, and the second end of the second maintenance transistor T26 is connected to the first end of the pull-down transistor T14, so as to isolate the second pull-up transistor T13 from the pull-down transistor T14 under the control of the fifth control signal DCLK5, avoid the pull-down transistor T14 affecting the level of the control terminal of the first inverter transistor T15, and further avoid affecting the level of the pull-down node QB, thereby maintaining the level of the control terminal of the sensing transistor, and improving the accuracy of the sensing sub-circuit 41 in detecting the threshold voltage of the target transistor.

[0184] Fig. 20 is a timing diagram of the signals related to the sensing compensation circuit of Figs. 18 and 19. Referring to Fig. 20, the fifth control signal DCLK5 is high during the scanning phase, and the first sustain transistor T25 and the second sustain transistor T26 are both turned on, so that the pull-down node control circuit 20 operates normally. The fifth control signal DCLK5 is low first and then high during the blanking phase, so that the level of the pull-down node QB is not affected, and the level of the control terminal of the sensing transistor is maintained, thereby improving the accuracy of the sensing sub-circuit 41 in detecting the threshold voltage of the target transistor.

[0185] Fig. 21 is another circuit diagram of the shift register of Fig. 1. Referring to Fig. 21, in another possible embodiment, the sustain sub-circuit 46 can include a third sustain transistor T27 and a fourth sustain transistor T28. The third sustain transistor T27 is connected in series between the pull-down node QB and the control terminal of the sensing transistor. The control terminal of the third sustain transistor T27 is connected to the fifth control signal DCLK5, the first terminal of the third sustain transistor T27 is connected to the pull-down node QB, and the second terminal of the third sustain transistor T27 is connected to the control terminal of the sensing transistor. The control terminal of the fourth sustain transistor T28 is connected to the first control signal DCLK1, the first terminal of the fourth sustain transistor T28 is connected to the sixth control signal DCLK6, and the second terminal of the fourth sustain transistor T28 is connected to the second terminal of the third sustain transistor T27 and the control terminal of the sensing transistor.

[0186] The control terminal of the third sustain transistor T27 is connected to the fifth control signal DCLK5, the first terminal of the third sustain transistor T27 is connected to the pull-down node QB, and the second terminal of the third sustain transistor T27 is connected to the control terminal of the sensing transistor, so that the pull-down node QB can be isolated from the control terminal of the sensing transistor under the control of the fifth control signal DCLK5, and the level of the pull-down node QB does not affect the level of the control terminal of the sensing transistor. At the same time, the control terminal of the fourth sustain transistor T28 is connected to the first control signal DCLK1, the first terminal of the fourth sustain transistor T28 is connected to the sixth control signal DCLK6, and the second terminal of the fourth sustain transistor T28 is connected to the second terminal of the third sustain transistor T27 and the control terminal of the sensing transistor, so that the sensing transistor can be turned on by the sixth control signal DCLK6 under the control of the first control signal DCLK1, and the level of the control terminal of the sensing transistor is maintained, thereby improving the accuracy of the sensing sub-circuit 41 in detecting the threshold voltage of the target transistor.

[0187] Fig. 22 is a timing diagram of the signals related to the sensing compensation circuit of Fig. 21. Referring to Fig. 22, the fifth control signal DCLK5 is high during the scanning phase, and the third sustain transistor T27 is turned on, so that the voltage level of the pull-down node QB can be applied to the sensing transistor, so that the sensing transistor and the target transistor have the same voltage environment. The fifth control signal DCLK5 is first low and then high during the blanking phase, so that the voltage level of the pull-down node QB can not affect the voltage level of the control terminal of the sensing transistor. The first control signal DCLK1 is high after the fifth control signal DCLK5 is low and before the fifth control signal DCLK5 is high, the fourth sustain transistor T28 is turned on, and the sixth control signal DCLK6 drives the sensing transistor to be turned on, so that the first control signal DCLK1 generates the sensing signal Se through the sensing transistor.

[0188] Fig. 23 is another timing diagram of the signals related to the sensing compensation circuit of Fig. 21. Referring to Fig. 23, the sixth control signal DCLK6 can share the same signal line with the first control signal DCLK1, so that the number of signal lines can be reduced.

[0189] Fig. 24 is another timing diagram of the signals related to the sensing compensation circuit of Fig. 21. Referring to Fig. 24, the sixth control signal DCLK6 can share the same signal line with the second power signal GVDD2, so that the number of signal lines can be reduced.

[0190] Fig. 25 is a simulation diagram of the signals of the shift register of Fig. 3. Referring to Fig. 25, when the high voltage level of the pull-down node QB changes due to the threshold voltage Vth of the transistor, the high voltage level of the sensing signal Se also changes accordingly, so that the threshold voltage Vth of the transistor can be detected through the sensing signal Se.

[0191] Fig. 26 is a structural schematic diagram of a gate drive circuit in one or more embodiments of the present disclosure. Referring to Fig. 26, the second aspect embodiment of the present disclosure provides a gate drive circuit, which includes at least one first shift register 100 and a plurality of second shift registers 200 connected in cascade with the first shift register 100. The first shift register 100 or the second shift register 200 is the shift register provided in any of the above embodiments.

[0192] Exemplarily, the first shift register 100 can be a dummy GOA, and only output one output signal OUT as a charging input signal STU and / or a display total reset signal STD of other shift registers cascaded with the shift register. The second shift register 200 can be a driving GOA, and output at least two output signals OUT, one output signal OUT as a charging input signal STU and / or a display total reset signal STD of other shift registers cascaded with the shift register, and the other output signal OUT as a scan signal of at least a pixel sub-circuit, different output signals OUT being scan signals of different rows of pixel sub-circuits.

[0193] Taking FIG. 26 as an example, the gate driving circuit includes four first shift registers 100 and N second shift registers 200, the four first shift registers 100 are respectively a first shift register a1, a first shift register a2, a first shift register a3, and a first shift register a4, and the N second shift registers 200 are respectively a second shift register b1, a second shift register b2, a second shift register b3, …, a second shift register bN-1, and a second shift register bN. The output signal OUT output by the first shift register a1 is a charging input signal STU of the first shift register a2 and the second shift register b1, the output signal OUT output by the first shift register a2 is a charging input signal STU of the second shift register b2, the output signal OUT output by the second shift register b1 is a display total reset signal STD of the first shift register a1 and a charging input signal STU of the second shift register b3, the output signal OUT output by the second shift register b2 is a display total reset signal STD of the first shift register a2 and a charging input signal STU of the second shift register b4, …, the output signal OUT output by the second shift register bN-1 is a display total reset signal STD of the second shift register bN-3 and a charging input signal STU of the first shift register a3, the output signal OUT output by the second shift register bN is a display total reset signal STD of the second shift register bN-2 and a charging input signal STU of the first shift register a4, the output signal OUT output by the first shift register a3 is a display total reset signal STD of the second shift register bN-1, and the output signal OUT output by the first shift register a4 is a display total reset signal STD of the second shift register bN. In addition, the charging input signal STU of the first shift register a1 and the display total reset signals STD of the first shift register a3 and the first shift register a4 are external access signals.

[0194] Any one of the first shift register a1, the first shift register a2, the first shift register a3, the first shift register a4 is the shift register provided in any one of the above embodiments, or any one of the second shift register b1, the second shift register b2, the second shift register b3, …, the second shift register bN-1, the second shift register bN is the shift register provided in any one of the above embodiments. FIG. 26 takes the first shift register a4 as an example, and the first control signal DCLK1 is connected to the first shift register a4.

[0195] FIG. 27 is a structural block diagram of part of the first shift register of FIG. 26, and FIG. 28 is a structural block diagram of part of the second shift register of FIG. 26. Referring to FIGS. 27, 28 and 2, in some embodiments, the first shift register 100 and the second shift register 200 can each include the pull-up node control circuit 10, the pull-down node control circuit 20 and the output circuit 30, and the pull-up node control circuit 10, the pull-down node control circuit 20 and the output circuit 30 of the first shift register 100 and the pull-up node control circuit 10, the pull-down node control circuit 20 and the output circuit 30 of the second shift register 200 are the same as the pull-up node control circuit 10, the pull-down node control circuit 20 and the output circuit 30 of the shift register provided in any one of the above embodiments. At least one of the first shift register 100 and the second shift register 200 further includes the sensing compensation circuit 40, that is, the shift register provided in any one of the above embodiments. The second shift register 200 further includes the selection compensation circuit 80, which is configured to compensate the composite signal under the control of the selection compensation control signal OE, which can include but is not limited to charging the pull-up control node Q4 under the control of the selection compensation control signal OE and charging the pull-up node QA under the control of the sub-clock signal CKA.

[0196] Exemplarily, referring to FIGS. 27, 28 and 2, the first shift register 100 and the second shift register 200 can further include at least one of the first stabilization circuit 50, the second stabilization circuit 60 and the pull-down node stabilization circuit 70, and the first stabilization circuit 50, the second stabilization circuit 60 and the pull-down node stabilization circuit 70 of the first shift register 100 and the first stabilization circuit 50, the second stabilization circuit 60 and the pull-down node stabilization circuit 70 of the second shift register 200 are the same as the first stabilization circuit 50, the second stabilization circuit 60 and the pull-down node stabilization circuit 70 of the shift register provided in any one of the above embodiments.

[0197] Exemplarily, the sensing signal Se carries a threshold voltage of a target transistor. When at least one of the first shift register 100 and the second shift register 200 comprises the first stabilizing circuit 50, the target transistor can comprise a noise reduction transistor in the respective shift register. When at least one of the first shift register 100 and the second shift register 200 comprises the output sub-circuit, the target transistor can comprise a second output transistor in the respective shift register.

[0198] Exemplarily, referring to FIG. 28, the selection compensation circuit 80 can comprise a charging sub-circuit 81, a storage sub-circuit 82 and an isolation sub-circuit 83. The charging sub-circuit 81 is configured to write a charging input signal STU to a pull-up control node Q4 under control of a selection compensation control signal OE. The storage sub-circuit 82 is configured to store the charging input signal STU written to the pull-up control node Q4. The isolation sub-circuit 83 is configured to write the charging input signal STU to a pull-up node QA based on levels of the pull-up control node Q4 and a sub-clock signal CKA.

[0199] FIG. 29 is a circuit diagram of the second shift register of FIG. 28. Referring to FIG. 29, the charging sub-circuit 81 can comprise a charging capacitor C3, a first charging transistor T29, a second charging transistor T30 and a third charging transistor T31. A first pole of the charging capacitor C3, a control terminal of the first charging transistor T29 and a control terminal of the second charging transistor T30 are connected to the selection compensation control signal OE, and a second pole of the charging capacitor C3 is connected to the pull-up control node Q4. A first terminal of the first charging transistor T29 is connected to the charging input signal STU, a first terminal of the second charging transistor T30 is connected to a second terminal of the first charging transistor T29, and a second terminal of the second charging transistor T30 is connected to the pull-up control node Q4. A control terminal of the third charging transistor T31 is connected to the pull-up control node Q4, a first terminal of the third charging transistor T31 is connected to the first power supply signal GVDD1, and a second terminal of the third charging transistor T31 is connected to the second terminal of the first charging transistor T29 and the first terminal of the second charging transistor T30.

[0200] The storage sub-circuit 82 can comprise a storage capacitor C4, a first pole of the storage capacitor C4 is connected to the first power supply signal GVDD1, and a second pole of the storage capacitor C4 is connected to the pull-up control node Q4.

[0201] The isolation circuit 83 can include a first isolation transistor T32 and a second isolation transistor T33. The control terminal of the first isolation transistor T32 is connected to the pull-up control node Q4, and the first terminal of the first isolation transistor T32 is connected to the first power supply signal GVDD1. The control terminal of the second isolation transistor T33 is connected to the sub-clock signal CKA, the first terminal of the second isolation transistor T33 is connected to the second terminal of the first isolation transistor T32, and the second terminal of the second isolation transistor T33 is connected to the pull-up node QA.

[0202] For example, in FIG. 29, the working process of the selection compensation circuit 80 is as follows: when the level of the selection compensation control signal OE is higher than the threshold voltage, the first charging transistor T29 and the second charging transistor T30 are turned on, the charging input signal STU is written to the pull-up control node Q4 and stored in the charging capacitor C3 and the storage capacitor C4. Therefore, the pull-up control node Q4 is at a high level.

[0203] When the pull-up control node Q4 is at a high level, the third charging transistor T31 is turned on, the first power supply signal GVDD1 is written to the pull-up control node Q4, the first power supply signal GVDD1 further pulls up the level of the pull-up control node Q4, and is stored in the charging capacitor C3 and the storage capacitor C4.

[0204] When the level of the pull-up control node Q4 is higher than the threshold voltage, the first isolation transistor T32 is turned on, and the second isolation transistor T33 is turned on when the level of the sub-clock signal CKA is higher than the threshold voltage. The first power supply signal GVDD1 is written to the pull-up node QA, and the pull-up node QA is at a high level. When the level of the sub-clock signal CKA is lower than the threshold voltage, the second isolation transistor T33 is turned off, and the pull-up node QA can remain at a high level.

[0205] For example, the pull-down node control circuit 70 can also be configured to write the first voltage terminal signal VGL1 to the pull-down node QB based on the level of the pull-up control node Q4 and the sub-clock signal CKA.

[0206] FIG. 30 is another circuit diagram of the second shift register of FIG. 28. Referring to FIG. 30, the pull-down node control circuit 70 can further include a first discharge transistor T34 and a second discharge transistor T35. The control terminal of the first discharge transistor T34 is connected to the sub-clock signal CKA, and the first terminal of the first discharge transistor T34 is connected to the pull-up node QA. The control terminal of the second discharge transistor T35 is connected to the pull-up control node Q4, the first terminal of the second discharge transistor T35 is connected to the second terminal of the first discharge transistor T34, and the second terminal of the second discharge transistor T35 is connected to the first voltage terminal signal VGL1.

[0207] Still taking FIG. 30 as an example, the first discharging transistor T34 is turned on when the level of the sub-clock signal CKA is higher than the threshold voltage, the second discharging transistor T35 is turned on when the level of the pull-up control node Q4 is higher than the threshold voltage, the first voltage terminal signal VGL1 is written to the pull-down node QB, and the pull-down node QB is at a low level, which is just opposite to the high level of the pull-up node QA.

[0208] In a third aspect, the present disclosure provides a display device, which comprises the gate driving circuit provided in any of the above embodiments.

[0209] FIG. 31 is a flow chart of a gate driving method in one or more embodiments of the present disclosure. As shown in FIG. 31, the gate driving method comprises the following steps S101-S104.

[0210] In step S101, the level of the pull-up node is pulled high under the control of the charging input signal, and the level of the pull-down node is adjusted based on the level of the pull-up node, the level of the pull-down node being opposite to the level of the pull-up node.

[0211] In step S102, a composite signal is output based on the level of the pull-up node and the level of the pull-down node.

[0212] In step S103, the level of the pull-up node is pulled low under the control of the display global reset signal, and the level of the pull-down node is adjusted based on the level of the pull-up node.

[0213] In step S104, a sensing signal is output based on the level of the pull-down node to adjust the driving voltage of the target transistor, the sensing signal carrying the threshold voltage of the target transistor.

[0214] In the present disclosure, unless otherwise explicitly specified and limited, the first feature is "on" or "under" the second feature, which can include that the first and second features are in direct contact, or that the first and second features are not in direct contact but are in contact through another feature between them. Moreover, the first feature is "on", "above" and "on top of" the second feature, which includes that the first feature is directly above and obliquely above the second feature, or only means that the horizontal height of the first feature is higher than that of the second feature. The first feature is "under", "below" and "underneath" the second feature, which includes that the first feature is directly below and obliquely below the second feature, or only means that the horizontal height of the first feature is less than that of the second feature.

[0215] In the description of the present disclosure, it needs to be understood that the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise" indicate the orientation or positional relationship shown in the drawings, which are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the present disclosure.

[0216] In the present disclosure, unless otherwise explicitly specified and limited, the terms "connection", "fixation" and the like should be understood broadly, for example, "fixation" can be fixed connection, or detachable connection, or integral; can be mechanical connection, or electrical connection; can be direct connection, or indirect connection through intermediate medium; can be internal connection of two elements or interaction relationship between two elements. For those skilled in the art, the specific meaning of the above terms in the present disclosure can be understood according to the specific circumstances.

[0217] In addition, in the present disclosure, the description such as "first", "second" and the like is only for the purpose of description, and cannot be understood as indicating or implying the relative importance of the indicated technical features or implicitly indicating the number of the indicated technical features. Therefore, the features defined with "first", "second" can explicitly or implicitly include one or more features. In the description of the present disclosure, the meaning of "multiple" is two or more, unless otherwise explicitly specified and limited.

[0218] Although the embodiments of the present disclosure have been shown and described, those skilled in the art can understand that various changes, modifications, replacements and variations can be made to these embodiments without departing from the principles and purposes of the present disclosure, and the scope of the present disclosure is defined by the claims and their equivalents.

Claims

1. A shift register, comprising: a pull-up node control circuit configured to control an electrical signal of a pull-up node; an output circuit comprising a gate drive output, the output circuit configured to output a composite signal to the gate drive output under control of the electrical signal of the pull-up node; a pull-down node control circuit configured to input a first voltage terminal signal to a pull-down node under control of the electrical signal of the pull-up node; a sensing compensation circuit configured to output a sensing signal under control of an electrical signal of the pull-down node.

2. The shift register of claim 1, further comprising: a first stabilization circuit configured to control the electrical signal of the pull-up node under control of the electrical signal of the pull-down node.

3. The shift register of claim 2, wherein, the pull-up node control circuit comprises: an input sub-circuit configured to input a first power supply signal to the pull-up node under control of a charging input signal; the pull-down node control circuit is configured to input a second power supply signal or the first voltage terminal signal to the pull-down node under control of the electrical signal of the pull-up node.

4. The shift register of claim 3, wherein, the pull-up node control circuit further comprises: a reset protection sub-circuit configured to control an electrical signal of a pull-up synchronization node under control of the electrical signal of the pull-up node, the pull-up synchronization node connected to the first stabilization circuit; the first stabilization circuit is further configured to control the electrical signal of the pull-up synchronization node under control of the electrical signal of the pull-down node.

5. The shift register of claim 4, further comprising: a selection compensation circuit configured to charge a pull-up control node under control of a selection compensation control signal and to charge the pull-up node under control of a sub-clock signal.

6. The shift register of any one of claims 1-5, wherein, the sensing compensation circuit comprises: a sensing sub-circuit configured to generate the sensing signal based on a first control signal when a level of the pull-down node is higher than a threshold voltage.

7. The shift register of claim 6, wherein, the sensing sub-circuit comprises: at least one sensing transistor, a control terminal of the at least one sensing transistor connected to the pull-down node, the at least one sensing transistor configured to turn on when the level of the pull-down node is higher than the threshold voltage to cause the first control signal to generate the sensing signal through the at least one sensing transistor.

8. The shift register of claim 7, wherein, the at least one sensing transistor comprises: a first sensing transistor, a first terminal of the first sensing transistor connected to the first control signal; a second sensing transistor, a first terminal of the second sensing transistor connected to a second terminal of the first sensing transistor, the sensing signal output through a second terminal of the second sensing transistor.

9. The shift register of claim 8, wherein, the first control signal and a selection compensation control signal share a same signal line, the selection compensation control signal being a control signal for compensating the composite signal.

10. The shift register of claim 8, wherein, the sensing compensation circuit further comprises: an output control sub-circuit configured to output the sensing signal under control of a second control signal.

11. The shift register of claim 10, wherein, the output control sub-circuit comprises: an output control transistor, a control terminal of the output control transistor connected to the second control signal, a first terminal of the output control transistor connected to the second terminal of the second sensing transistor, the sensing signal output through a second terminal of the output control transistor.

12. The shift register of claim 11, wherein, The first control signal is a delayed signal of the second control signal.

13. The shift register of claim 6, wherein, The sensing compensation circuit further comprises: A voltage stabilizing sub-circuit configured to stabilize the level of the pull-down node when the level of the first control signal jumps.

14. The shift register of claim 13, wherein, The voltage stabilizing sub-circuit comprises: A voltage stabilizing capacitor, a first end of the voltage stabilizing capacitor being connected with the pull-down node, and a second end of the voltage stabilizing capacitor being connected with a second voltage terminal signal.

15. The shift register of claim 6, wherein, The sensing compensation circuit further comprises: A voltage regulating sub-circuit configured to adjust the level of the pull-down node under the control of a third control signal.

16. The shift register of claim 15, wherein, The voltage regulating sub-circuit comprises: A voltage regulating transistor, a control end of the voltage regulating transistor being connected with the third control signal, a first end of the voltage regulating transistor being connected with the pull-down node, and a second end of the voltage regulating transistor being connected with a first voltage terminal signal.

17. The shift register of claim 8, further comprising a first stabilizing circuit, the first stabilizing circuit comprising: A first noise reducing transistor, a control end of the first noise reducing transistor being connected with the pull-down node, and a first end of the first noise reducing transistor being connected with the pull-up node; A second noise reducing transistor, a control end of the second noise reducing transistor being connected with the pull-down node, a first end of the second noise reducing transistor being connected with a second end of the first noise reducing transistor, and a second end of the second noise reducing transistor being connected with the first voltage terminal signal.

18. The shift register of claim 17, wherein, The sensing compensation circuit further comprises: A sensing control sub-circuit configured to connect the level of the connection point of the first noise reducing transistor and the second noise reducing transistor to the sensing sub-circuit under the control of a fourth control signal.

19. The shift register of claim 18, wherein, The sensing control sub-circuit comprises: A sensing control transistor, a control end of the sensing control transistor being connected with the fourth control signal, a first end of the sensing control transistor being connected with the second end of the first noise reducing transistor and the first end of the second noise reducing transistor, and a second end of the sensing control transistor being connected with the second end of the first sensing transistor and the first end of the second sensing transistor.

20. The shift register of claim 17, wherein, The pull-up node control circuit comprises: A first input transistor, a control end of the first input transistor being connected with a charging input signal, and a first end of the first input transistor being connected with a first power supply signal; A second input transistor, a control end of the second input transistor being connected with the charging input signal, a first end of the second input transistor being connected with the first end of the first input transistor, and a second end of the second input transistor being connected with the pull-up node; An input protection transistor, a control end of the input protection transistor being connected with the pull-down node, a first end of the input protection transistor being connected with the first power supply signal, and a second end of the input protection transistor being connected with the second end of the first input transistor and the first end of the second input transistor; A first reset transistor, a control end of the first reset transistor being connected with a display total reset signal, and a first end of the first reset transistor being connected with the pull-up node; a second reset transistor, a control terminal of the second reset transistor being connected to the display total reset signal, a first terminal of the second reset transistor being connected to the second terminal of the first reset transistor, the second terminal of the first noise reduction transistor, and the first terminal of the second noise reduction transistor, and a second terminal of the second reset transistor being connected to the first voltage terminal signal; a first reset protection transistor, a control terminal of the first reset protection transistor being connected to the pull-up node, and a first terminal of the first reset protection transistor being connected to the first power supply signal; a second reset protection transistor, a control terminal of the second reset protection transistor being connected to the pull-up node, a first terminal of the second reset protection transistor being connected to the second terminal of the first reset protection transistor, and a second terminal of the second reset protection transistor being connected to the second terminal of the first reset transistor, the first terminal of the second reset transistor, and the second terminal of the first noise reduction transistor.

21. The shift register of claim 20, further comprising a second stabilization circuit, the second stabilization circuit comprising: a first total reset transistor, a control terminal of the first total reset transistor being connected to the total reset signal, and a first terminal of the first total reset transistor being connected to the pull-up node; a second total reset transistor, a control terminal of the second total reset transistor being connected to the total reset signal, a first terminal of the second total reset transistor being connected to the second terminal of the first total reset transistor, the first terminal of the second noise reduction transistor, the second terminal of the first noise reduction transistor, the second terminal of the second reset protection transistor, the second terminal of the first reset transistor, and the first terminal of the second reset transistor, and a second terminal of the second total reset transistor being connected to the first power supply terminal signal.

22. The shift register of claim 17, wherein, the pull-down node control circuit comprises: a first pull-up transistor, a control terminal and a first terminal of the first pull-up transistor being connected to the second power supply signal; a second pull-up transistor, a control terminal of the second pull-up transistor being connected to the second power supply signal, and a first terminal of the second pull-up transistor being connected to the second terminal of the first pull-up transistor; a pull-down transistor, a control terminal of the pull-down transistor being connected to the pull-up node, a first terminal of the pull-down transistor being connected to the second terminal of the second pull-up transistor, and a second terminal of the pull-down transistor being connected to the second voltage terminal signal; a first inverting transistor, a control terminal of the first inverting transistor being connected to the second terminal of the second pull-up transistor, a first terminal of the first inverting transistor being connected to the second power supply signal, and a second terminal of the first inverting transistor being connected to the pull-down node; a second inverting transistor, a control terminal of the second inverting transistor being connected to the pull-up node, a first terminal of the second inverting transistor being connected to the pull-down node, and a second terminal of the second inverting transistor being connected to the first voltage terminal signal.

23. The shift register of claim 22, wherein, a connection point of the first sensing transistor and the second sensing transistor is connected to a connection point of the first noise reduction transistor and the second noise reduction transistor.

24. The shift register of claim 23, wherein, the sensing compensation circuit further comprises: a maintaining sub-circuit configured to maintain a level of the control terminal of the sensing transistor under control of a fifth control signal.

25. The shift register of claim 24, wherein, The maintaining sub-circuit comprises: a first maintaining transistor connected in series between the pull-down node and the second inverting transistor, a control terminal of the first maintaining transistor connected to the fifth control signal, a first terminal of the first maintaining transistor connected to the pull-down node, and a second terminal of the first maintaining transistor connected to a first terminal of the second inverting transistor.

26. The shift register of claim 25, wherein, The maintaining sub-circuit further comprises: a second maintaining transistor connected in series between the second pull-up transistor and the pull-down transistor, a control terminal of the second maintaining transistor connected to the fifth control signal, a first terminal of the second maintaining transistor connected to a second terminal of the second pull-up transistor, and a second terminal of the second maintaining transistor connected to a first terminal of the pull-down transistor.

27. The shift register of claim 24, wherein, The maintaining sub-circuit comprises: a third maintaining transistor connected in series between the pull-down node and a control terminal of the sensing transistor, a control terminal of the third maintaining transistor connected to the fifth control signal, a first terminal of the third maintaining transistor connected to the pull-down node, and a second terminal of the third maintaining transistor connected to the control terminal of the sensing transistor; a fourth maintaining transistor, a control terminal of the fourth maintaining transistor connected to the first control signal, a first terminal of the fourth maintaining transistor connected to a sixth control signal, and a second terminal of the fourth maintaining transistor connected to the second terminal of the third maintaining transistor and the control terminal of the sensing transistor.

28. The shift register of claim 27, wherein, The sixth control signal shares the same signal line with the second power signal.

29. The shift register of any one of claims 1-5, wherein, The output circuit comprises at least one output sub-circuit, and the composite signal comprises output signals of each output sub-circuit in the output circuit; each output sub-circuit comprises: a first output transistor, a control terminal of the first output transistor connected to the pull-up node, a first terminal of the first output transistor connected to a clock signal, and a second terminal of the first output transistor outputting an output signal of the output sub-circuit; an output capacitor, a first pole of the output capacitor connected to the pull-up node and the control terminal of the first output transistor, and a second pole of the output capacitor connected to the second terminal of the first output transistor; a second output transistor, a control terminal of the second output transistor connected to the pull-down node, a first terminal of the second output transistor connected to the second terminal of the first output transistor, and a second terminal of the second output transistor connected to a first voltage terminal signal.

30. The shift register of any one of claims 1-5, further comprising a pull-down node stabilizing circuit, the pull-down node stabilizing circuit comprising: an initial inverting transistor, a control terminal of the initial inverting transistor connected to a charging input signal, a first terminal of the initial inverting transistor connected to the pull-down node, and a second terminal of the initial inverting transistor connected to the first voltage terminal signal.

31. The shift register of claim 30, further comprising a selection compensation circuit, the selection compensation circuit comprising: a charging sub-circuit comprising a charging capacitor, a first charging transistor, a second charging transistor, and a third charging transistor. The first pole of the charging capacitor, the control end of the first charging transistor and the control end of the second charging transistor are connected to a selection compensation control signal, the second pole of the charging capacitor is connected to a pull-up control node, the first end of the first charging transistor is connected to a charging input signal, the first end of the second charging transistor is connected to the second end of the first charging transistor, the second end of the second charging transistor is connected to the pull-up control node, the control end of the third charging transistor is connected to the pull-up control node, the first end of the third charging transistor is connected to a first power supply signal, and the second end of the third charging transistor is connected to the second end of the first charging transistor and the first end of the second charging transistor; The storage sub-circuit includes a storage capacitor, the first pole of the storage capacitor is connected to the first power supply signal, and the second pole of the storage capacitor is connected to the pull-up control node; The isolation sub-circuit includes a first isolation transistor and a second isolation transistor; The control end of the first isolation transistor is connected to the pull-up control node, the first end of the first isolation transistor is connected to the first power supply signal, the control end of the second isolation transistor is connected to a sub-clock signal, the first end of the second isolation transistor is connected to the second end of the first isolation transistor, and the second end of the second isolation transistor is connected to the pull-up node.

32. The shift register of claim 31, wherein, The pull-down node stabilization circuit further includes: The first discharge transistor, the control end of the first discharge transistor is connected to the sub-clock signal, and the first end of the first discharge transistor is connected to the pull-down node; The second discharge transistor, the control end of the second discharge transistor is connected to the pull-up control node, the first end of the second discharge transistor is connected to the second end of the first discharge transistor, and the second end of the second discharge transistor is connected to the first voltage terminal signal. 33.A gate driving circuit, comprising at least one first shift register and a plurality of second shift registers cascaded with the first shift register, at least one of the first shift register and the second shift registers being the shift register of any one of claims 1-32.

34. The gate drive circuit of claim 33, wherein, The sensing signal carries a threshold voltage of a target transistor; When at least one of the first shift register and the second shift register comprises the first stabilization circuit of claim 17, the target transistor comprises a first noise reduction transistor and a second noise reduction transistor in each of the shift registers; When at least one of the first shift register and the second shift register comprises the output sub-circuit of claim 25, the target transistor comprises a second output transistor in each of the shift registers. 35.A display device, comprising the gate driving circuit of claim 33 or 34. 36.A gate driving method, comprising: pulling up a level of a pull-up node under control of a charging input signal, and adjusting a level of a pull-down node based on the level of the pull-up node, the level of the pull-down node being opposite to the level of the pull-up node; output a composite signal based on the level of the pull-up node and the level of the pull-down node; pull down the level of the pull-up node under the control of a display global reset signal, and adjust the level of the pull-down node based on the level of the pull-up node; output a sensing signal based on the level of the pull-down node to adjust the drive voltage of a target transistor, the sensing signal carrying the threshold voltage of the target transistor.

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