Chip, chip packaging structure and electronic device

Abstract

The present application provides a chip, a chip packaging structure and an electronic device. The chip comprises a substrate, an electrode, a pad, and an organic dielectric layer, wherein the organic dielectric layer wraps a side surface of the pad, and covers a portion of a second surface of the pad facing away from the electrode. When the pad deforms under the effect of high temperature, the organic dielectric layer is well attached to the second surface and the side surface of the pad, thereby preventing the formation of a gap between the organic dielectric layer and the pad, and thus preventing solder on the pad from entering an interface between the organic dielectric layer and the pad due to melting during soldering; and in addition, even if the solder enters the connecting interface, the larger connecting interface can provide more buffer space, thereby effectively preventing the solder from overflowing to the surface of the electrode serving as surface metal of the chip. In addition, the larger connecting interface also contributes to releasing stress, thereby preventing cracks in the surface metal of the chip caused by stress mismatch. When the chip is applied to the chip packaging structure, the reliability of the chip packaging structure can be improved.

Description

Chip, chip packaging structure and electronic device

[0001] Cross-reference to related applications

[0002] The present application claims priority to the Chinese patent application No. 202411060220.3, filed on August 2, 2024, and entitled "Chip, chip packaging structure and electronic device", the entire content of which is incorporated herein by reference. TECHNICAL FIELD

[0003] The present application relates to the technical field of semiconductor technology, and in particular to a chip, a chip packaging structure and an electronic device. BACKGROUND

[0004] Generally, a chip packaging structure generally integrates multiple chips on the same substrate through a redistribution layer, which can have higher packaging density and achieve greater interconnection density. Exemplarily, two adjacent chips in a stacked arrangement and the chip and the redistribution layer can be electrically connected by soldering, but in reliability tests, due to the stress mismatch between the solder and the surface layer metal of the chip, the surface layer metal of the chip is prone to cracking, resulting in electrical connection failure between the chip and other chips or the redistribution layer, thereby reducing the reliability of the chip packaging structure. SUMMARY

[0005] The present application provides a chip, a chip packaging structure and an electronic device to avoid cracking of the surface layer metal of the chip and improve the reliability of the chip and the chip packaging structure.

[0006] In a first aspect, an embodiment of the present application provides a chip, which can include: a substrate; an electrode disposed on the substrate; a pad disposed on a first surface of the electrode away from the substrate, the pad covering part of the first surface; and an organic medium layer wrapping a side surface of the pad and covering part of a second surface of the pad away from the electrode, so that there are more connection interfaces between the organic medium layer and the pad; since the adhesion of the organic medium layer is good, even if the pad deforms under high temperature during welding or subsequent reliability testing, the organic medium layer can be well attached to the second surface and the side surface of the pad, avoiding the generation of gaps between the organic medium layer and the pad, and thus avoiding the molten solder on the pad from entering the interface between the organic medium layer and the pad during welding; and even if the solder enters the connection interface, the more connection interfaces can provide more buffer space, effectively preventing the solder from overflowing to the surface of the electrode (i.e., the surface metal of the chip); in addition, the more connection interfaces also help to release stress, thereby avoiding the cracking of the surface metal of the chip due to stress mismatch; when the chip is applied to a chip packaging structure, the reliability of the chip packaging structure can be improved.

[0007] Optionally, the organic medium layer covers the periphery of the second surface, which can prevent the solder from overflowing to the surface of the electrode from any position around the pad, thereby effectively preventing the electrode from cracking. The length of any edge of the second surface covered by the organic medium layer along the normal direction thereof can be greater than 10 μm, and can be further set to 40 μm, 60 μm, 80 μm, 100 μm, or other values, which can be set according to actual needs and are not limited herein.

[0008] Optionally, the organic medium layer includes a plurality of organic film layers, part of the organic film layers covering part of the second surface; the organic film layers not covering the second surface have openings, and the pad is disposed in the openings. In this way, the solder can be prevented from overflowing to the surface of the electrode (i.e., the surface metal of the chip), thereby preventing the cracking of the surface metal of the chip due to stress mismatch, and the reliability of the chip packaging structure can be improved when the chip is applied to a chip packaging structure; and the manufacturing difficulty and cost of the organic medium layer and the pad can be reduced.

[0009] Optionally, the pad includes: a plurality of welding layers stacked in a first direction, the first direction being the arrangement direction of the pad and the electrode; and the organic medium layer covering the side surface of at least part of the welding layers away from the substrate. In this way, the pad can be formed in layers to achieve a predetermined thickness, thereby enabling the welding of the chip to other structures.

[0010] Further, the welding layers are provided with at least three layers, and the area of each welding layer is in an increasing trend along a direction from the welding layers to the electrode; the organic medium layer comprises a plurality of organic film layers stacked along a first direction, and at least part of the organic film layers cover different welding layers. In this way, the manufacturing difficulty of each welding layer and each organic film layer can be reduced, the manufacturing efficiency is improved, and the manufacturing cost is reduced.

[0011] Further, the organic film layers are provided in the same number as the welding layers and are provided correspondingly, each organic film layer has an opening, and the welding layer is located in the opening of the corresponding organic film layer. In this way, when each organic film layer is manufactured, an opening is formed in the organic film layer, then the welding layer is formed in the opening, and then the next organic film layer is continuously manufactured, and the process of forming the opening and the welding layer is repeated, so that each time an organic film layer is formed, a corresponding welding layer can be formed, thereby reducing the manufacturing difficulty of the organic medium layer and the welding layer, and reducing the manufacturing cost.

[0012] Optionally, the chip further comprises an inorganic medium layer, at least part of the inorganic medium layer is arranged between the electrode and the organic medium layer, and the inorganic medium layer is connected with the pad. Compared with the organic medium layer, the inorganic medium layer is relatively hard and brittle, and is prone to small cracks at high temperature. Assuming that the solder enters the side of the pad through the gap between the pad and the organic medium layer, when the inorganic medium layer is connected with the pad, the solder will first contact the inorganic medium layer without directly contacting the electrode, at this time, the small cracks in the inorganic medium layer can accelerate the release of the stress of the solder, thereby avoiding causing the electrode to crack and improving the reliability of the chip.

[0013] Further, the inorganic medium layer extends to the interface (referred to as interface a) between the pad and the electrode. In this way, since the inorganic medium layer extends to the interface a, the area of the interface (referred to as interface b) between the second section and the pad is increased, even if the solder overflows to the side of the pad, the interface b provides a larger stress release space, so the degree of stress release can be effectively increased, thereby further improving the reliability of the chip.

[0014] Alternatively, the inorganic medium layer extends along the side surface of the pad into the second surface, which further increases the area of the interface b between the inorganic medium layer and the pad, thereby further increasing the degree of stress release. Moreover, the side surface of the inorganic medium layer located at the second surface towards the center of the second surface is the first side surface, and the organic medium layer wraps the first side surface. That is, when the inorganic medium layer covers part of the area of the second surface of the pad, the organic medium layer not only wraps the first side surface, but also covers part of the area of the second surface of the pad, so that both the organic medium layer and the inorganic medium layer are in contact with the second surface of the pad. Thus, when the solder overflows, it first contacts the connecting interface between the organic medium layer and the pad, and then enters the connecting interface between the inorganic medium layer and the pad. Therefore, the contact between the organic medium layer and the pad can effectively prevent the solder from overflowing to the connecting interface therebetween, and even if the solder overflows to the connecting interface, the stress of the solder can be released under the action of the inorganic medium layer, thereby avoiding electrode cracking through the dual action of the organic medium layer and the inorganic medium layer.

[0015] In a second aspect, the embodiments of the present application also provide a chip packaging structure, which can include: a chip and a bonding object, the chip being the chip as described in the first aspect and any one of the embodiments of the first aspect, and the chip being bonded to the bonding object through a solder column. Thus, since the organic medium layer in the chip covers part of the area of the second surface of the pad, the solder can be prevented from overflowing to the electrode surface, thereby avoiding electrode cracking caused by stress mismatch and improving the reliability of the chip packaging structure.

[0016] Optionally, the solder column is arranged on the second surface of the pad in the chip, and part of the solder column extends into the connecting interface between the organic medium layer and the second surface; the included angle between the contact interface of the solder column extending into the connecting interface and the organic medium layer and the first plane is a first included angle, and the first plane is parallel to the surface of the substrate; the included angle between the side surface of the solder column not extending into the connecting interface and the first plane is a second included angle, and the first included angle is smaller than the second included angle. This indicates that the distance of the solder column entering into the connecting interface between the organic medium layer and the second surface is small, and the organic medium layer plays a blocking role on the solder entering into the connecting interface between the organic medium layer and the second surface, thereby preventing the solder from overflowing to the electrode surface.

[0017] Further, the size of the first included angle reflects the distance of the solder column entering into the connecting interface between the organic medium layer and the second surface, and the smaller the distance, the smaller the first included angle. For example, but not limited to, when the first included angle is not greater than 50°, it indicates that the connection between the organic medium layer and the second surface of the pad is tighter, the blocking effect on the solder is better, and the inhibitory effect on the solder overflowing to the electrode surface is better.

[0018] It should be understood that since the principle of solving the problem by the chip packaging structure is similar to the principle of solving the problem by the chip, the implementation and technical effects of the chip packaging structure can be referred to the implementation and technical effects of the chip, and the repeated parts will not be described herein.

[0019] In a third aspect, the embodiments of the present application further provide an electronic device, which can include a shell and the chip packaging structure as described in the second aspect and any one of the embodiments of the second aspect, and the chip packaging structure is arranged in the shell. In this way, on the basis of improving the reliability of the chip packaging structure, the reliability of the electronic device is also improved.

[0020] It should be understood that since the principle of solving the problem by the electronic device is similar to the principle of solving the problem by the chip packaging structure, the implementation and technical effects of the electronic device can be referred to the implementation and technical effects of the chip packaging structure, and the repeated parts will not be described herein. BRIEF DESCRIPTION OF DRAWINGS

[0021] FIG. 1 is a structural schematic diagram of an electronic device provided by an embodiment of the present application;

[0022] FIG. 2 is a structural schematic diagram of a chip provided by an embodiment of the present application;

[0023] FIG. 3 is a top view of the positional relationship between a pad and an organic medium layer provided by an embodiment of the present application;

[0024] FIG. 4 is a structural schematic diagram of another chip provided by an embodiment of the present application;

[0025] FIG. 5 is a structural schematic diagram of still another chip provided by an embodiment of the present application;

[0026] FIG. 6 is a structural schematic diagram of yet another chip provided by an embodiment of the present application;

[0027] FIG. 7 is a structural schematic diagram of still another chip provided by an embodiment of the present application;

[0028] FIG. 8 is a structural schematic diagram of yet another chip provided by an embodiment of the present application;

[0029] FIG. 9 is a structural schematic diagram of still another chip provided by an embodiment of the present application;

[0030] FIG. 10 is a structural schematic diagram of yet another chip provided by an embodiment of the present application;

[0031] FIG. 11 is a structural schematic diagram of still another chip provided by an embodiment of the present application;

[0032] FIG. 12 is a structural schematic diagram of yet another chip provided by an embodiment of the present application;

[0033] FIG. 13 is a structural schematic diagram of still another chip provided by an embodiment of the present application;

[0034] Fig. 14 is a schematic diagram of another chip structure according to an embodiment of the present application;

[0035] Fig. 15 is a schematic diagram of another chip structure according to an embodiment of the present application;

[0036] Fig. 16 is a schematic diagram of another chip structure according to an embodiment of the present application;

[0037] Fig. 17 is a schematic diagram of another chip structure according to an embodiment of the present application;

[0038] Fig. 18 is a schematic diagram of another chip structure according to an embodiment of the present application;

[0039] Fig. 19 is a schematic diagram of another chip structure according to an embodiment of the present application;

[0040] Fig. 20 is a schematic diagram of a chip package structure according to an embodiment of the present application;

[0041] Fig. 21 is a flow chart of a manufacturing process of a chip according to an embodiment of the present application.

[0042] Fig. 21 is a flow chart of a manufacturing process of a chip according to an embodiment of the present application. DETAILED DESCRIPTION

[0043] In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the accompanying drawings.

[0044] It should be noted that the same reference signs in the drawings of the present application represent the same or similar structures, and thus repeated description thereof will be omitted. The expressions of position and direction described in the present application are described with reference to the drawings, but changes can also be made as needed, and the changes are included in the protection scope of the present application. The drawings of the present application are only used to show the relative position relationship and do not represent the real proportion.

[0045] For the convenience of understanding the technical solutions provided by the embodiments of the present application, the application scenarios thereof will be first described below.

[0046] The chip and the chip packaging structure provided by the embodiments of the present application can be widely applied in various electronic devices, for example, can be applied in electronic devices such as smart phones, smart televisions, smart television set-top boxes, personal computers (PCs), wearable devices, smart broadband, etc. It should be noted that the chip and the chip packaging structure proposed by the embodiments of the present application are intended to include but are not limited to being applied in these and any other suitable types of electronic devices. FIG. 1 exemplarily shows a structural schematic diagram of the chip packaging structure when applied in an electronic device. Referring to FIG. 1, the electronic device includes a shell 100 and a circuit board 200 arranged in the shell 100, and a chip packaging structure 300 is arranged on the circuit board 200. The circuit board 200 can be a printed circuit board (PCB), of course, the circuit board 200 can also be other types of circuit boards 200, which are not limited here.

[0047] Generally, the chip packaging structure generally integrates multiple chips on the same substrate through a redistribution layer, which can have higher packaging density and realize greater interconnection density. Exemplarily, the adjacent two chips arranged in a stack and the chip and the redistribution layer can be electrically connected through soldering, but in the reliability test, due to the stress mismatch between the solder and the surface metal of the chip, the surface metal of the chip is prone to cracking, which causes the electrical connection between the chip and other chips or the redistribution layer to fail, thereby reducing the reliability of the chip packaging structure.

[0048] Based on this, the embodiment of the present application provides a chip, which can comprise: a substrate; an electrode, which is arranged on the substrate; a pad, which is arranged on a first surface of the electrode away from the substrate, the pad covers part of the first surface; and an organic medium layer, which wraps the side surface of the pad and covers part of a second surface of the pad away from the electrode, so that there are more connection interfaces between the organic medium layer and the pad; because the adhesion of the organic medium layer is good, even if the pad is deformed under high temperature during welding or subsequent reliability testing, the organic medium layer can be well attached to the second surface and the side surface of the pad, avoiding the gap between the organic medium layer and the pad, and then avoiding the solder on the pad from entering the interface between the organic medium layer and the pad during welding; and even if the solder enters the connection interface, more connection interfaces can provide more buffer space, effectively avoiding the solder from overflowing to the surface of the electrode (i.e. the surface metal of the chip); in addition, more connection interfaces also help to release stress, thereby avoiding the cracking of the surface metal of the chip due to stress mismatch, and when the chip is applied to a chip packaging structure, the reliability of the chip packaging structure can be improved.

[0049] The chip packaging structure will be described below in combination with specific embodiments.

[0050] FIG. 2 exemplarily shows a structural schematic diagram of a chip provided by the present application, referring to FIG. 2, the chip can comprise: a substrate 10, an epitaxial layer 20, a first medium layer 40, an electrode 60, a second medium layer 51, a third medium layer 74 and a pad 80.

[0051] The substrate 10 can be made of semiconductor material, such as but not limited to heavily doped silicon carbide, heavily doped silicon, etc., and can be set according to actual needs, which is not limited here.

[0052] The epitaxial layer 20 can be made of a semiconductor material, such as but not limited to doped silicon carbide, doped silicon, etc., and can be set as required, which is not limited herein. The epitaxial layer 20 and the substrate 10 have the same doping type, such as both N-type doping or both P-type doping, but the doping concentration of the epitaxial layer 20 is different from that of the substrate 10. The doping concentration of the epitaxial layer 20 can be lower than that of the substrate 10. The epitaxial layer 20 and the substrate 10 can be formed by doping the same material to different degrees, or the epitaxial layer 20 and the substrate 10 can be formed by doping different materials to different degrees, which can be set as required, which is not limited herein. The epitaxial layer 20 is arranged on the substrate 10, and the epitaxial layer 20 is provided with a doped region 30. The doped region 30 is arranged on a side of the epitaxial layer 20 away from the substrate 10. The doped region 30 has a different doping type from the epitaxial layer 20. For example, when the epitaxial layer 20 is N-type doped, the doped region 30 is P-type doped, or when the epitaxial layer 20 is P-type doped, the doped region 30 is N-type doped. Thus, a PN junction can be formed between the doped region 30 and the epitaxial layer 20. It should be understood that the number, shape, and arrangement of the doped region 30 are not limited to those shown in FIG. 2, which are only used as an example for illustration. The number, shape, and arrangement of the doped region 30 can be set in any form as required, which is not limited herein.

[0053] The first dielectric layer 40 is arranged on a side surface of the epitaxial layer 20 away from the substrate 10, and the first dielectric layer 40 has a first hollow structure (not shown in FIG. 2). The first hollow structure can expose part of the doped region 30. The electrode 60 can be in contact with and connected to the doped region 30 through the first dielectric layer 40, and the epitaxial layer 20 and the electrode 60 are isolated, so that the electrode 60 can inject carriers into the doped region 30, thereby realizing the function of the chip. The first dielectric layer 40 can be made of an insulating material such as silicon oxide, silicon nitride, semi-insulating polysilicon, or an inorganic dielectric material containing nitrogen, carbon, oxygen, phosphorus, boron, etc. The thickness of the first dielectric layer 40 can be greater than 0.1 μm, and further, the thickness of the first dielectric layer 40 can be but not limited to 1 μm, which can be set as required, which is not limited herein.

[0054] Part of the electrode 60 is located on the doped region 30 exposed by the first hollow structure and connected with the doped region 30, and the other part of the electrode 60 is arranged on the first dielectric layer 40. The electrode 60 can include a bottom electrode 61 and a top electrode 62. The thickness of the bottom electrode 61 is small, for example, but not limited to, the thickness of the bottom electrode 61 is less than 1 μm, and further, the thickness of the bottom electrode 61 is 0.2 μm. The thickness of the top electrode 62 can be set to be larger, for example, but not limited to, the thickness of the top electrode 62 is greater than 1 μm, and further, the thickness of the top electrode 62 is 4 μm. Of course, the electrode 60 is not limited to a two-layer structure, but can also be a three-layer structure, a four-layer structure, etc., which can be set according to actual needs, which is not limited here. And no matter whether it is the bottom electrode 61 or the top electrode 62, the material used for manufacturing can include, but is not limited to, aluminum, copper, nickel, titanium, silver, gold and other good conductive metals and their oxides, so that the electrode 60 has good conductivity.

[0055] The second dielectric layer 51 has a second hollow structure (not shown in FIG. 2), which can expose part of the electrode 60. If the side surface of the electrode 60 facing away from the substrate 10 is referred to as the first surface b1, the second dielectric layer 51 covers the first dielectric layer 40, wraps the side surface of the electrode 60, and covers part of the first surface b1. It should be understood that the side surface of the electrode 60 refers to the surface connected with the first surface b1 and having a certain angle with the first surface b1. The second dielectric layer 51 can be made of inorganic insulating materials such as silicon oxide, silicon nitride, and semi-insulating polysilicon, or can be made of inorganic dielectric materials containing nitrogen, carbon, oxygen, phosphorus, boron, etc. Therefore, the second dielectric layer 51 can also be referred to as an inorganic dielectric layer 50. In the following content, the second dielectric layer 51 and the inorganic dielectric layer 50 refer to the same structure. And the thickness of the second dielectric layer 51 can be set to be greater than 0.1 μm, and further, the thickness of the second dielectric layer 51 can be, but not limited to, 1 μm, which can be set according to actual needs, which is not limited here.

[0056] The pad 80 is arranged on the part of the electrode 60 exposed by the second hollow structure, so that the pad 80 covers part of the first surface b1 of the electrode 60, and the pad 80 is connected with the electrode 60, wherein the pad 80 has a gap d1 between the second dielectric layer 51 covering the electrode 60, so that the second dielectric layer 51 and the pad 80 are arranged separately, and the specific value of the gap d1 can be set according to actual needs, which is not limited here. The pad 80 can be a single-layer structure, which can be made of any one of titanium, nickel, silver, palladium, gold and metal oxides. If the welding of the chip and other structures (such as chips, interlayers, rewiring layers or substrates, etc.) is to be realized, solder (not shown in FIG. 2) can be placed on the pad 80, and under the action of high temperature, the solder melts and fully contacts the pad 80, and after cooling, the pad 80 in the chip and other structures are fixed together, thereby realizing welding.

[0057] The third dielectric layer 74 is a single-layer structure, and the third dielectric layer 74 has a third hollow structure (not shown in FIG. 2), which can expose part of the pad 80, so that the third dielectric layer 74 covers the second dielectric layer 51, fills the gap between the second dielectric layer 51 and the pad 80, wraps the side surface of the pad 80, and covers part of the surface of the pad 80 away from the electrode 60. If the surface of the pad 80 away from the electrode 60 is referred to as the second surface b2, then the third dielectric layer 74 covers part of the second surface b2, so that the third dielectric layer 74 and the pad 80 have more connection interfaces. The third dielectric layer 74 can be made of an organic insulating material, such as but not limited to polyimide, photoresist, etc., so that the third dielectric layer 74 can also be referred to as an organic dielectric layer 70, and then the organic dielectric layer 70 covers part of the second surface b2 of the pad 80. In the following content, the third dielectric layer 74 and the organic dielectric layer 70 refer to the same structure. It should be understood that the side surface of the pad 80 refers to the surface connected with the second surface b2 and having a certain angle with the second surface b2.

[0058] Thus, since the organic medium layer 70 has good adhesion, even if the pad 80 deforms under high temperature during soldering or subsequent reliability testing, the organic medium layer 70 can be well attached to the second surface b2 and the side surface of the pad 80, avoiding the generation of gaps between the organic medium layer 70 and the pad 80, and thus avoiding the solder on the pad 80 from entering the connection interface between the organic medium layer 70 and the pad 80 during soldering. Even if the solder enters the connection interface, the more connection interfaces can provide more buffer space, effectively preventing the solder from overflowing onto the surface of the electrode 60 (i.e., the surface of the chip). In addition, the more connection interfaces also help to release stress, thereby avoiding the cracking of the surface of the chip due to stress mismatch. When this kind of chip is applied to a chip packaging structure, the reliability of the chip packaging structure can be improved.

[0059] For example, as shown in FIG. 3, the dashed box s1 in FIG. 3 represents the second surface b2 of the pad 80, and the organic medium layer 70 can cover the periphery of the second surface. In this way, the solder can be prevented from overflowing onto the surface of the electrode 60 from any position around the pad 80, thereby effectively preventing the cracking of the electrode 60. The length d2 of any edge of the second surface covered by the organic medium layer 70 along the normal direction thereof can be greater than 10 μm, and further, the d2 can be 40 μm, 60 μm, 80 μm, 100 μm, or other values. The specific value can be set according to actual needs, and is not specifically limited herein.

[0060] Referring back to FIG. 2, the chip can further include a back electrode 90 disposed on the side surface of the substrate 10 away from the epitaxial layer 20. In this case, the obtained chip can be a diode chip or a chip containing a diode and other devices. The back electrode 90 can be made of a metal or a metal oxide with good conductivity, such as but not limited to nickel, titanium, silver, gold, and metal oxides thereof. The specific material can be set according to actual needs, and is not specifically limited herein.

[0061] FIGS. 4-6 schematically show another structure of a chip provided by the present application. The chip in this embodiment is basically similar to the chip described in the above embodiments of FIGS. 2 and 3, and the difference is that the organic medium layer 70 is a multi-layer structure. For example, the organic medium layer 70 can include a plurality of organic film layers, and some of the organic film layers cover part of the second surface b2. The organic film layers that do not cover the second surface b2 have openings, and the pads 80 are arranged in the openings. For example, as shown in FIG. 4, the organic medium layer 70 includes a first organic film layer 71 and a second organic film layer 72, and the pads 80 are arranged in the first openings k1 of the first organic film layer 71, so that the first organic film layer 71 does not cover the second surface b2 of the pads 80. The depth h2 of the first openings k1 can be greater than the height h1 of the pads 80, or the depth h2 of the first openings k1 can be equal to the height h1 of the pads 80, which can be set according to actual needs, and is not limited herein. The second organic film layer 72 is arranged on the side surface of the first organic film layer 71 away from the substrate 10, and the second openings k2 (which can also be regarded as a hollow structure) in the second organic film layer 72 expose part of the second surface b2 of the pads 80, so that the second organic film layer 72 covers part of the second surface b2, and the connection interface between the second organic film layer 72 and the second surface b2 can avoid the solder from overflowing to the surface of the electrode 60 (i.e., the surface metal of the chip), thereby avoiding the cracking of the surface metal of the chip due to stress mismatch, and improving the reliability of the chip packaging structure when the chip is applied to the chip packaging structure.

[0062] For example, the organic medium layer 70 in FIGS. 4-6 is schematically shown as including two organic film layers, but this does not mean that the organic film layer is only provided with two layers, but can also be provided with three, four, five or more layers, which can be set according to actual needs, and is not limited herein. The following is described by way of example with two layers of organic film layers.

[0063] For example, the first opening k1 in the first organic film layer 71 can have an area equal to that of the second surface b2 of the pad 80, so that the pad 80 can be just accommodated in the first opening k1 of the first organic film layer 71, as shown in FIG. 4 and FIG. 5. Alternatively, the first opening k1 in the first organic film layer 71 can have an area greater than that of the second surface b2 of the pad 80, so that after the pad 80 is accommodated in the first opening k1 of the first organic film layer 71, there is still a remaining space in the first opening k1 of the first organic film layer 71, and thus there is a gap d3 between the pad 80 and the sidewall of the first opening k1 of the first organic film layer 71, and the gap d3 can be greater than 1 μm, and further, the gap d3 can be 10 μm, and in this case, the second organic film layer 72 can fill the gap d3 between the pad 80 and the sidewall of the first opening k1 of the first organic film layer 71, as shown in FIG. 6. In this way, when the chip is manufactured, the first organic film layer 71 can be formed first, then the pad 80 is formed, and then the second organic film layer 72 is formed, so that the manufacturing difficulty of the organic dielectric layer 70 and the pad 80 can be reduced, and the manufacturing cost can be reduced.

[0064] In addition, the second organic film layer 72 can have a large area, and can cover most or all of the side surface of the first organic film layer 71 away from the substrate 10, such as but not limited to as shown in FIG. 4. Alternatively, the second organic film layer 72 can have a small area, as shown in FIG. 5 and FIG. 6, and the second organic film layer 72 covers a small part of the side surface of the first organic film layer 71 away from the substrate 10, and as long as the second organic film layer 72 can cover the second surface b2 of the pad 80 and the gap between the pad 80 and the second organic film layer 72, the area of the region of the first organic film layer 71 covered by the second organic film layer 72 can be set according to actual needs, and is not specifically limited herein.

[0065] In addition, for the organic film layer covering the pad 80, an organic material having good adhesion to the pad 80 can be selected, such as polyimide, etc., so that the adhesion of the organic film layer to the second surface b2 of the pad 80 can be increased, and the solder can be more effectively prevented from overflowing to the surface of the electrode 60 (i.e., the surface metal of the chip); for the organic film layer not covering the pad 80, any organic material facilitating the formation of the film layer can be selected to meet the needs of different scenarios. Of course, for the film layer in the organic dielectric layer 70 not covering the pad 80, in addition to being made of an organic material, it can also be made of an inorganic material, so that the flexibility of chip design can be increased.

[0066] In this way, by arranging the film layers in the organic medium layer 70, not only can the adhesion of the organic medium layer 70 and the second surface b2 of the pad 80 be increased, but solder overflow to the surface of the electrode 60 (i.e., the surface of the metal layer of the chip) can be more effectively avoided, and the needs of different application scenarios can be met, and the flexibility of the design can be improved.

[0067] It should be understood that the similarities between the chip in this embodiment and the chip described in Embodiments 2 and 3 above can be understood with reference to the relevant descriptions in the above embodiments, and the repeated parts will not be described again.

[0068] FIGS. 7-13 schematically show another structure of a chip provided by the present application. As shown in FIGS. 7-13, the chip in this embodiment is basically similar to any one of the chips described in Embodiments 2-6 above, and the difference is that the pad 80 is a multilayer structure. For example, the pad 80 can include a plurality of solder layers (e.g., the structures denoted by 81, 82, and 83 in FIGS. 7-13) arranged in a first direction, the first direction being the arrangement direction of the pad 80 and the electrode 60, i.e., the z direction in FIG. 7; and the organic medium layer 70 covers at least part of the side surface of the solder layers away from the substrate 10. In this way, the pad 80 can be formed in layers so that the pad 80 can reach a predetermined thickness, thereby achieving soldering of the chip with other structures.

[0069] In FIGS. 7-13, the solder layers are shown as having three layers, but in actual situations, the number of layers of the solder layers is not limited to three, and can be two, four, five, or other numbers, which can be set according to actual needs, and will not be limited here. The following is described by way of example with the solder layers having three layers, and for ease of description, the side surface of each solder layer away from the substrate 10 is referred to as the top surface of the solder layer.

[0070] Exemplarily, the top surface area of each solder layer can be set to be the same. Alternatively, when the solder layers are provided with at least three layers, the area of each solder layer increases along a direction from the solder layer to the electrode 60, and the increasing trend can include layer-by-layer increasing or stepwise increasing. For example, taking the top surface area of the solder layer as an example, if the solder layer farthest from the substrate 10 is referred to as a top solder layer 83, the solder layer closest to the substrate 10 is referred to as a bottom solder layer 81, and the solder layer between the bottom solder layer 81 and the top solder layer 83 is referred to as a middle solder layer 82, as shown in FIG. 8, the top surface area of the top solder layer 83 and the middle solder layer 82 can be the same, and the top surface area of the bottom solder layer 81 can be greater than that of the middle solder layer 82, so that the area of the three solder layers increases stepwise. Alternatively, as shown in FIG. 9, the top surface area of the bottom solder layer 81 is equal to that of the middle solder layer 82, and the top surface area of the top solder layer 83 is less than that of the middle solder layer 82, so that the area of the three solder layers increases stepwise. Alternatively, as shown in FIG. 13, the top surface area of the top solder layer 83 can be less than that of the middle solder layer 82, and the top surface area of the middle solder layer 82 can be less than that of the bottom solder layer 81, so that the area of the three solder layers increases layer by layer.

[0071] Based on this, when the organic medium layer 70 is a single-layer structure, the following cases can be included:

[0072] The organic medium layer 70 can cover part of the top surface of the top solder layer 83 and wrap the side surface of each solder layer, as shown in FIG. 7. At this time, the top surface area of each solder layer can be set to be the same, which can simplify the manufacturing process of each solder layer and improve the manufacturing efficiency of the chip. Alternatively, the top surface area of at least part of the solder layers is different, and the area of each solder layer increases, which can increase the flexibility of the solder pad 80 and meet the needs of different application scenarios.

[0073] Alternatively, the organic medium layer 70 can cover part of the top surface of the bottom solder layer 81 and wrap the side surface of each solder layer, as shown in FIG. 8. At this time, the top surface area of the bottom solder layer 81 can be greater than that of the other solder layers, and the area of each solder layer increases, which can reduce the size of the other solder layers and reduce the manufacturing cost.

[0074] Alternatively, the organic medium layer 70 can cover part of the top surface of the middle solder layer 82 and wrap the side surface of each solder layer, as shown in FIG. 9. In this case, the top surface area of the bottom solder layer 81 and the middle solder layer 82 can be set to be the same, and greater than the top surface area of the other solder layers. The area of each solder layer increases in a trend. It should be understood that the other solder layers in this paragraph refer to the solder layers on the side of the middle solder layer 82 away from the substrate 10 that are covered. In this way, the size of the other solder layers can be reduced, and the manufacturing cost can be reduced.

[0075] When the organic medium layer 70 is a multi-layer structure and includes a plurality of organic film layers, the following configurations can be included. Some of the organic film layers (such as the structure indicated by 71 in FIG. 10) do not cover the top surface of any solder layer, and some of the organic film layers (such as the structure indicated by 72 in FIG. 10) cover the top surface of the bottom solder layer 81, as shown in FIG. 10. Alternatively, some of the organic film layers (such as the structure indicated by 71 in FIG. 11) do not cover the top surface of any solder layer, and some of the organic film layers (such as the structure indicated by 72 in FIG. 11) cover the top surface of the middle solder layer 82, as shown in FIG. 11. Alternatively, some of the organic film layers (such as the structure indicated by 71 in FIG. 12) do not cover the top surface of any solder layer, some of the organic film layers (such as the structure indicated by 72 in FIG. 12) cover the top surface of the bottom solder layer 81, and some of the organic film layers (such as the structure indicated by 73 in FIG. 12) cover the top surface of the middle solder layer 82, so that some of the organic film layers cover different solder layers, as shown in FIG. 12. Alternatively, some of the organic film layers (such as the structure indicated by 71 in FIG. 13) cover the top surface of the bottom solder layer 81, and some of the organic film layers (such as the structure indicated by 72 in FIG. 13) cover the top surface of the middle solder layer 82, so that each organic film layer covers a different solder layer, as shown in FIG. 13. The covering relationship between each organic film layer and each solder layer can be set as needed, and is not limited herein. In this way, the manufacturing difficulty of each solder layer and each organic film layer can be reduced, the manufacturing efficiency can be improved, and the manufacturing cost can be reduced.

[0076] When the number of organic film layers is the same as the number of solder layers and is set correspondingly, each organic film layer has an opening, and the solder layer is located in the opening of the corresponding organic film layer, for example, as shown in FIG. 12. In this way, when each organic film layer is manufactured, an opening can be formed in the organic film layer. Then, the solder layer can be formed in the opening. Next, the next organic film layer can be continuously manufactured, and the process of forming the opening and forming the solder layer can be repeated. In this way, when each organic film layer is formed, the corresponding solder layer can be formed. Therefore, the manufacturing difficulty of the organic medium layer 70 and the solder layer can be reduced, and the manufacturing cost can be reduced.

[0077] It should be understood that the chip in this embodiment is similar to the chip in the above-mentioned embodiments 2-6 in structure, and the relevant description is referred to the above-mentioned embodiments, and the repeated description is omitted.

[0078] FIGS. 14-16 schematically show another structure of a chip provided by the present application. Referring to FIGS. 14-16, the chip in this embodiment is similar to any one of the chips in the above-mentioned embodiments 2-13 in structure, and the difference is that at least part of the inorganic dielectric layer 50 is arranged between the electrode 60 and the organic dielectric layer 70, and the inorganic dielectric layer 50 is connected to the pad 80. For example, the inorganic dielectric layer 50 can include a first section m1 and a second section m2 connected to each other, the first section m1 is arranged between the organic dielectric layer 70 and the substrate 10, and further, the first section m1 is arranged between the first dielectric layer 40 and the organic dielectric layer 70; the second section m2 is arranged between the electrode 60 and the organic dielectric layer 70, and the second section m2 wraps the side surface of the electrode 60 and covers part of the first surface b1 of the electrode 60. Compared with the organic dielectric layer 70, the inorganic dielectric layer 50 is relatively hard and brittle, and thus small cracks are prone to occur at high temperature. Assuming that the solder enters the side surface of the pad 80 through the gap between the pad 80 and the organic dielectric layer 70, when the second section m2 is connected to the pad 80, the solder will first contact the inorganic dielectric layer 50 without directly contacting the electrode 60, and at this time, the small cracks in the inorganic dielectric layer 50 can accelerate the release of the stress of the solder, thereby avoiding the cracking of the electrode 60 and improving the reliability of the chip.

[0079] Exemplarily, when the second section m2 is connected with the pad 80, the specific arrangement mode can include: as shown in FIG. 14, the side surface of the second section m2 in the inorganic medium layer 50 is in contact with and connected with the side surface of the pad 80; or as shown in FIG. 15, the second section m2 in the inorganic medium layer 50 extends to the interface (referred to as interface a for short) between the pad 80 and the electrode 60, and the distance d4 of the second section m2 deep into the interface a can be but is not limited to 1 μm-5 μm, and can be specifically arranged according to actual needs, and the distance d4 of the second section m2 deep into the interface a is not limited herein. Since the second section m2 extends into the interface a, the area of the interface (referred to as interface b for short) between the second section m2 and the pad 80 is increased, so that even if the solder overflows to the side surface of the pad 80, the interface b provides a larger stress release space, so that the degree of stress release can be effectively increased, thereby further improving the reliability of the chip. Alternatively, as shown in FIG. 16, the inorganic medium layer 50 can further include a third section m3, the second section m2 is connected between the first section m1 and the third section m3, and the third section m3 is arranged between the organic medium layer 70 and the pad 80, so that the third section m3 covers part of the second surface b2 of the pad 80, and the third section m3 extends into the second surface b2 along the side surface of the pad 80, thereby further increasing the area of the interface b between the inorganic medium layer 50 and the pad 80, thereby further increasing the degree of stress release.

[0080] Continuing as shown in FIG. 16, the side surface of the inorganic medium layer 50 located at the second surface b2 towards the center of the second surface b2 is a first side surface b3, and the organic medium layer 70 wraps the first side surface b3. That is, when the third section m3 in the inorganic medium layer 50 covers part of the second surface b2 of the pad 80, the organic medium layer 70 not only covers the third section m3, but also covers part of the second surface b2 of the pad 80, so that the organic medium layer 70 and the third section m3 will both be in contact with the second surface b2 of the pad 80. In this way, when the solder overflows, it first contacts the connection interface between the organic medium layer 70 and the pad 80, and then enters the connection interface between the third section m3 and the pad 80, so that the contact between the organic medium layer 70 and the pad 80 can effectively prevent the solder from overflowing to the connection interface therebetween. Even if it overflows to the connection interface, the stress of the solder will be released under the action of the inorganic medium layer 50, thereby avoiding cracking of the electrode 60 through the dual action of the organic medium layer 70 and the inorganic medium layer 50.

[0081] It should be understood that the chip in this embodiment has similar structures to the chip described in the above embodiments of FIGS. 2-13, and the relevant descriptions can be referred to the above embodiments, and the repeated descriptions will not be repeated.

[0082] FIGS. 17-19 schematically show another chip structure provided by the present application. The chip in this embodiment is similar to any of the chips described in the above embodiments of FIGS. 14-16, except that the inorganic dielectric layer 50 only includes the first section m1. For example, the first section m1 can have a gap with the electrode 60, as shown in FIG. 17; or the first section m1 can contact and connect with the side surface of the electrode 60, as shown in FIG. 18; or the first section m1 can extend into the interface between the electrode 60 and the first dielectric layer 40, as shown in FIG. 19. In this way, the position of the first section m1 can be set according to actual needs to meet the needs of different application scenarios, improving the flexibility of the design.

[0083] It should be understood that the chip in this embodiment is similar to the chip described in the above embodiments of FIGS. 14-16, and the similarities can be referred to the above embodiments. The repeated parts will not be described again.

[0084] FIG. 20 schematically shows a chip packaging structure provided by the present application. The chip packaging structure can include a chip 110 and a bonding object 120. The chip 110 can be any of the chips 110 described in the above embodiments of FIGS. 2-16. The chip 110 is bonded to the bonding object 120 through a solder column 130. The bonding object 120 can include, but is not limited to, a chip 110, a redistribution layer, an interposer, a board, or a substrate, which can be set according to actual needs and will not be limited here. In this way, since the organic dielectric layer 70 in the chip 110 covers part of the second surface b2 of the pad 80, the solder can be prevented from overflowing onto the surface of the electrode 60, thereby avoiding cracking of the electrode 60 due to stress mismatch and improving the reliability of the chip packaging structure.

[0085] During the welding of the chip 110 and the bonding object 120, the solder is first melted and then cooled to form the solder column 130, thereby realizing the welding of the chip 110 and the bonding object 120. Since the solder flows when it is in a molten state, the solder can enter the connection interface between the organic dielectric layer 70 and the pad 80. After cooling, the molten solder becomes solid, so the solder that enters the connection interface between the organic dielectric layer 70 and the second surface b2 of the pad 80 becomes part of the solder column 130, so part of the solder column 130 extends into the connection interface between the organic dielectric layer 70 and the second surface b2. However, since the organic dielectric layer 70 has good adhesion, even if the solder in the molten state enters the connection interface between the organic dielectric layer 70 and the second surface b2 of the pad 80, the distance entered by the solder will be small when the connection between the organic dielectric layer 70 and the second surface b2 of the pad 80 is tight, so the distance entered by the solder column 130 will be small, which can prevent the solder from overflowing onto the surface of the electrode 60, thereby improving the reliability of the chip packaging structure.

[0086] If the contact interface between the solder column 130 extending into the organic medium layer 70 and the first plane is a first angle w1, the first plane is parallel to the surface of the substrate, and the contact interface between the side of the solder column 130 not extending into the first plane and the first plane is a second angle w2, the first angle w1 is smaller than the second angle w2, which means that the distance of the solder column 130 entering the contact interface between the organic medium layer 70 and the second surface b2 is small, which can effectively prevent the solder from overflowing to the surface of the electrode 60.

[0087] In addition, the size of the first angle w1 reflects the distance of the solder column 130 entering the contact interface between the organic medium layer 70 and the second surface b2. The smaller the distance, the smaller the first angle w1. For example, but not limited to, when the first angle w1 is not greater than 50°, it means that the organic medium layer 70 is more closely connected to the second surface b2 of the pad 80, and the barrier effect of the solder is better, which means that the inhibition effect of the solder overflowing to the surface of the electrode 60 is better.

[0088] It should be understood that the chip in this embodiment has similar structures to the chip described in the above embodiments of FIGS. 2 to 16. For details, please refer to the above description. The repeated parts will not be described again.

[0089] FIG. 21 exemplarily shows a schematic diagram of a manufacturing process of a chip provided by the present application. Referring to FIG. 21, the manufacturing process can include:

[0090] S101, forming an epitaxial layer on a substrate;

[0091] S102, forming a doped region in the epitaxial layer;

[0092] S103, forming a first dielectric layer on the epitaxial layer, and the first dielectric layer has a first hollow structure, and the first hollow structure exposes part of the doped region;

[0093] S104, forming an electrode on the exposed doped region;

[0094] S105, forming an inorganic medium layer, and the inorganic medium layer has a second hollow structure, and the second hollow structure exposes part of the first surface of the electrode;

[0095] S106, forming a pad and an organic medium layer, the pad is arranged on the exposed electrode, and the organic medium layer has a third hollow structure, and the third hollow structure exposes part of the second surface of the pad.

[0096] Exemplarily, the specific implementation of S106 can include the following ways:

[0097] The first mode: when the organic medium layer is a single layer structure, first, a conductive film layer is deposited on the structure obtained in S105, then an etching process is used to etch the conductive film layer, the conductive film layer above the electrode is reserved, and the conductive film layer at other positions is etched away, thereby forming the pad; then the organic layer is deposited, and then the organic layer is etched to etch a third hollow structure in the organic layer, and the third hollow structure exposes part of the area in the second surface of the pad, thereby forming the organic medium layer.

[0098] The second mode: when the organic medium layer includes multiple organic film layers, and part of the organic film layers do not cover the second surface of the pad, taking an example that the organic film layers are two, and are denoted as a first organic film layer and a second organic film layer, first, the first organic layer is deposited on the structure obtained in S105, and the first organic layer is etched to etch a first opening, the first opening exposes part of the area in the first surface of the electrode, thereby obtaining the first organic film layer; then the conductive film layer is deposited, and then an etching process is used to etch the conductive film layer, the conductive film layer in the first opening is reserved, and the conductive film layer at other positions is etched away, thereby forming the pad in the first opening, and the pad is connected with the electrode; then, the second organic layer is deposited, and the second organic layer is etched to etch a second opening, the second opening exposes part of the area in the second surface of the pad, thereby forming the second organic film layer, and the first organic film layer and the second organic film layer constitute the organic medium layer.

[0099] The third mode: when the organic medium layer includes multiple organic film layers, and the pad includes multiple welding layers, if part of the organic film layers do not cover the top layer of any welding layer, then similar to the second mode, the organic film layer not covering the top layer of any welding layer is formed first, and then the welding layer and other organic film layers are formed; if each organic film layer covers the welding layer, then the welding layer is formed first, and then the corresponding organic film layer is formed, so that the organic film layer can cover the top layer of the corresponding welding layer.

[0100] Of course, in addition to the above-mentioned three modes, other modes capable of manufacturing the pad and the organic medium layer can also be used, and specific designs can be made according to actual needs, which are not limited here.

[0101] Obviously, those skilled in the art can make various modifications and variations to the embodiments of the present application without departing from the spirit and scope of the embodiments of the present application. Thus, if these modifications and variations of the embodiments of the present application fall within the scope of the claims of the present application and the equivalent technology thereof, the present application also intends to include these modifications and variations.

Claims

1. A chip, characterized by The chip comprises: a substrate; an electrode disposed on the substrate; a pad disposed on a first surface of the electrode away from the substrate, the pad covering a partial area in the first surface; and an organic medium layer wrapping a side surface of the pad and covering a partial area in a second surface of the pad away from the electrode.

2. The chip of claim 1, wherein, The organic medium layer covers a periphery of the second surface.

3. The chip according to claim 1 or 2, wherein The organic medium layer comprises a plurality of organic film layers, and a partial of the organic film layers cover a partial area in the second surface; The organic film layers not covering the second surface have openings, and the pad is disposed in the openings.

4. The chip of any one of claims 1-3, wherein, The pad comprises a plurality of pad layers stacked along a first direction, the first direction being a direction of arrangement of the pad and the electrode; The organic medium layer covers a side surface of at least a partial of the pad layers away from the substrate.

5. The chip of claim 4, wherein, The pad layers are disposed in at least three layers, and an area of each of the pad layers increases along a direction from the pad layer to the electrode; The organic medium layer comprises a plurality of organic film layers stacked along the first direction, and at least a partial of the organic film layers cover different pad layers.

6. The chip of claim 5, wherein, The organic film layers are disposed in a same number as the pad layers and correspondingly, and each of the organic film layers has an opening, and the pad layer is disposed in the opening corresponding to the organic film layer.

7. The chip of any one of claims 1-6, wherein, The chip further comprises an inorganic medium layer, and at least a partial of the inorganic medium layer is disposed between the electrode and the organic medium layer, and the inorganic medium layer is connected with the pad.

8. The chip of claim 7, wherein, The inorganic medium layer extends to an interface between the pad and the electrode.

9. The chip of claim 7, wherein, The inorganic medium layer extends to the second surface along a side surface of the pad.

10. The chip of claim 9, wherein, A side surface of the inorganic medium layer at a center of the second surface is a first side surface, and the organic medium layer wraps the first side surface.

11. A chip package structure, comprising: The chip comprises: a chip and a bonding object, the chip being the chip as claimed in any one of claims 1-10, and the chip is bonded with the bonding object through a solder column.

12. The chip package structure of claim 11, wherein, The solder column is disposed on a second surface of the pad in the chip, and a partial of the solder column extends to a connecting interface between the organic medium layer and the second surface; An included angle between a contact interface of the solder column extending to the connecting interface and a first plane is a first included angle, and the first plane is parallel to a surface of the substrate; An included angle between a side surface of the solder column not extending to the connecting interface and the first plane is a second included angle, and the first included angle is smaller than the second included angle.

13. The chip package structure of claim 12, wherein, The first included angle is not greater than 50°.

14. An electronic device, comprising: The chip package structure comprises: a housing, and the chip package structure as claimed in any one of claims 11-13 is disposed in the housing.

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