Transistor device and preparation method therefor, and display substrate

Abstract

A transistor device and a preparation method therefor, and a display substrate. The transistor device is arranged on a base (100). The transistor device comprises a gate electrode (201), a gate insulating layer (300), an active layer (202), a first electrode (203) and a second electrode (204), wherein the first electrode (203) and the second electrode (204) are arranged on the side of the active layer (202) and the gate electrode (201) away from the base (100), and the gate insulating layer (300) is arranged between the active layer (202) and the gate electrode (201). The gate insulating layer (300) comprises a first insulating layer (301) and a second insulating layer (302) that are stacked on the base, wherein one of the first insulating layer (301) and the second insulating layer (302) is provided with a via hole (VV), and the orthographic projection of the via hole (VV) on the base (100) at least partially overlaps with the orthographic projection of the active layer (202) on the base (100).

Description

Transistor devices and their fabrication methods, display substrates

[0001] This application claims priority to PCT International Application No. PCT / CN2024 / 108632, filed on July 30, 2024, entitled "Display Substrate and Method for Fabrication Thereof", and to Chinese Patent Application No. 202511038242.4, filed on July 25, 2025, entitled "Transistor Device and Method for Fabrication Thereof, Display Substrate", the contents of which shall be construed as incorporated herein by reference. Technical Field

[0002] This disclosure relates to, but is not limited to, the field of display technology, specifically to a transistor device and its fabrication method, and a display substrate. Background Technology

[0003] In recent years, thin-film transistor (TFT) flat panel displays have been widely used in various fields of social production and daily life, including watches, mobile phones, tablets, desktop computers, automotive displays, industrial IoT displays, and televisions. With the expansion of flat panel display applications, display technologies with excellent image quality, high smoothness, high touch performance, high refresh rate, and high touch frequency have become the cutting edge in the display industry. Summary of the Invention

[0004] The following is an overview of the subject matter described in detail in this disclosure. This overview is not intended to limit the scope of the claims.

[0005] This disclosure provides a transistor device, a method for fabricating the same, and a display substrate.

[0006] In a first aspect, this disclosure provides a transistor device disposed on a substrate. The transistor device includes: a gate electrode, a gate insulating layer, an active layer, a first electrode, and a second electrode. The first electrode and the second electrode are disposed on the side of the active layer and the gate electrode away from the substrate, and the gate insulating layer is disposed between the active layer and the gate electrode.

[0007] The gate insulating layer includes: a first insulating layer and a second insulating layer stacked on the substrate, wherein one of the first insulating layer and the second insulating layer is provided with a via;

[0008] The orthographic projection of the via on the substrate at least partially overlaps with the orthographic projection of the active layer on the substrate.

[0009] Secondly, this disclosure also provides a display substrate, including: a plurality of the above-described transistor devices.

[0010] Thirdly, this disclosure also provides a method for fabricating a transistor device, configured to fabricate the aforementioned transistor device, the method comprising:

[0011] The gate electrode of a transistor device is formed on the substrate;

[0012] A gate insulating layer and an active layer of a transistor device are formed on the gate electrode. The gate insulating layer includes a first insulating layer and a second insulating layer stacked on the substrate. One of the first insulating layer and the second insulating layer is provided with a via. The orthographic projection of the via on the substrate at least partially overlaps with the orthographic projection of the active layer on the substrate.

[0013] A first electrode and a second electrode are formed on the active layer;

[0014] The formation of the gate insulating layer and active layer of the transistor device on the gate electrode includes:

[0015] A first insulating layer is formed on the gate electrode, and the first insulating layer has a via.

[0016] A second insulating layer is formed from the first insulating layer;

[0017] A primary semiconductor layer is formed on the second insulating layer, the primary semiconductor layer comprising: a first active layer and a third active layer;

[0018] A first electrode, a second electrode, and an active layer are formed on the original semiconductor layer. The active layer includes a first active layer and a second active layer.

[0019] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood.

[0020] Overview of the attached figures

[0021] The accompanying drawings are used to provide an understanding of the technical solutions of this application and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of this application and do not constitute a limitation on the technical solutions of this application.

[0022] Figure 1 is a schematic diagram of the structure of a display substrate provided in an embodiment of this disclosure;

[0023] Figure 2 is a schematic diagram of the structure of some of the membrane layers provided in Figure 1;

[0024] Figure 3 is a schematic diagram of the structure of the display substrate provided in an embodiment of this disclosure;

[0025] Figure 4 is a schematic diagram of the structure of some of the membrane layers provided in Figure 3;

[0026] Figure 5 is a top view of the transistor device shown in Figures 1 and 3;

[0027] Figure 6 is a curve showing the relationship between the gate insulation layer thickness and the Ion normalization coefficient;

[0028] Figure 7 shows the curves of the voltage Vg of the gate electrode and the current Id flowing through the source electrode under different gate insulation layer thicknesses.

[0029] Figure 8 is a top view of a transistor device;

[0030] Figure 9 is a cross-sectional view along direction AA in Figure 8;

[0031] Figure 10 is a cross-sectional view along the BB direction of Figure 8;

[0032] Figure 11 is a schematic diagram of a display substrate structure;

[0033] Figure 12 is another schematic diagram of the display substrate structure;

[0034] Figure 13 is a schematic diagram after the gate electrode is formed in Figure 11;

[0035] Figure 14 is a schematic diagram after the grid insulating layer is formed in Figure 11;

[0036] Figure 15 is a schematic diagram after the formation of the original semiconductor layer in Figure 11;

[0037] Figure 16 is a schematic diagram after the first and second electrodes in Figure 11 are formed;

[0038] Figure 17 is a schematic diagram after the passivation layer is formed in Figure 11;

[0039] Figure 18 is a schematic diagram after the gate insulating layer is formed in Figure 12;

[0040] Figure 19 is a schematic diagram after the original semiconductor layer in Figure 12 has been formed;

[0041] Figure 20 is a schematic diagram after the first and second electrodes in Figure 12 are formed;

[0042] Figure 21 is a schematic diagram of the passivation layer formed in Figure 12;

[0043] Figure 22A is a cross-sectional schematic diagram of a transistor device provided in an embodiment of this disclosure;

[0044] Figure 22B is a partial cross-sectional view of Figure 22A;

[0045] Figures 23a to 23e are schematic diagrams of forming the transistor device provided in Figure 22A;

[0046] Figure 24 is a top view of a transistor device;

[0047] Figure 25 is a top view of a transistor device (II).

[0048] Figure 26 is a top view of a transistor device;

[0049] Figure 27 is a top view of a transistor device;

[0050] Figure 28 is a top view of a transistor device;

[0051] Figure 29 is a top view of a transistor device.

[0052] Figure 30 is a top view of a transistor device;

[0053] Figure 31 is a top view of a transistor device.

[0054] Figure 32 is a top view of a transistor device (nine).

[0055] Figure 33 is a top view of a transistor device;

[0056] Figure 34 is a top view of a transistor device;

[0057] Figure 35 is a top view of a transistor device, number twelve.

[0058] Figure 36 is a top view of a transistor device.

[0059] Figure 37 is a top view of a transistor device, number fourteen.

[0060] Figure 38 is a top view of a transistor device, number fifteen.

[0061] Figure 39 is a top view of a transistor device, number sixteen.

[0062] Figure 40 is a top view of a transistor device.

[0063] Figure 41 is a top view of a transistor device.

[0064] Figure 42 is a top view of a transistor device.

[0065] Figure 43 is a top view of a transistor device.

[0066] Figure 44 is a top view of a transistor device.

[0067] Figure 45 is a top view of a transistor device, number twenty-two.

[0068] Figure 46 is a top view of a transistor device (23).

[0069] Figure 47 is a top view of a transistor device (24).

[0070] Figure 48 is a top view of a transistor device, number twenty-five.

[0071] Figure 49 is a top view of a transistor device.

[0072] Figure 50 is a top view of a transistor device.

[0073] Figure 51 is a top view of a transistor device, number twenty-eight.

[0074] Figure 52 is a top view of a transistor device, number twenty-nine.

[0075] Figure 53 is a top view of a transistor device.

[0076] Figure 54 is a top view of a transistor device.

[0077] Figure 55 is a top view of another transistor device;

[0078] Figure 56 is a schematic diagram of the structure of the display substrate provided in an embodiment of this disclosure;

[0079] Figure 57 is a partial connection diagram of the display substrate provided in Figure 56;

[0080] Figure 58 is the equivalent circuit diagram of at least one shift register;

[0081] Figure 59 is a schematic diagram of the structure of the shift register provided in an embodiment of this disclosure;

[0082] Figure 60 is a top view of the photosensitive switch device;

[0083] Figure 61 is a top view of the photosensitive switch device (II).

[0084] Figure 62 is a schematic diagram of the structure of some switching devices located on the data side;

[0085] Figure 63 is a schematic diagram of the structure of some switching devices located on the non-data side;

[0086] Figure 64 is a schematic diagram of some of the switching devices in the electrostatic discharge circuit;

[0087] Figure 65 is a schematic flowchart of the method for fabricating a transistor device provided in an embodiment of this disclosure.

[0088] Detailed Explanation

[0089] To make the objectives, technical solutions, and advantages of this disclosure clearer, the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. Note that the implementation methods can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be transformed into various forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the content described in the following embodiments. Without conflict, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other. To keep the following description of the embodiments of this disclosure clear and concise, detailed descriptions of some known functions and components have been omitted. The accompanying drawings of the embodiments of this disclosure only relate to the structures involved in the embodiments of this disclosure; other structures can be referred to in general design.

[0090] The scale of the figures in this disclosure can be used as a reference in actual manufacturing processes, but is not limited thereto. For example, the aspect ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the quantities shown in the figures. The figures described in this disclosure are only schematic diagrams of the structure, and one aspect of this disclosure is not limited to the shapes or values ​​shown in the figures.

[0091] The ordinal numbers “first,” “second,” and “third” used in this specification are used to avoid confusion among the constituent elements, not to limit their quantity.

[0092] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the orientation of each constituent element being described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0093] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they may refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the specific meaning of these terms in this disclosure based on the specific circumstances.

[0094] In this specification, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0095] In this specification, the first electrode can be the drain electrode and the second electrode can be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or the current direction changes during circuit operation, the functions of the "source electrode" and "drain electrode" may sometimes be interchanged. Therefore, in this specification, the "source electrode" and "drain electrode" can be interchanged.

[0096] In this specification, "electrical connection" includes the situation where components are connected together by elements that have a certain electrical function. There are no particular limitations on what constitutes an "electrical function," as long as it allows for the transmission and reception of electrical signals between the connected components. Examples of "electrical functions" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions.

[0097] In this specification, "parallel" refers to the state where the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore also includes the state where the angle is greater than or equal to -5° and less than 5°. Similarly, "perpendicular" refers to the state where the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore also includes the state where the angle is greater than or equal to 85° and less than 95°.

[0098] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may sometimes be replaced with "conductive film." Similarly, "insulating film" may sometimes be replaced with "insulating layer."

[0099] In this specification, the term "same-layer arrangement" refers to a structure formed by patterning two (or more) structures through the same patterning process, and their materials may be the same or different. For example, the precursors forming multiple structures in a same-layer arrangement may be made of the same material, while the final materials may be the same or different.

[0100] In this specification, triangles, rectangles, trapezoids, pentagons, or hexagons are not strictly defined; they can be approximate triangles, rectangles, trapezoids, pentagons, or hexagons. Small deformations due to tolerances are possible, as are chamfers, curved edges, and other variations.

[0101] Due to the limitations of transistors' semiconductor characteristics, namely the limitation of carrier mobility, it is difficult to further increase the turn-on current of transistors, thus limiting the improvement of the refresh rate of display products.

[0102] Therefore, this disclosure provides a transistor device.

[0103] Figure 1 is a schematic diagram of the structure of a display substrate provided in an embodiment of this disclosure; Figure 2 is a schematic diagram of the structure of a portion of the film layer provided in Figure 1; Figure 3 is a schematic diagram of the structure of a display substrate provided in an embodiment of this disclosure; and Figure 4 is a schematic diagram of the structure of a portion of the film layer provided in Figure 3. As shown in Figures 1 to 4, the display substrate provided in an embodiment of this disclosure may include: a substrate and a transistor device disposed on the substrate. The transistor device may include: a gate electrode 11, a gate insulating layer 21, and an active layer 12 sequentially stacked on the substrate 10. In Figures 1 to 4, the second direction Y is the direction in which the gate electrode, the gate insulating layer, and the active layer are stacked, and the first direction X may be the extension direction of the active layer. The first direction X intersects with the second direction Y.

[0104] As shown in Figures 1 to 4, a groove structure 1 is provided on the side of the gate insulating layer 21 away from the substrate 10. At least a portion of the active layer 12 is disposed within the groove structure 1, and at least two boundaries of the active layer 12 have a predetermined distance from the corresponding boundaries of the groove structure. That is, the orthographic projection of the active layer 12 on the substrate 10 in this disclosure is within the range of the orthographic projection of the groove structure 1 on the substrate 10, and the entire width of the longitudinal section of the active layer 12 falls within the groove structure 1.

[0105] In an exemplary embodiment, the substrate 10 may be a rigid substrate or a flexible substrate. The rigid substrate may be, but is not limited to, one or more of glass and conductive foil. The flexible substrate may be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers.

[0106] In an exemplary embodiment, the transistor device in this disclosure has a bottom-gate structure.

[0107] In an exemplary embodiment, the gate electrode 11 can be made of a metallic material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or an alloy of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). It can be a single-layer structure or a multi-layer composite structure, such as Mo / Cu / Mo. Exemplarily, the gate electrode can be made of Al / Mo or MoNb / Cu.

[0108] In an exemplary embodiment, the gate insulating layer 21 may be any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer, multiple layers, or a composite layer.

[0109] In an exemplary embodiment, the active layer material may comprise one or more of amorphous silicon (a-Si) and low-temperature polycrystalline silicon (LTPS) metal oxides. The metal oxide layer may be an oxide containing indium and tin, an oxide containing tungsten and indium, an oxide containing tungsten, indium, and zinc, an oxide containing titanium and indium, an oxide containing titanium, indium, and tin, an oxide containing indium and zinc, an oxide containing silicon, indium, and tin, or an oxide containing indium or gallium and zinc.

[0110] In some embodiments, the active layer material can be M1OaNb, where M1 is a single metal or a combination of multiple metals, a > 0 and b ≥ 0, O represents oxygen, and N represents nitrogen. That is, the active layer material is a metal oxide material or a metal nitride material. Suitable metal oxide materials include, but are not limited to: indium gallium zinc oxide (IGZO), indium gallium tin oxide (IGTO), indium tin zinc oxide (ITZO), indium gallium oxide (IGO), indium gallium zinc tin oxide (IGZTO), indium zinc oxide (IZO), zinc tin oxide (ZTO), indium-free metal oxides (In-free OS), rare earth doped oxides (Ln-OS, such as rare earth element doped IGZO / IZO), zinc oxide (ZnO), gallium oxide (GaO), indium oxide (InO), HfInZnO (HIZO), ZnO:F, In2O3:Sn, In2O3:Mo, Cd2SnO4, ZnO:Al, TiO2:Nb, and Cd-Sn-O.

[0111] Suitable metal oxynitride materials include, but are not limited to, zinc oxynitride, indium oxynitride, gallium oxynitride, tin oxynitride, cadmium oxynitride, aluminum oxynitride, germanium oxynitride, titanium oxynitride, silicon oxynitride, or combinations thereof. In one example, the material for the channel region CH1 / CH2 / CH3 includes indium gallium zinc oxide (IGZO). The active layer material can be amorphous, partially crystalline, single-crystal, or polycrystalline, and can also be a single-layer or multi-layer structure.

[0112] In an exemplary embodiment, the transistor device further includes a first electrode 13 and a second electrode 14 located on the side of the active layer 12 away from the substrate 10, wherein the first electrode 13 and the second electrode 14 are respectively connected to the active layer 12. In an exemplary embodiment, the first electrode 13 may be one of a source electrode and a drain electrode, and the second electrode 14 may be the other of a source electrode and a drain electrode.

[0113] In an exemplary embodiment, the first electrode 13 and the second electrode 14 can be made of metallic materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), niobium (Nb), neodymium (Nd), nickel (Ni), and molybdenum (Mo), or alloys composed of at least two of the above metals, such as aluminum-neodymium alloy (AlNd), titanium-aluminum alloy (TiAl), molybdenum-nickel-titanium alloy (Mo-Ni-Ti, MTD), or molybdenum-niobium alloy (MoNb). They can also be single-layer structures or multi-layer composite structures, such as Mo / Cu / Mo. Exemplarily, the first electrode 13 and the second electrode 14 can be made of Mo / Al / Mo, MoNb / Cu, MTD / Cu / MTD, or Cu / MTD.

[0114] In an exemplary embodiment, the transistor's turn-on current Ion satisfies the following formula:

[0115] Ion=(W / L)*C*[(Vgs-Vth)*Vds-0.5*(Vds)2]

[0116] Where W is the width of the channel region of the active layer, L is the length of the channel region of the active layer, C is the parasitic capacitance between the channel region of the active layer and the gate electrode, Vgs is the voltage difference between the gate electrode and the source electrode of the transistor, Vds is the voltage difference between the drain electrode and the source electrode of the transistor, and Vth is the threshold voltage of the transistor. From the above formula, it can be seen that the transistor's turn-on current Ion depends on the parameters C, W, L, Vgs, Vth, and Vds.

[0117] This disclosure provides a groove structure on the side of the gate insulating layer away from the substrate, with at least a portion of the active layer disposed within the groove structure, and at least two boundaries of the active layer having a predetermined distance from the corresponding boundaries of the groove structure. This reduces the thickness of the gate insulating layer that overlaps with the active layer, increases the capacitance value of the parasitic capacitance between the channel region of the active layer and the gate electrode, increases the turn-on current of the transistor device, and thus improves the refresh rate of the display product.

[0118] In an exemplary embodiment, as shown in Figures 2 and 4, the gate insulating layer 21 includes a first region R1 and a second region R2, wherein the second region R2 comprises all regions except the first region R1, and the second region R2 surrounds at least one side of the first region R1.

[0119] In an exemplary embodiment, as shown in Figures 2 and 4, the groove structure 1 is located in the first region R1, and the thickness H1 of the gate insulating layer 21 located in the first region R1 is less than the thickness H2 of the gate insulating layer 21 located in the second region R2.

[0120] In an exemplary embodiment, FIG5 is a top view of the transistor device provided in FIG1 and FIG3. As shown in FIG5, the orthographic projection of the groove structure 1 on the substrate is within the range of the orthographic projection of the gate electrode 11 on the substrate.

[0121] In an exemplary embodiment, the shape of the cross-section of the groove structure along the direction parallel to the substrate can be circular, square, rectangular, or other shapes, and this disclosure does not limit it in any way. Figure 5 illustrates an example where the cross-section of the groove structure along the direction parallel to the substrate is square.

[0122] In an exemplary embodiment, as shown in Figures 1, 3, and 5, the active layer 12 may include a first active layer 121 and a second active layer 122. The second active layer 122 is disposed on the side of the first active layer 121 away from the substrate 10.

[0123] In an exemplary embodiment, as shown in FIG5, the orthographic projection of the second active layer 122 on the substrate 10 may be within the range of the orthographic projection of the first active layer 121 on the substrate 10.

[0124] In an exemplary embodiment, the thickness of the first active layer 121 is greater than the thickness of the second active layer 122.

[0125] In an exemplary embodiment, the conductivity of the second active layer 122 is greater than that of the first active layer 121.

[0126] In an exemplary embodiment, the first active layer 121 may be an amorphous silicon layer or a metal oxide layer.

[0127] In an exemplary embodiment, the second active layer 122 is an N-type semiconductor layer. Exemplarily, the second active layer 122 is an N-type doped amorphous silicon layer or a metal oxide layer.

[0128] In an exemplary embodiment, as shown in Figures 1 and 3, the distance L1 between the surface of the first active layer 121 away from the substrate 10 and the surface of the gate electrode 11 away from the substrate 10 is less than or equal to the distance L2 between the surface of the gate insulating layer 21 in the second region away from the substrate 10 and the surface of the gate electrode 11 in the second region away from the substrate 10. Figures 1 and 3 show that the distance L1 between the surface of the first active layer 121 away from the substrate 10 and the surface of the gate electrode 11 away from the substrate 10 is equal to the distance L2 between the surface of the gate insulating layer 21 in the second region away from the substrate 10 and the surface of the gate electrode 11 in the second region away from the substrate 10.

[0129] In an exemplary embodiment, as shown in Figures 1 and 3, the distance L3 between the surface of the second active layer 122 away from the substrate 10 and the surface of the gate electrode 11 away from the substrate 10 is greater than the distance L2 between the surface of the gate insulating layer 21 in the second region away from the substrate 10 and the surface of the gate electrode 11 away from the substrate 10.

[0130] In an exemplary embodiment, as shown in Figures 1 and 3, at least a portion of the second active layer 122 is projected onto the substrate 10 within the range of the first electrode 13 projected onto the substrate 10, i.e., the first electrode 13 covers at least a portion of the second active layer.

[0131] In an exemplary embodiment, as shown in Figures 1 and 3, at least a portion of the second active layer 122 is projected onto the substrate 10 within the range of the second electrode 14 projected onto the substrate 10, i.e., the second electrode 14 covers at least a portion of the second active layer.

[0132] In an exemplary embodiment, as shown in Figures 1, 3 and 5, at least one of the first electrode 13 and the second electrode 14 partially fills the groove structure 1 and covers the sidewall of the active layer 12.

[0133] In an exemplary embodiment, as shown in Figures 1, 3, and 5, the orthographic projection of at least one of the first electrode 13 and the second electrode 14 onto the substrate 10 at least partially overlaps with the orthographic projection of the gate insulating layer 21 located in the second region onto the substrate 10. This at least partial overlap ensures that the first and second electrodes can make sufficient contact with the active layer 12.

[0134] In an exemplary embodiment, as shown in Figures 1 and 2, the gate insulating layer 21 can be a single-layer structure.

[0135] In an exemplary embodiment, as shown in FIG2, the thickness H1 of the gate insulating layer 21 located in the first region R1 is in the range of 2000 angstroms to 3500 angstroms. Exemplarily, the thickness H1 of the gate insulating layer 21 located in the first region R1 can be 2000 angstroms.

[0136] In an exemplary embodiment, when the gate insulating layer 21 is a single-layer structure, the material used to fabricate the gate insulating layer 21 may include silicon oxide or silicon nitride.

[0137] In an exemplary embodiment, as shown in FIG2, the distance H between the surface of the gate insulating layer 21 in the second region R2 away from the substrate 10 and the surface of the gate electrode 11 away from the substrate 10 is in the range of 3800 angstroms to 4200 angstroms. Exemplarily, the distance H between the surface of the gate insulating layer 21 in the second region R2 away from the substrate 10 and the surface of the gate electrode 11 away from the substrate 10 can be 4000 angstroms.

[0138] In an exemplary embodiment, when the gate insulating layer is a single-layer structure, the thickness of the gate insulating layer is the same as the thickness of the gate insulating layer located in the second region. The thickness of the gate insulating layer is in the range of 3800 angstroms to 4200 angstroms.

[0139] In an exemplary embodiment, the distance H between the surface of the gate insulating layer 21 located in the second region R2 away from the substrate 10 and the surface of the gate electrode 11 located away from the substrate 10 can be controlled by the etching time of the gate insulating layer.

[0140] In an exemplary embodiment, as shown in Figures 3 and 4, the gate insulating layer 21 may include a first gate insulating layer 22 and a second gate insulating layer 23 sequentially stacked on the substrate 10.

[0141] In an exemplary embodiment, as shown in FIG4, the second gate insulating layer 23 has a via V that exposes the first gate insulating layer 22, and the via V of the second gate insulating layer 23 and the first gate insulating layer 22 form a groove structure 1.

[0142] In an exemplary embodiment, as shown in FIG4, the orthographic projection of the active layer 12 on the substrate 10 is within the range of the orthographic projection of the via V on the substrate 10.

[0143] In an exemplary embodiment, as shown in FIG4, the thickness H2 of the first gate insulating layer 22 is in the range of 2000 angstroms to 3500 angstroms. Exemplarily, the thickness H3 of the first gate insulating layer 22 can be 2000 angstroms. In this exemplary embodiment, the thinner the first gate insulating layer, the more significant the improvement in the turn-on current of the transistor device.

[0144] In an exemplary embodiment, as shown in FIG3, the distance H between the surface of the second gate insulating layer 23 away from the substrate 10 and the surface of the gate electrode 11 away from the substrate 10 is in the range of 3800 angstroms to 4200 angstroms.

[0145] In an exemplary embodiment, when the gate insulating layer has a double-layer structure, the thickness of the gate insulating layer is equal to the sum of the thicknesses of the first and second gate insulating layers. The thickness of the gate insulating layer is in the range of 3800 angstroms to 4200 angstroms.

[0146] In an exemplary embodiment, the materials used to fabricate the first gate insulating layer 22 and the second gate insulating layer 23 may be different. Specifically, the material used to fabricate the first gate insulating layer 22 includes one of silicon oxide and silicon nitride, and the material used to fabricate the second gate insulating layer 23 includes the other of silicon oxide and silicon nitride.

[0147] In an exemplary embodiment, the first gate insulating layer 22 and the second gate insulating layer 23 are made of different materials, and the dry etching gases required for the first gate insulating layer 22 and the second gate insulating layer 23 are different. When forming the gate insulating layer, only the etching gas for the second gate insulating layer is used, and the etching gas for the first gate insulating layer is not used. This ensures that the second gate insulating layer can be etched while the first gate insulating layer is completely preserved, thereby avoiding changes in transistor characteristics caused by fluctuations in the etching amount.

[0148] In an exemplary embodiment, the active layer 12 is made of a metal oxide. The first gate insulating layer 22 is made of silicon oxide, and the second gate insulating layer 23 is made of silicon nitride.

[0149] In an exemplary embodiment, the active layer 12 is made of amorphous silicon. The first gate insulating layer 22 is made of silicon nitride, and the second gate insulating layer 23 is made of silicon oxide.

[0150] Figure 6 shows the curve of gate insulating layer thickness versus Ion normalization coefficient. As shown in Figure 6, the smaller the gate insulating layer thickness, the greater the increase in transistor turn-on current Ion.

[0151] Figure 7 shows the curves of the gate electrode voltage Vg and the current Id flowing through the source electrode under different gate insulating layer thicknesses. As shown in Figure 7, S1 is the curve of the gate electrode voltage and the current flowing through the source electrode when the gate insulating layer thickness is 3500 angstroms, and S2 is the curve of the gate electrode voltage and the current flowing through the source electrode when the gate insulating layer thickness is 4000 angstroms. As shown in Figure 7, the smaller the gate insulating layer thickness, the greater the increase in the transistor's turn-on current Ion.

[0152] The thinner the gate insulation layer, the higher the failure rate of the display product's load and short circuits between the data line and the gate line.

[0153] This disclosure allows for increasing the transistor's turn-on current while reducing the load on display products and the failure rate of short circuits between data lines and gate lines, by using a gate insulation layer thickness ranging from 3800 angstroms to 4200 angstroms.

[0154] In an exemplary embodiment, the thickness of the gate electrode 11 is in the range of 2000 angstroms to 5000 angstroms. The thickness of the gate electrode 11 depends on the resolution and refresh rate of the display product, and this disclosure does not limit it in any way.

[0155] In an exemplary embodiment, the thickness of at least one of the first electrode 13 and the second electrode 14 is in the range of 2000 angstroms to 5000 angstroms. The thickness of at least one of the first electrode 13 and the second electrode 14 depends on the resolution and refresh rate of the display product, and this disclosure does not limit it in any way.

[0156] In an exemplary embodiment, the thickness of the active layer 12 is in the range of 1700 angstroms to 2200 angstroms.

[0157] The subsequent process flow is shown in Figure 2. Thus, by adjusting the thickness of the GI1 deposition, the overall Ion value of the TFT can be adjusted. As can be seen from the above formula, the Ion value ratio is directly proportional to the ratio of the GI thinning value to the initial GI value, i.e., Ion / Ionref = GIref / GI. Figure 4, using a-Si as an example, illustrates the relationship between the Ion normalization coefficient and GI. Theoretically, the thinner the GI, the greater the Ion increase. However, GI thinning will increase the parasitic capacitance of the TFT gate and the parasitic capacitance of the source and drain, and the DGS defect rate will also increase. Therefore, in general industrial production, the common GI1 thickness is [value missing].

[0158] In an exemplary embodiment, the thickness of the gate electrode of the transistor is determined by the product characteristics, including resolution and refresh rate.

[0159] In an exemplary embodiment, the thickness of the first and second electrodes of the transistor is determined by the product characteristics of the product.

[0160] In an exemplary embodiment, the thickness of the gate insulation layer may be 4000 angstroms.

[0161] In an exemplary embodiment, the thickness of the first gate insulating layer can be between 2000 and 3500 angstroms. The thinner the first gate insulating layer, the more significant the improvement in the turn-on current of the transistor device.

[0162] Figure 8 is a top view of a transistor device, Figure 9 is a cross-sectional view of Figure 8 along the AA direction, and Figure 10 is a cross-sectional view of Figure 8 along the BB direction. As shown in Figures 8 to 10, the first electrode 13 may surround at least one side of the second electrode 14, and the orthographic projection of the first electrode 13 on the substrate 10 covers the sidewall of the active layer 12. The orthographic projection of the second electrode 14 on the substrate 10 at least partially overlaps with the orthographic projection of the middle part of the active layer 12 on the substrate 10. That is, the first electrode 13 in Figure 8 at least partially surrounds the second electrode 14. Figure 5 is illustrated with the example of the first and second electrodes being strip-shaped, and Figure 8 is illustrated with the example of the first electrode 13 at least partially surrounding the second electrode 14.

[0163] In an exemplary embodiment, as shown in Figures 5 and 8, the minimum width W of at least one of the first electrode 13 and the second electrode 14 along the arrangement direction of the first electrode 13 and the second electrode 14 is in the range of 2.5 micrometers to 3.5 micrometers.

[0164] In an exemplary embodiment, as shown in Figures 5 and 8, the distance W2 between the orthographic projection of the boundary of the groove structure 1 on the substrate 10 and the orthographic projection of the boundary of the active layer 12 on the substrate 10 is less than the distance W3 between the orthographic projection of the boundary of the first electrode 13 near the second electrode 14 on the substrate 10 and the orthographic projection of the boundary of the active layer 12 on the substrate 10.

[0165] In an exemplary embodiment, as shown in Figures 5 and 8, the distance W3 between the orthographic projection of the boundary of the first electrode 13 near the second electrode 14 on the substrate 10 and the orthographic projection of the boundary of the active layer 12 on the substrate 10 is greater than the distance W1 between the orthographic projection of the boundary of the first electrode 13 away from the second electrode 14 on the substrate 10 and the orthographic projection of the boundary of the gate electrode 11 on the substrate 10.

[0166] In an exemplary embodiment, the distance W1 between the orthographic projection of the boundary of the first electrode 13 away from the second electrode 14 onto the substrate 10 and the orthographic projection of the boundary of the gate electrode 11 onto the substrate 10 must satisfy the overlap error between the film layer where the gate electrode is located and the film layers where the first electrode 13 and the second electrode 14 are located. That is, the distance W1 between the orthographic projection of the boundary of the first electrode 13 away from the second electrode 14 onto the substrate 10 and the orthographic projection of the boundary of the gate electrode 11 onto the substrate 10 is greater than or equal to the overlap error between the film layer where the gate electrode 11 is located and the film layers where the first electrode 13 and the second electrode 14 are located.

[0167] In an exemplary embodiment, the distance W2 between the orthographic projection of the boundary of the groove structure 1 on the substrate 10 and the orthographic projection of the boundary of the active layer 12 on the substrate 10 must satisfy the overlap error of the film layer where the active layer and the gate insulating layer are located. That is, the distance W1 between the orthographic projection of the boundary of the groove structure 1 on the substrate 10 and the orthographic projection of the boundary of the active layer 12 on the substrate 10 must be greater than or equal to the overlap error of the film layer where the active layer and the gate insulating layer are located.

[0168] In an exemplary embodiment, the distance W3 between the orthographic projection of the boundary of the first electrode 13 near the second electrode 14 on the substrate 10 and the orthographic projection of the boundary of the active layer 12 on the substrate 10 is greater than or equal to the overlap error between the active layer and the first and second electrodes plus 1 micrometer, so as to ensure that the overlap area between one of the first and second electrodes and the active layer can improve the reliability of the transistor device.

[0169] In an exemplary embodiment, the distance W4 between the first electrode 13 and the second electrode 14 along the arrangement direction of the first electrode and the second electrode is determined by the resolution, process type, and product model of the exposure machine used in the process of forming the first electrode and the second electrode, and this disclosure does not limit it in any way.

[0170] In an exemplary embodiment, FIG11 is a schematic diagram of one structure of the display substrate, and FIG12 is a schematic diagram of another structure of the display substrate. As shown in FIG11 and FIG12, the transistor device further includes a passivation layer 31. The passivation layer 31 is located on the side of the transistor's first electrode 13 and second electrode 14 away from the substrate 10. In an exemplary embodiment, the passivation layer can protect the metal film layer on which the first electrode and second electrode of the transistor are located, can prevent the metal film layer on which the first electrode and second electrode of the transistor are located from being corroded, and can improve the reliability of the transistor device.

[0171] In an exemplary embodiment, the passivation layer 31 may be any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer, multiple layers, or a composite layer.

[0172] The "patterning process" described in this disclosure includes, for metallic, inorganic, or transparent conductive materials, processes such as photoresist coating, mask exposure, development, etching, and photoresist stripping; for organic materials, it includes processes such as organic material coating, mask exposure, and development. Deposition can be performed using any one or more of sputtering, evaporation, and chemical vapor deposition; coating can be performed using any one or more of spraying, spin coating, and inkjet printing; etching can be performed using any one or more of dry and wet etching. This disclosure does not limit the methods used. A "thin film" refers to a thin film made by depositing, coating, or other processes onto a substrate using a certain material. If the "thin film" does not require a patterning process during the entire fabrication process, it can also be called a "layer." If the "thin film" requires a patterning process during the entire fabrication process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern." The phrase "A and B are set in the same layer" in this disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A includes the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0173] The fabrication process of the transistor device shown in Figure 11 is illustrated below.

[0174] (1) Forming a gate electrode. In an exemplary embodiment, forming a gate electrode includes: depositing a first metal thin film on a substrate, and patterning the first metal thin film using a patterning process to form a gate electrode 11. As shown in FIG13, FIG13 is a schematic diagram of FIG11 after the gate electrode has been formed.

[0175] (2) Forming a gate insulating layer. In an exemplary embodiment, forming a gate insulating layer includes: depositing a gate insulating film on a substrate on which a gate electrode is formed, and patterning the gate insulating film using a patterning process to form a gate insulating layer 21 having a groove structure 1. As shown in FIG14, FIG14 is a schematic diagram after the gate insulating layer in FIG11 has been formed.

[0176] In an exemplary embodiment, a gate insulating film is deposited on a substrate on which the gate electrode is formed using a chemical vapor deposition process.

[0177] (3) Forming the original semiconductor layer. In an exemplary embodiment, forming the original semiconductor layer includes: depositing a semiconductor thin film on a substrate on which a gate insulating layer is formed, performing N-type doping on the surface of the semiconductor thin film by a hydrogenation process, and patterning the doped semiconductor thin film by a patterning process to form an original semiconductor layer including a first active layer 121 and a third active layer 123. As shown in FIG15, FIG15 is a schematic diagram after the original semiconductor layer in FIG11 is formed.

[0178] In an exemplary embodiment, the third active layer 123 is an N-type semiconductor layer.

[0179] In an exemplary embodiment, the orthographic projection of the third active layer 123 onto the substrate coincides with the orthographic projection of the surface of the first active layer 121 away from the substrate onto the substrate.

[0180] (4) Forming the first electrode and the second electrode. In an exemplary embodiment, forming the first electrode and the second electrode includes: depositing a second metal thin film on a substrate on which the original semiconductor layer is formed, and patterning the second metal thin film and the third active layer respectively by a patterning process to form a first electrode 13, a fourth electrode 14 and a second active layer 122. As shown in FIG16, FIG16 is a schematic diagram after the first electrode and the second electrode in FIG11 are formed.

[0181] In an exemplary embodiment, the active layer includes a first active layer 121 and a second active layer 122.

[0182] (5) Forming a passivation layer. In an exemplary embodiment, forming a passivation layer includes depositing a passivation layer on a substrate on which the first electrode and the second electrode are formed. As shown in FIG17, FIG17 is a schematic diagram after the passivation layer in FIG11 is formed.

[0183] The fabrication process of the transistor device shown in Figure 12 is illustrated below.

[0184] (1) Forming a gate electrode. In an exemplary embodiment, forming a gate electrode includes: depositing a first metal thin film on a substrate, and patterning the first metal thin film using a patterning process to form a gate electrode. Figure 12 is the same as the schematic diagram of the gate electrode after formation in Figure 9.

[0185] (2) Forming a gate insulating layer. In an exemplary embodiment, forming a gate insulating layer includes: sequentially depositing a first gate insulating film and a second gate insulating film on a substrate on which gate electrodes are formed, and patterning the second gate insulating film by a patterning process to form a gate insulating layer 21 including a first gate insulating layer 22 and a second gate insulating layer 23. As shown in FIG18, FIG18 is a schematic diagram after the gate insulating layer in FIG12 is formed.

[0186] In an exemplary embodiment, the second gate insulating layer 23 is provided with a via V that exposes the first gate insulating layer 22. The via V and the first gate insulating layer 22 form a groove structure.

[0187] In an exemplary embodiment, a first gate insulating film and a second gate insulating film are sequentially deposited on a substrate on which the gate electrode is formed using a chemical vapor deposition process.

[0188] (3) Forming the original semiconductor layer. In an exemplary embodiment, forming the original semiconductor layer includes: depositing a semiconductor thin film on a substrate on which a gate insulating layer is formed, performing N-type doping on the surface of the semiconductor thin film by a hydrogenation process, and patterning the doped semiconductor thin film by a patterning process to form an original semiconductor layer including a first active layer 121 and a third active layer 123. As shown in FIG19, FIG19 is a schematic diagram after the original semiconductor layer in FIG12 is formed.

[0189] In an exemplary embodiment, the third active layer 123 is an N-type semiconductor layer.

[0190] In an exemplary embodiment, the orthographic projection of the third active layer 123 onto the substrate coincides with the orthographic projection of the surface of the first active layer 121 away from the substrate onto the substrate.

[0191] (4) Forming the first electrode and the second electrode. In an exemplary embodiment, forming the first electrode and the second electrode includes: depositing a second metal thin film on a substrate on which the original semiconductor layer is formed, and patterning the second metal thin film and the third active layer respectively by a patterning process to form a first electrode 13, a fourth electrode 14 and a second active layer 122. As shown in FIG20, FIG20 is a schematic diagram after the formation of the first electrode and the second electrode in FIG12.

[0192] In an exemplary embodiment, the active layer includes a first active layer 121 and a second active layer 122.

[0193] (5) Forming a passivation layer. In an exemplary embodiment, forming a passivation layer includes depositing a passivation layer on a substrate on which the first electrode and the second electrode are formed. As shown in FIG21, FIG21 is a schematic diagram after the passivation layer is formed in FIG12.

[0194] This disclosure also provides a method for fabricating a transistor device, configured to fabricate the transistor device provided in any of the foregoing embodiments. The method for fabricating the transistor device includes:

[0195] Step 100: Form the gate electrode of the transistor device on the substrate.

[0196] Step 200: Form a gate insulating layer for a transistor device on the gate electrode. The gate insulating layer has a groove structure, and the groove structure is located on the side of the gate insulating layer away from the substrate.

[0197] Step 300: Form the active layer of the transistor device within the groove structure of the gate insulating layer.

[0198] The active layer has at least two boundaries that are spaced at a predetermined distance from the corresponding boundaries of the groove structure.

[0199] In an exemplary embodiment, step 200 may include: coating a gate insulating film on the gate electrode and forming grooves on the gate insulating film through a patterning process to form a gate insulating layer of the transistor device.

[0200] In an exemplary embodiment, step 200 may include: sequentially coating a first gate insulating film and a second gate insulating film on the gate electrode, and forming a gate insulating layer with a groove structure consisting of the via and the first gate insulating film by patterning process.

[0201] In an exemplary embodiment, the active layer includes a first active layer and a second active layer. Step 300 includes: depositing a semiconductor thin film on a gate insulating layer; and processing the semiconductor thin film by a hydrogenation process to form the first active layer and the third active layer.

[0202] A source / drain metal thin film is deposited on the third active layer. The source / drain metal thin film and the third active layer are then processed by a patterning process to form a second active layer, a first electrode, and a second electrode.

[0203] In an exemplary embodiment, the method for fabricating a transistor device further includes:

[0204] Step 400: Form a passivation layer on the first electrode and the second electrode.

[0205] Figure 22A is a cross-sectional schematic diagram of the transistor device provided in an embodiment of this disclosure, and Figure 22B is a partial cross-sectional view of Figure 22A. As shown in Figures 22A and 22B, the transistor device provided in this embodiment of the disclosure is disposed on a substrate 100, and the transistor device includes: a gate electrode 201, an active layer 202, a first electrode 203, a second electrode 204, and a gate insulating layer 300. The first electrode 203 and the second electrode 204 are disposed on the side of the active layer 202 and the gate electrode 201 away from the substrate 100, and the gate insulating layer 300 is disposed between the active layer 202 and the gate electrode 201.

[0206] In an exemplary embodiment, the gate electrode 201 can be disposed on the side of the gate insulating layer 300 near the substrate 100, and the active layer 20 can be disposed on the side of the gate insulating layer 300 away from the substrate 100; that is, the transistor device can be a bottom-gate structure. Alternatively, the gate electrode 201 can be disposed on the side of the gate insulating layer 300 away from the substrate 100, and the active layer 20 can be disposed on the side of the gate insulating layer 300 near the substrate 100; that is, the transistor device can be a top-gate structure. Figures 22A and 22B are illustrated using a bottom-gate transistor device as an example.

[0207] As shown in Figures 22A and 22B, the gate insulating layer 300 may include a first insulating layer 301 and a second insulating layer 302 stacked on the substrate 100, wherein one of the first insulating layer 301 and the second insulating layer 302 is provided with a via VV. Figure 22B illustrates the case where the first insulating layer 301 is provided with a via VV.

[0208] As shown in Figures 22A and 22B, the orthographic projection of the via VV on the substrate 100 at least partially overlaps with the orthographic projection of the active layer 202 on the substrate 100. In this disclosure, the at least partial overlap of the orthographic projection of the via VV on the substrate 100 and the orthographic projection of the active layer 202 on the substrate 100 can reduce the thickness of the gate insulating layer disposed between the channel region and the gate electrode of the active layer, increase the capacitance value of the parasitic capacitance between the channel region and the gate electrode of the active layer, increase the turn-on current Ion of the transistor device, and thus improve the refresh rate of the display product.

[0209] This disclosure provides a gate insulating layer comprising a first insulating layer and a second insulating layer, and a via is provided in one of the first and second insulating layers. This ensures the etching accuracy of the gate insulating layer, improves the process stability of the transistor device, and reduces the fluctuation of the turn-on current of the transistor device.

[0210] In an exemplary embodiment, as shown in FIG22A, the orthographic projection of at least one of the first electrode 203 and the second electrode 204 on the substrate at least partially overlaps with the orthographic projection of the active layer 202 on the substrate.

[0211] In an exemplary embodiment, as shown in Figures 22A and 22B, the active layer 202 includes a first active layer 2021 and a second active layer 2022. The second active layer 2022 is disposed on the side of the first active layer 2021 away from the substrate 100. The second active layer 2022 includes a first active structure 2021 and a second active structure 2022.

[0212] In an exemplary embodiment, as shown in Figures 22A and 22B, the orthographic projection of the second active layer 202 onto the substrate 100 is within the range of the orthographic projection of the first active layer 201 onto the substrate 100.

[0213] In an exemplary embodiment, as shown in Figures 22A and 22B, the orthographic projection of the first active structure 2021 on the substrate 100 is within the range of the orthographic projection of the first electrode 203 on the substrate 100.

[0214] In an exemplary embodiment, as shown in Figures 22A and 22B, the orthographic projection of the second active structure 3222 onto the substrate 100 lies within the range of the orthographic projection of the second electrode 204 onto the substrate 100.

[0215] In an exemplary embodiment, the second active layer 202 may be fabricated using the same mask as the first electrode 203 and the second electrode 204, and this disclosure does not limit this in any way.

[0216] In an exemplary embodiment, the thickness of the first active layer 201 is greater than the thickness of the second active layer 202.

[0217] In an exemplary embodiment, the conductivity of the second active layer 202 is greater than that of the first active layer 201. In an exemplary embodiment, the second active layer may be an N-type semiconductor layer.

[0218] In an exemplary embodiment, the maximum distance H between the surface of the gate insulating layer 300 away from the substrate 100 and the surface of the gate electrode 31 away from the substrate 100 is in the range of 3800 angstroms to 4200 angstroms. Exemplarily, the maximum distance H between the surface of the gate insulating layer 300 away from the substrate 100 and the surface of the gate electrode 31 away from the substrate 100 can be 4000 angstroms.

[0219] In an exemplary embodiment, the thickness H0 of the via VV along the direction perpendicular to the substrate is in the range of 1500 angstroms to 3500 angstroms.

[0220] In an exemplary embodiment, the first insulating layer 301 is made of one of silicon oxide and silicon nitride, and the second insulating layer 302 is made of the other of silicon oxide and silicon nitride. Exemplarily, when the first insulating layer 301 is made of silicon oxide, the second insulating layer 302 may be made of silicon nitride; or, when the first insulating layer 301 is made of silicon nitride, the second insulating layer 302 may be made of silicon oxide. This disclosure does not impose any limitations in this regard.

[0221] In an exemplary embodiment, the semiconductor layer can be an amorphous silicon layer or a metal oxide layer. The metal oxide layer can be an oxide containing indium and tin, an oxide containing tungsten and indium, an oxide containing tungsten, indium, and zinc, an oxide containing titanium and indium, an oxide containing titanium, indium, and tin, an oxide containing indium and zinc, an oxide containing silicon, indium, and tin, or an oxide containing indium or gallium and zinc. The metal oxide layer can be a single layer, a double layer, or a multilayer.

[0222] In an exemplary embodiment, the gate electrode may be made of a metallic material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or an alloy of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). It may be a single-layer structure or a multi-layer composite structure, such as a material made of Mo / Cu / Mo, etc. This disclosure does not limit it in any way.

[0223] In an exemplary embodiment, the first electrode and the second electrode are made of metallic materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or alloys of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). They can be single-layer structures or multi-layer composite structures, such as Mo / Al / Mo or MoNb / Cu, etc. This disclosure does not limit them in any way.

[0224] The following describes the transistor device provided in the embodiments of this disclosure by way of the fabrication process of the transistor device shown in Figure 22A.

[0225] (1) Forming a gate electrode. In an exemplary embodiment, forming a gate electrode includes: depositing a first metal thin film on a substrate, and patterning the first metal thin film by a patterning process to form a gate electrode 201, as shown in FIG23a.

[0226] (2) Forming a first insulating layer. In an exemplary embodiment, forming a first insulating layer includes depositing a first insulating film on a substrate on which a gate electrode is formed to form a first insulating layer 301, as shown in FIG23b.

[0227] In an exemplary embodiment, a first insulating film is deposited on a substrate on which a gate electrode is formed using a chemical vapor deposition process.

[0228] In an exemplary embodiment, the first insulating layer 301 is provided with a through hole VV.

[0229] [Correction 26.09.2025 according to Rule 91] (3) Forming a second insulating layer. In an exemplary embodiment, forming a second insulating layer includes forming a second insulating layer 302 on a substrate on which a first insulating layer is formed, as shown in FIG23c.

[0230] (4) Forming a primitive semiconductor layer. In an exemplary embodiment, forming a primitive semiconductor layer includes: depositing a semiconductor thin film on a substrate on which a second insulating layer is formed, performing N-type doping on the surface of the semiconductor thin film by a hydrogenation process, and patterning the doped semiconductor thin film by a patterning process to form a primitive semiconductor layer including a first active layer 2021 and a third active layer 2025, as shown in FIG23d.

[0231] In an exemplary embodiment, the orthographic projection of the third active layer 2025 onto the substrate coincides with the orthographic projection of the surface of the first active layer 2021 away from the substrate onto the substrate.

[0232] (5) Forming a first electrode and a second electrode. In an exemplary embodiment, forming the first electrode and the second electrode includes: depositing a second metal thin film on a substrate on which a second insulating layer is formed, and patterning the second metal thin film and the third active layer respectively by a patterning process to form a first electrode 203, a fourth electrode 204 and a second active layer 2022, as shown in FIG23e.

[0233] (6) Forming a passivation layer. In an exemplary embodiment, forming a passivation layer includes forming a passivation layer on a substrate on which a first electrode and a second electrode are formed.

[0234] In an exemplary embodiment, the first electrode can be U-shaped, I-shaped, or L-shaped. The second electrode can be I-shaped. When the first electrode is U-shaped, the transistor device can be called a U-type transistor device; when the first electrode is I-shaped, the transistor device can be called an I-type transistor device; and when the first electrode is L-shaped, the transistor device can be called an L-type transistor device.

[0235] In an exemplary embodiment, Figure 24 is a top view of the transistor device, Figure 25 is a top view of the transistor device, Figure 26 is a top view of the transistor device, Figure 27 is a top view of the transistor device, and Figure 28 is a top view of the transistor device. As shown in Figures 24 to 28, the orthographic projection of the active layer 42 on the substrate is within the range of the orthographic projection of the gate electrode 41 on the substrate, the orthographic projection of the via VV on the substrate is within the range of the orthographic projection of the active layer 42 on the substrate, the orthographic projection of the first electrode 43 on the substrate is within the range of the orthographic projection of the active layer 42 on the substrate, and the orthographic projection of a portion of the second electrode 44 on the substrate does not overlap with the orthographic projection of the gate electrode 41 on the substrate.

[0236] As shown in Figures 24 to 28, the via VV includes multiple boundaries, including a first boundary L11, a second boundary L12, a third boundary L13, and a fourth boundary L14. The first boundary L11 and the second boundary L12 extend along a first direction D1, and the third boundary L13 and the fourth boundary L14 extend along a second direction D2. The first boundary L11, the fourth boundary L14, the second boundary L12, and the third boundary L13 are connected sequentially.

[0237] In an exemplary embodiment, as shown in Figures 24 to 28, the first electrode 43 includes an electrode connecting segment 434, a first branch segment 431, a second branch segment 432, and a third branch segment 433. The electrode connecting segment 434 extends at least partially along a first direction D1, the first branch segment 431, the second branch segment 432, and the third branch segment 433 are arranged along the first direction D1, and at least one branch segment extends along a second direction D2. The electrode connecting segment 434 is connected to the first branch segment 431, the second branch segment 432, and the third branch segment 433, respectively; the first direction D1 intersects the second direction D2.

[0238] In an exemplary embodiment, as shown in Figures 24 to 28, the second electrode 44 includes a first sub-electrode 441 and a second sub-electrode 442; the first sub-electrode 441 and the second sub-electrode 442 extend along a second direction D2, the orthographic projection of the first sub-electrode 441 on the substrate is located between the orthographic projection of the first branch segment 431 on the substrate and the orthographic projection of the second branch segment 432 on the substrate, and the orthographic projection of the second sub-electrode 442 on the substrate is located between the orthographic projection of the second branch segment 432 on the substrate and the orthographic projection of the third branch segment 433 on the substrate.

[0239] In an exemplary embodiment, as shown in Figures 24 to 28, the orthographic projection of the second boundary L12 on the substrate is located on the side of the first boundary L11 that is close to the orthographic projection of the electrode connection segment 434 on the substrate.

[0240] In an exemplary embodiment, as shown in FIG24, the first boundary L11, the second boundary L12, the third boundary L13 and the fourth boundary L14 are straight lines.

[0241] In an exemplary embodiment, as shown in FIG24, the orthographic projection of the electrode connection segment 434 on the substrate does not overlap with the orthographic projections of the multiple boundaries on the substrate. The orthographic projection of the first branch segment 431 on the substrate overlaps with the orthographic projections of the first boundary L11, the second boundary L12, and the third boundary L13 on the substrate, respectively. The orthographic projection of the second branch segment 432 on the substrate overlaps with the orthographic projections of the first boundary L11 and the second boundary L12 on the substrate, respectively. The orthographic projection of the third branch segment 433 on the substrate overlaps with the orthographic projections of the first boundary L11, the second boundary L12, and the fourth boundary L14 on the substrate, respectively. The orthographic projections of the first sub-electrode 441 and the second sub-electrode 442 on the substrate overlap with the orthographic projections of the first boundary L11 and the second boundary L12 on the substrate, respectively.

[0242] In an exemplary embodiment, as shown in FIG24, the distance a1 between the orthographic projection of the boundary of the first branch segment 431 near the first sub-electrode 441 on the substrate and the orthographic projection of the third boundary L13 on the substrate along the first direction D1 is in the range of 1 micrometer to 1.5 micrometers.

[0243] In an exemplary embodiment, as shown in FIG24, the distance b1 between the orthographic projection of the boundary of at least one of the first sub-electrode 441 and the second sub-electrode 442 on the substrate and the orthographic projection of the second boundary L12 on the substrate along the second direction D2 is in the range of 1 micrometer to 1.5 micrometer.

[0244] In an exemplary embodiment, as shown in FIG24, the distance c1 between the orthographic projection of the boundary of the third branch segment 433 near the second sub-electrode 442 on the substrate and the orthographic projection of the fourth boundary L14 on the substrate along the first direction D1 is in the range of 1 micrometer to 1.5 micrometers.

[0245] In the exemplary embodiment, in the transistor device provided in FIG24, since the orthographic projection of the first electrode of the transistor device on the substrate overlaps with the orthographic projections of the third boundary and the fourth boundary on the substrate, respectively, and the orthographic projection of the second electrode of the transistor device on the substrate overlaps with the orthographic projections of the first boundary and the second boundary on the substrate, the parasitic capacitance between the gate electrode and the first electrode and the parasitic capacitance between the gate electrode and the second electrode will not fluctuate when there is a misalignment between the first electrode and the second electrode relative to the gate insulating layer in the first direction. However, since the thickness of the portion of the channel region of the active layer located between the first electrode and the second electrode is not reduced, the transistor device provided in FIG24 has a limited effect on improving the turn-on current of the transistor device.

[0246] In an exemplary embodiment, as shown in Figures 25 and 26, the first boundary L11, the third boundary L13, and the fourth boundary L14 are straight lines, and the shape of the second boundary L12 is adapted to the shape of the electrode connection segment 434. In another exemplary embodiment, the electrode connection segment 434 may be M-shaped.

[0247] In an exemplary embodiment, as shown in Figures 25 and 26, the orthographic projection of electrode connection segment 434 on the substrate overlaps with the orthographic projection of the second boundary L12 on the substrate; the orthographic projection of the first branch segment 431 on the substrate overlaps with the orthographic projection of the third boundary L13 on the substrate, but does not overlap with the orthographic projection of the first boundary L11 on the substrate; the orthographic projection of the second branch segment 432 on the substrate does not overlap with the orthographic projections of multiple boundaries on the substrate; the orthographic projection of the third branch segment 433 on the substrate overlaps with the orthographic projection of the fourth boundary L14 on the substrate, but does not overlap with the orthographic projection of the first boundary L11 on the substrate; and the orthographic projections of the first sub-electrode 441 and the second sub-electrode 442 on the substrate partially overlap with the orthographic projection of the first boundary L11 on the substrate.

[0248] In an exemplary embodiment, as shown in Figures 25 and 26, the distance a2 between the orthographic projection of the boundary of the first branch segment 431 near the first sub-electrode 441 on the substrate and the orthographic projection of the third boundary L13 on the substrate along the first direction D1 is in the range of 1 micrometer to 1.5 micrometers.

[0249] In an exemplary embodiment, as shown in Figures 25 and 26, the distance b2 between the orthographic projection of the boundary of the electrode connection segment 434 near the second electrode 44 on the substrate and the orthographic projection of the second boundary L12 on the substrate along the second direction D2 is in the range of 1 micrometer to 1.5 micrometers.

[0250] In an exemplary embodiment, as shown in Figures 25 and 26, the distance c2 between the orthographic projection of the boundary of the third branch segment 433 near the second sub-electrode 442 on the substrate and the orthographic projection of the fourth boundary L14 on the substrate along the first direction D1 is in the range of 1 micrometer to 1.5 micrometers.

[0251] In an exemplary embodiment, as shown in FIG26, the plurality of boundaries further include: a first protruding boundary L21, a second protruding boundary L22, a third protruding boundary L23, a fourth protruding boundary L24, a fifth protruding boundary L25, a sixth protruding boundary L26, a seventh boundary, and an eighth protruding boundary L28. The first protruding boundary L21, the third protruding boundary L23, the fifth protruding boundary L25, and the seventh protruding boundary L27 extend along a first direction D1, and the second protruding boundary L22, the fourth protruding boundary L24, the sixth protruding boundary L26, and the eighth protruding boundary L28 extend along a second direction D2.

[0252] In an exemplary embodiment, as shown in FIG26, the third boundary L13 is connected to the first boundary L11 in sequence through the first protruding boundary L21, the second protruding boundary L22, the third protruding boundary L23 and the fourth protruding boundary L24, and the fourth boundary L14 is connected to the first boundary L11 in sequence through the fifth protruding boundary L25, the sixth protruding boundary L26, the seventh protruding boundary L27 and the eighth protruding boundary L28.

[0253] In an exemplary embodiment, as shown in FIG26, the orthographic projections of the first electrode 43 and the second electrode 44 on the substrate do not overlap with the orthographic projections of at least one of the protruding boundaries L21, L22, L23, L24, L25, L26, L27, and L28 on the substrate.

[0254] In an exemplary embodiment, as shown in FIG26, the distance d1 between the second protruding boundary L22 and the fourth protruding boundary L24 along the second direction D2 is in the range of 1 micrometer to 4 micrometers.

[0255] In an exemplary embodiment, as shown in FIG26, the distance d2 between the sixth protruding boundary L26 and the eighth protruding boundary L28 along the second direction D2 is in the range of 1 micrometer to 4 micrometers.

[0256] In the exemplary embodiments, in the transistor devices provided in Figures 25 and 26, since the orthographic projection of the first electrode of the transistor device on the substrate overlaps with the orthographic projections of the second boundary, the third boundary, and the fourth boundary on the substrate, respectively, and the orthographic projection of the second electrode of the transistor device on the substrate overlaps with the orthographic projection of the first boundary on the substrate, the parasitic capacitance between the first electrode and the second electrode and the gate insulating layer will not fluctuate when there is a misalignment between the first electrode and the second electrode in the first or second direction. Furthermore, since the thickness of the entire channel region of the active layer located between the first electrode and the second electrode is reduced, the transistor devices provided in Figures 25 and 26 exhibit a better improvement in the turn-on current of the transistor device.

[0257] Compared to the transistor device shown in Figure 25, the transistor device shown in Figure 26 has an additional first to eighth protruding branch segments in its via VV. These first to eighth protruding branch segments can be referred to as optical compensation structures. In the transistor device shown in Figure 26, after exposure, the via structures at the first and third boundaries approach right angles, and the structures at the first and fourth boundaries also approach right angles. This avoids the loss of turn-on current caused by the near-arc structure at the first and third boundaries of the via in the transistor device shown in Figure 25 after exposure, thus improving the performance of the transistor device.

[0258] In an exemplary embodiment, as shown in FIG27, the vias include: a first via V1, a second via V2, a third via V3 and a fourth via V4, which are arranged along a first direction D1.

[0259] In an exemplary embodiment, as shown in FIG27, the orthographic projection of the first via V1 on the substrate is located between the orthographic projection of the first branch segment 431 on the substrate and the orthographic projection of the first sub-electrode 441 on the substrate; the orthographic projection of the second via V2 on the substrate is located between the orthographic projection of the first sub-electrode 441 on the substrate and the orthographic projection of the second branch segment 432 on the substrate; the orthographic projection of the third via V3 on the substrate is located between the orthographic projection of the second branch segment 432 on the substrate and the orthographic projection of the second sub-electrode 442 on the substrate; and the orthographic projection of the fourth via V4 on the substrate is located between the orthographic projection of the second sub-electrode 442 on the substrate and the orthographic projection of the third branch segment 433 on the substrate.

[0260] In an exemplary embodiment, the distance between the orthographic projection of the third boundary L13 of the first via V1 onto the substrate and the orthographic projection of the boundary of the first branch segment 431 near the first via V1 onto the substrate along the first direction D1 is greater than or equal to 0, and the distance between the orthographic projection of the fourth boundary L14 of the first via V1 onto the substrate and the orthographic projection of the boundary of the first sub-electrode 441 near the first via V1 onto the substrate along the first direction D1 is greater than or equal to 0. Figure 27 illustrates an example where the distance between the orthographic projection of the third boundary L13 of the first via V1 onto the substrate and the orthographic projection of the boundary of the first branch segment 431 near the first via V1 onto the substrate along the first direction D1 is equal to 0, and the distance between the orthographic projection of the fourth boundary L14 of the first via V1 onto the substrate and the orthographic projection of the first sub-electrode 441 near the boundary of the first via V1 onto the substrate along the first direction D1 is equal to 0.

[0261] In an exemplary embodiment, the distance between the orthographic projection of the third boundary L13 of the second via V2 onto the substrate and the orthographic projection of the boundary of the first sub-electrode 441 near the second via V2 onto the substrate along the first direction D1 is greater than or equal to 0, and the distance between the orthographic projection of the fourth boundary L14 of the second via V2 onto the substrate and the orthographic projection of the second branch segment 432 near the boundary of the second via V2 onto the substrate along the first direction D1 is greater than or equal to 0. Figure 27 illustrates an example where the distance between the orthographic projection of the third boundary L13 of the second via V2 onto the substrate and the orthographic projection of the first sub-electrode 441 near the boundary of the second via V2 onto the substrate along the first direction D1 is equal to 0, and the distance between the orthographic projection of the fourth boundary L14 of the second via V2 onto the substrate and the orthographic projection of the second branch segment 432 near the boundary of the second via V2 onto the substrate along the first direction D1 is equal to 0.

[0262] In an exemplary embodiment, the distance between the orthographic projection of the third boundary L13 of the third via V3 onto the substrate and the orthographic projection of the boundary of the second branch segment 432 near the third via V3 onto the substrate along the first direction D1 is greater than or equal to 0, and the distance between the orthographic projection of the fourth boundary L14 of the third via V3 onto the substrate and the orthographic projection of the boundary of the second sub-electrode 442 near the third via V3 onto the substrate along the first direction D1 is greater than or equal to 0. Figure 27 illustrates an example where the distance between the orthographic projection of the third boundary L13 of the third via V3 onto the substrate and the orthographic projection of the boundary of the second branch segment 432 near the third via V3 onto the substrate along the first direction D1 is equal to 0, and the distance between the orthographic projection of the fourth boundary L14 of the third via V3 onto the substrate and the orthographic projection of the second sub-electrode 442 near the boundary of the third via V3 onto the substrate along the first direction D1 is equal to 0.

[0263] In an exemplary embodiment, the distance between the orthographic projection of the third boundary L13 of the fourth via V4 onto the substrate and the orthographic projection of the boundary of the second sub-electrode 442 near the fourth via V4 onto the substrate along the first direction D1 is greater than or equal to 0, and the distance between the orthographic projection of the fourth boundary L14 of the fourth via V4 onto the substrate and the orthographic projection of the third branch segment 433 near the boundary of the fourth via V4 onto the substrate along the first direction D1 is greater than or equal to 0. Figure 27 illustrates an example where the distance between the orthographic projection of the third boundary L13 of the fourth via V4 onto the substrate and the orthographic projection of the second sub-electrode 442 near the boundary of the fourth via V4 onto the substrate along the first direction D1 is equal to 0, and the distance between the orthographic projection of the fourth boundary L14 of the fourth via V4 onto the substrate and the orthographic projection of the third branch segment 433 near the boundary of the fourth via V4 onto the substrate along the first direction D1 is equal to 0.

[0264] The orthographic projections of the first and second electrodes on the substrate in the transistor device shown in Figure 27 do not overlap with the orthographic projections of the vias on the substrate, which can reduce the load on the transistor device. However, when there is a misalignment between the first and second electrodes and the gate insulating layer in the first direction, the parasitic capacitance between the gate electrode and the first electrode, as well as the parasitic capacitance between the gate electrode and the second electrode, will fluctuate.

[0265] In an exemplary embodiment, as shown in FIG28, the via includes: a first via V1, a second via V2 and a third via V3, wherein the first via V1, the second via V2 and the third via V3 are arranged along a first direction D1.

[0266] In an exemplary embodiment, as shown in FIG28, the orthographic projection of the first via V1 on the substrate overlaps with the orthographic projection of the first branch segment 431 on the substrate, but does not overlap with the orthographic projection of the first sub-electrode 441 on the substrate. The orthographic projection of the second via V2 on the substrate overlaps with the orthographic projection of the second branch segment 432 on the substrate, but does not overlap with the orthographic projections of the first sub-electrode 441 and the second sub-electrode 442 on the substrate, respectively. The orthographic projection of the third via V3 on the substrate overlaps with the orthographic projection of the third branch segment 433 on the substrate, but does not overlap with the orthographic projection of the second sub-electrode 442 on the substrate.

[0267] In an exemplary embodiment, as shown in FIG28, the orthographic projection of the first branch segment 431 on the substrate at least partially overlaps with the orthographic projections of the first boundary L11, the second boundary L12, and the third boundary L13 of the first via V1 on the substrate; the orthographic projection of the second branch segment 432 on the substrate at least partially overlaps with the orthographic projections of the first boundary L11 and the second boundary L12 of the second via V2 on the substrate; and the orthographic projection of the third branch segment 433 on the substrate at least partially overlaps with the orthographic projections of the first boundary L11, the second boundary L12, and the fourth boundary L14 of the third via V3 on the substrate.

[0268] In an exemplary embodiment, as shown in FIG28, the distance a4 between the orthographic projection of the boundary of the first branch segment 431 near the first sub-electrode 441 on the substrate and the orthographic projection of the third boundary L13 of the first via V1 on the substrate is in the range of 1 micrometer to 1.5 micrometers, and the distance c4 between the orthographic projection of the boundary of the third branch segment 433 near the second sub-electrode 442 on the substrate and the orthographic projection of the fourth boundary L14 of the third via V3 on the substrate is in the range of 1 micrometer to 1.5 micrometers.

[0269] In an exemplary embodiment, as shown in Figures 27 and 28, the orthographic projection of the boundary of at least one of the first sub-electrodes 441 and 442 near the electrode connection segment 434 onto the substrate, and the distance between the first boundary L11 of at least one of the first vias V1, second via V2, and third via V3 along the second direction D2, is greater than the distance between the first boundary L11 and the second boundary L12 of at least one of the first vias V1, second via V2, and third via V3 along the second direction D2. Similarly, the orthographic projection of the boundary of the first branch segment 431 away from the electrode connection segment 434 onto the substrate, and the distance between the second boundary L12 of at least one of the first vias V1, second via V2, and third via V3 along the second direction D2, is greater than the distance between the first boundary L11 and the second boundary L12 of at least one of the first vias V1, second via V2, and third via V3 along the second direction D2.

[0270] In an exemplary embodiment, as shown in Figures 27 and 28, the distance b4 between the orthographic projection of the boundary of at least one of the first sub-electrodes 441 and the second sub-electrodes 442 near the electrode connection segment 434 on the substrate and the orthographic projection of the second boundary L12 of at least one of the first vias V1, the second via V2 and the third via V3 on the substrate along the second direction D2 is in the range of 1 micrometer to 1.5 micrometers.

[0271] In the exemplary embodiment, in the transistor device provided in FIG28, since the orthographic projection of the first electrode of the transistor device on the substrate overlaps with the orthographic projections of the plurality of vias on the substrate, and the orthographic projection of the second electrode of the transistor device on the substrate does not overlap with the orthographic projections of the vias on the substrate, when there is a misalignment between the first electrode and the second electrode relative to the gate insulating layer in the first direction, the parasitic capacitance between the gate electrode and the first electrode and the parasitic capacitance between the gate electrode and the second electrode will not fluctuate. However, since the overlapping area between the vias and the active layer is small, the transistor device provided in FIG28 has a limited effect on improving the turn-on current of the transistor device.

[0272] In an exemplary embodiment, Figure 29 is a top view of the transistor device (Figure 6), Figure 30 is a top view of the transistor device (Figure 7), Figure 31 is a top view of the transistor device (Figure 8), Figure 32 is a top view of the transistor device (Figure 9), and Figure 33 is a top view of the transistor device (Figure 10). As shown in Figures 29 to 33, the first electrode 53 includes: an electrode connection segment 533, a first branch segment 531, and a second branch segment 532. The electrode connection segment 533 extends at least partially along a first direction D1. The first branch segment 531 and the second branch segment 532 are arranged along the first direction D1, and at least one branch segment extends along a second direction D2. The electrode connection segment 533 is connected to the first branch segment 531 and the second branch segment 532, respectively. The first direction D1 intersects with the second direction D2. The second electrode 54 extends along the second direction D2, and the orthographic projection of the second electrode 54 on the substrate is located between the orthographic projection of the first branch segment 531 on the substrate and the orthographic projection of the second branch segment 532 on the substrate; the orthographic projection of the second boundary L12 on the substrate is located on the side of the first boundary L11 close to the orthographic projection of the electrode connection segment 533 on the substrate.

[0273] In an exemplary embodiment, as shown in FIG29, the first boundary L11, the second boundary L12, the third boundary L13, and the fourth boundary L14 are straight lines. The orthographic projection of the electrode connection segment 533 on the substrate does not overlap with the orthographic projections of the multiple boundaries on the substrate. The orthographic projection of the first branch segment 531 on the substrate overlaps with the orthographic projections of the first boundary L11, the second boundary L12, and the third boundary L13 on the substrate, respectively. The orthographic projection of the second branch segment 532 on the substrate overlaps with the orthographic projections of the first boundary L11, the second boundary L12, and the fourth boundary on the substrate, respectively. The orthographic projection of the second electrode 54 on the substrate overlaps with the orthographic projections of the first boundary L11 and the second boundary L12 on the substrate, respectively.

[0274] In an exemplary embodiment, as shown in FIG29, the distance x1 between the orthographic projection of the boundary of the first branch segment 531 near the second electrode 54 on the substrate and the orthographic projection of the third boundary L13 on the substrate along the first direction D1 is in the range of 1 micrometer to 1.5 micrometers; the distance y1 between the orthographic projection of the boundary of the second electrode 54 near the electrode connection segment 533 on the substrate and the orthographic projection of the second boundary L12 on the substrate along the second direction D2 is in the range of 1 micrometer to 1.5 micrometers; and the distance z1 between the orthographic projection of the boundary of the third branch segment near the second electrode 54 on the substrate and the orthographic projection of the fourth boundary on the substrate along the first direction D1 is in the range of 1 micrometer to 1.5 micrometers.

[0275] In the exemplary embodiment, in the transistor device provided in FIG29, since the orthographic projection of the first electrode of the transistor device on the substrate overlaps with the orthographic projections of the third boundary and the fourth boundary on the substrate, respectively, and the orthographic projection of the second electrode of the transistor device on the substrate overlaps with the orthographic projections of the first boundary and the second boundary on the substrate, the parasitic capacitance between the gate electrode and the first electrode and the parasitic capacitance between the gate electrode and the second electrode will not fluctuate when there is a misalignment between the first electrode and the second electrode relative to the gate insulating layer in the first direction. However, since the thickness of the portion of the channel region of the active layer located between the first electrode and the second electrode is not reduced, the transistor device provided in FIG29 has a limited effect on improving the turn-on current of the transistor device.

[0276] In an exemplary embodiment, as shown in Figures 30 and 31, the first boundary L11, the third boundary L13, and the fourth boundary L14 are straight lines, and the shape of the second boundary L12 is adapted to the shape of the electrode connection segment 533. The shape of the electrode connection segment 533 can be an inverted "U".

[0277] In an exemplary embodiment, as shown in Figures 30 and 31, the orthographic projection of the electrode connection segment 533 on the substrate overlaps with the orthographic projection of the second boundary L12 on the substrate; the orthographic projection of the first branch segment 531 on the substrate overlaps with the orthographic projection of the third boundary L13 on the substrate, but does not overlap with the orthographic projection of the first boundary L11 on the substrate; the orthographic projection of the second branch segment 532 on the substrate at least partially overlaps with the orthographic projection of the fourth boundary L14 on the substrate, but does not overlap with the orthographic projection of the first boundary L11 on the substrate; and the orthographic projection of the second electrode 54 on the substrate at least partially overlaps with the orthographic projection of the first boundary L11 on the substrate.

[0278] In an exemplary embodiment, as shown in Figures 30 and 31, the distance x2 between the orthographic projection of the boundary of the first branch segment 531 near the first sub-electrode on the substrate and the orthographic projection of the third boundary L13 on the substrate along the first direction D1 is in the range of 1 micrometer to 1.5 micrometers; the distance y2 between the orthographic projection of the boundary of the electrode connection segment 533 near the second electrode 54 on the substrate and the orthographic projection of the boundary of the second boundary L12 near the second electrode 54 on the substrate along the second direction D2 is in the range of 1 micrometer to 1.5 micrometers; and the distance z2 between the orthographic projection of the boundary of the third branch segment near the second electrode 54 on the substrate and the orthographic projection of the fourth boundary L14 on the substrate along the first direction D1 is in the range of 1 micrometer to 1.5 micrometers.

[0279] In an exemplary embodiment, the via in FIG30 is rectangular in shape.

[0280] In an exemplary embodiment, as shown in FIG31, the multiple boundaries of the via VV further include: a first protruding boundary L21, a second protruding boundary L22, a third protruding boundary L23, a fourth protruding boundary L24, a fifth protruding boundary L25, a sixth protruding boundary L26, a seventh protruding boundary L27, and an eighth protruding boundary L28. The first protruding boundary L21, the third protruding boundary L23, the fifth protruding boundary L25, and the seventh protruding boundary L27 extend along a first direction D1, while the second protruding boundary L22, the fourth protruding boundary L24, the sixth protruding boundary L26, and the eighth protruding boundary L28 extend along a second direction D2.

[0281] In an exemplary embodiment, as shown in FIG31, the third boundary L13 is connected to the first boundary L11 in sequence through the first protruding boundary L21, the second protruding boundary L22, the third protruding boundary L23 and the fourth protruding boundary L24, and the fourth boundary L14 is connected to the first boundary L11 in sequence through the fifth protruding boundary L25, the sixth protruding boundary L26, the seventh protruding boundary L27 and the eighth protruding boundary L28.

[0282] In an exemplary embodiment, as shown in FIG31, the orthographic projections of the first electrode 53 and the second electrode 54 on the substrate do not overlap with the orthographic projections of at least one of the protruding boundaries L21, L22, L23, L24, L25, L26, L27, and L28 on the substrate.

[0283] In an exemplary embodiment, as shown in FIG31, the distance d1 between the second protruding boundary L22 and the fourth protruding boundary L24 along the second direction D2 is in the range of 1 micrometer to 4 micrometers.

[0284] In an exemplary embodiment, as shown in FIG31, the distance d2 between the sixth protruding boundary L26 and the eighth protruding boundary L28 along the second direction D2 is in the range of 1 micrometer to 4 micrometers.

[0285] In the exemplary embodiments, in the transistor devices provided in FIG30 and FIG31, since the orthographic projection of the first electrode of the transistor device on the substrate overlaps with the orthographic projections of the second boundary, the third boundary, and the fourth boundary on the substrate, respectively, and the orthographic projection of the second electrode of the transistor device on the substrate overlaps with the orthographic projection of the first boundary on the substrate, the parasitic capacitance between the first electrode and the second electrode and the gate insulating layer in the first or second direction will not fluctuate when there is a misalignment between the first electrode and the second electrode and the gate insulating layer in the first direction or the second direction. Furthermore, since the thickness of the entire channel region of the active layer located between the first electrode and the second electrode is reduced, the transistor devices provided in FIG30 and FIG31 provide a better improvement in the turn-on current of the transistor device.

[0286] Compared to the transistor device shown in Figure 30, the via VV in Figure 31 has an additional first to eighth protruding branch segments. These first to eighth protruding branch segments can be referred to as optical compensation structures. In the transistor device shown in Figure 31, after exposure, the via structures at the first and third boundaries approach right angles, and the structures at the first and fourth boundaries also approach right angles. This avoids the loss of turn-on current caused by the near-arc structure at the first and third boundaries of the via in the transistor device shown in Figure 30 after exposure, thus improving the performance of the transistor device.

[0287] In an exemplary embodiment, as shown in FIG32, the via VV includes: a first via V1 and a second via V2, wherein the first via V1 and the second via V2 are arranged along a first direction D1.

[0288] In an exemplary embodiment, as shown in FIG32, the orthographic projection of the first via V1 on the substrate is located between the orthographic projection of the first branch segment 531 on the substrate and the orthographic projection of the second electrode 54 on the substrate, and the orthographic projection of the second via V2 on the substrate is located between the orthographic projection of the second electrode 54 on the substrate and the orthographic projection of the second branch segment 532 on the substrate.

[0289] In an exemplary embodiment, as shown in FIG32, the distance between the orthographic projection of the third boundary L13 of the first via V1 on the substrate and the orthographic projection of the boundary of the first branch segment 531 near the first via V1 on the substrate along the first direction D1 is greater than or equal to 0, and the distance between the orthographic projection of the fourth boundary L14 of the first via V1 on the substrate and the orthographic projection of the second electrode 54 near the boundary of the first via V1 on the substrate along the first direction D1 is greater than or equal to 0. FIG32 is illustrated using the example that the distance between the orthographic projection of the third boundary L13 of the first via V1 on the substrate and the orthographic projection of the first branch segment 531 near the boundary of the first via V1 on the substrate along the first direction D1 is equal to 0, and the distance between the orthographic projection of the fourth boundary L14 of the first via V1 on the substrate and the orthographic projection of the second electrode 54 near the boundary of the first via V1 on the substrate along the first direction D1 is equal to 0.

[0290] In an exemplary embodiment, as shown in FIG32, the distance between the orthographic projection of the third boundary L13 of the second via V2 onto the substrate and the orthographic projection of the boundary of the second electrode 54 near the second via V2 onto the substrate along the first direction D1 is greater than or equal to 0, and the distance between the orthographic projection of the fourth boundary L14 of the second via V2 onto the substrate and the orthographic projection of the second branch segment 532 near the boundary of the second via V2 onto the substrate along the first direction D1 is greater than or equal to 0. FIG32 is illustrated using the example where the distance between the orthographic projection of the third boundary L13 of the second via V2 onto the substrate and the orthographic projection of the second electrode 54 near the boundary of the second via V2 onto the substrate along the first direction D1 is equal to 0, and the distance between the orthographic projection of the fourth boundary L14 of the second via V2 onto the substrate and the orthographic projection of the second branch segment 532 near the boundary of the second via V2 onto the substrate along the first direction D1 is equal to 0.

[0291] As shown in Figure 32, the distance y3 between the orthographic projection of the boundary of the second electrode 54 near the electrode connection section 533 on the substrate and the orthographic projection of the second boundary L12 of at least one of the vias on the substrate along the second direction D2 is in the range of 1 micrometer to 1.5 micrometers.

[0292] The orthographic projections of the first and second electrodes on the substrate in the transistor device shown in Figure 32 do not overlap with the orthographic projections of the vias on the substrate, which can reduce the load on the transistor device. However, when there is a misalignment between the first and second electrodes and the gate insulating layer in the first direction, the parasitic capacitance between the gate electrode and the first electrode, as well as the parasitic capacitance between the gate electrode and the second electrode, will fluctuate.

[0293] In an exemplary embodiment, as shown in FIG33, the via includes a first via V1 and a second via V2, wherein the first via V1 and the second via V2 are arranged along a first direction D1.

[0294] In an exemplary embodiment, as shown in FIG33, the orthographic projection of the first via V1 on the substrate at least partially overlaps with the orthographic projection of the first branch segment 531 on the substrate, but does not overlap with the orthographic projection of the second electrode 54 on the substrate. The orthographic projection of the second via V2 on the substrate at least partially overlaps with the orthographic projection of the second branch segment 532 on the substrate, but does not overlap with the orthographic projection of the second electrode 54 on the substrate. The orthographic projection of the first branch segment 531 on the substrate at least partially overlaps with the orthographic projections of the first boundary L11, the second boundary L12, and the third boundary L13 of the first via V1 on the substrate. The orthographic projection of the second branch segment 532 on the substrate at least partially overlaps with the orthographic projections of the first boundary L11, the second boundary L12, and the fourth boundary L14 of the third via V3 on the substrate.

[0295] In an exemplary embodiment, as shown in FIG33, the distance x4 between the orthographic projection of the boundary of the first branch segment 531 near the second electrode 54 on the substrate and the orthographic projection of the third boundary L13 of the first via V1 on the substrate is in the range of 1 micrometer to 1.5 micrometers; the distance y4 between the orthographic projection of the boundary of the second electrode 54 near the electrode connection segment 533 on the substrate and the orthographic projection of the second boundary L12 of at least one of the vias on the substrate along the second direction D2 is in the range of 1 micrometer to 1.5 micrometers; and the distance z4 between the orthographic projection of the boundary of the second branch segment 532 near the second electrode 54 on the substrate and the orthographic projection of the fourth boundary L14 of the second via V2 on the substrate is in the range of 1 micrometer to 1.5 micrometers.

[0296] In an exemplary embodiment, as shown in Figures 32 and 33, the distance between the orthographic projection of the boundary of the second electrode 54 near the electrode connection segment 533 on the substrate and the first boundary L11 of the plurality of vias along the second direction D2 is greater than the distance between the first boundary L11 and the second boundary L12 of the plurality of vias along the second direction D2. The distance between the orthographic projection of the boundary of the first branch segment 531 away from the electrode connection segment 533 on the substrate and the second boundary L12 of at least one of the first vias and the second via V2 along the second direction D2 is greater than the distance between the first boundary L11 and the second boundary L12 of at least one of the first vias and the second via V2 along the second direction D2.

[0297] In the exemplary embodiment, in the transistor device provided in FIG33, since the orthographic projection of the first electrode of the transistor device on the substrate overlaps with the orthographic projections of the plurality of vias on the substrate, and the orthographic projection of the second electrode of the transistor device on the substrate does not overlap with the orthographic projections of the vias on the substrate, when there is a misalignment between the first electrode and the second electrode relative to the gate insulating layer in the first direction, the parasitic capacitance between the gate electrode and the first electrode and the parasitic capacitance between the gate electrode and the second electrode will not fluctuate. However, since the overlapping area between the vias and the active layer is small, the transistor device provided in FIG33 has a limited effect on improving the turn-on current of the transistor device.

[0298] The transistor devices shown in Figures 24 to 28 are equivalent to two transistor devices shown in Figures 29 to 33 connected in parallel. The first electrode in the transistor devices shown in Figures 24 to 33 is U-shaped.

[0299] In an exemplary embodiment, FIG34 is a top view eleven of a transistor device, FIG35 is a top view twelve of a transistor device, FIG36 is a top view thirteen of a transistor device, and FIG37 is a top view fourteen of a transistor device. As shown in FIG34 to FIG37, the transistor device includes: a gate electrode 61, an active layer 62, a first electrode 63, and a second electrode 64. The first electrode 63 and the second electrode 64 extend along a second direction D2. The orthographic projection of the active layer 62 onto the substrate is within the range of the orthographic projection of the gate electrode 61 onto the substrate, and the orthographic projection of the via VV onto the substrate is within the range of the orthographic projection of the active layer 62 onto the substrate. The orthographic projection of a portion of at least one of the first electrode 63 and the second electrode 64 onto the substrate does not overlap with the orthographic projection of the gate electrode 61 onto the substrate.

[0300] In an exemplary embodiment, as shown in Figures 34 to 37, the via includes multiple boundaries, including a first boundary L11, a second boundary L12, a third boundary L13, and a fourth boundary L14. The first boundary L11 and the second boundary L12 extend along a first direction D1, and the third boundary L13 and the fourth boundary L14 extend along a second direction D2. The first boundary L11, the fourth boundary L14, the second boundary L12, and the third boundary L13 are connected sequentially, and the shapes of the first boundary L11, the second boundary L12, the third boundary L13, and the fourth boundary L14 are straight lines. The distance between the orthographic projection of the first target boundary GL1 on the substrate and the orthographic projection of the first boundary L11 on the substrate along the second direction D2 is less than the distance between the orthographic projection of the first target boundary on the substrate and the orthographic projection of the second boundary L12 on the substrate along the second direction D2. The distance between the orthographic projection of the second target boundary GL2 on the substrate and the orthographic projection of the second boundary L12 on the substrate along the second direction D2 is less than the distance between the orthographic projection of the second target boundary on the substrate and the orthographic projection of the first boundary L11 on the substrate along the second direction D2. The first target boundary is the boundary where the first electrode 63 and the active layer 62 overlap and extend along the first direction D1. The second target boundary is the boundary where the second electrode 64 and the active layer 62 overlap and extend along the first direction D1.

[0301] In an exemplary embodiment, as shown in FIG34, the orthographic projection of at least one of the first electrode 63 and the second electrode 64 on the substrate at least partially overlaps with the orthographic projections of the first boundary L11 and the second boundary L12 on the substrate, and does not overlap with the orthographic projections of the third boundary L13 and the fourth boundary L14 on the substrate.

[0302] In an exemplary embodiment, as shown in FIG34, the maximum distance r1 between the orthographic projection of the first electrode 63 near the third boundary L13 on the substrate and the orthographic projection of the third boundary L13 on the substrate along the first direction D1 is in the range of 1 micrometer to 1.5 micrometers; the distance t1 between the orthographic projection of the first target boundary GL1 on the substrate and the orthographic projection of the first boundary L11 on the substrate along the second direction D2 is in the range of 1 micrometer to 1.5 micrometers; the distance t2 between the orthographic projection of the second target boundary GL2 on the substrate and the orthographic projection of the second boundary L12 on the substrate along the second direction D2 is in the range of 1 micrometer to 1.5 micrometers; and the maximum distance s1 between the orthographic projection of the second electrode 64 near the fourth boundary L14 on the substrate and the orthographic projection of the fourth boundary L14 on the substrate along the first direction D1 is in the range of 1 micrometer to 1.5 micrometers.

[0303] In the exemplary embodiment, in the transistor device provided in FIG34, since the orthographic projections of the first electrode and the second electrode of the transistor device on the substrate overlap with the orthographic projections of the first boundary and the second boundary on the substrate, respectively, when there is an alignment deviation between the first electrode and the second electrode relative to the gate insulating layer in the first and second directions, the parasitic capacitance between the gate electrode and the first electrode, as well as the parasitic capacitance between the gate electrode and the second electrode, will not fluctuate. However, the channel region of the active layer has a large thinning area; therefore, the transistor device provided in FIG34 has a significant effect on improving the turn-on current of the transistor device.

[0304] In an exemplary embodiment, as shown in Figures 35 and 36, the orthographic projection of the via VV on the substrate does not overlap with the orthographic projections of the first electrode 63 and the second electrode 64 on the substrate.

[0305] In an exemplary embodiment, as shown in Figures 35 and 36, the distance between the orthographic projection of the first electrode 63 near the boundary of the via VV on the substrate and the orthographic projection of the third boundary L13 of the via VV on the substrate along the first direction D1 is greater than or equal to 0, and the distance between the orthographic projection of the second electrode 64 near the boundary of the via VV on the substrate and the orthographic projection of the fourth boundary L14 of the via VV on the substrate along the first direction D1 is greater than or equal to 0. Figures 35 and 36 are illustrated using the example where the distance between the orthographic projection of the first electrode 63 near the boundary of the via VV on the substrate and the orthographic projection of the third boundary L13 of the via VV on the substrate along the first direction D1 is equal to 0, and the distance between the orthographic projection of the second electrode 64 near the boundary of the via VV on the substrate and the orthographic projection of the fourth boundary L14 of the via VV on the substrate along the first direction D1 is equal to 0.

[0306] In an exemplary embodiment, as shown in FIG35, the shape of the active layer 62 is adapted to the shape of the gate electrode 61. The distance between the orthographic projection of the boundary of the active layer 62 near the first boundary L11 on the substrate and the orthographic projection of the first boundary L11 on the substrate along the second direction D2 is greater than the distance between the orthographic projection of the boundary of the active layer 62 near the first boundary L11 on the substrate and the orthographic projection of the first target boundary GL1 on the substrate along the second direction D2; the distance between the orthographic projection of the boundary of the active layer 62 near the second boundary L12 on the substrate and the orthographic projection of the second boundary L12 on the substrate along the second direction D2 is greater than the distance between the orthographic projection of the boundary of the active layer 62 near the second boundary L12 on the substrate and the orthographic projection of the second target boundary GL2 on the substrate along the second direction D2.

[0307] In an exemplary embodiment, as shown in FIG36, the distance between the orthographic projection of the active layer 62 near the first boundary L11 on the substrate and the orthographic projection of the first boundary L11 on the substrate along the second direction D2 is less than the distance between the orthographic projection of the active layer 62 near the first boundary L11 on the substrate and the orthographic projection of the first target boundary GL1 on the substrate along the second direction D2; the distance between the orthographic projection of the active layer 62 near the second boundary L12 on the substrate and the orthographic projection of the second boundary L12 on the substrate along the second direction D2 is also less than the distance between the orthographic projection of the active layer 62 near the second boundary L12 on the substrate and the orthographic projection of the second target boundary GL2 on the substrate along the second direction D2.

[0308] In an exemplary embodiment, the orthographic projections of the first electrode and the second electrode on the substrate in the transistor device provided in Figures 35 and 36 do not overlap with the orthographic projections of the via on the substrate, which can reduce the load on the transistor device. However, when there is an alignment deviation between the first electrode and the second electrode relative to the gate insulating layer in the first direction, the parasitic capacitance between the gate electrode and the first electrode and the parasitic capacitance between the gate electrode and the second electrode will fluctuate.

[0309] In an exemplary embodiment, as shown in FIG37, the orthographic projection of the via VV on the substrate partially overlaps with the orthographic projection of the first electrode 63 on the substrate, but does not overlap with the orthographic projection of the second electrode 64 on the substrate. The orthographic projection of the first electrode 63 on the substrate overlaps with the orthographic projections of the first boundary L11 and the second boundary L12 on the substrate, respectively.

[0310] In an exemplary embodiment, as shown in FIG37, the distance t1 between the orthographic projection of the boundary of the second electrode 64 near the third boundary L13 on the substrate and the orthographic projection of the third boundary L13 on the substrate along the first direction D1 is in the range of 1 micrometer to 1.5 micrometers; the maximum distance s2 between the orthographic projection of the boundary of the first electrode 63 near the fourth boundary L14 on the substrate and the orthographic projection of the fourth boundary L14 on the substrate along the first direction D1 is in the range of 1 micrometer to 1.5 micrometers; the distance t1 between the orthographic projection of the first target boundary GL1 on the substrate and the orthographic projection of the first boundary L11 on the substrate along the second direction D2 is in the range of 1 micrometer to 1.5 micrometers; and the distance t2 between the orthographic projection of the second target boundary GL2 on the substrate and the orthographic projection of the second boundary L12 on the substrate along the second direction D2 is in the range of 1 micrometer to 1.5 micrometers.

[0311] In an exemplary embodiment, as shown in FIG37, the active layer 62 is shaped to match the gate electrode 61. The distance between the orthographic projection of the active layer 62 near the first boundary L11 on the substrate and the orthographic projection of the first boundary L11 on the substrate along the second direction D2 is greater than the distance between the orthographic projection of the active layer 62 near the first boundary L11 on the substrate and the orthographic projection of the first target boundary GL1 on the substrate along the second direction D2. The distance between the orthographic projection of the active layer 62 near the second boundary L12 on the substrate and the orthographic projection of the second boundary L12 on the substrate along the second direction D2 is greater than the distance between the orthographic projection of the active layer 62 near the second boundary L12 on the substrate and the orthographic projection of the second target boundary GL2 on the substrate along the second direction D2.

[0312] In the exemplary embodiment, in the transistor device provided in FIG37, since the orthographic projection of the first electrode of the transistor device on the substrate overlaps with the orthographic projection of the via on the substrate, and the orthographic projection of the second electrode of the transistor device on the substrate does not overlap with the orthographic projection of the via on the substrate, when there is a misalignment between the first electrode and the second electrode relative to the gate insulating layer in the first direction, the parasitic capacitance between the gate electrode and the first electrode and the parasitic capacitance between the gate electrode and the second electrode will not fluctuate. However, since the overlapping area between the via and the active layer is small, the transistor device provided in FIG37 has a limited effect on improving the turn-on current of the transistor device.

[0313] In an exemplary embodiment, FIG38 is a top view of a transistor device, FIG39 is a top view of a transistor device, FIG40 is a top view of a transistor device, FIG41 is a top view of a transistor device, and FIG42 is a top view of a transistor device. As shown in FIG38 to FIG42, the transistor device includes: a gate electrode 71, an active layer 72, a first electrode 73, and a second electrode 74.

[0314] In an exemplary embodiment, as shown in Figures 38 to 42, the first electrode 73 includes a first electrode connection portion 731 and a second electrode connection portion 732 connected to each other. The first electrode connection portion 731 extends along a first direction D1, and the second electrode connection portion 732 extends along a second direction D2. A portion of the orthographic projection of the first electrode connection portion 731 onto the substrate overlaps with a portion of the orthographic projection of the active layer 72 onto the substrate. Another portion of the orthographic projection of the first electrode connection portion 731 onto the substrate does not overlap with the orthographic projection of the gate electrode onto the substrate. The orthographic projection of the second electrode connection portion 732 onto the substrate is located within the range of the orthographic projection of the active layer 72 onto the substrate. The orthographic projection of the active layer 72 onto the substrate is located within the range of the orthographic projection of the gate electrode 71 onto the substrate. The orthographic projection of the via VV onto the substrate is located within the range of the orthographic projection of the active layer 72 onto the substrate. A portion of the orthographic projection of the second electrode 74 onto the substrate overlaps with a portion of the orthographic projection of the active layer 72 onto the substrate. Another portion of the orthographic projection of the second electrode 74 onto the substrate does not overlap with the orthographic projection of the gate electrode onto the substrate.

[0315] In an exemplary embodiment, as shown in Figures 38 to 42, the via VV includes multiple boundaries, including a first boundary L11, a second boundary L12, a third boundary L13, and a fourth boundary L14. The first boundary L11 and the second boundary L12 extend along a first direction D1, and the third boundary L13 and the fourth boundary L14 extend along a second direction D2. The first boundary L11, the fourth boundary L14, the second boundary L12, and the third boundary L13 are connected sequentially, and the shapes of the first boundary L11, the second boundary L12, the third boundary L13, and the fourth boundary L14 are straight lines. The distance between the orthographic projection of the first target boundary GL1 on the substrate and the orthographic projection of the first boundary L11 on the substrate along the second direction D2 is less than the distance between the orthographic projection of the first target boundary GL1 on the substrate and the orthographic projection of the second boundary L12 on the substrate along the second direction D2. The distance between the orthographic projection of the second target boundary GL2 on the substrate and the orthographic projection of the second boundary L12 on the substrate along the second direction D2 is less than the distance between the orthographic projection of the second target boundary GL2 on the substrate and the orthographic projection of the first boundary L11 on the substrate along the second direction D2. The first target boundary GL1 is the boundary of the second electrode connection portion 732 that is close to the first boundary L11 and extends along the first direction D1. The second target boundary GL2 is the boundary of the second electrode connection portion 732 that is close to the first boundary L11 and extends along the first direction D1.

[0316] In an exemplary embodiment, as shown in FIG38, the orthographic projection of the first electrode connection portion 731 and the third boundary L13 on the substrate at least partially overlaps, the orthographic projection of the second electrode connection portion 732 on the substrate does not overlap with the orthographic projections of the plurality of boundaries on the substrate, the orthographic projection of the second electrode 74 on the substrate partially overlaps with the orthographic projections of the first boundary L11 and the second boundary L12 on the substrate, and the orthographic projection of the fourth boundary L14 on the substrate does not overlap.

[0317] In the exemplary embodiment, in the transistor device provided in FIG38, since the orthographic projection of the first electrode on the substrate overlaps with the orthographic projection of the third boundary on the substrate, and the orthographic projection of the second electrode on the substrate overlaps with the orthographic projections of the first boundary and the second boundary on the substrate respectively, the parasitic capacitance between the gate electrode and the first electrode and the parasitic capacitance between the gate electrode and the second electrode will not fluctuate when there is an alignment deviation between the first electrode and the second electrode relative to the gate insulating layer in the first and second directions. However, the channel region of the active layer has a large thinning area, therefore, the transistor device provided in FIG38 has a significant effect on improving the turn-on current of the transistor device.

[0318] In an exemplary embodiment, as shown in FIG39, the orthographic projection of the first electrode connection portion 731 on the substrate at least partially overlaps with the orthographic projection of the third boundary L13 on the substrate, the orthographic projection of the second electrode connection portion 732 on the substrate partially overlaps with the orthographic projections of the first boundary L11 and the second boundary L12 on the substrate, the orthographic projection of the second electrode 74 on the substrate partially overlaps with the orthographic projections of the first boundary L11 and the second boundary L12 on the substrate, and the orthographic projection of the fourth boundary L14 on the substrate does not overlap.

[0319] In the exemplary embodiment, in the transistor device provided in FIG39, since the orthographic projection of the first electrode of the transistor device on the substrate overlaps with the orthographic projections of the first boundary, the second boundary, and the third boundary on the substrate, and the orthographic projection of the second electrode of the transistor device on the substrate overlaps with the orthographic projections of the first boundary and the second boundary on the substrate, the parasitic capacitance between the gate electrode and the first electrode and the parasitic capacitance between the gate electrode and the second electrode will not fluctuate when there is a misalignment between the first electrode and the second electrode relative to the gate insulating layer in the first and second directions. However, the channel region thinning area of ​​the active layer is not large; therefore, the transistor device provided in FIG39 is effective in improving the turn-on current of the transistor device.

[0320] In an exemplary embodiment, as shown in Figures 40 and 41, the orthographic projection of the via VV on the substrate does not overlap with the orthographic projections of the first electrode 73 and the second electrode 74 on the substrate, and is located between the orthographic projection of the second electrode connection portion 732 on the substrate and the orthographic projection of the second electrode 74 on the substrate.

[0321] In an exemplary embodiment, as shown in Figures 40 and 41, the distance t1 between the orthographic projection of the first target boundary GL1 on the substrate and the orthographic projection of the first boundary L11 on the substrate along the second direction D2 is in the range of 1 micrometer to 1.5 micrometers, and the distance t2 between the orthographic projection of the second target boundary GL2 on the substrate and the orthographic projection of the second boundary L12 on the substrate along the second direction D2 is in the range of 1 micrometer to 1.5 micrometers.

[0322] In an exemplary embodiment, as shown in Figures 40 and 41, the distance between the orthographic projection of the boundary of the first electrode 73 near the via VV onto the substrate and the orthographic projection of the third boundary L13 of the via VV onto the substrate along the first direction D1 is greater than or equal to 0, and the distance between the orthographic projection of the boundary of the second electrode 74 near the via VV onto the substrate and the orthographic projection of the fourth boundary L14 of the via onto the substrate along the first direction D1 is greater than or equal to 0. Figures 40 and 41 are illustrated using the example where the distance between the orthographic projection of the boundary of the first electrode 73 near the via VV onto the substrate and the orthographic projection of the third boundary L13 of the via VV onto the substrate along the first direction D1 is equal to 0, and the distance between the orthographic projection of the boundary of the second electrode 74 near the via VV onto the substrate and the orthographic projection of the fourth boundary L14 of the via onto the substrate along the first direction D1 is equal to 0.

[0323] In an exemplary embodiment, as shown in FIG40, the shape of the active layer 72 is adapted to the shape of the gate electrode 71. The distance between the orthographic projection of the boundary of the active layer 72 near the first boundary L11 on the substrate and the orthographic projection of the first boundary L11 on the substrate along the second direction D2 is greater than the distance between the orthographic projection of the boundary of the active layer 72 near the first boundary L11 on the substrate and the orthographic projection of the first target boundary GL1 on the substrate along the second direction D2; the distance between the orthographic projection of the boundary of the active layer 72 near the second boundary L12 on the substrate and the orthographic projection of the second boundary L12 on the substrate along the second direction D2 is greater than the distance between the orthographic projection of the boundary of the active layer 72 near the second boundary L12 on the substrate and the orthographic projection of the second target boundary GL2 on the substrate along the second direction D2.

[0324] In an exemplary embodiment, as shown in FIG41, the distance between the orthographic projection of the active layer 72 near the first boundary L11 on the substrate and the orthographic projection of the first boundary L11 on the substrate along the second direction D2 is less than the distance between the orthographic projection of the active layer 72 near the first boundary L11 on the substrate and the orthographic projection of the first target boundary GL1 on the substrate along the second direction D2; the distance between the orthographic projection of the active layer 72 near the second boundary L12 on the substrate and the orthographic projection of the second boundary L12 on the substrate along the second direction D2 is also less than the distance between the orthographic projection of the active layer 72 near the second boundary L12 on the substrate and the orthographic projection of the second target boundary GL2 on the substrate along the second direction D2.

[0325] The orthographic projections of the first and second electrodes on the substrate in the transistor devices shown in Figures 40 and 41 do not overlap with the orthographic projections of the vias on the substrate, which can reduce the load on the transistor device. However, when there is a misalignment between the first and second electrodes and the gate insulating layer in the first direction, the parasitic capacitance between the gate electrode and the first electrode, as well as the parasitic capacitance between the gate electrode and the second electrode, will fluctuate.

[0326] In an exemplary embodiment, as shown in FIG42, the orthographic projection of the via VV on the substrate overlaps with the orthographic projection of the first electrode 73 on the substrate, but does not overlap with the orthographic projection of the second electrode 74 on the substrate. The orthographic projection of the first electrode connection portion 731 on the substrate overlaps with the orthographic projection of the third boundary L13 on the substrate, and the orthographic projection of the second electrode connection portion 732 on the substrate overlaps with the orthographic projections of the first boundary L11 and the second boundary L12 on the substrate, respectively.

[0327] In an exemplary embodiment, as shown in FIG42, the active layer 72 is shaped to match the gate electrode 71. The distance between the orthographic projection of the active layer 72 near the first boundary L11 on the substrate and the orthographic projection of the first boundary L11 on the substrate along the second direction D2 is greater than the distance between the orthographic projection of the active layer 72 near the first boundary L11 on the substrate and the orthographic projection of the first target boundary GL1 on the substrate along the second direction D2. The distance between the orthographic projection of the active layer 72 near the second boundary L12 on the substrate and the orthographic projection of the second boundary L12 on the substrate along the second direction D2 is greater than the distance between the orthographic projection of the active layer 72 near the second boundary L12 on the substrate and the orthographic projection of the second target boundary GL2 on the substrate along the second direction D2.

[0328] In the exemplary embodiment, in the transistor device provided in FIG42, since the orthographic projection of the first electrode of the transistor device on the substrate overlaps with the orthographic projection of the via on the substrate, and the orthographic projection of the second electrode of the transistor device on the substrate does not overlap with the orthographic projection of the via on the substrate, when there is an alignment deviation between the first electrode and the second electrode relative to the gate insulating layer in the first direction, the parasitic capacitance between the gate electrode and the first electrode and the parasitic capacitance between the gate electrode and the second electrode will not fluctuate. However, since the overlapping area between the via and the active layer is small, the transistor device provided in FIG42 has a limited effect on improving the turn-on current of the transistor device.

[0329] In an exemplary embodiment, FIG43 is a top view of a transistor device, FIG44 is a top view of a transistor device, FIG45 is a top view of a transistor device, FIG46 is a top view of a transistor device, and FIG47 is a top view of a transistor device. As shown in FIG43 to FIG47, the transistor device includes: a gate electrode 81, an active layer 82, a first electrode 83, and a second electrode 84.

[0330] In an exemplary embodiment, as shown in Figures 43 to 47, the active layer 82 includes: a first active connection portion 821 and a second active connection portion 822 connected to each other, the first active connection portion 821 extending at least partially along a first direction D1, and the second active connection portion 822 extending at least partially along a second direction D2; the first electrode 83 includes: a first electrode connection portion 831 and a second electrode connection portion 832 connected to each other, the first electrode connection portion 831 extending along the first direction D1, and the second electrode connection portion 832 extending along the second direction D2. In this configuration, the orthographic projection of a portion of the first active connection portion 821 onto the substrate overlaps with the orthographic projection of the gate electrode 81 onto the substrate; the orthographic projection of another portion of the first electrode connection portion 831 onto the substrate does not overlap with the orthographic projection of the gate electrode 81 onto the substrate; the orthographic projection of a portion of the second active connection portion 822 onto the substrate overlaps with the orthographic projection of the gate electrode 81 onto the substrate; the orthographic projection of another portion of the second electrode connection portion 832 onto the substrate does not overlap with the orthographic projection of the gate electrode 81 onto the substrate; the orthographic projection of the first electrode 83 onto the substrate is within the range of the orthographic projection of the first active connection portion 821 onto the substrate; and the orthographic projection of the second electrode 84 onto the substrate is within the range of the orthographic projection of the second active connection portion 822 onto the substrate.

[0331] In an exemplary embodiment, as shown in Figures 43 to 47, the orthographic projection of the via VV on the substrate is within the range of the orthographic projection of the active layer 82 on the substrate, and overlaps with the orthographic projections of the first active connection portion 821 and the second active connection portion 822 on the substrate.

[0332] In an exemplary embodiment, as shown in Figures 43 to 47, the via includes multiple boundaries, including a first boundary L11, a second boundary L12, a third boundary L13, and a fourth boundary L14. The first boundary L11 and the second boundary L12 extend along a first direction D1, and the third boundary L13 and the fourth boundary L14 extend along a second direction D2. The first boundary L11, the fourth boundary L14, the second boundary L12, and the third boundary L13 are connected sequentially, and the shapes of the first boundary L11, the second boundary L12, the third boundary L13, and the fourth boundary L14 are straight lines. The orthographic projection of the first target boundary GL1 on the substrate and the orthographic projection of the first boundary L11 on the substrate are along the second direction D2. The distance between directions D2 is less than the distance between the orthographic projection of the first target boundary GL1 on the substrate and the orthographic projection of the second boundary L12 on the substrate along the second direction D2. The distance between the orthographic projection of the second target boundary GL2 on the substrate and the orthographic projection of the second boundary L12 on the substrate along the second direction D2 is less than the distance between the orthographic projection of the second target boundary GL2 on the substrate and the orthographic projection of the first boundary L11 on the substrate along the second direction D2. The first target boundary GL1 is the boundary of the second electrode connection portion that is close to the first boundary L11 and extends along the first direction D1. The second target boundary GL2 is the boundary of the second electrode connection portion that is close to the first boundary L11 and extends along the first direction D1.

[0333] In an exemplary embodiment, as shown in FIG43, the orthographic projection of the first electrode connection portion 831 and the third boundary L13 on the substrate at least partially overlaps, the orthographic projection of the second electrode connection portion 832 on the substrate does not overlap with the orthographic projections of the plurality of boundaries on the substrate, the orthographic projection of the second electrode 84 on the substrate partially overlaps with the orthographic projections of the first boundary L11 and the second boundary L12 on the substrate, and the orthographic projection of the fourth boundary L14 on the substrate does not overlap.

[0334] In the exemplary embodiment, in the transistor device provided in FIG43, since the orthographic projection of the first electrode on the substrate overlaps with the orthographic projection of the third boundary on the substrate, and the orthographic projection of the second electrode on the substrate overlaps with the orthographic projections of the first boundary and the second boundary on the substrate respectively, the parasitic capacitance between the gate electrode and the first electrode and the parasitic capacitance between the gate electrode and the second electrode will not fluctuate when there is an alignment deviation between the first electrode and the second electrode relative to the gate insulating layer in the first and second directions. However, the channel region of the active layer has a large thinning area, therefore, the transistor device provided in FIG43 has a significant effect on improving the turn-on current of the transistor device.

[0335] In an exemplary embodiment, as shown in FIG44, the orthographic projection of the first electrode connection portion 831 on the substrate at least partially overlaps with the orthographic projection of the third boundary L13 on the substrate, the orthographic projection of the second electrode connection portion 832 on the substrate partially overlaps with the orthographic projections of the first boundary L11 and the second boundary L12 on the substrate, the orthographic projection of the second electrode 74 on the substrate partially overlaps with the orthographic projections of the first boundary L11 and the second boundary L12 on the substrate, and the orthographic projection of the fourth boundary L14 on the substrate does not overlap.

[0336] In the exemplary embodiment, in the transistor device provided in FIG44, since the orthographic projection of the first electrode of the transistor device on the substrate overlaps with the orthographic projections of the first boundary, the second boundary, and the third boundary on the substrate, and the orthographic projection of the second electrode of the transistor device on the substrate overlaps with the orthographic projections of the first boundary and the second boundary on the substrate, the parasitic capacitance between the gate electrode and the first electrode and the parasitic capacitance between the gate electrode and the second electrode will not fluctuate when there is a misalignment between the first electrode and the second electrode relative to the gate insulating layer in the first and second directions. However, the channel region thinning area of ​​the active layer is not large; therefore, the transistor device provided in FIG44 is effective in improving the turn-on current of the transistor device.

[0337] In an exemplary embodiment, as shown in Figures 45 and 46, the orthographic projection of the via VV on the substrate does not overlap with the orthographic projections of the first electrode 83 and the second electrode 84 on the substrate, and is located between the orthographic projection of the second electrode connection portion 832 on the substrate and the orthographic projection of the second electrode 84 on the substrate.

[0338] In an exemplary embodiment, as shown in Figures 45 and 46, the distance between the orthographic projection of the first electrode 83 near the boundary of the via VV on the substrate and the orthographic projection of the third boundary L13 of the via VV on the substrate along the first direction D1 is greater than or equal to 0, and the distance between the orthographic projection of the second electrode 84 near the boundary of the via VV on the substrate and the orthographic projection of the fourth boundary L14 of the via on the substrate along the first direction D1 is greater than or equal to 0. Figures 45 and 46 are illustrated using the example where the distance between the orthographic projection of the first electrode 83 near the boundary of the via VV on the substrate and the orthographic projection of the third boundary L13 of the via VV on the substrate along the first direction D1 is equal to 0, and the distance between the orthographic projection of the second electrode 84 near the boundary of the via VV on the substrate and the orthographic projection of the fourth boundary L14 of the via on the substrate along the first direction D1 is equal to 0.

[0339] In an exemplary embodiment, as shown in FIG45, the distance between the orthographic projection of the active layer 82 near the first boundary L11 on the substrate and the orthographic projection of the first boundary L11 on the substrate along the second direction D2 is greater than the distance between the orthographic projection of the active layer 82 near the first boundary L11 on the substrate and the orthographic projection of the first target boundary GL1 on the substrate along the second direction D2; the distance between the orthographic projection of the active layer 82 near the second boundary L12 on the substrate and the orthographic projection of the second boundary L12 on the substrate along the second direction D2 is greater than the distance between the orthographic projection of the active layer 82 near the second boundary L12 on the substrate and the orthographic projection of the second target boundary GL2 on the substrate along the second direction D2.

[0340] In an exemplary embodiment, as shown in FIG46, the distance between the orthographic projection of the active layer 82 near the first boundary L11 on the substrate and the orthographic projection of the first boundary L11 on the substrate along the second direction D2 is less than the distance between the orthographic projection of the active layer 82 near the first boundary L11 on the substrate and the orthographic projection of the first target boundary GL1 on the substrate along the second direction D2; the distance between the orthographic projection of the active layer 82 near the second boundary L12 on the substrate and the orthographic projection of the second boundary L12 on the substrate along the second direction D2 is also less than the distance between the orthographic projection of the active layer 82 near the second boundary L12 on the substrate and the orthographic projection of the second target boundary GL2 on the substrate along the second direction D2.

[0341] In an exemplary embodiment, as shown in Figures 45 and 46, the distance t1 between the orthographic projection of the first target boundary GL1 on the substrate and the orthographic projection of the first boundary L11 on the substrate along the second direction D2 is in the range of 1 micrometer to 1.5 micrometers, and the distance t2 between the orthographic projection of the second target boundary GL2 on the substrate and the orthographic projection of the second boundary L12 on the substrate along the second direction D2 is in the range of 1 micrometer to 1.5 micrometers.

[0342] The orthographic projections of the first and second electrodes on the substrate in the transistor devices shown in Figures 45 and 46 do not overlap with the orthographic projections of the vias on the substrate, which can reduce the load on the transistor device. However, when there is a misalignment between the first and second electrodes and the gate insulating layer in the first direction, the parasitic capacitance between the gate electrode and the first electrode, as well as the parasitic capacitance between the gate electrode and the second electrode, will fluctuate.

[0343] In an exemplary embodiment, as shown in FIG47, the orthographic projection of the via VV on the substrate overlaps with the orthographic projection of the first electrode 83 on the substrate, but does not overlap with the orthographic projection of the second electrode 84 on the substrate. The orthographic projection of the first electrode connection portion 831 on the substrate overlaps with the orthographic projection of the third boundary L13 on the substrate, and the orthographic projection of the second electrode connection portion 832 on the substrate overlaps with the orthographic projections of the first boundary L11 and the second boundary L12 on the substrate, respectively.

[0344] In an exemplary embodiment, as shown in FIG47, the distance between the orthographic projection of the active layer 82 near the first boundary L11 on the substrate and the orthographic projection of the first boundary L11 on the substrate along the second direction D2 is greater than the distance between the orthographic projection of the active layer 82 near the first boundary L11 on the substrate and the orthographic projection of the first target boundary GL1 on the substrate along the second direction D2, and the distance between the orthographic projection of the active layer 82 near the second boundary L12 on the substrate and the orthographic projection of the second boundary L12 on the substrate along the second direction D2 is greater than the distance between the orthographic projection of the active layer 82 near the second boundary L12 on the substrate and the orthographic projection of the second target boundary GL2 on the substrate along the second direction D2.

[0345] In the exemplary embodiment, in the transistor device provided in FIG43, since the orthographic projection of the first electrode of the transistor device on the substrate overlaps with the orthographic projection of the via on the substrate, and the orthographic projection of the second electrode of the transistor device on the substrate does not overlap with the orthographic projection of the via on the substrate, when there is a misalignment between the first electrode and the second electrode relative to the gate insulating layer in the first direction, the parasitic capacitance between the gate electrode and the first electrode and the parasitic capacitance between the gate electrode and the second electrode will not fluctuate. However, since the overlapping area between the via and the active layer is small, the transistor device provided in FIG43 has a limited effect on improving the turn-on current of the transistor device.

[0346] Figure 48 is a top view of a transistor device, Figure 49 is a top view of a transistor device, Figure 50 is a top view of a transistor device, Figure 51 is a top view of a transistor device, Figure 52 is a top view of a transistor device, Figure 53 is a top view of a transistor device, and Figure 54 is a top view of a transistor device. As shown in Figures 48 to 54, the transistor device includes: a gate electrode 91, an active layer 92, a first electrode 93, and a second electrode 94.

[0347] In an exemplary embodiment, as shown in Figures 48 to 54, the first electrode 93 includes a first electrode connecting portion 931, a second electrode connecting portion 932, a third electrode connecting portion 933, and a fourth electrode connecting portion 934. The first electrode connecting portion 931 and the fourth electrode connecting portion 934 extend along a first direction D1, the third electrode connecting portion 933 extends along a second direction D2, the second electrode connecting portion 932 is connected to both the first electrode connecting portion 931 and the third electrode connecting portion 933, and the first electrode connecting portion 931 and the second electrode connecting portion 932 are set at an obtuse angle, the second electrode connecting portion 932 and the third electrode connecting portion 933 are set at an obtuse angle, the fourth electrode connecting portion 934 and the third electrode connecting portion 933 are set at a right angle, and the second electrode 94 extends along the second direction D2. The orthographic projection of a portion of at least one of the first electrode 93 and the second electrode 94 onto the substrate does not overlap with the orthographic projection of the gate electrode 91 onto the substrate.

[0348] In an exemplary embodiment, as shown in Figures 48 to 54, the orthographic projection of the active layer 92 on the substrate is within the range of the orthographic projection of the gate electrode 91 on the substrate.

[0349] In an exemplary embodiment, as shown in FIG48, the orthographic projection of the active layer 92 on the substrate is within the range of the orthographic projection of the via on the substrate, or the orthographic projection of the via on the substrate is within the range of the orthographic projection of the active layer 92 on the substrate. The via includes: a first boundary L11, a second boundary L12, a third boundary L13, and a fourth boundary L14; the first boundary L11 and the second boundary L12 extend along a first direction D1, and the third boundary L13 and the fourth boundary L14 extend along a second direction D2. The first boundary L11, the fourth boundary L14, the second boundary L12, and the third boundary L13 are connected sequentially, and the shapes of the first boundary L11, the second boundary L12, the third boundary L13, and the fourth boundary L14 are straight lines.

[0350] In an exemplary embodiment, as shown in FIG48, the orthographic projection of the second electrode 94 on the substrate overlaps with the orthographic projection of the second boundary L12 on the substrate, the orthographic projection of the first electrode connection portion 931 on the substrate overlaps with the orthographic projection of the third boundary L13 on the substrate, the orthographic projections of the second electrode connection portion 932 and the third electrode connection portion 933 on the substrate do not overlap with the orthographic projections of the plurality of boundaries on the substrate, and the orthographic projection of the fourth electrode connection portion 934 on the substrate overlaps with the orthographic projection of the fourth boundary L14 on the substrate.

[0351] In the exemplary embodiment, in the transistor device provided in FIG48, since the orthographic projection of the first electrode of the transistor device on the substrate overlaps with the orthographic projections of the third boundary and the fourth boundary on the substrate, respectively, and the orthographic projection of the second electrode of the transistor device on the substrate overlaps with the orthographic projection of the second boundary on the substrate, the parasitic capacitance between the first electrode and the second electrode and the gate insulating layer in the first direction will not fluctuate. However, since the thickness of the channel region of the active layer located between the first electrode and the second electrode is completely reduced, the transistor device provided in FIG48 has a significant effect on improving the turn-on current of the transistor device.

[0352] In an exemplary embodiment, as shown in FIG49, the orthographic projection of the via VV on the substrate is located within the range of the orthographic projection of the active layer 92 on the substrate. The via VV includes: a first boundary L21, a second boundary L22, a third boundary L23, a fourth boundary L24, and a fifth boundary L25. The first boundary L21 and the second boundary L22 extend along a first direction D1, and the third boundary L23 and the fourth boundary L24 extend along a second direction D2. The first boundary L21, the fifth boundary L25, the fourth boundary L24, the second boundary L22, and the third boundary L23 are connected in sequence. The first boundary L21, the second boundary L22, the third boundary L23, the fourth boundary L24, and the fifth boundary L25 are straight lines. The fifth boundary L25 is set at an obtuse angle to the first boundary L21, and the fourth boundary L24 is set at an obtuse angle to the fifth boundary L25.

[0353] In an exemplary embodiment, as shown in FIG49, the orthographic projection of the first electrode connection portion 931 on the substrate overlaps with the orthographic projections of the first boundary L21 and the third boundary L23 on the substrate, respectively; the orthographic projection of the second electrode connection portion 932 on the substrate overlaps with the orthographic projection of the fifth boundary on the substrate; the orthographic projection of the third electrode connection portion 933 on the substrate overlaps with the orthographic projection of the fourth boundary L24 on the substrate; and the orthographic projection of the fourth electrode connection portion 934 on the substrate does not overlap with the orthographic projections of the plurality of boundaries on the substrate.

[0354] In the exemplary embodiment, in the transistor device provided in FIG49, since the orthographic projection of the first electrode of the transistor device on the substrate overlaps with the orthographic projections of the first boundary, the third boundary, the fourth boundary, and the fifth boundary on the substrate, respectively, and the orthographic projection of the second electrode of the transistor device on the substrate overlaps with the orthographic projection of the second boundary on the substrate, when there is a misalignment between the first electrode and the second electrode relative to the gate insulating layer in the first direction, the parasitic capacitance between the gate electrode and the first electrode, as well as the parasitic capacitance between the gate electrode and the second electrode, will not fluctuate. The thickness of the channel region of the active layer located between the first electrode and the second electrode is reduced; therefore, the transistor device provided in FIG49 has a significant effect on improving the turn-on current of the transistor device.

[0355] In an exemplary embodiment, as shown in FIG54, the orthographic projection of the via VV on the substrate is located within the range of the orthographic projection of the active layer 92 on the substrate. The via VV includes: a first boundary L41, a second boundary L42, a third boundary L43, a fourth boundary L44, and a fifth boundary L45. The first boundary L41 and the second boundary L42 extend along a first direction D1, and the third boundary L43 and the fourth boundary L44 extend along a second direction D2. The first boundary L41, the fifth boundary L45, the fourth boundary L44, the second boundary L42, and the third boundary L43 are connected in sequence. The first boundary L41, the second boundary L42, the third boundary L43, the fourth boundary L44, and the fifth boundary L45 are straight lines. The fifth boundary L45 is set at an obtuse angle to the first boundary L41, and the fourth boundary L44 is set at an obtuse angle to the fifth boundary L45.

[0356] In an exemplary embodiment, as shown in FIG54, the orthographic projection of the first electrode 93 on the substrate does not overlap with the orthographic projections of the plurality of boundaries on the substrate, the orthographic projection of the second electrode 93 on the substrate overlaps with the orthographic projection of the second boundary L42 on the substrate, and the distance between the boundary of the third electrode connection portion 933 on the substrate near the second boundary L42 and the boundary of the active layer 92 near the second boundary L42 along the second direction D2 is less than the distance between the orthographic projection of the second boundary L42 on the substrate and the boundary of the active layer 92 near the second boundary L42 along the second direction D2.

[0357] In an exemplary embodiment, as shown in FIG54, the distance between the orthographic projection of the boundary of the first electrode connection portion 931 near the via's first boundary L31 on the substrate and the orthographic projection of the first boundary L31 on the substrate along the second direction is greater than or equal to 0; the distance between the orthographic projection of the boundary of the second electrode connection portion near the via's second boundary on the substrate and the orthographic projection of the second boundary on the substrate is greater than or equal to 0; and the distance between the orthographic projection of the boundary of the third electrode connection portion near the via's third boundary on the substrate and the orthographic projection of the third boundary on the substrate along the second direction is greater than or equal to 0. FIG54 is illustrated using the example where the distance between the orthographic projection of the boundary of the first electrode connection portion 931 near the via's first boundary L31 on the substrate and the orthographic projection of the first boundary L31 on the substrate along the second direction is equal to 0; the distance between the orthographic projection of the boundary of the second electrode connection portion near the via's second boundary on the substrate and the orthographic projection of the second boundary on the substrate is equal to 0; and the distance between the orthographic projection of the boundary of the third electrode connection portion near the via's third boundary on the substrate and the orthographic projection of the third boundary on the substrate along the second direction is equal to 0.

[0358] In the exemplary embodiment, in the transistor device provided in FIG54, since the orthographic projection of the first electrode of the transistor device on the substrate does not overlap with the orthographic projections of the multiple boundaries on the substrate, while the orthographic projection of the second electrode of the transistor device on the substrate overlaps with the orthographic projection of the second boundary on the substrate, when there is a misalignment between the first electrode and the second electrode relative to the gate insulating layer in the first direction, the parasitic capacitance between the gate electrode and the first electrode, as well as the parasitic capacitance between the gate electrode and the second electrode, will fluctuate. However, since the overlapping area between the via and the active layer is small, the transistor device provided in FIG54 has a significant effect on improving the turn-on current of the transistor device.

[0359] In an exemplary embodiment, as shown in Figures 50 to 53, the orthographic projection of the via VV on the substrate is within the range of the orthographic projection of the active layer 92 on the substrate.

[0360] In an exemplary embodiment, as shown in Figures 50 to 53, the via VV includes: a first boundary L31, a second boundary L32, a third boundary L33, a fourth boundary L34, a fifth boundary L35, a sixth boundary L36, and a seventh boundary L37. The first boundary L31, the fourth boundary L34, and the sixth boundary L36 extend along a second direction D2, and the third boundary L33, the fifth boundary L35, and the seventh boundary L37 extend along a first direction D1. The first boundary L31 to the seventh boundary L37 are connected sequentially, and at least one of the first boundary L31 to the seventh boundary L37 has a straight line shape. The second boundary L32 is set at an obtuse angle to the first boundary L31 and the third boundary L33. The third boundary L33 is set at a right angle to the fourth boundary L34. The fourth boundary L34 is set at a right angle to the fifth boundary L35. The fifth boundary L35 is set at a right angle to the sixth boundary L36. The sixth boundary L36 is set at a right angle to the seventh boundary L37. The seventh boundary L37 is set at a right angle to the first boundary L31. The distance between the sixth boundary L36 and the first boundary L31 is less than the distance between the fourth boundary L34 and the first boundary L31.

[0361] In an exemplary embodiment, as shown in Figures 50 and 51, the orthographic projection of the first electrode connection portion 931 on the substrate overlaps with the orthographic projections of the first boundary L31 and the seventh boundary L37 on the substrate, respectively; the orthographic projection of the second electrode connection portion 932 on the substrate overlaps with the orthographic projection of the second boundary L32 on the substrate; the orthographic projection of the third electrode connection portion 933 on the substrate overlaps with the orthographic projection of the third boundary L33 on the substrate; the orthographic projection of the fourth electrode connection portion 934 on the substrate does not overlap with the plurality of boundaries; and the orthographic projection of the second electrode 94 on the substrate overlaps with the orthographic projections of the fourth boundary L34, the fifth boundary L35, and the sixth boundary L36 on the substrate, respectively.

[0362] In an exemplary embodiment, FIG50 is illustrated using a single transistor device as an example. FIG51 is illustrated using two transistor devices as an example. In FIG51, the target transistor device is at least partially symmetrically arranged with respect to a straight line extending along the second direction with respect to a straight line extending along the first direction with respect to a first direction; wherein the second electrode of the first transistor device and the second electrode of the second transistor device are the same electrode.

[0363] In the exemplary embodiments, in the transistor devices provided in Figures 50 and 51, since the orthographic projection of the first electrode of the transistor device on the substrate overlaps with the orthographic projections of the first boundary, the second boundary, the third boundary, and the seventh boundary on the substrate, respectively, and the orthographic projection of the second electrode of the transistor device on the substrate overlaps with the orthographic projections of the fifth boundary and the sixth boundary on the substrate, the parasitic capacitance between the first electrode and the second electrode and the gate insulating layer in the first direction will not fluctuate. However, since the thickness of the channel region of the active layer located between the first electrode and the second electrode is partially reduced, the transistor devices provided in Figures 50 and 51 have a limited effect on improving the turn-on current of the transistor device.

[0364] In an exemplary embodiment, as shown in Figures 52 and 53, the orthographic projections of the first electrode 93 and the second electrode 94 on the substrate do not overlap with the orthographic projections of the plurality of boundaries on the substrate.

[0365] In an exemplary embodiment, as shown in Figures 52 and 53, the distance between the orthographic projection of the boundary of the first electrode connection portion 931 near the via VV on the substrate and the orthographic projection of the first boundary L31 on the substrate is greater than or equal to 0; the distance between the orthographic projection of the boundary of the second electrode connection portion 932 near the via VV on the substrate and the orthographic projection of the second boundary L32 on the substrate is greater than or equal to 0; the distance between the orthographic projection of the boundary of the third electrode connection portion 933 near the via VV on the substrate and the orthographic projection of the third boundary L33 on the substrate is greater than or equal to 0; the distance between the orthographic projection of the boundary of the second electrode near the via VV and extending along the second direction D2 on the substrate and the orthographic projection of the fifth boundary L35 on the substrate is greater than or equal to 0; and the distance between the orthographic projection of the boundary of the second electrode near the via VV and extending along the first direction D1 on the substrate and the orthographic projection of the sixth boundary L36 on the substrate is greater than or equal to 0. Figures 52 and 53 illustrate examples where the distance between the orthographic projection of the boundary of the first electrode connection 931 near the via VV and the orthographic projection of the first boundary L31 on the substrate is 0; the distance between the orthographic projection of the boundary of the second electrode connection 932 near the via VV and the orthographic projection of the second boundary L32 on the substrate is 0; the distance between the orthographic projection of the boundary of the third electrode connection 933 near the via VV and the orthographic projection of the third boundary L33 on the substrate is 0; the distance between the orthographic projection of the boundary of the second electrode near the via VV and extending along the second direction D2 on the substrate and the orthographic projection of the fifth boundary L35 on the substrate is 0; and the distance between the orthographic projection of the boundary of the second electrode near the via VV and extending along the first direction D1 on the substrate and the orthographic projection of the sixth boundary L36 on the substrate is 0.

[0366] As shown in Figure 52, the distance between the orthographic projection of the active layer 92 near the fourth boundary L34 on the substrate and the orthographic projection of the fourth boundary L34 on the substrate along the second direction D2 is less than the distance between the boundary of the third electrode connection 933 near the fourth boundary L34 and the orthographic projection of the fourth boundary L34 on the substrate along the second direction D2. The distance between the orthographic projection of the active layer 92 near the seventh boundary L37 on the substrate and the orthographic projection of the seventh boundary on the substrate along the second direction D2 is less than the maximum distance between the boundary of the second electrode 94 near the seventh boundary L37 and the orthographic projection of the seventh boundary L37 on the substrate along the second direction D2.

[0367] As shown in Figure 53, the distance between the orthographic projection of the active layer 92 near the fourth boundary L34 on the substrate and the orthographic projection of the fourth boundary L34 on the substrate along the second direction D2 is greater than the distance between the boundary of the third electrode connection 933 near the fourth boundary L34 and the orthographic projection of the fourth boundary L34 on the substrate along the second direction D2. The distance between the orthographic projection of the active layer 92 near the seventh boundary L37 on the substrate and the orthographic projection of the seventh boundary on the substrate along the second direction D2 is greater than the maximum distance between the boundary of the second electrode 94 near the seventh boundary L37 and the orthographic projection of the seventh boundary L37 on the substrate along the second direction D2.

[0368] As shown in Figures 52 and 53, the maximum distance m along the second direction D2 between the boundary of the second electrode 94 near the seventh boundary L37 and the orthographic projection of the seventh boundary L37 on the substrate is in the range of 1 micrometer to 1.5 micrometers, and the distance n along the second direction D2 between the boundary of the third electrode connection 933 near the fourth boundary L34 and the orthographic projection of the fourth boundary L34 on the substrate is in the range of 1 micrometer to 1.5 micrometers.

[0369] The orthographic projections of the first and second electrodes on the substrate in the transistor devices shown in Figures 52 and 53 do not overlap with the orthographic projections of the vias on the substrate, which can reduce the load on the transistor device. However, when there is a misalignment between the first and second electrodes and the gate insulating layer in the first direction, the parasitic capacitance between the gate electrode and the first electrode, as well as the parasitic capacitance between the gate electrode and the second electrode, will fluctuate.

[0370] In an exemplary embodiment, the transistor devices provided in Figures 24 to 54 are single-gate structures.

[0371] Figure 55 is a top view of another transistor device. As shown in Figure 55, the gate electrode 201 includes a first gate electrode 2011 and a second gate electrode 2012 interconnected with each other. The transistor device also includes a connection electrode 205, which is located on the side of the first electrode 203 and the second electrode 204 away from the substrate. The orthographic projection of the active layer 202 on the substrate at least partially overlaps with the orthographic projection of the first gate electrode 2011 on the substrate, but does not overlap with the orthographic projection of the second gate electrode 2012 on the substrate. The connection electrode 205 is electrically connected to the second gate electrode 2012.

[0372] In an exemplary embodiment, the connecting electrode 205 is a transparent electrode.

[0373] In an exemplary embodiment, the connection electrode is connected to the gate electrode, which can serve as the two gate electrodes of the transistor device, making the transistor device a dual-gate structure.

[0374] In an exemplary embodiment, the transistor device structure including multiple transistor devices in Figures 24 to 28 and Figure 51 can be applied to products with high requirements for parasitic capacitance fluctuations between the gate electrode and the source electrode.

[0375] In an exemplary embodiment, the transistor device provided in this disclosure uses the following masks during its formation: a first mask is used when forming the first insulating layer, a second mask is used when forming the gate electrode, a third mask is used when forming the original semiconductor layer, a fourth mask is used when forming the second active layer, and a fifth mask is used when forming the first electrode and the second electrode.

[0376] In an exemplary embodiment, when the transistor devices provided in Figures 38 to 42 are formed, the fourth and fifth masks are different masks, and five masks are required to form the transistor devices provided in Figures 38 and 42.

[0377] In an exemplary embodiment, when the transistor devices provided in Figures 24 to 37 and Figures 42 to 54 are formed, the fourth mask and the fifth mask can be the same mask, and four masks are required to form the transistor devices provided in Figures 24 to 37 and Figures 42 to 54.

[0378] This disclosure also provides a display substrate, including: a plurality of transistor devices provided in any of the foregoing embodiments.

[0379] Figure 56 is a structural schematic diagram of the display substrate provided in the embodiment of this disclosure, and Figure 57 is a partial connection schematic diagram of the display substrate provided in Figure 56. As shown in Figures 56 and 57, the display substrate provided in the embodiment of this disclosure has a display area AA and a non-display area BB. The display area AA is provided with a plurality of first circuits Px, and the non-display area AA is provided with a plurality of second circuits. At least one of the first electrodes Px and the second circuit includes at least one switching device; the at least one switching device in the at least one of the first circuits and the second circuit is a transistor device.

[0380] In an exemplary embodiment, the second circuit includes at least one of the following: a gate driving circuit, a source driving circuit, a multiplexing circuit, an electrostatic discharge circuit, an array test circuit, and a lamp testing circuit.

[0381] In an exemplary embodiment, the second circuit may be located on at least one of the first, second, third, and fourth sides of the display area. The first and second sides are disposed opposite to each other, and the third and fourth sides are disposed opposite to each other. Exemplarily, the gate driving circuit may be located on at least one of the first and second sides of the display area. The source driving circuit, multiplexing circuit, and lamp testing circuit may be located on the fourth side of the display area; the array testing circuit may be located on at least one of the third and fourth sides of the display area; and the electrostatic discharge circuit may be located on at least one of the third and fourth sides of the display area.

[0382] The fourth side of the display area can be called the data side, and the third side of the display area can be called the non-data side.

[0383] In an exemplary embodiment, the transistor devices provided in Figures 38 to 54 are suitable for the first circuit.

[0384] In an exemplary embodiment, the transistor devices provided in Figures 24 to 37 are suitable for both the first circuit and the gate drive circuit.

[0385] The gate drive circuit includes multiple cascaded shift registers, and at least one shift register includes an input transistor and an output transistor, wherein the input transistor and the output transistor are transistor devices provided in any of the foregoing embodiments. In an exemplary embodiment, at least one shift register may include an input sub-circuit, an output sub-circuit, a blanking reset sub-circuit, a display reset sub-circuit, a pull-down control sub-circuit, and a noise reduction sub-circuit.

[0386] Figure 58 is an equivalent circuit diagram of at least one shift register. As shown in Figure 58, the input sub-circuit includes: a first transistor T1; the output sub-circuit includes: a third transistor T3 and a capacitor C; the display reset sub-circuit includes: a second transistor T2; the blanking reset sub-circuit includes: an eighteenth transistor T18 and a nineteenth transistor T19; the pull-down control sub-circuit includes: a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, an eleventh transistor T11, a twelfth transistor T12, and a thirteenth transistor T13; and the noise reduction sub-circuit includes: a fourteenth transistor T14, a fifteenth transistor T15, a sixteenth transistor T16, and a seventeenth transistor T17.

[0387] As shown in Figure 58, the control electrode and first electrode of the first transistor T1 are electrically connected to the signal input terminal IN, and the second electrode of the first transistor T1 is electrically connected to the pull-up node PU; the control electrode of the second transistor T2 is electrically connected to the reset signal terminal RST, the first electrode of the second transistor T2 is electrically connected to the pull-up node PU, and the second electrode of the second transistor T2 is electrically connected to the third power supply terminal VGL; the control electrode of the third transistor T3 is electrically connected to the pull-up node PU, the first electrode of the third transistor T3 is electrically connected to the clock signal terminal CLK, and the second electrode of the third transistor T3 is electrically connected to the signal output terminal OUT; the control electrode and first electrode of the fourth transistor T4 are electrically connected to the first power supply terminal VDD1, and the second electrode of the fourth transistor T4 is electrically connected to the fifth transistor… The control electrode of transistor T5 is electrically connected to the first electrode of transistor T6; the first electrode of transistor T5 is electrically connected to the first power supply terminal VDD1, and the second electrode of transistor T5 is electrically connected to the first pull-down node PD1; the control electrode of transistor T6 is electrically connected to the pull-up node PU, and the second electrode of transistor T6 is electrically connected to the third power supply terminal VGL; the control electrode of transistor T7 is electrically connected to the pull-up node PU, the first electrode of transistor T7 is electrically connected to the first pull-down node PD1, and the second electrode of transistor T7 is electrically connected to the third power supply terminal VGL; the control electrode of transistor T8 is electrically connected to the signal input terminal IN, the first electrode of transistor T8 is electrically connected to the first pull-down node PD1, and the second electrode of transistor T8 is electrically connected to... The third power supply terminal VGL is electrically connected; the control electrode and first electrode of the ninth transistor T9 are electrically connected to the second power supply terminal VDD2, and the second electrode of the ninth transistor T9 is electrically connected to the control electrode of the tenth transistor T10 and the first electrode of the eleventh transistor T11, respectively; the first electrode of the tenth transistor T10 is electrically connected to the second power supply terminal VDD2, and the second electrode of the tenth transistor T10 is electrically connected to the second pull-down node PD2; the control electrode of the eleventh transistor T11 is electrically connected to the pull-up node PU, and the second electrode of the eleventh transistor T11 is electrically connected to the third power supply terminal VGL; the control electrode of the twelfth transistor T12 is electrically connected to the pull-up node PU, and the first electrode of the twelfth transistor T12 is electrically connected to the second pull-down node PD2, and the twelfth transistor T12... The second terminal of the thirteenth transistor T13 is electrically connected to the third power supply terminal VGL; the control terminal of the thirteenth transistor T13 is electrically connected to the signal input terminal IN; the first terminal of the thirteenth transistor T13 is electrically connected to the second pull-down node PD2; and the second terminal of the thirteenth transistor T13 is electrically connected to the third power supply terminal VGL. The control terminal of the fourteenth transistor T14 is electrically connected to the first pull-down node PD1; the first terminal of the fourteenth transistor T14 is electrically connected to the pull-up node PU; and the second terminal of the fourteenth transistor T14 is electrically connected to the third power supply terminal VGL. The control terminal of the fifteenth transistor T15 is electrically connected to the second pull-down node PD2; the first terminal of the fifteenth transistor T15 is electrically connected to the pull-up node PU; and the second terminal of the fifteenth transistor T15 is electrically connected to the third power supply terminal VGL.The control electrode of the sixteenth transistor T16 is electrically connected to the first pull-down node PD1, the first electrode of the sixteenth transistor T16 is electrically connected to the signal output terminal OUT, and the second electrode of the sixteenth transistor T16 is electrically connected to the third power supply terminal VGL; the control electrode of the seventeenth transistor T17 is electrically connected to the second pull-down node PD2, the first electrode of the seventeenth transistor T17 is electrically connected to the signal output terminal OUT, and the second electrode of the sixteenth transistor T16 is electrically connected to the third power supply terminal VGL; the control electrode of the eighteenth transistor T18 is electrically connected to the blanking reset signal terminal TRST, the first electrode of the eighteenth transistor T18 is electrically connected to the pull-up node PU, and the second electrode of the eighteenth transistor T18 is electrically connected to the third power supply terminal VGL; the control electrode of the nineteenth transistor T19 is electrically connected to the blanking reset signal terminal TRST, the first electrode of the nineteenth transistor T19 is electrically connected to the signal output terminal OUT, and the second electrode of the nineteenth transistor T19 is electrically connected to the third power supply terminal VGL; the first plate C1 of capacitor C is electrically connected to the pull-up node PU, and the second plate C2 of capacitor C is electrically connected to the signal output terminal OUT.

[0388] In an exemplary embodiment, the first transistor T1 can be referred to as the input transistor. The third transistor T3 can be referred to as the output transistor.

[0389] In an exemplary embodiment, the signal output terminal of at least one shift register is electrically connected to the reset signal terminal of at least one shift register, and is also electrically connected to the signal input terminal of at least one shift register. Exemplarily, the cascaded signal output terminals of at least one shift register are electrically connected to the reset signal terminal of the preceding shift register and the signal input terminal of the following shift register, respectively.

[0390] In an exemplary embodiment, the operation of the display substrate includes a display phase and a power-off phase. During the power-off phase, the display substrate has an Xon function to promptly release the charge from the pixel units in the display substrate.

[0391] In an exemplary embodiment, the display phase includes multiple display frames, with a silencing period set between adjacent display frames.

[0392] In an exemplary embodiment, in at least one display frame, the signal received at the signal input terminal IN is a single pulse signal.

[0393] In an exemplary embodiment, in at least one display frame, the signal output terminal OUT of at least one level shift register is configured to provide an output cascade signal to the signal input terminal of at least one level shift register and the reset signal terminal of at least one level shift register, and to provide a drive signal to the scan signal line connected to the pixel driving circuit located in the display area.

[0394] In an exemplary embodiment, during the display phase, the signal at the third power supply terminal VGL is a low-level signal.

[0395] In an exemplary embodiment, during the power-off phase, the signal of the third power supply terminal VGL is a high-level signal to pull up the signal of the drive signal output terminal OUT of at least one shift register, thereby discharging the pixel unit. The signal of the third power supply terminal VGL is a low-level signal to pull down the signal of the pull-up node PU to prevent charge accumulation in the pull-up node PU of at least one shift register, so as to ensure that at least one shift register can work normally during the display phase.

[0396] In an exemplary embodiment, during the display phase, the signal at at least one of the first power supply terminal VDD1 and the second power supply terminal VDD2 is a periodic signal.

[0397] In an exemplary embodiment, during the display phase, the signals of the first power supply terminal VDD1 and the second power supply terminal VDD2 are at least partially inverted signals. When the signal of the first power supply terminal VDD1 is a high-level signal, the signal of the second power supply terminal VDD2 is a low-level signal, and when the signal of the second power supply terminal VDD2 is a high-level signal, the signal of the first power supply terminal VDD1 is a low-level signal.

[0398] In an exemplary embodiment, the display frame includes: a first display frame and a second display frame. In at least one first display frame, the signal of the first power terminal VDD1 is a high-level signal and the signal of the second power terminal VDD2 is a low-level signal. In at least one second display frame, the signal of the second power terminal VDD2 is a high-level signal and the signal of the first power terminal VDD1 is a low-level signal.

[0399] In an exemplary embodiment, the TRST signal at the blanking reset terminal is an active level signal during the blanking period and an inactive level signal during the display phase. An active level signal means that the signal terminal is electrically connected to the control electrode of the transistor, causing the transistor connected to the signal terminal to conduct; an inactive level signal means that the signal terminal is electrically connected to the control electrode of the transistor, causing the transistor connected to the signal terminal to disconnect.

[0400] In an exemplary embodiment, the reset signal terminal RST is an active level signal for a portion of at least one display frame.

[0401] In an exemplary embodiment, this disclosure reduces noise in the shift register by alternately changing the first power supply terminal VDD1 and the second power supply terminal VDD2 to high-level signals, which can reduce the stress on at least one transistor in the shift register and thus improve the lifespan of the shift register.

[0402] In an exemplary embodiment, FIG59 is a schematic diagram of the structure of a shift register provided in an embodiment of the present disclosure. The display substrate provided in FIG59 includes a shift register as shown in FIG58. The at least one shift register includes a plurality of transistors. The plurality of transistors includes a first transistor T1 to a nineteenth transistor T19. At least one of the plurality of transistors is a transistor device provided in any of the preceding embodiments.

[0403] As shown in Figure 59, at least one transistor includes: an input transistor (first transistor T1), which is electrically connected to a signal input terminal and a pull-up node. At least one transistor also includes: an output transistor (third transistor T3), which is electrically connected to a pull-up node, a signal output terminal, and a clock signal terminal.

[0404] In an exemplary embodiment, the display substrate includes a substrate and a gate insulating layer disposed on the substrate, the gate insulating layer including a first insulating layer and a second insulating layer stacked on the substrate.

[0405] In an exemplary embodiment, as shown in FIG59, one of the first insulating layer and the second insulating layer is provided with a first device via VV1. The orthographic projection of the active layer of the input transistor (first transistor T1) onto the substrate at least partially overlaps with the orthographic projection of the first device via VV1 onto the substrate.

[0406] In an exemplary embodiment, as shown in FIG59, one of the first insulating layer and the second insulating layer is further provided with a second device via VV2. The orthographic projection of the active layer 3-2 of the output transistor (third transistor T3) on the substrate at least partially overlaps with the orthographic projection of the second device via VV2 on the substrate.

[0407] In an exemplary embodiment, the first device via VV1 and the second device via VV2 may be disposed on the same insulating layer. Exemplarily, the first device via VV1 and the second device via VV2 may be disposed on the first insulating layer, or the first device via VV1 and the second device via VV2 may be disposed on the second insulating layer.

[0408] In an exemplary embodiment, at least one level of the shift register's input transistor drives the signal of the pull-up node, and the output transistor drives the signal at the signal output terminal. Therefore, the display substrate has a large demand for increasing the turn-on current of the input and output transistors. This disclosure improves the charging capability of the pull-up node by setting the input transistor to the transistor device provided in the aforementioned embodiment, thereby increasing the voltage of the pull-up node signal. By setting the output transistor to the transistor device provided in the aforementioned embodiment, the driving circuit of the shift register can be enlarged, thereby improving the overall driving capability of the shift register and thus improving the reliability of the gate driving circuit.

[0409] In an exemplary embodiment, the transistors of at least one shift register, excluding the input and output transistors, are not sensitive to the turn-on current of the transistor device. Therefore, the active layers of the transistors of at least one shift register, excluding the input and output transistors, have overlapping gate insulating layers on the substrate and do not require vias.

[0410] In an exemplary embodiment, the display substrate includes a substrate and a circuit structure layer disposed on the substrate. The circuit structure layer includes a first conductive layer, a semiconductor layer, and a second conductive layer sequentially stacked on the substrate.

[0411] In an exemplary embodiment, the first conductive layer includes the gate electrodes of a plurality of transistors located in at least one level shift register.

[0412] In an exemplary embodiment, the semiconductor layer includes an active layer of a plurality of transistors located in at least one level shift register.

[0413] In an exemplary embodiment, the second conductive layer includes: a first electrode and a second electrode of a plurality of transistors located in at least one level shift register.

[0414] In an exemplary embodiment, as shown in FIG59, the display substrate further includes: a plurality of clock signal lines disposed on the substrate, a first power supply line VDDL1, a second power supply line VDDL2, a third power supply line VGLL, and a total reset signal line TRL. FIG59 is illustrated using an example of a plurality of clock signal lines including: a first clock signal line CLKL1, a second clock signal line CLKL2, a third clock signal line CLKL3, and a fourth clock signal line CLKL4.

[0415] In an exemplary embodiment, at least one of the first and second electrodes of at least one transistor (fourth transistor T4 and fifth transistor T5) in at least one level shift register is electrically connected to a first power supply terminal. At least one of the first and second electrodes of at least one transistor (ninth transistor T9 and tenth transistor T10) in at least one level shift register is electrically connected to a second power supply terminal. The second electrode of at least one transistor (sixth transistor T6, seventh transistor T7, eighth transistor T8, eleventh transistor T11, twelfth transistor T12, thirteenth transistor T13, fourteenth transistor T14, fifteenth transistor T15, sixteenth transistor T16, seventeenth transistor T17, eighteenth transistor T18, and nineteenth transistor T19) in at least one level shift register is electrically connected to a third power supply terminal. The control electrode of at least one transistor (eighteenth transistor T18 and nineteenth transistor T19) in at least one level shift register is electrically connected to the total reset signal line TRL.

[0416] In an exemplary embodiment, at least one of the multiple clock signal lines, the first power line VDDL1, the second power line VDDL2, the third power line VGLL, and the total reset signal line TRL extends at least partially along the third direction D3 and is located in the first conductive layer.

[0417] In an exemplary embodiment, as shown in FIG59, the orthogonal projection of at least one of the multiple clock signal lines, the first power line VDDL1, the second power line VDDL2, and the third power line VGLL onto the substrate is located on the side of the orthogonal projection of the multiple transistors in at least one level shift register away from the display area.

[0418] In an exemplary embodiment, as shown in FIG59, the orthogonal projection of the total reset signal line TRL on the substrate lies between the orthogonal projections of the plurality of transistors on the substrate, and between the orthogonal projections of the output transistors and the input transistors on the substrate. Exemplarily, the orthogonal projection of the total reset signal line TRL on the substrate may lie between the orthogonal projections of at least one of the first transistors T1 to the seventeenth transistor T17 on the substrate and the orthogonal projection of the third transistor T3 on the substrate, and at least partially overlap with the orthogonal projections of at least one of the eighteenth transistor T18 and the nineteenth transistor T19 on the substrate.

[0419] In an exemplary embodiment, as shown in FIG59, the display substrate may further include: multiple cascaded signal lines OUTL, which may be electrically connected to the signal input terminal of at least one shift register and to the reset signal terminal of at least one shift register.

[0420] In an exemplary embodiment, as shown in FIG59, multiple cascaded signal lines OUTL are located in the first conductive layer.

[0421] In an exemplary embodiment, as shown in FIG59, the orthogonal projection of the plurality of cascaded signal lines OUTL on the substrate lies between the orthogonal projection of at least one of the first transistors T1 to the seventeenth transistor T17 on the substrate and the orthogonal projection of at least one of the eighteenth transistor T18 and the nineteenth transistor T19 on the substrate.

[0422] In an exemplary embodiment, the display substrate further includes a light-sensing structure configured to convert light signals into electrical signals. The light-sensing structure includes at least one light-sensing switch device, which is the transistor device.

[0423] In an exemplary embodiment, the light-sensing structure may be located in the display area.

[0424] Figure 60 is a top view of a photosensitive switching device. As shown in Figure 60, the photosensitive switching device includes: a gate electrode 301, an active layer 302, a first electrode 303, and a second electrode 304. The photosensitive switching device also includes: a gate insulating layer.

[0425] In an exemplary embodiment, as shown in FIG60, the orthographic projection of the active layer 302 on the substrate is within the range of the orthographic projection of the gate electrode 301 on the substrate. The gate insulating layer is provided with a via VV4, the number of which is one, and the orthographic projection of the via VV4 on the substrate is within the range of the orthographic projection of the active layer 302 on the substrate.

[0426] In an exemplary embodiment, as shown in FIG60, the first electrode 303 includes a first connecting portion 3031 and a plurality of first branch portions 3032. The first connecting portion 3031 is connected to the plurality of first branch portions 3032 respectively. The first connecting portion 3031 extends along a first direction D1, the plurality of first branch portions 3032 are arranged along the first direction D1, and at least one branch portion 3032 extends along a second direction D2.

[0427] In an exemplary embodiment, as shown in FIG60, the orthographic projection of the first connection portion 3031 on the substrate does not overlap with the orthographic projection of the gate electrode 301 on the substrate, and the orthographic projection of at least one of the plurality of first branches 3032 on the substrate at least partially overlaps with the orthographic projection of the via VV3 on the substrate.

[0428] In an exemplary embodiment, as shown in FIG60, the second electrode 304 includes: a second connecting portion 3041, a third connecting portion 3043, a plurality of second branch portions 3042, and a plurality of third branch portions 3044. The second connecting portion 3041 and the third connecting portion 3043 extend along a first direction D1, and the plurality of second branch portions 3042 and the plurality of third branch portions 3044 extend along a second direction D2. The plurality of second branch portions 3042 are respectively connected to the second connecting portion 3041 and the third connecting portion 3043, and the plurality of third branch portions 3044 are connected to the third connecting portion 3043.

[0429] In an exemplary embodiment, as shown in FIG60, the orthographic projection of the second connection portion 3041 on the substrate does not overlap with the orthographic projection of the gate electrode 301 on the substrate, the orthographic projection of at least one of the plurality of second branches 3042 on the substrate at least partially overlaps with the orthographic projection of the via VV3 on the substrate, and the orthographic projections of the third connection portion 3043 and the plurality of third branches 3044 on the substrate are located within the range of the orthographic projection of the via VV3 on the substrate.

[0430] In an exemplary embodiment, as shown in FIG60, a plurality of second branches 3042 and a plurality of third branches 3044 are alternately arranged. The plurality of second branches 3042 correspond one-to-one with a plurality of first branches 3032, and the second branches 3042 and their corresponding first branches 3032 are arranged along a second direction D2.

[0431] In an exemplary embodiment, the photosensitive switch device provided in FIG60 includes: a plurality of transistor devices, wherein the first electrode of the plurality of transistor devices is the same electrode, the second electrode of the plurality of transistor devices is the same electrode, the gate electrode of the plurality of transistor devices is the same electrode, the active layer of the plurality of transistor devices is the same active layer, and the via of each transistor device is the same via.

[0432] In an exemplary embodiment, the photosensitive switch device provided in FIG60 can be referred to as a combined photosensitive switch device.

[0433] In an exemplary embodiment, FIG61 is a top view of a photosensitive switching device. As shown in FIG61, the photosensitive switching device includes: a gate electrode 401, an active layer 402, a first electrode 403, and a second electrode 404. The photosensitive switching device also includes: a gate insulating layer.

[0434] In an exemplary embodiment, as shown in FIG61, the orthographic projection of the active layer 402 on the substrate is within the range of the orthographic projection of the gate electrode 401 on the substrate. The gate insulating layer is provided with vias VV4, and there are multiple vias VV4. The multiple vias VV4 are arranged along the first direction D1, and their orthographic projections on the substrate are within the range of the orthographic projection of the active layer 402 on the substrate.

[0435] In an exemplary embodiment, as shown in FIG61, the first electrode 403 includes a first connecting portion 4031 and a plurality of first branch portions 4032. The first connecting portion 4031 is connected to the plurality of first branch portions 4032 respectively. The first connecting portion 4031 extends along a first direction D1, the plurality of first branch portions 4032 are arranged along the first direction D1, and at least one branch portion 4032 extends along a second direction D2.

[0436] In an exemplary embodiment, as shown in FIG61, the orthographic projection of the first connection portion 4031 on the substrate does not overlap with the orthographic projection of the gate electrode 401 on the substrate, and the orthographic projection of at least one of the plurality of first branches 4032 on the substrate at least partially overlaps with the orthographic projection of the via VV3 on the substrate.

[0437] In an exemplary embodiment, as shown in FIG61, the second electrode 404 includes: a second connecting portion 4041, a plurality of second branch portions 4042, and a plurality of third branch portions 4043. The second connecting portion 4041 extends along a first direction D1, and the plurality of second branch portions 4042 and the plurality of third branch portions 4043 extend along a second direction D2. The plurality of second branch portions and the plurality of third branch portions correspond one-to-one, and the plurality of second branch portions 4042 are respectively connected to the second connecting portion 4041 and the plurality of third branch portions 4043.

[0438] In an exemplary embodiment, as shown in FIG61, a plurality of second branches 4042 and a plurality of third branches 4043 are corresponding one-to-one, and the second branches 4042 are connected to the corresponding third branches 4043. A plurality of second branches 4042 and a plurality of first branches 4032 are corresponding one-to-one, and the second branches 4042 and the corresponding first branches 4032 are arranged along the second direction D2.

[0439] In an exemplary embodiment, the third branch 4043 includes a first sub-branch 4051, a second sub-branch 4052, and a third sub-branch 4053. The first sub-branch 4051 and the second sub-branch 4052 extend along a second direction D2, and the third sub-branch 4053 extends along a first direction D1. The third sub-branch 4053 is connected to the first sub-branch 4051 and the second sub-branch 4052, respectively.

[0440] In an exemplary embodiment, the second branch 4042 is connected to the middle section of the third sub-branch 4053 of the corresponding third branch 4043.

[0441] In an exemplary embodiment, as shown in FIG61, the orthographic projection of the second connection portion 4041 on the substrate does not overlap with the orthographic projection of the gate electrode 401 on the substrate. The orthographic projection of at least one of the plurality of second branches 4042 on the substrate at least partially overlaps with the orthographic projection of the via VV3 on the substrate. The orthographic projections of the plurality of third branches 4043 on the substrate are located within the range of the orthographic projection of the via VV4 on the substrate. Each of the plurality of third branches 4043 corresponds one-to-one with a plurality of via VV4. The orthographic projection of the third branch 4043 on the substrate is located within the range of the orthographic projection of the corresponding via VV4 on the substrate.

[0442] In an exemplary embodiment, the photosensitive switch device provided in FIG61 includes: a plurality of transistor devices, wherein the first electrode of the plurality of transistor devices is the same electrode, the second electrode of the plurality of transistor devices is the same electrode, the gate electrode of the plurality of transistor devices is the same electrode, the active layer of the plurality of transistor devices is the same active layer, and the via of each transistor device is a different via.

[0443] The optical sensor device shown in Figure 61 can be called a discrete optical sensor device.

[0444] In an exemplary embodiment, the photosensitive switching device provided in this disclosure can increase the leakage current of the photosensitive switching device, thereby enhancing the photosensitive switching device's ability to detect changes in light.

[0445] Figure 62 is a schematic diagram of the structure of some switching devices located on the data side. The gate insulating layer of the switching device STFT1 on the data side in Figure 62 has a via VV5.

[0446] Figure 63 is a schematic diagram of the structure of some switching devices located on the non-data side. The gate insulating layer of the switching device STFT2 on the non-data side in Figure 63 has a via VV6.

[0447] In an exemplary embodiment, the switching devices on the data side and the non-data side are transistor devices provided in any of the foregoing embodiments, which can reduce the channel width in the switching devices, thereby reducing the area occupied by the switching devices on the data side and the non-data side.

[0448] Figure 64 is a schematic diagram of some of the switching devices in the electrostatic discharge circuit. The gate insulating layer of the switching device STFT3 in the electrostatic discharge circuit shown in Figure 64 has a via VV7.

[0449] In an exemplary embodiment, the switching device in the electrostatic discharge circuit adopts the transistor device provided in any of the foregoing embodiments, which can further enhance the transient turn-on capability of the electrostatic discharge circuit, thereby improving the charge release capability of the electrostatic discharge circuit.

[0450] Figure 65 is a schematic flowchart of the method for fabricating a transistor device according to an embodiment of this disclosure. As shown in Figure 65, the method for fabricating a transistor device according to an embodiment of this disclosure may include the following steps:

[0451] Step S101: Form the gate electrode of the transistor device on the substrate.

[0452] Step 102: Form the gate insulating layer and active layer of the transistor device on the gate electrode.

[0453] The gate insulating layer includes: a first insulating layer and a second insulating layer stacked on the substrate, wherein one of the first insulating layer and the second insulating layer is provided with a via; the orthographic projection of the via on the substrate at least partially overlaps with the orthographic projection of the active layer on the substrate.

[0454] Step 103: Form the first electrode and the second electrode on the active layer.

[0455] In an exemplary embodiment, step 102 includes:

[0456] A first insulating layer is formed on the gate electrode, and the first insulating layer has a via.

[0457] A second insulating layer is formed from the first insulating layer;

[0458] A primary semiconductor layer is formed on the second insulating layer, the primary semiconductor layer comprising: a first active layer and a third active layer;

[0459] A first electrode, a second electrode, and an active layer are formed on the original semiconductor layer. The active layer includes a first active layer and a second active layer.

[0460] For clarity, the thickness and dimensions of layers or microstructures are enlarged in the accompanying drawings used to describe embodiments of this disclosure. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” or “below” another element, the element may be located “directly” on or “below” the other element, or there may be intermediate elements present.

[0461] While the embodiments disclosed herein are as described above, the content is merely for the purpose of facilitating understanding of this disclosure and is not intended to limit this disclosure. Any person skilled in the art to which this disclosure pertains may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed herein; however, the scope of patent protection of this disclosure shall still be determined by the scope defined in the appended claims.

Claims

1. A transistor device, wherein, The transistor device, disposed on a substrate, includes: a gate electrode, a gate insulating layer, an active layer, a first electrode, and a second electrode. The first electrode and the second electrode are disposed on the side of the active layer and the gate electrode away from the substrate, and the gate insulating layer is disposed between the active layer and the gate electrode. The gate insulating layer includes: a first insulating layer and a second insulating layer stacked on the substrate, wherein one of the first insulating layer and the second insulating layer is provided with a via; The orthographic projection of the via on the substrate at least partially overlaps with the orthographic projection of the active layer on the substrate.

2. The transistor device according to claim 1, wherein, The orthographic projection of the active layer on the substrate is within the range of the orthographic projection of the gate electrode on the substrate, and the orthographic projection of at least one of the first electrode and the second electrode on the substrate at least partially overlaps with the orthographic projection of the active layer on the substrate. The orthographic projection of the via on the substrate is within the range of the orthographic projection of the active layer on the substrate.

3. The transistor device according to claim 2, wherein, The orthographic projection of the first electrode on the substrate is within the range of the orthographic projection of the active layer on the substrate, and the orthographic projection of a portion of the second electrode on the substrate does not overlap with the orthographic projection of the gate electrode on the substrate; The via includes multiple boundaries, namely a first boundary, a second boundary, a third boundary, and a fourth boundary. The first boundary and the second boundary extend along a first direction, and the third boundary and the fourth boundary extend along a second direction. The first boundary, the fourth boundary, the second boundary, and the third boundary are connected sequentially.

4. The transistor device according to claim 3, wherein, The first electrode includes: an electrode connecting segment, a first branch segment, a second branch segment, and a third branch segment. The electrode connecting segment extends at least partially along a first direction. The first branch segment, the second branch segment, and the third branch segment are arranged along the first direction, and at least one branch segment extends along a second direction. The electrode connecting segment is connected to the first branch segment, the second branch segment, and the third branch segment, respectively. The first direction intersects the second direction. The second electrode includes: a first sub-electrode and a second sub-electrode; the first sub-electrode and the second sub-electrode extend along a second direction, the orthographic projection of the first sub-electrode on the substrate is located between the orthographic projection of the first branch segment on the substrate and the orthographic projection of the second branch segment on the substrate, and the orthographic projection of the second sub-electrode on the substrate is located between the orthographic projection of the second branch segment on the substrate and the orthographic projection of the third branch segment on the substrate; The orthographic projection of the second boundary onto the substrate is located on the side of the first boundary closest to the orthographic projection of the electrode connection segment onto the substrate.

5. The transistor device according to claim 4, wherein, The first boundary, the second boundary, the third boundary, and the fourth boundary are all straight lines. The orthographic projection of the electrode connection segment on the substrate does not overlap with the orthographic projection of the plurality of boundaries on the substrate. The orthographic projection of the first branch segment on the substrate overlaps with the orthographic projections of the first boundary, the second boundary, and the third boundary on the substrate, respectively. The orthographic projection of the second branch segment on the substrate overlaps with the orthographic projections of the first boundary and the second boundary on the substrate, respectively. The orthographic projection of the third branch segment on the substrate overlaps with the orthographic projections of the first boundary, the second boundary, and the fourth boundary on the substrate, respectively. The orthographic projections of the first sub-electrode and the second sub-electrode on the substrate overlap with the orthographic projections of the first boundary and the second boundary on the substrate, respectively. The distance between the orthographic projection of the boundary of the first branch segment near the first sub-electrode on the substrate and the orthographic projection of the third boundary on the substrate along the first direction is in the range of 1 micrometer to 1.5 micrometers; the distance between the orthographic projection of the boundary of at least one of the first and second sub-electrodes near the electrode connection segment on the substrate and the orthographic projection of the second boundary on the substrate along the second direction is in the range of 1 micrometer to 1.5 micrometers; and the distance between the orthographic projection of the boundary of the third branch segment near the second sub-electrode on the substrate and the orthographic projection of the fourth boundary on the substrate along the first direction is in the range of 1 micrometer to 1.5 micrometers.

6. The transistor device according to claim 4, wherein, The first boundary, the third boundary, and the fourth boundary are straight lines, and the shape of the second boundary is adapted to the shape of the electrode connection segment; The orthographic projection of the electrode connection segment on the substrate overlaps with the orthographic projection of the second boundary on the substrate; the orthographic projection of the first branch segment on the substrate overlaps with the orthographic projection of the third boundary on the substrate, but does not overlap with the orthographic projection of the first boundary on the substrate; the orthographic projection of the second branch segment on the substrate does not overlap with the orthographic projections of the plurality of boundaries on the substrate; the orthographic projection of the third branch segment on the substrate overlaps with the orthographic projection of the fourth boundary on the substrate, but does not overlap with the orthographic projection of the first boundary on the substrate; the orthographic projections of the first sub-electrode and the second sub-electrode on the substrate partially overlap with the orthographic projection of the first boundary on the substrate. The distance between the orthographic projection of the boundary of the first branch segment near the first sub-electrode on the substrate and the orthographic projection of the third boundary on the substrate along the first direction is in the range of 1 micrometer to 1.5 micrometers; the distance between the orthographic projection of the boundary of the electrode connection segment near the second electrode on the substrate and the orthographic projection of the second boundary on the substrate along the second direction is in the range of 1 micrometer to 1.5 micrometers; and the distance between the orthographic projection of the boundary of the third branch segment near the second sub-electrode on the substrate and the orthographic projection of the fourth boundary on the substrate along the first direction is in the range of 1 micrometer to 1.5 micrometers.

7. The transistor device according to claim 4, wherein, The vias include: a first via, a second via, a third via, and a fourth via, which are arranged along a first direction; The orthographic projection of the first via on the substrate is located between the orthographic projection of the first branch segment on the substrate and the orthographic projection of the first sub-electrode on the substrate; the orthographic projection of the second via on the substrate is located between the orthographic projection of the first sub-electrode on the substrate and the orthographic projection of the second branch segment on the substrate; the orthographic projection of the third via on the substrate is located between the orthographic projection of the second branch segment on the substrate and the orthographic projection of the second sub-electrode on the substrate; and the orthographic projection of the fourth via on the substrate is located between the orthographic projection of the second sub-electrode on the substrate and the orthographic projection of the third branch segment on the substrate. The distance between the orthographic projection of the third boundary of the first via on the substrate and the orthographic projection of the boundary of the first branch segment near the first via on the substrate along the first direction is greater than or equal to 0. The distance between the orthographic projection of the fourth boundary of the first via on the substrate and the orthographic projection of the boundary of the first sub-electrode near the first via on the substrate along the first direction is greater than or equal to 0. The distance between the orthographic projection of the third boundary of the second via on the substrate and the orthographic projection of the boundary of the first sub-electrode near the second via on the substrate along the first direction is greater than or equal to 0. The distance between the orthographic projection of the fourth boundary of the second via on the substrate and the orthographic projection of the boundary of the second branch segment near the second via on the substrate along the first direction is greater than or equal to 0. The distance between the orthographic projection of the third boundary of the third via on the substrate and the orthographic projection of the boundary of the second branch segment near the third via on the substrate along the first direction is greater than or equal to 0. The distance between the orthographic projection of the fourth boundary of the third via on the substrate and the orthographic projection of the boundary of the second sub-electrode near the third via on the substrate along the first direction is greater than or equal to 0. The distance between the orthographic projection of the third boundary of the fourth via on the substrate and the orthographic projection of the boundary of the second sub-electrode near the fourth via on the substrate along the first direction is greater than or equal to 0. The distance between the orthographic projection of the fourth boundary of the fourth via on the substrate and the orthographic projection of the boundary of the third branch segment near the fourth via on the substrate along the first direction is greater than or equal to 0.

8. The transistor device according to claim 4, wherein, The via includes: a first via, a second via, and a third via, wherein the first via, the second via, and the third via are arranged along a first direction; The orthographic projection of the first via on the substrate overlaps with the orthographic projection of the first branch segment on the substrate, but does not overlap with the orthographic projection of the first sub-electrode on the substrate. The orthographic projection of the second via on the substrate overlaps with the orthographic projection of the second branch segment on the substrate, but does not overlap with the orthographic projections of the first sub-electrode and the second sub-electrode on the substrate, respectively. The orthographic projection of the third via on the substrate overlaps with the orthographic projection of the third branch segment on the substrate, but does not overlap with the orthographic projection of the second sub-electrode on the substrate. The orthographic projection of the first branch segment on the substrate at least partially overlaps with the orthographic projections of the first boundary, second boundary and third boundary of the first via on the substrate, respectively; the orthographic projection of the second branch segment on the substrate at least partially overlaps with the orthographic projections of the first boundary and second boundary of the second via on the substrate, respectively; and the orthographic projection of the third branch segment on the substrate at least partially overlaps with the orthographic projections of the first boundary, second boundary and fourth boundary of the third via on the substrate, respectively. The distance between the orthographic projection of the boundary of the first branch segment near the first sub-electrode on the substrate and the orthographic projection of the third boundary of the first via on the substrate is in the range of 1 micrometer to 1.5 micrometers, and the distance between the orthographic projection of the boundary of the third branch segment near the second sub-electrode on the substrate and the orthographic projection of the fourth boundary of the third via on the substrate is in the range of 1 micrometer to 1.5 micrometers. The distance between the orthographic projection of the boundary of at least one of the first and second sub-electrodes near the electrode connection segment on the substrate and the first boundary of at least one of the first, second, and third vias along the second direction is greater than the distance between the first and second boundaries of at least one of the first, second, and third vias along the second direction; the distance between the orthographic projection of the boundary of the first branch segment away from the electrode connection segment on the substrate and the second boundary of at least one of the first, second, and third vias along the second direction is greater than the distance between the first and second boundaries of at least one of the first, second, and third vias along the second direction. The distance between the orthographic projection of the boundary of at least one of the first and second sub-electrodes near the electrode connection segment on the substrate and the orthographic projection of the second boundary of at least one of the first, second, and third vias on the substrate along the second direction is in the range of 1 micrometer to 1.5 micrometers.

9. The transistor device according to claim 3, wherein, The first electrode includes: an electrode connecting segment, a first branch segment, and a second branch segment. The electrode connecting segment extends at least partially along a first direction. The first branch segment and the second branch segment are arranged along the first direction, and at least one branch segment extends along a second direction. The electrode connecting segment is connected to the first branch segment and the second branch segment respectively. The first direction intersects the second direction. The second electrode extends along the second direction, and the orthographic projection of the second electrode on the substrate is located between the orthographic projection of the first branch segment on the substrate and the orthographic projection of the second branch segment on the substrate; The orthographic projection of the second boundary onto the substrate is located on the side of the first boundary closest to the orthographic projection of the electrode connection segment onto the substrate.

10. The transistor device according to claim 9, wherein, The first boundary, the second boundary, the third boundary, and the fourth boundary are all straight lines. The orthographic projection of the electrode connection segment on the substrate does not overlap with the orthographic projection of the plurality of boundaries on the substrate. The orthographic projection of the first branch segment on the substrate overlaps with the orthographic projections of the first boundary, the second boundary, and the third boundary on the substrate, respectively. The orthographic projection of the second branch segment on the substrate overlaps with the orthographic projections of the first boundary, the second boundary, and the fourth boundary on the substrate, respectively. The orthographic projection of the second electrode on the substrate overlaps with the orthographic projections of the first boundary and the second boundary on the substrate, respectively. The distance between the orthographic projection of the boundary of the first branch segment near the second electrode on the substrate and the orthographic projection of the third boundary on the substrate along the first direction is in the range of 1 micrometer to 1.5 micrometers; the distance between the orthographic projection of the boundary of the second electrode near the electrode connection segment on the substrate and the orthographic projection of the second boundary on the substrate along the second direction is in the range of 1 micrometer to 1.5 micrometers; and the distance between the orthographic projection of the boundary of the third branch segment near the second electrode on the substrate and the orthographic projection of the fourth boundary on the substrate along the first direction is in the range of 1 micrometer to 1.5 micrometers.

11. The transistor device according to claim 9, wherein, The first boundary, the third boundary, and the fourth boundary are straight lines, and the shape of the second boundary is adapted to the shape of the electrode connection segment; The orthographic projection of the electrode connection segment on the substrate overlaps with the orthographic projection of the second boundary on the substrate; the orthographic projection of the first branch segment on the substrate overlaps with the orthographic projection of the third boundary on the substrate, but does not overlap with the orthographic projection of the first boundary on the substrate; the orthographic projection of the second branch segment on the substrate at least partially overlaps with the orthographic projection of the fourth boundary on the substrate, but does not overlap with the orthographic projection of the first boundary on the substrate; the orthographic projection of the second electrode on the substrate at least partially overlaps with the orthographic projection of the first boundary on the substrate. The distance between the orthographic projection of the boundary of the first branch segment near the first sub-electrode on the substrate and the orthographic projection of the third boundary on the substrate along the first direction is in the range of 1 micrometer to 1.5 micrometers; the distance between the orthographic projection of the boundary of the electrode connection segment near the second electrode on the substrate and the orthographic projection of the second boundary near the second electrode on the substrate along the second direction is in the range of 1 micrometer to 1.5 micrometers; and the distance between the orthographic projection of the boundary of the third branch segment near the second electrode on the substrate and the orthographic projection of the fourth boundary on the substrate along the first direction is in the range of 1 micrometer to 1.5 micrometers.

12. The transistor device according to claim 9, wherein, The via includes: a first via and a second via, wherein the first via and the second via are arranged along a first direction; The orthographic projection of the first via on the substrate is located between the orthographic projection of the first branch segment on the substrate and the orthographic projection of the second electrode on the substrate, and the orthographic projection of the second via on the substrate is located between the orthographic projection of the second electrode on the substrate and the orthographic projection of the second branch segment on the substrate; The distance between the orthographic projection of the third boundary of the first via on the substrate and the orthographic projection of the boundary of the first branch segment near the first via on the substrate along the first direction is greater than or equal to 0. The distance between the orthographic projection of the fourth boundary of the first via on the substrate and the orthographic projection of the boundary of the second electrode near the first via on the substrate along the first direction is greater than or equal to 0. The distance between the orthographic projection of the third boundary of the second via on the substrate and the orthographic projection of the boundary of the second electrode near the second via on the substrate along the first direction is greater than or equal to 0. The distance between the orthographic projection of the fourth boundary of the second via on the substrate and the orthographic projection of the boundary of the second branch segment near the second via on the substrate along the first direction is greater than or equal to 0.

13. The transistor device according to claim 9, wherein, The via includes: a first via and a second via, wherein the first via and the second via are arranged along a first direction; The orthographic projection of the first via on the substrate at least partially overlaps with the orthographic projection of the first branch segment on the substrate, and does not overlap with the orthographic projection of the second electrode on the substrate. The orthographic projection of the second via on the substrate at least partially overlaps with the orthographic projection of the second branch segment on the substrate, and does not overlap with the orthographic projection of the second electrode on the substrate. The orthographic projection of the first branch segment on the substrate at least partially overlaps with the orthographic projections of the first boundary, second boundary and third boundary of the first via on the substrate, and the orthographic projection of the second branch segment on the substrate at least partially overlaps with the orthographic projections of the first boundary, second boundary and fourth boundary of the second via on the substrate. The distance between the orthographic projection of the boundary of the first branch segment near the second electrode on the substrate and the orthographic projection of the third boundary of the first via on the substrate is in the range of 1 micrometer to 1.5 micrometers, and the distance between the orthographic projection of the boundary of the second branch segment near the second electrode on the substrate and the orthographic projection of the fourth boundary of the second via on the substrate is in the range of 1 micrometer to 1.5 micrometers.

14. The transistor device according to claim 6 or 11, wherein, The plurality of boundaries further includes: a first protruding boundary, a second protruding boundary, a third protruding boundary, a fourth protruding boundary, a fifth protruding boundary, a sixth protruding boundary, a seventh protruding boundary, and an eighth protruding boundary, wherein the first protruding boundary, the third protruding boundary, the fifth protruding boundary, and the seventh protruding boundary extend along a first direction, and the second protruding boundary, the fourth protruding boundary, the sixth protruding boundary, and the eighth protruding boundary extend along a second direction; The third boundary is connected to the first boundary in sequence through the first protruding boundary, the second protruding boundary, the third protruding boundary and the fourth protruding boundary, and the fourth boundary is connected to the first boundary in sequence through the fifth protruding boundary, the sixth protruding boundary, the seventh protruding boundary and the eighth protruding boundary. The orthographic projections of the first electrode and the second electrode on the substrate do not overlap with the orthographic projections of at least one of the following protruding boundaries on the substrate: the first protruding boundary, the second protruding boundary, the third protruding boundary, the fourth protruding boundary, the fifth protruding boundary, the sixth protruding boundary, the seventh protruding boundary, and the eighth protruding boundary. The distance between the second protruding boundary and the fourth protruding boundary along the second direction is in the range of 1 micrometer to 4 micrometers, and the distance between the sixth protruding boundary and the eighth protruding boundary along the second direction is in the range of 1 micrometer to 4 micrometers.

15. The transistor device according to any one of claims 7, 8, 12, and 13, wherein, The distance between the orthographic projection of the boundary of the second electrode near the electrode connection segment on the substrate and the first boundary of the plurality of vias along the second direction is greater than the distance between the first boundary and the second boundary of the plurality of vias along the second direction. The distance between the orthographic projection of the boundary of the first branch segment away from the electrode connection segment on the substrate and the second boundary of at least one of the plurality of vias along the second direction is greater than the distance between the first boundary and the second boundary of at least one of the plurality of vias along the second direction. The distance between the orthographic projection of the boundary of the second electrode near the electrode connection segment on the substrate and the orthographic projection of the second boundary of at least one of the plurality of vias on the substrate along the second direction is in the range of 1 micrometer to 1.5 micrometers.

16. The transistor device according to claim 2, wherein, The first electrode and the second electrode extend along a second direction, and the orthographic projection of a portion of at least one of the first electrode and the second electrode onto the substrate does not overlap with the orthographic projection of the gate electrode onto the substrate; The via includes multiple boundaries, including a first boundary, a second boundary, a third boundary, and a fourth boundary. The first boundary and the second boundary extend along a first direction, and the third boundary and the fourth boundary extend along a second direction. The first boundary, the fourth boundary, the second boundary, and the third boundary are connected sequentially, and the first boundary, the second boundary, the third boundary, and the fourth boundary are straight lines. The distance between the orthographic projection of the first target boundary on the substrate and the orthographic projection of the first boundary on the substrate along the second direction is less than the distance between the orthographic projection of the first target boundary on the substrate and the orthographic projection of the second boundary on the substrate along the second direction. The distance between the orthographic projection of the second target boundary on the substrate and the orthographic projection of the second boundary on the substrate along the second direction is less than the distance between the orthographic projection of the second target boundary on the substrate and the orthographic projection of the first boundary on the substrate along the second direction. The first target boundary is the boundary where the first electrode and the active layer overlap and extend along the first direction. The second target boundary is the boundary where the second electrode and the active layer overlap and extend along the first direction.

17. The transistor device of claim 16, wherein, The orthographic projection of at least one of the first and second electrodes on the substrate at least partially overlaps with the orthographic projections of the first and second boundaries on the substrate, but does not overlap with the orthographic projections of the third and fourth boundaries on the substrate. Alternatively, the orthographic projection of the via on the substrate does not overlap with the orthographic projections of the first electrode and the second electrode on the substrate; Alternatively, the orthographic projection of the via on the substrate partially overlaps with the orthographic projection of the first electrode on the substrate, but does not overlap with the orthographic projection of the second electrode on the substrate, and the orthographic projection of the first electrode on the substrate overlaps with the orthographic projections of the first boundary and the second boundary on the substrate, respectively. The distance between the orthographic projection of the first target boundary on the substrate and the orthographic projection of the first boundary on the substrate along the second direction is in the range of 1 micrometer to 1.5 micrometers, and the distance between the orthographic projection of the second target boundary on the substrate and the orthographic projection of the second boundary on the substrate along the second direction is in the range of 1 micrometer to 1.5 micrometers.

18. The transistor device according to claim 2, wherein, The first electrode includes: a first electrode connection portion and a second electrode connection portion connected to each other, the first electrode connection portion extending along a first direction, and the second electrode connection portion extending along a second direction; the orthographic projection of a portion of the first electrode connection portion on the substrate overlaps with the orthographic projection of the active layer on the substrate, the orthographic projection of another portion of the first electrode connection portion on the substrate does not overlap with the orthographic projection of the gate electrode on the substrate, and the orthographic projection of the second electrode connection portion on the substrate is located within the range of the orthographic projection of the active layer on the substrate; The orthographic projection of the second electrode portion onto the substrate does not overlap with the orthographic projection of the gate electrode onto the substrate; The via includes multiple boundaries, including a first boundary, a second boundary, a third boundary, and a fourth boundary. The first boundary and the second boundary extend along a first direction, and the third boundary and the fourth boundary extend along a second direction. The first boundary, the fourth boundary, the second boundary, and the third boundary are connected sequentially, and the first boundary, the second boundary, the third boundary, and the fourth boundary are straight lines. The distance between the orthographic projection of the first target boundary on the substrate and the orthographic projection of the first boundary on the substrate along the second direction is less than the distance between the orthographic projection of the first target boundary on the substrate and the orthographic projection of the second boundary on the substrate along the second direction. The distance between the orthographic projection of the second target boundary on the substrate and the orthographic projection of the second boundary on the substrate along the second direction is less than the distance between the orthographic projection of the second target boundary on the substrate and the orthographic projection of the first boundary on the substrate along the second direction. The first target boundary is the boundary where the second electrode connection is close to the first boundary and extends along the first direction. The second target boundary is the boundary where the second electrode connection is close to the first boundary and extends along the first direction.

19. The transistor device according to claim 1, wherein, The active layer includes: a first active connection portion and a second active connection portion connected to each other, wherein the first active connection portion extends at least partially along a first direction and the second active connection portion extends at least partially along a second direction; the first electrode includes: a first electrode connection portion and a second electrode connection portion connected to each other, wherein the first electrode connection portion extends along the first direction and the second electrode connection portion extends along the second direction. The orthographic projection of a portion of the first active connection on the substrate overlaps with the orthographic projection of the gate electrode on the substrate, while the orthographic projection of another portion of the first electrode connection on the substrate does not overlap with the orthographic projection of the gate electrode on the substrate. The orthographic projection of a portion of the second active connection on the substrate overlaps with the orthographic projection of the gate electrode on the substrate, while the orthographic projection of another portion of the second electrode connection on the substrate does not overlap with the orthographic projection of the gate electrode on the substrate. The orthographic projection of the first electrode on the substrate is located within the range of the orthographic projection of the first active connection on the substrate, and the orthographic projection of the second electrode on the substrate is located within the range of the orthographic projection of the second active connection on the substrate. The orthographic projection of the via on the substrate is within the range of the orthographic projection of the active layer on the substrate, and overlaps with the orthographic projections of the first active connection portion and the second active connection portion on the substrate. The via includes multiple boundaries, including a first boundary, a second boundary, a third boundary, and a fourth boundary. The first boundary and the second boundary extend along a first direction, and the third boundary and the fourth boundary extend along a second direction. The first boundary, the fourth boundary, the second boundary, and the third boundary are connected sequentially, and the first boundary, the second boundary, the third boundary, and the fourth boundary are straight lines. The distance between the orthographic projection of the first target boundary on the substrate and the orthographic projection of the first boundary on the substrate along the second direction is less than the distance between the orthographic projection of the first target boundary on the substrate and the orthographic projection of the second boundary on the substrate along the second direction. The distance between the orthographic projection of the second target boundary on the substrate and the orthographic projection of the second boundary on the substrate along the second direction is less than the distance between the orthographic projection of the second target boundary on the substrate and the orthographic projection of the first boundary on the substrate along the second direction. The first target boundary is the boundary where the second electrode connection is close to the first boundary and extends along the first direction. The second target boundary is the boundary where the second electrode connection is close to the first boundary and extends along the first direction.

20. The transistor device according to claim 18 or 19, wherein, The first electrode connection portion and the third boundary at least partially overlap on the substrate, the second electrode connection portion does not overlap with the multiple boundaries on the substrate, the second electrode on the substrate partially overlaps with the first boundary and the second boundary on the substrate, and the fourth boundary does not overlap on the substrate. Alternatively, the orthographic projection of the first electrode connection portion on the substrate at least partially overlaps with the orthographic projection of the third boundary on the substrate, the orthographic projection of the second electrode connection portion on the substrate partially overlaps with the orthographic projections of the first boundary and the second boundary on the substrate, the orthographic projection of the second electrode on the substrate partially overlaps with the orthographic projections of the first boundary and the second boundary on the substrate, and the orthographic projection of the fourth boundary on the substrate does not overlap. Alternatively, the orthographic projection of the via on the substrate does not overlap with the orthographic projections of the first electrode and the second electrode on the substrate, and is located between the orthographic projection of the second electrode connection portion on the substrate and the orthographic projection of the second electrode on the substrate. Alternatively, the orthographic projection of the via on the substrate overlaps with the orthographic projection of the first electrode on the substrate, but does not overlap with the orthographic projection of the second electrode on the substrate, and the orthographic projection of the first electrode connection on the substrate overlaps with the orthographic projection of the third boundary on the substrate, and the orthographic projection of the second electrode connection on the substrate overlaps with the orthographic projections of the first boundary and the second boundary on the substrate, respectively. The distance between the orthographic projection of the first target boundary on the substrate and the orthographic projection of the first boundary on the substrate along the second direction is in the range of 1 micrometer to 1.5 micrometers, and the distance between the orthographic projection of the second target boundary on the substrate and the orthographic projection of the second boundary on the substrate along the second direction is in the range of 1 micrometer to 1.5 micrometers.

21. The transistor device according to claim 20, wherein, When the orthographic projection of the via on the substrate does not overlap with the orthographic projections of the first electrode and the second electrode on the substrate, the distance between the orthographic projection of the boundary of the first electrode near the via on the substrate and the orthographic projection of the third boundary of the via on the substrate along the first direction is greater than or equal to 0, and the distance between the orthographic projection of the boundary of the second electrode near the via on the substrate and the orthographic projection of the fourth boundary of the via on the substrate along the first direction is greater than or equal to 0. The distance between the orthographic projection of the active layer near the first boundary on the substrate and the orthographic projection of the first boundary on the substrate along the second direction is greater than the distance between the orthographic projection of the active layer near the first boundary on the substrate and the orthographic projection of the first target boundary on the substrate along the second direction. The distance between the orthographic projection of the active layer near the second boundary on the substrate and the orthographic projection of the second boundary on the substrate along the second direction is greater than the distance between the orthographic projection of the active layer near the second boundary on the substrate and the orthographic projection of the second target boundary on the substrate along the second direction; or, the distance between the orthographic projection of the active layer near the first boundary on the substrate and the orthographic projection of the first boundary on the substrate along the second direction is less than the distance between the orthographic projection of the active layer near the first boundary on the substrate and the orthographic projection of the first target boundary on the substrate along the second direction. The distance between the orthographic projection of the active layer near the second boundary onto the substrate and the orthographic projection of the second boundary onto the substrate along the second direction is less than the distance between the orthographic projection of the active layer near the second boundary onto the substrate and the orthographic projection of the second target boundary onto the substrate along the second direction.

22. The transistor device of claim 20, wherein, When the orthographic projection of the via on the substrate partially overlaps with the orthographic projection of the first electrode on the substrate, but does not overlap with the orthographic projection of the second electrode on the substrate, The distance between the orthographic projection of the active layer near the first boundary on the substrate and the orthographic projection of the first boundary on the substrate along the second direction is greater than the distance between the orthographic projection of the active layer near the first boundary on the substrate and the orthographic projection of the first target boundary on the substrate along the second direction. The distance between the orthographic projection of the active layer near the second boundary on the substrate and the orthographic projection of the second boundary on the substrate along the second direction is greater than the distance between the orthographic projection of the active layer near the second boundary on the substrate and the orthographic projection of the second target boundary on the substrate along the second direction.

23. The transistor device according to claim 2, wherein, The first electrode includes: a first electrode connecting portion, a second electrode connecting portion, a third electrode connecting portion, and a fourth electrode connecting portion; the first electrode connecting portion and the fourth electrode connecting portion extend along a first direction, the third electrode connecting portion extends along a second direction, the second electrode connecting portion is connected to the first electrode connecting portion and the third electrode connecting portion respectively, and the first electrode connecting portion and the second electrode connecting portion are set at an obtuse angle, the second electrode connecting portion and the third electrode connecting portion are set at an obtuse angle, the fourth electrode connecting portion and the third electrode connecting portion are set at a right angle, and the second electrode extends along the second direction; The orthographic projection of a portion of at least one of the first and second electrodes onto the substrate does not overlap with the orthographic projection of the gate electrode onto the substrate.

24. The transistor device of claim 23, wherein, The via includes: a first boundary, a second boundary, a third boundary, and a fourth boundary; the first boundary and the second boundary extend along a first direction, and the third boundary and the fourth boundary extend along a second direction; the first boundary, the fourth boundary, the second boundary, and the third boundary are connected in sequence; the first boundary, the second boundary, the third boundary, and the fourth boundary are straight in shape. The orthographic projection of the second electrode on the substrate overlaps with the orthographic projection of the second boundary on the substrate; the orthographic projection of the first electrode connection on the substrate overlaps with the orthographic projection of the third boundary on the substrate; the orthographic projections of the second electrode connection and the third electrode connection on the substrate do not overlap with the orthographic projections of the multiple boundaries on the substrate; and the orthographic projection of the fourth electrode connection on the substrate overlaps with the orthographic projection of the fourth boundary on the substrate.

25. The transistor device according to claim 23, wherein, The via includes: a first boundary, a second boundary, a third boundary, a fourth boundary, and a fifth boundary; the first and second boundaries extend along a first direction, the third and fourth boundaries extend along a second direction, and the first, fifth, fourth, second, and third boundaries are connected sequentially; the first, second, third, fourth, and fifth boundaries are straight lines, the fifth boundary is set at an obtuse angle to the first boundary, and the fourth boundary is set at an obtuse angle to the fifth boundary; The orthographic projection of the first electrode connection portion on the substrate overlaps with the orthographic projections of the first boundary and the third boundary on the substrate, respectively. The orthographic projection of the second electrode connection portion on the substrate overlaps with the orthographic projection of the fifth boundary on the substrate. The orthographic projection of the third electrode connection portion on the substrate overlaps with the orthographic projection of the fourth boundary on the substrate. The orthographic projection of the fourth electrode connection portion on the substrate does not overlap with the orthographic projections of the multiple boundaries on the substrate. Alternatively, the orthographic projection of the first electrode on the substrate does not overlap with the orthographic projections of multiple boundaries on the substrate; the orthographic projection of the second electrode on the substrate overlaps with the orthographic projection of the second boundary on the substrate; the distance along the second direction between the boundary of the third electrode connection near the second boundary on the substrate and the boundary of the active layer near the second boundary is less than the distance along the second direction between the orthographic projection of the second boundary on the substrate and the boundary of the active layer near the second boundary; the distance along the second direction between the orthographic projection of the first electrode connection near the first boundary of the via on the substrate and the orthographic projection of the first boundary on the substrate is greater than or equal to 0; the distance along the second direction between the orthographic projection of the second electrode connection near the second boundary of the via on the substrate and the orthographic projection of the second boundary on the substrate is greater than or equal to 0; and the distance along the second direction between the orthographic projection of the third electrode connection near the third boundary of the via on the substrate and the orthographic projection of the third boundary on the substrate is greater than or equal to 0.

26. The transistor device according to claim 23, wherein, The via includes: a first boundary, a second boundary, a third boundary, a fourth boundary, a fifth boundary, a sixth boundary, and a seventh boundary. The first boundary, the fourth boundary, and the sixth boundary extend along a second direction, and the third boundary, the fifth boundary, and the seventh boundary extend along a first direction. The first boundary to the seventh boundary are connected sequentially, and at least one of the first boundary to the seventh boundary has a straight line shape. The second boundary is set at an obtuse angle to the first boundary and the third boundary, the third boundary is set at a right angle to the fourth boundary, the fourth boundary is set at a right angle to the fifth boundary, the fifth boundary is set at a right angle to the sixth boundary, the sixth boundary is set at a right angle to the seventh boundary, the seventh boundary is set at a right angle to the first boundary, and the distance between the sixth boundary and the first boundary is less than the distance between the fourth boundary and the first boundary; The orthographic projection of the first electrode connection portion on the substrate overlaps with the orthographic projections of the first boundary and the seventh boundary on the substrate, respectively. The orthographic projection of the second electrode connection portion on the substrate overlaps with the orthographic projection of the second boundary on the substrate. The orthographic projection of the third electrode connection portion on the substrate overlaps with the orthographic projection of the third boundary on the substrate. The orthographic projection of the fourth electrode connection portion on the substrate does not overlap with multiple boundaries. The orthographic projection of the second electrode on the substrate overlaps with the orthographic projections of the fourth boundary, the fifth boundary and the sixth boundary on the substrate, respectively. Alternatively, the orthographic projections of the first electrode and the second electrode onto the substrate do not overlap with the orthographic projections of the plurality of boundaries onto the substrate.

27. The transistor device of claim 26, wherein, When the orthographic projections of the first electrode and the second electrode on the substrate do not overlap with the orthographic projections of the multiple boundaries on the substrate. The distance between the orthographic projection of the boundary of the first electrode connection near the via on the substrate and the orthographic projection of the first boundary on the substrate is greater than or equal to 0; the distance between the orthographic projection of the boundary of the second electrode connection near the via on the substrate and the orthographic projection of the second boundary on the substrate is greater than or equal to 0; the distance between the orthographic projection of the boundary of the third electrode connection near the via on the substrate and the orthographic projection of the third boundary on the substrate is greater than or equal to 0; the distance between the orthographic projection of the boundary of the second electrode near the via and extending along the second direction on the substrate and the orthographic projection of the fifth boundary on the substrate is greater than or equal to 0; the distance between the orthographic projection of the boundary of the second electrode near the via and extending along the first direction on the substrate and the orthographic projection of the sixth boundary on the substrate is greater than or equal to 0. The distance between the orthographic projection of the active layer near the fourth boundary onto the substrate and the orthographic projection of the fourth boundary onto the substrate along the second direction is greater than the distance between the boundary of the third electrode connection near the fourth boundary and the orthographic projection of the fourth boundary onto the substrate along the second direction. The distance between the orthographic projection of the active layer near the seventh boundary onto the substrate and the orthographic projection of the seventh boundary onto the substrate along the second direction is greater than the maximum distance between the boundary of the second electrode near the seventh boundary and the orthographic projection of the seventh boundary onto the substrate along the second direction. Alternatively, the distance between the orthographic projection of the active layer near the fourth boundary onto the substrate and the orthographic projection of the fourth boundary onto the substrate along the second direction is less than the distance between the boundary of the third electrode connection near the fourth boundary and the orthographic projection of the fourth boundary onto the substrate along the second direction. The distance between the orthographic projection of the active layer near the seventh boundary onto the substrate and the orthographic projection of the seventh boundary onto the substrate along the second direction is less than the maximum distance between the boundary of the second electrode near the seventh boundary and the orthographic projection of the seventh boundary onto the substrate along the second direction. The maximum distance along the second direction between the boundary of the second electrode near the seventh boundary and the orthographic projection of the seventh boundary on the substrate is in the range of 1 micrometer to 1.5 micrometers, and the distance along the second direction between the boundary of the third electrode connection near the fourth boundary and the orthographic projection of the fourth boundary on the substrate is in the range of 1 micrometer to 1.5 micrometers.

28. The transistor device of claim 26, wherein, The number of transistor devices is two, and the target transistor device is at least partially symmetrical with respect to the straight line extending along the second direction with respect to the straight line extending along the first direction. The second electrode of the first transistor device and the second electrode of the second transistor device are the same electrode.

29. The transistor device according to claim 1, wherein, The gate electrode includes a first gate electrode and a second gate electrode that are connected to each other. The transistor device further includes a connection electrode located on the side of the first electrode and the second electrode away from the substrate. The orthographic projection of the active layer on the substrate at least partially overlaps with the orthographic projection of the first gate electrode on the substrate, but does not overlap with the orthographic projection of the second gate electrode on the substrate, and the connecting electrode is electrically connected to the second gate electrode. The connecting electrode is a transparent electrode.

30. The transistor device according to claim 1, wherein, In the direction perpendicular to the substrate, the active layer includes: a first active layer and a second active layer, the second active layer being disposed on the side of the first active layer away from the substrate, and the second active layer including: a first active structure and a second active structure; The orthographic projection of the second active layer on the substrate is within the range of the orthographic projection of the first active layer on the substrate, the orthographic projection of the first active structure on the substrate is within the range of the orthographic projection of the first electrode on the substrate, and the orthographic projection of the second active structure on the substrate is within the range of the orthographic projection of the second electrode on the substrate. The thickness of the first active layer is greater than the thickness of the second active layer, and the conductivity of the second active layer is greater than that of the first active layer.

31. The transistor device according to claim 1, wherein, The thickness of the via along the direction perpendicular to the substrate is in the range of 1500 angstroms to 3500 angstroms.

32. A display substrate, comprising: Multiple transistor devices as described in any one of claims 1 to 31.

33. The display substrate according to claim 32, wherein, The display substrate has a display area and a non-display area. The display area is provided with a plurality of first circuits, and the non-display area is provided with a plurality of second circuits. At least one of the first circuits and the second circuits includes at least one switching device. The second circuit includes a gate driving circuit, a source driving circuit, a multiplexing circuit, an electrostatic discharge circuit, an array test circuit, and a lamp testing circuit. At least one switching device in at least one of the first circuit and the second circuit is a transistor device.

34. The display substrate according to claim 32, wherein, The gate drive circuit includes multiple shift registers, and at least one shift register includes an input transistor and an output transistor; The input transistor and the output transistor are the transistor devices.

35. The display substrate according to claim 32, further comprising: A photosensitive structure configured to convert optical signals into electrical signals; The photosensitive structure includes at least one photosensitive switching device, wherein the at least one photosensitive switching device is the transistor device.

36. A method for fabricating a transistor device, wherein, The method, configured to manufacture a transistor device as described in any one of claims 1 to 31, comprises: The gate electrode of a transistor device is formed on the substrate; A gate insulating layer and an active layer of a transistor device are formed on the gate electrode. The gate insulating layer includes a first insulating layer and a second insulating layer stacked on the substrate. One of the first insulating layer and the second insulating layer is provided with a via. The orthographic projection of the via on the substrate at least partially overlaps with the orthographic projection of the active layer on the substrate. A first electrode and a second electrode are formed on the active layer; The formation of the gate insulating layer and active layer of the transistor device on the gate electrode includes: A first insulating layer is formed on the gate electrode, and the first insulating layer has a via. A second insulating layer is formed from the first insulating layer; A primary semiconductor layer is formed on the second insulating layer, the primary semiconductor layer comprising: a first active layer and a third active layer; A first electrode, a second electrode, and an active layer are formed on the original semiconductor layer. The active layer includes a first active layer and a second active layer.

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