Pixel circuit, display panel and display apparatus

By introducing driving transistors and threshold compensation transistors into the pixel circuit of the OLED display panel and using shielding capacitors to stabilize the gate potential of the driving transistors, the flickering problem caused by unstable potential at the control terminal of the driving module is solved, resulting in a more stable display effect.

WO2026129673A1PCT designated stage Publication Date: 2026-06-25WUHAN TIANMA MICROELECTRONICS CO LTD SHANGHAI BRANCH +1
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Patent Information

Authority / Receiving Office
WO · WO
Patent Type
Applications
Current Assignee / Owner
WUHAN TIANMA MICROELECTRONICS CO LTD SHANGHAI BRANCH
Filing Date
2025-08-06
Publication Date
2026-06-25

AI Technical Summary

Technical Problem

When certain modules of an existing OLED display panel are turned off, the control terminal potential of the driving module becomes unstable, causing changes in the display brightness of the light-emitting module. This is especially noticeable in low-frequency displays, where varying degrees of flickering occur, affecting the display effect.

Method used

A pixel circuit design is adopted, including a driving transistor and a threshold compensation transistor. The threshold compensation transistor includes a first sub-threshold compensation transistor and a second sub-threshold compensation transistor. By setting the overlap area of ​​the first connection region and the shielding layer to satisfy a specific formula, a shielding capacitor is formed to store charge to stabilize the gate potential of the driving transistor.

Benefits of technology

It effectively reduces the leakage current of the threshold compensation transistor to the gate of the driving transistor, maintains the gate potential stability of the driving transistor, solves the low-frequency flicker problem of the display panel, and improves the uniformity of the display.

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Abstract

The present application relates to a pixel circuit, a display panel and a display apparatus. The pixel circuit comprises: a driving transistor, a threshold compensation transistor and a shielding layer, wherein the threshold compensation transistor comprises a first threshold compensation sub-transistor and a second threshold compensation sub-transistor; an active layer of the threshold compensation transistor comprises a first channel sub-region, a second channel sub-region and a first connection region; the first channel sub-region and the second channel sub-region are electrically connected to each other by means of the first connection region; and in a direction perpendicular to the active layer, the first channel sub-region at least partially overlaps a gate electrode of the first threshold compensation sub-transistor, the second channel sub-region at least partially overlaps a gate electrode of the second threshold compensation sub-transistor, and the overlapping area A of the first connection region and the shielding layer satisfies formula (I) and formula (II). In the present application, the stability of the potential of a gate electrode of a driving transistor can be maintained, thereby solving the problem of the low-frequency flicker of the display panel.
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Claims

1. A pixel circuit, characterized in that, include: Drive transistors; Threshold compensation transistor; The threshold compensation transistor includes a first sub-threshold compensation transistor and a second sub-threshold compensation transistor; The first terminal of the first sub-threshold compensation transistor is electrically connected to the gate of the driving transistor; the second terminal of the first sub-threshold compensation transistor is electrically connected to the first terminal of the second sub-threshold compensation transistor; the second terminal of the second sub-threshold compensation transistor is electrically connected to the first terminal of the driving transistor; the gates of the first sub-threshold compensation transistor and the gates of the second sub-threshold compensation transistor are electrically connected; the active layer of the threshold compensation transistor includes a first sub-channel region, a second sub-channel region, and a first connection region; the first sub-channel region and the second sub-channel region are electrically connected through the first connection region; Shielding layer; Wherein, in the direction perpendicular to the active layer, the first sub-channel region at least partially overlaps with the gate of the first sub-threshold compensation transistor, the second sub-channel region at least partially overlaps with the gate of the second sub-threshold compensation transistor, and the overlap area A between the first connection region and the shielding layer satisfies: Among them, C ox1 V is the unit area capacitance of the MIS structure of the threshold compensation transistor; 01 d1 is the gate potential of the driving transistor before the threshold compensation transistor is turned off; d1 is the thickness of the insulating layer between the shielding layer and the first connection region; ε1 is the relative permittivity of the insulating layer between the shielding layer and the first connection region; N1 is the gate potential of the driving transistor before the pixel is driven to emit light by the pixel circuit; V g1 The threshold compensation transistor is the gate potential of the threshold compensation transistor after it is turned off; a1 is a preset constant; W1 is the channel width of the first sub-threshold compensation transistor; L1 is the channel length of the first sub-threshold compensation transistor; W2 is the channel width of the second sub-threshold compensation transistor; L2 is the channel length of the second sub-threshold compensation transistor.

2. The pixel circuit according to claim 1, characterized in that, The overlap area A between the first connection area and the shielding layer also satisfies: A <b1(W1*L1+W2*L2); Where b1 is a preset constant.

3. The pixel circuit according to claim 1, characterized in that, This also includes initializing transistors; The initialization transistor includes a first sub-initialization transistor and a second sub-initialization transistor; the first terminal of the first sub-initialization transistor is electrically connected to an initialization signal line; the second terminal of the first sub-initialization transistor is electrically connected to the first terminal of the second sub-initialization transistor; the second terminal of the second sub-initialization transistor is electrically connected to the gate of the driving transistor; the gates of the first and second sub-initialization transistors are electrically connected; the active layer of the initialization transistor includes a third sub-channel region, a fourth sub-channel region, and a second connection region; the third sub-channel region and the fourth sub-channel region are electrically connected through the second connection region. In the direction perpendicular to the active layer, the third sub-channel region at least partially overlaps with the gate of the first sub-initialization transistor, the fourth sub-channel region at least partially overlaps with the gate of the second sub-initialization transistor, and the overlap area B between the second connection region and the shielding layer satisfies: Among them, C ox2 The unit area capacitance of the MIS structure of the initialization transistor; V 02 d2 is the gate potential of the driving transistor before the initialization transistor is turned off; d2 is the thickness of the insulating layer between the shielding layer and the second connection region; ε2 is the relative permittivity of the insulating layer between the shielding layer and the second connection region; N1 is the gate potential of the driving transistor before the pixel circuit drives the pixel to emit light; V g2 The initialization transistor is the gate potential of the initialization transistor after it is turned off; a2 is a preset constant; W3 is the channel width of the second sub-initialization transistor; L3 is the channel length of the second sub-initialization transistor; W4 is the channel width of the first sub-initialization transistor; L4 is the channel length of the first sub-initialization transistor.

4. The pixel circuit according to claim 1, characterized in that, 0≤a1≤2。 5. The pixel circuit according to claim 3, characterized in that, The overlap area A between the first connection area and the shielding layer, and the overlap area B between the second connection area and the shielding layer satisfy the following: Where b2 is a preset constant.

6. The pixel circuit according to claim 1, characterized in that, It also includes the third-sub-initialization transistor; The first terminal of the third sub-initialization transistor is electrically connected to the initialization signal line; The second terminal of the third sub-initialization transistor is electrically connected to the second terminal of the second sub-threshold compensation transistor.

7. The pixel circuit according to claim 1, characterized in that, The shielding layer is disposed on the same layer as the capacitor metal layer of the pixel circuit.

8. The pixel circuit according to claim 1, characterized in that, The shielding layer is disposed on the same layer as any one of the source / drain metal layer, gate metal layer, and light-shielding metal layer of the pixel circuit.

9. The pixel circuit according to claim 1, characterized in that, The shielding layer is disposed in the same layer as the metal layer of the nearest adjacent active layer.

10. The pixel circuit according to claim 1, characterized in that, It also includes a storage capacitor; the storage capacitor is connected between the gate of the driving transistor and the first power supply line.

11. The pixel circuit according to claim 1, characterized in that, The shielding layer is used to receive power signals or reset signals.

12. The pixel circuit according to any one of claims 1-11, characterized in that, W1 / L1 is less than or equal to W2 / L2.

13. The pixel circuit according to any one of claims 3-5, characterized in that, W3 / L3 is less than or equal to W4 / L4.

14. A display panel, characterized in that, Includes the pixel circuit as described in any one of claims 1-13.

15. A display device, characterized in that, Includes the display panel as described in claim 14.