Display panel

Abstract

A display panel (1) includes: an auxiliary capacitance unit (SLSCP) that is for a scanning signal line (SL3) and includes a first auxiliary capacitance electrode (SCE1) electrically connected to the scanning signal line (SL3), and a first auxiliary capacitance-forming counter electrode (SCE 1') opposite to the first auxiliary capacitance electrode (SCE1); and an auxiliary capacitance unit (DLSCP) that is for data signal lines (D7, D8, D9) and includes second auxiliary capacitance electrodes (SCE2, SCE2', SCE2") electrically connected to the data signal lines (D7, D8, D9), and a first auxiliary capacitance-forming counter electrode (SCE1') opposite to the second auxiliary capacitance electrodes (SCE2, SCE2', SCE2").

Description

Display panel

[0001] The present disclosure relates to a display panel.

[0002] In recent years, in the field of display panels, such as display panels equipped with light-emitting elements, for example, OLEDs (Organic Light Emitting Diodes) or QLEDs (Quantum dot Light Emitting Diodes), and display panels equipped with liquid crystal layers, active development has been underway to meet demands for improved design and diversified uses, including display areas of irregular shapes, such as circles, ellipses, triangles, polygons with pentagons or more, and trapezoids.

[0003] Patent Document 1 describes forming a capacitance in a display panel including an irregularly shaped display area by crossing a portion of a scanning signal line with a small load capacitance with a portion of a data signal line with a small load capacitance, with an insulating layer sandwiched between them.

[0004] International Publication WO2008 / 062575 A1

[0005] However, in the display panel described in Patent Document 1, the above-mentioned capacitance is configured by a scanning signal line, a data signal line, and an insulating layer provided between the scanning signal line and the data signal line. Therefore, due to capacitive coupling between the scanning signal line and the data signal line in the portion forming the capacitance, the scanning signal supplied to the scanning signal line and the data signal supplied to the data signal line affect each other, which causes a problem of a deterioration in display quality.

[0006] An aspect of the present disclosure aims to provide a display panel that improves display image quality by reducing the difference in load capacitance between multiple scanning signal lines and the difference in load capacitance between multiple data signal lines, while suppressing an increase in the non-display area and capacitive coupling between scanning signal lines and data signal lines in portions that form capacitance.

[0007] In order to solve the above-mentioned problems, the display panel of the present disclosure includes: a plurality of pixel circuits; a first scanning signal line electrically connected to M (M is a natural number greater than or equal to 2) pixel circuits of the plurality of pixel circuits that are provided in a first region; a second scanning signal line electrically connected to less than M pixel circuits of the plurality of pixel circuits that are provided in a second region; a first data signal line electrically connected to N (N is a natural number greater than or equal to 2) pixel circuits of the plurality of pixel circuits that are provided in a third region; a second data signal line electrically connected to less than N pixel circuits of the plurality of pixel circuits that are provided in a fourth region; an auxiliary capacitance section of the second scanning signal line including a first auxiliary capacitance electrode electrically connected to the second scanning signal line and a first auxiliary capacitance-forming opposing electrode facing the first auxiliary capacitance electrode; and an auxiliary capacitance section of the second data signal line including a second auxiliary capacitance electrode electrically connected to the second data signal line and the first auxiliary capacitance-forming opposing electrode facing the second auxiliary capacitance electrode.

[0008] According to one aspect of the present disclosure, a display panel can be provided that improves display image quality by reducing the difference in load capacitance between multiple scanning signal lines and the difference in load capacitance between multiple data signal lines, while suppressing an increase in the non-display area and capacitive coupling between scanning signal lines and data signal lines in the portion that forms capacitance.

[0009] 1 is a plan view showing a schematic configuration of a display panel of Embodiment 1. FIG. 2 is a partially enlarged view of an X portion of the display panel of Embodiment 1 shown in FIG. 1. FIG. 3 is a circuit diagram showing an example of a pixel circuit provided in the display panel of Embodiment 1. FIG. 4 is a cross-sectional view taken along line A-A' of the display panel of Embodiment 1 shown in FIG. 2, showing a schematic configuration of an auxiliary capacitance section. FIG. 5 is a cross-sectional view taken along line B-B' of the display panel of Embodiment 1 shown in FIG. 2, showing a schematic configuration of an auxiliary capacitance section. FIG. 6 is a diagram showing a schematic configuration of another auxiliary capacitance section that can be provided in the display panel of Embodiment 1. FIG. 7 is a diagram for explaining that the number of electrically connected pixel circuits varies depending on the positions of the scanning signal lines and the data signal lines in the display panel of Embodiment 1. FIG. 8 is a diagram showing an example of an auxiliary capacitance section that is preferably provided in a Y portion of the display panel of Embodiment 1 shown in FIG. 7. FIG. 9 is a diagram showing another example of an auxiliary capacitance section that is preferably provided in a Z ...10 is a diagram showing a first frame region in the display panel of Embodiment 1, in which a plurality of auxiliary capacitance sections are provided. 13 is a diagram showing a first frame region in which a plurality of storage capacitors are provided in a display panel that is a first modified example of the display panel of Embodiment 1 shown in Fig. 12. FIG. 14 is a diagram showing a first frame region in which a plurality of storage capacitors are provided in a display panel that is a second modified example of the display panel of Embodiment 1 shown in Fig. 12. FIG. 15 is a plan view showing a schematic configuration of a display panel of Embodiment 2. FIG. 16 is a cross-sectional view taken along line CC' of the display panel of Embodiment 3 shown in Fig. 16, showing a schematic configuration of a storage capacitor.

[0010] The following describes embodiments of the present disclosure with reference to Figures 1 to 17. For the sake of convenience, components having the same functions as those described in specific embodiments will be denoted by the same reference numerals, and their description may be omitted.

[0011] [Embodiment 1] FIG. 1 is a plan view showing a schematic configuration of a display panel 1 of Embodiment 1. FIG. 2 is a partial enlarged view of portion X of the display panel 1 of Embodiment 1 shown in FIG. 1. FIG. 3 is a circuit diagram showing an example of a pixel circuit GC(1,1) provided in the display panel 1 of Embodiment 1. FIG. 4 is a cross-sectional view taken along line A-A' of the display panel 1 of Embodiment 1 shown in FIG. 2, showing a schematic configuration of the storage capacitance unit SCP3. FIG. 5 is a cross-sectional view taken along line B-B' of the display panel 1 of Embodiment 1 shown in FIG. 2, showing a schematic configuration of the storage capacitance unit SCP3.

[0012] In this embodiment, as shown in FIG. 1 , the display panel 1 includes a circular display area DA, and the shape of the display panel itself is also circular. However, this is not limiting. The display panel 1 may have an irregularly shaped display area DA, and may have a display area DA that is not circular, but is instead elliptical, triangular, polygonal with pentagons or more, trapezoidal, or other shapes. Furthermore, since the display panel 1 has an irregularly shaped display area DA, the shape of the display panel itself may be different from the irregularly shaped display area DA. For example, the shape of the display panel itself may be rectangular, which is different from the irregularly shaped display area DA, such as a circle, ellipse, triangle, polygonal with pentagons or more, trapezoidal, or other irregularly shaped display area DA.

[0013] As shown in Fig. 1 , a plurality of scanning signal lines, to which scanning signals necessary for displaying in the display area DA are supplied, are spaced a predetermined distance apart in the vertical direction (vertical direction in Fig. 1 ) of the circular display area DA of the display panel 1, and a plurality of data signal lines, to which data signals necessary for displaying in the display area DA are supplied, are spaced a predetermined distance apart in the horizontal direction (horizontal direction in Fig. 1 ) of the circular display area DA of the display panel 1. A relatively long scanning signal line Sl is provided near the vertical center of the display area DA, and relatively short scanning signal lines Ss are provided near the top and bottom ends of the display area DA. On the other hand, a relatively long data signal line Dl is provided near the horizontal center of the display area DA, and relatively short data signal lines Ds are provided near the right and left ends of the display area DA.

[0014] As shown in Fig. 2, a circular display area DA of the display panel 1 includes a plurality of pixels PIX. Each of the plurality of pixels PIX includes a pixel circuit GC. The pixel PIX(1,1) shown in Fig. 2 includes a pixel circuit GC(1,1) shown in Fig. 3 that is electrically connected to a scanning signal line SL1 and a data signal line D1, and each pixel other than the pixel PIX(1,1) also includes a pixel circuit GC similar to the pixel circuit GC(1,1) shown in Fig. 3 that is electrically connected to the scanning signal line and the data signal line that control the corresponding pixel.

[0015] As shown in FIG. 3 , in a pixel circuit GC(1,1) including a light-emitting element LED, the drain electrode of a transistor TR1, which is a driving transistor, is electrically connected to a pixel electrode E1, which is one electrode (e.g., an anode) of the light-emitting element LED. The gate electrode of the transistor TR1 is electrically connected to one electrode of a storage capacitor C1 and a drain electrode of a transistor TR2, which is a selection transistor. The source electrode of the transistor TR1 is electrically connected to the other electrode of the storage capacitor C1 and an ELVDD wiring VL, to which a high-level power supply voltage ELVDD is supplied from a power supply circuit (not shown). The counter electrode E2, which is the other electrode (e.g., a cathode) of the light-emitting element LED, is electrically connected to an ELVSS wiring, to which a low-level power supply voltage ELVSS is supplied from a power supply circuit (not shown). The source electrode of the transistor TR2, which is a selection transistor, is electrically connected to a data signal line D1, to which a data signal output from a data-side driving circuit (not shown) is supplied. The gate electrode of the transistor TR2 is electrically connected to a scanning signal line SL1, to which a scanning signal output from a scanning-side driving circuit SC1 (shown in FIG. 2) is supplied. The light-emitting element LED included in the pixel circuit GC(1,1) shown in FIG. 3 may include, for example, a quantum dot-containing light-emitting layer or an organic light-emitting layer. In this embodiment, as shown in FIG. 3 , the transistor TR2 serving as a selection transistor having a gate electrode electrically connected to the scanning signal line SL1 is described as a P-type transistor, but this is not limiting, and the transistor TR2 serving as a selection transistor may be an N-type transistor. Note that in this embodiment, the pixel circuit GC provided in the display panel 1 is described as including a light-emitting element LED as shown in FIG. 3 , but this is not limiting. The pixel circuit GC provided in the display panel 1 may be, for example, a pixel circuit including a display element including a pixel electrode E1, a counter electrode E2, and a liquid crystal layer provided between the pixel electrode E1 and the counter electrode E2, and a transistor whose gate electrode is electrically connected to the scanning signal line, whose source electrode is electrically connected to the data signal line, and whose drain electrode is electrically connected to the pixel electrode E1.

[0016] As described above, when the display area DA is circular, the plurality of scanning signal lines provided in the display area DA having an irregular shape other than a circle, such as an ellipse, a triangle, a polygon having five or more sides, or a trapezoid, necessarily include relatively long scanning signal lines Sl and relatively short scanning signal lines Ss, as shown in Fig. 1. Similarly, when the display area DA is circular, the plurality of data signal lines provided in the display area DA having an irregular shape other than a circle, such as an ellipse, a triangle, a polygon having five or more sides, or a trapezoid, necessarily include relatively long data signal lines Dl and relatively short data signal lines Ds, as shown in Fig. 1. Here, an example will be described in which the relatively long scanning signal line Sl shown in FIG. 1 is the scanning signal line SL1 shown in FIG. 2, and the relatively short scanning signal line Ss shown in FIG. 1 is the scanning signal line SL3 shown in FIG. 2, but this is not limiting, and the relatively long scanning signal line Sl shown in FIG. 1 may be any scanning signal line that is longer, and the relatively short scanning signal line Ss shown in FIG. 1 may be any scanning signal line that is shorter. 2 , the scanning signal line (first scanning signal line) SL1 is electrically connected to M (M is a natural number equal to or greater than 2) pixel circuits GC arranged in a first region among the plurality of pixel circuits GC, i.e., the first region corresponding to a pixel group having a Y value of 1 among the plurality of pixels PIX(X, Y) arranged on the XY coordinate system, and the scanning signal line (second scanning signal line) SL3 is electrically connected to less than M pixel circuits GC arranged in a second region among the plurality of pixel circuits GC, i.e., the pixel group having a Y value of 3 among the plurality of pixels PIX(X, Y) arranged on the XY coordinate system. Therefore, the load capacitance of the scanning signal line (first scanning signal line) SL1 shown in FIG. 2 , the scanning signal line (second scanning signal line) SL3 is larger than the load capacitance of the scanning signal line (second scanning signal line) SL3 shown in FIG. 2 , the scanning signal line (first scanning signal line) SL1 is shorter.1 is the data signal line D1 shown in FIG. 2, and the relatively short data signal line Ds shown in FIG. 1 is the data signal line D7 shown in FIG. 2. However, the present invention is not limited to this example, and the relatively long data signal line Dl shown in FIG. 1 may be any data signal line having a longer length, and the relatively short data signal line Ds shown in FIG. 1 may be any data signal line having a shorter length. 2 , which is longer, is electrically connected to N (N is a natural number greater than or equal to 2) pixel circuits GC provided in a third region among the plurality of pixel circuits GC, i.e., the third region corresponding to a pixel group having an X value of 1 among the plurality of pixels PIX(X, Y) arranged on the XY coordinate system, and the data signal line (second data signal line) D7 shown in FIG. 2 , which is shorter, is electrically connected to a fourth region among the plurality of pixel circuits GC, i.e., less than N pixel circuits GC provided in a pixel group having an X value of 7 among the plurality of pixels PIX(X, Y) arranged on the XY coordinate system. Therefore, the load capacitance of the longer data signal line (first data signal line) D1 shown in FIG. 2 is greater than the load capacitance of the shorter data signal line (second data signal line) D7 shown in FIG. 2 .

[0017] As shown in FIG. 3 , each of the plurality of pixel circuits GC includes a pixel electrode E1. Therefore, in a display area DA of the display panel 1 including the plurality of pixel electrodes E1, the number of pixel electrodes E1 in some regions along the vertical direction in FIG. 2 , for example, the region where the data signal line (first data signal line) D1 is provided, is different from the number of pixel electrodes E1 in other regions along the vertical direction in FIG. 2 , for example, the region where the data signal line (second data signal line) D7 is provided, and the number of pixel electrodes E1 in some regions along the horizontal direction in FIG. 2 , for example, the region where the scanning signal line (first scanning signal line) SL1 is provided, is different from the number of pixel electrodes E1 in other regions along the horizontal direction in FIG. 2 , for example, the region where the scanning signal line (second scanning signal line) SL3 is provided.

[0018] As described above, if the load capacitance of the scanning signal lines or the load capacitance of the data signal lines differs depending on the location within the display area DA of the display panel 1, the target voltage to be applied to the scanning signal lines cannot be applied with high precision to each of the multiple scanning signal lines, and the target voltage to be applied to the data signal lines cannot be applied with high precision to each of the multiple data signal lines. In such cases, as a result, when displaying, the brightness and color will differ slightly depending on the location within the display area DA, which will be perceived as display unevenness and will result in a deterioration in display quality.

[0019] Therefore, in the display panel 1 of this embodiment, in order to reduce the differences in the load capacitance of the scanning signal lines and the data signal lines that occur depending on the location within the display area DA, a scanning signal line auxiliary capacitance portion is provided for each of the multiple scanning signal lines, and a data signal line auxiliary capacitance portion is provided for each of the multiple data signal lines. The scanning signal line auxiliary capacitance portion and the data signal line auxiliary capacitance portion share a common auxiliary capacitance-forming opposing electrode and are arranged to overlap in a plan view to form an auxiliary capacitance portion. Here, the function and configuration of auxiliary capacitance portions SCP1, SCP2, SCP3, and SCP4 shown in FIG. 2, which are some of the auxiliary capacitance portions provided in the display panel 1, will be described as an example. As shown in FIGS. 2, 4, and 5, the auxiliary capacitance portion SCP3 includes an auxiliary capacitance portion SLSCP of the scanning signal line SL3 and auxiliary capacitance portions DLSCP of the data signal line D7, data signal line D8, and data signal line D9. 4 and 5, the storage capacitance portion SLSCP of the scanning signal line SL3 is composed of a first storage capacitance electrode SCE1 electrically connected to the scanning signal line SL3 and an extension portion SL3' of the scanning signal line SL3, a first insulating layer INS1, and a first storage capacitance-forming counter electrode SCE1' facing the first storage capacitance electrode SCE1. The extension portion SL3' of the scanning signal line SL3 is electrically connected to the scanning-side driving circuit SC3 shown in FIG. 2 and is also electrically connected to the first storage capacitance electrode SCE1 via a conductive member CNP2. The scanning signal line SL3 is electrically connected to the first storage capacitance electrode SCE1 via a conductive member CNP1.As shown in FIG. 4, the storage capacitance portion DLSCP of the data signal line D9 is composed of a first storage capacitance-forming counter electrode SCE1′, a second insulating layer INS2 and a third insulating layer INS3, and a second storage capacitance electrode SCE2 electrically connected to the data signal line D9. As shown in FIGS. 4 and 5, the storage capacitance portion DLSCP of the data signal line D8 is composed of a first storage capacitance-forming counter electrode SCE1′, a second insulating layer INS2 and a third insulating layer INS3, and a second storage capacitance electrode SCE2′ electrically connected to the data signal line D8. As shown in FIG. 4, the storage capacitance portion DLSCP of the data signal line D7 is composed of a first storage capacitance-forming counter electrode SCE1′, a second insulating layer INS2 and a third insulating layer INS3, and a second storage capacitance electrode SCE2″ electrically connected to the data signal line D7. 4 and 5 , the storage capacitance portion SLSCP of the scanning signal line SL3 and the storage capacitance portions DLSCP of the data signal line D7, the data signal line D8, and the data signal line D9 have a common first storage capacitance-forming counter electrode SCE1′ and are arranged so as to overlap in a plan view to form the storage capacitance portion SCP3. In the storage capacitance portion SCP3, a first storage capacitance-forming counter electrode SCE1′ is provided between the first storage capacitance electrode SCE1 electrically connected to the scanning signal line SL3 and each of the second storage capacitance electrode SCE2″ electrically connected to the data signal line D7, the second storage capacitance electrode SCE2′ electrically connected to the data signal line D8, and the second storage capacitance electrode SCE2 electrically connected to the data signal line D9. It is preferable to apply a specific voltage, i.e., a certain constant voltage, to the first storage capacitance-forming counter electrode SCE1′. In this way, by applying a certain constant voltage to the first auxiliary capacitance forming counter electrode SCE1', it is possible to suppress the influence of capacitive coupling that may occur due to the scanning signal or data signal, which is a pulse-like voltage signal.Furthermore, the second auxiliary capacitance electrode SCE2″ electrically connected to the second data signal line D7, the second auxiliary capacitance electrode SCE2′ electrically connected to the second data signal line D8, and the second auxiliary capacitance electrode SCE2 electrically connected to the second data signal line D9, and the first auxiliary capacitance electrode SCE1 electrically connected to the scanning signal line SL3, respectively, form separate auxiliary capacitance portions, such as the data signal line auxiliary capacitance portion DLSCP and the scanning signal line auxiliary capacitance portion SLSCP. This makes it possible to reduce the influence of coupling between the scanning signal supplied to the scanning signal line SL3 and the data signals supplied to the data signal lines D7, D8, and D9. In this embodiment, as shown in FIG. 4 , for example, a high-level power supply voltage ELVDD is supplied to the first auxiliary capacitance-forming counter electrode SCE1′ as a stable DC power supply from the power supply circuit PSU. This configuration makes it possible to reduce the influence of coupling between the scanning signal supplied to the scanning signal line SL3 and the data signals supplied to the data signal lines D7, D8, and D9. In the above-described storage capacitance section SCP3, the storage capacitance section SLSCP of the scanning signal line SL3 and the storage capacitance sections DLSCP of the data signal lines D7, D8, and D9 are arranged to overlap each other in a planar view, so that the required capacitance can be secured while preventing the non-display area from becoming larger. Note that each of the multiple storage capacitance sections provided in the display panel 1, including the storage capacitance sections SCP1, SCP2, and SCP4 other than the storage capacitance section SCP3, differs from the storage capacitance section SCP3 only in the capacitance of the storage capacitance section DLSCP of the data signal line and the storage capacitance section SLSCP of the scanning signal line, and the rest of the configuration is the same as that of the storage capacitance section SCP3.

[0020] As shown in FIG. 2, the length of scanning signal line SL1 is longer than the length of scanning signal line SL2, which is longer than the length of scanning signal line SL3, which is longer than the length of scanning signal line SL4. Therefore, as described above, the load capacitance of scanning signal line SL1 is larger than the load capacitance of scanning signal line SL2, which is larger than the load capacitance of scanning signal line SL3, and which is larger than the load capacitance of scanning signal line SL4. Therefore, in this embodiment, the capacitance of the auxiliary capacitance portion SLSCP of the scanning signal line SL1 provided in the auxiliary capacitance portion SCP1 is set to be smaller than the capacitance of the auxiliary capacitance portion SLSCP of the scanning signal line SL2 provided in the auxiliary capacitance portion SCP2, the capacitance of the auxiliary capacitance portion SLSCP of the scanning signal line SL2 provided in the auxiliary capacitance portion SCP2 is set to be smaller than the capacitance of the auxiliary capacitance portion SLSCP of the scanning signal line SL3 provided in the auxiliary capacitance portion SCP3, and the capacitance of the auxiliary capacitance portion SLSCP of the scanning signal line SL4 provided in the auxiliary capacitance portion SCP4. The capacitances of the auxiliary capacitance portions SLSCP of the scanning signal lines provided in the auxiliary capacitance portions (not shown) can also be adjusted in the same manner according to the lengths of the scanning signal lines. In this embodiment, the case where the capacitance of the storage capacitance portion SLSCP of each scanning signal line is adjusted in accordance with the length of each scanning signal line has been described as an example, but the present invention is not limited to this, and the capacitance of the storage capacitance portion SLSCP of the scanning signal line may be changed for each group of scanning signal lines consisting of a plurality of adjacent scanning signal lines whose difference in length is relatively small. Note that a method for adjusting the capacitance of the storage capacitance portion SLSCP of the scanning signal line will be described later.

[0021] As shown in FIG. 2 , the length of each of the data signal lines D4, D5, and D6 is longer than the length of each of the data signal lines D7, D8, and D9, which are longer than the length of each of the data signal lines D10, D11, and D12, which are longer than the length of each of the data signal lines D13, D14, and D15. Therefore, as described above, the load capacitance of each of the data signal lines D4, D5, and D6 is greater than the load capacitance of each of the data signal lines D7, D8, and D9, which is greater than the load capacitance of each of the data signal lines D10, D11, and D12, which is greater than the load capacitance of each of the data signal lines D13, D14, and D15. Therefore, in this embodiment, the capacitance of the auxiliary capacitance portions DLSCP of the data signal lines D13, D14, and D15 provided in the auxiliary capacitance portion SCP1 is made larger than the capacitance of the auxiliary capacitance portions DLSCP of the data signal lines D10, D11, and D12 provided in the auxiliary capacitance portion SCP2, the capacitance of the auxiliary capacitance portions DLSCP of the data signal lines D10, D11, and D12 provided in the auxiliary capacitance portion SCP2 is made larger than the capacitance of the auxiliary capacitance portions DLSCP of the data signal lines D7, D8, and D9 provided in the auxiliary capacitance portion SCP3, and the capacitance of the auxiliary capacitance portions DLSCP of the data signal lines D7, D8, and D9 provided in the auxiliary capacitance portion SCP3 is made larger than the capacitance of the auxiliary capacitance portions DLSCP of the data signal lines D4, D5, and D6 provided in the auxiliary capacitance portion SCP4. The capacitances of the auxiliary capacitance portions DLSCP of the data signal lines provided in the auxiliary capacitance portion (not shown) can also be adjusted in the same manner according to the lengths of the data signal lines.In this embodiment, the lengths of three adjacent data signal lines are the same, and therefore the capacitance of the auxiliary capacitance unit DLSCP of the data signal lines is adjusted for each of the three data signal lines. However, this is not limited to this. If the lengths of the data signal lines are different, the capacitance of the auxiliary capacitance unit DLSCP of each corresponding data signal line may be adjusted according to the length of each data signal line, or the capacitance of the auxiliary capacitance unit DLSCP of the data signal line may be changed for each group of data signal lines consisting of a plurality of adjacent data signal lines whose difference in length is relatively small. Note that a method for adjusting the capacitance of the auxiliary capacitance unit DLSCP of a data signal line will be described later.

[0022] As shown in FIG. 2, in the display panel 1 of this embodiment, a first frame region SCPR is formed surrounding a circular display area DA, in which a plurality of auxiliary capacitance sections provided in the display panel 1, including auxiliary capacitance sections SCP1, SCP2, SCP3, and SCP4, are provided, and a second frame region NDA is formed surrounding the first frame region SCPR, in which a plurality of scanning side driving circuits provided in the display panel 1, including scanning side driving circuits SC1, SC2, SC3, and SC4, and a data side driving circuit (not shown) are provided (see FIG. 12). In the display panel 1, the first frame region SCPR and the second frame region NDA are non-display regions, and therefore in this embodiment, in each of the multiple storage capacitance sections provided in the display panel 1, including the storage capacitance sections SCP1, SCP2, SCP3, and SCP4, the storage capacitance section SLSCP of the scanning signal line and the storage capacitance section DLSCP of the data signal line are arranged so as to overlap in a planar view, as described above, thereby narrowing the first frame region SCPR and preventing the non-display region from becoming larger.

[0023] 4, the scanning signal line SL3 and the extension SL3' of the scanning signal line SL3 may be provided in a layer above the first auxiliary capacitance electrode SCE1, or, although not shown, the first auxiliary capacitance electrode SCE1 may be provided in a layer above the scanning signal line SL3 and the extension SL3' of the scanning signal line SL3. As described above, by forming the scanning signal line SL3 and the extension SL3' of the scanning signal line SL3 and the first auxiliary capacitance electrode SCE1 in different layers, long wiring is not formed in one layer, and therefore damage due to ESD (Electro-Static Discharge) can be suppressed.

[0024] 2, the first auxiliary capacitance-forming counter electrodes SCE1′ provided in each of the auxiliary capacitance units SCP1, SCP2, SCP3, and SCP4 may be connected to each other. With this configuration, as shown in FIG. 4, a stable DC power supply, for example, a high-level power supply voltage ELVDD, may be supplied from the power supply circuit PSU to the first auxiliary capacitance-forming counter electrode SCE1′ provided in one of the auxiliary capacitance units.

[0025] 4 and 5, the second auxiliary capacitance electrode SCE2", the second auxiliary capacitance electrode SCE2', and the second auxiliary capacitance electrode SCE2, and the conductive member CNP1 and the conductive member CNP2 may be formed of the same material or different materials, and may be formed of, for example, a single layer film or a laminated film of a metal containing at least one of aluminum, tungsten, molybdenum, tantalum, chromium, titanium, and copper. In addition, the scanning signal line SL3, the extension SL3' of the scanning signal line SL3, the first auxiliary capacitance electrode SCE1, and the first auxiliary capacitance-forming counter electrode SCE1' may also be formed of, for example, a single layer film or a laminated film of a metal containing at least one of aluminum, tungsten, molybdenum, tantalum, chromium, titanium, and copper.

[0026] Furthermore, the first insulating layer INS1, the second insulating layer INS2, and the third insulating layer INS3 shown in Figures 4 and 5 can be composed of, for example, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a laminated film of these, formed by a CVD method.

[0027] According to the display panel 1 described above, it is possible to reduce the difference in load capacitance between a plurality of scanning signal lines and a plurality of data signal lines, while suppressing an increase in the non-display area and capacitive coupling between the scanning signal lines and the data signal lines in the portion that forms capacitance, thereby improving the display image quality.

[0028] As described above, the display panel 1 of the present embodiment has been described with reference to an example in which a corresponding scanning signal line auxiliary capacitance portion SLSCP is provided for each of a plurality of scanning signal lines and a corresponding data signal line auxiliary capacitance portion DLSCP is provided for each of a plurality of data signal lines, but the present invention is not limited to this. The auxiliary capacitance portion SLSCP may be provided only for the scanning signal line (second scanning signal line) that requires additional load capacitance among the longer scanning signal line (first scanning signal line) and the shorter scanning signal line (second scanning signal line), the auxiliary capacitance portion DLSCP may be provided only for the data signal line (second data signal line) that requires additional load capacitance among the longer data signal line (first data signal line) and the shorter data signal line (second data signal line), and the auxiliary capacitance portion SLSCP of the scanning signal line (second scanning signal line) and the auxiliary capacitance portion DLSCP of the data signal line (second data signal line) may have a common first auxiliary capacitance-forming counter electrode SCE1′. For example, the longer scanning signal line (first scanning signal line) is the scanning signal line SL1 or the scanning signal line SL2 shown in FIG. 2, the shorter scanning signal line (second scanning signal line) is the scanning signal line SL3 shown in FIG. 2, the longer data signal line (first data signal line) is any one of the data signal lines D4, D5, and D6 shown in FIG. 2, and the shorter data signal line (second data signal line) is the data signal line D7, D8, or D9 shown in FIG. In the case where the scanning signal line SL3 is either the scanning signal line D7, the data signal line D8 or the data signal line D9, even if only the auxiliary capacitance unit SCP3 is provided without providing the auxiliary capacitance unit SCP1 and the auxiliary capacitance unit SCP2, the difference between the load capacitance of the scanning signal line SL3 and the load capacitance of the scanning signal line SL1 or the scanning signal line SL2 can be reduced, and the difference between the load capacitance of any of the data signal line D7, the data signal line D8 or the data signal line D9 and the load capacitance of any of the data signal line D4, the data signal line D5 or the data signal line D6 can also be reduced.2 , the longer scanning signal line (first scanning signal line) is the scanning signal line SL1 shown in FIG. 2 , the shorter scanning signal line (second scanning signal line) is the scanning signal line SL2 shown in FIG. 2 , the shorter scanning signal line (third scanning signal line) is the scanning signal line SL3 shown in FIG. 2 , the longer data signal line (first data signal line) is any of the data signal lines D4, D5, and D6 shown in FIG. 2 , the shorter data signal line (second data signal line) is any of the data signal lines D7, D8, and D9 shown in FIG. 2 , and the shorter data signal line (third data signal line) is any of the data signal lines D8, D9, and D10 shown in FIG. 2, even if only the auxiliary capacitance section SCP1 is provided and the auxiliary capacitance section SCP2 and the auxiliary capacitance section SCP3 are not provided, the difference between the load capacitance of the scanning signal line SL2 and the load capacitance of the scanning signal line SL3 and the load capacitance of the scanning signal line SL1 can be reduced, and the difference between the load capacitance of any of the data signal lines D7, D8, and D9 and the load capacitance of any of the data signal lines D10, D11, and D12 and the load capacitance of any of the data signal lines D4, D5, and D6 can also be reduced. Furthermore, the first auxiliary capacitance-forming counter electrode SCE1′ provided in the auxiliary capacitance section SCP2 and the first auxiliary capacitance-forming counter electrode (second auxiliary capacitance-forming counter electrode) SCE1′ provided in the auxiliary capacitance section SCP3 may be connected. In these configurations, the display quality can be improved by reducing the difference in load capacitance between multiple scanning signal lines and multiple data signal lines while suppressing the enlargement of the non-display area and the capacitive coupling between the scanning signal lines and the data signal lines in the portion that forms the capacitance.

[0029] FIG. 6 is a diagram showing a schematic configuration of another storage capacitor SCP3' that can be provided in the display panel 1 of the first embodiment.

[0030] 6 , the scanning signal line SL3, the extension SL3′ of the scanning signal line SL3, and the first auxiliary capacitance electrode SCE1 are provided in the same layer, the scanning signal line SL3 and the first auxiliary capacitance electrode SCE1 are each electrically connected to a conductive member CNP1′ provided in a different layer from the scanning signal line SL3 and the first auxiliary capacitance electrode SCE1, and the extension SL3′ of the scanning signal line SL3 and the first auxiliary capacitance electrode SCE1 are each electrically connected to a conductive member CNP2′ provided in a different layer from the extension SL3′ of the scanning signal line SL3 and the first auxiliary capacitance electrode SCE1. With this configuration, the scanning signal line SL3, the extension SL3′ of the scanning signal line SL3, and the first auxiliary capacitance electrode SCE1, which are formed in the same layer, can be prevented from being formed as a single long wiring, thereby preventing damage due to ESD (Electro-Static Discharge).

[0031] A method for adjusting the capacitance of the storage capacitor SLSCP of the scanning signal line and a method for adjusting the capacitance of the storage capacitor DLSCP of the data signal line will be described below with reference to FIGS.

[0032] Fig. 7 is a diagram illustrating that the number of electrically connected pixel circuits GC varies depending on the positions of the scanning signal lines Sl and Ss and the data signal lines Dl and Ds in the display panel 1 of Embodiment 1. Fig. 8 is a diagram illustrating an example of an auxiliary capacitance section SCPa that is preferably provided in the Y portion of the display panel 1 of Embodiment 1 shown in Fig. 7. Fig. 9 is a diagram illustrating another example of an auxiliary capacitance section SCPb that is preferably provided in the Y portion of the display panel 1 of Embodiment 1 shown in Fig. 7. Fig. 10 is a diagram illustrating an example of an auxiliary capacitance section SCPc that is preferably provided in the Z portion of the display panel 1 of Embodiment 1 shown in Fig. 7. Fig. 11 is a diagram illustrating another example of an auxiliary capacitance section SCPd that is preferably provided in the Z portion of the display panel 1 of Embodiment 1 shown in Fig. 7.

[0033] 7, a relatively long scanning signal line Sl is provided near the center of the display area DA in the vertical direction (vertical direction in FIG. 7), and a relatively short scanning signal line Ss is provided near each of the upper and lower ends of the display area DA. On the other hand, a relatively long data signal line Dl is provided near the center of the display area DA in the horizontal direction (horizontal direction in FIG. 7), and a relatively short data signal line Ds is provided near each of the right and left ends of the display area DA.

[0034] The number of pixel circuits GC electrically connected to the scanning signal line Ss having a relatively short length is smaller than the number of pixel circuits GC electrically connected to the scanning signal line Sl having a relatively long length. Therefore, it is preferable that the overlapping area in plan view between the first auxiliary capacitance electrode SCE1 electrically connected to the scanning signal line Ss having a relatively short length and the first auxiliary capacitance-forming counter electrode SCE1′ provided in the auxiliary capacitance portion provided in the Y region shown in FIG. 7 is larger than the overlapping area in plan view between the first auxiliary capacitance electrode SCE1 electrically connected to the scanning signal line Sl having a relatively long length and the first auxiliary capacitance-forming counter electrode SCE1′ provided in the auxiliary capacitance portion provided in the Z region shown in FIG.

[0035] Furthermore, the number of pixel circuits GC electrically connected to the relatively short data signal lines Ds is smaller than the number of pixel circuits GC electrically connected to the relatively long data signal lines Dl. Therefore, it is preferable that the overlapping area in plan view between the first auxiliary capacitance electrodes SCE2, SCE2', SCE2" electrically connected to the relatively short data signal lines Ds provided in the auxiliary capacitance portion provided in the Z region shown in Fig. 7 and the first auxiliary capacitance-forming counter electrode SCE1' is larger than the overlapping area in plan view between the first auxiliary capacitance electrodes SCE2, SCE2', SCE2" electrically connected to the relatively long data signal lines Dl provided in the auxiliary capacitance portion provided in the Y region shown in Fig. 7 and the first auxiliary capacitance-forming counter electrode SCE1'.

[0036] Preferable examples of the storage capacitance section that can be provided in the Y region shown in Fig. 7 include the storage capacitance section SCPa shown in Fig. 8 or the storage capacitance section SCPb shown in Fig. 9. In the case of the storage capacitance section SCPa shown in Fig. 8, by making the length of the first storage capacitance electrode SCE1 longer in the first direction H1 than the lengths of the second storage capacitance electrodes SCE2, SCE2', and SCE2'' in the first direction H1, it is possible to reduce or equalize the difference in load capacitance between the scanning signal lines including the relatively short scanning signal line Ss and the relatively long scanning signal line Sl, and it is also possible to reduce or equalize the difference in load capacitance between the data signal lines including the relatively short data signal line Ds and the relatively long data signal line Dl. 9 , similarly to the storage capacitance section SCPa shown in FIG. 8 , the length in the first direction H1 of the first storage capacitance electrode SCE1 is made longer than the lengths in the first direction H1 of the second storage capacitance electrodes SCE2, SCE2′, and SCE2″, and the first storage capacitance-forming counter electrode SCE1′ is made larger than that in the storage capacitance section SCPa shown in FIG. 8 , thereby ensuring the capacitance formed by the extension portion SL′ of the scanning signal line and the first storage capacitance-forming counter electrode SCE1′. In this way, it is possible to reduce or equalize the difference in load capacitance between the scanning signal lines including the relatively short scanning signal line Ss and the relatively long scanning signal line Sl, and it is also possible to reduce or equalize the difference in load capacitance between the data signal lines including the relatively short data signal line Ds and the relatively long data signal line Dl.

[0037] Preferable examples of the storage capacitance section that can be provided in the Z region shown in Fig. 7 include the storage capacitance section SCPc shown in Fig. 10 or the storage capacitance section SCPd shown in Fig. 11. In the case of the storage capacitance section SCPc shown in Fig. 10, by making the length in the first direction H1 of each of the second storage capacitance electrode SCE2, the second storage capacitance electrode SCE2', and the second storage capacitance electrode SCE2" longer than the length in the first direction H1 of the first storage capacitance electrode SCE1, it is possible to reduce or equalize the difference in load capacitance between the scanning signal lines including the relatively short scanning signal line Ss and the relatively long scanning signal line Sl, and it is also possible to reduce or equalize the difference in load capacitance between the data signal lines including the relatively short data signal line Ds and the relatively long data signal line Dl. In the case of the storage capacitance section SCPd shown in FIG. 11 , the length in the first direction H1 of each of the second storage capacitance electrodes SCE2, SCE2′, and SCE2″ is made longer than the length in the first direction H1 of the first storage capacitance electrode SCE1 indicated by the dotted line in the figure, and the length in the second direction H2 of each of the second storage capacitance electrodes SCE2, SCE2′, and SCE2″ is made longer than the length in the second direction H2 of each of the second storage capacitance electrodes SCE2, SCE2′, and SCE2″ shown in FIG. 10 . This makes it possible to reduce or equalize the difference in load capacitance between the scanning signal lines including the relatively short scanning signal line Ss and the relatively long scanning signal line Sl, and to reduce or equalize the difference in load capacitance between the data signal lines including the relatively short data signal line Ds and the relatively long data signal line Dl.

[0038] Fig. 12 is a diagram showing a first frame region SCPR provided with a plurality of storage capacitors including storage capacitors SCP1, SCP2, SCP3, and SCP4 in the display panel 1 of Embodiment 1. Fig. 13 is a diagram showing first frame regions SCPR1 and SCPR2 provided with a plurality of storage capacitors including storage capacitors SCP1, SCP2, SCP3, and SCP4 in a display panel 1a that is a first modified example of the display panel 1 of Embodiment 1 shown in Fig. 12. Fig. 14 is a diagram showing first frame regions SCPR1 and SCPR2 provided with a plurality of storage capacitors including storage capacitors SCP1, SCP2, SCP3, and SCP4 in a display panel 1b that is a second modified example of the display panel 1 of Embodiment 1 shown in Fig. 12.

[0039] 12 , a first frame region SCPR is formed surrounding a display region DA, and the first frame region SCPR is provided with a plurality of storage capacitors including storage capacitors SCP1, SCP2, SCP3, and SCP4. A second frame region NDA is formed surrounding the first frame region SCPR, and the second frame region NDA is provided with a plurality of scanning drive circuits and data drive circuits. With this configuration, a plurality of storage capacitors including storage capacitors SCP1, SCP2, SCP3, and SCP4 can be provided at both ends of each of the scanning signal lines and the data signal lines, and two storage capacitors can be provided for each of the scanning signal lines or the data signal lines. 13 which is a first modified example of the display panel 1 or the display panel 1b which is a second modified example of the display panel 1 shown in FIG. 14, the first frame region SCPR1 and the first frame region SCPR2 provided with a plurality of storage capacitance portions including the storage capacitance portions SCP1, SCP2, SCP3, and SCP4 may be arranged so that the first frame region SCPR1 located in the upper region of the display region DA and the first frame region SCPR2 located in the lower region of the display region DA are positioned on a diagonal line. With this configuration, a plurality of storage capacitance portions including the storage capacitance portions SCP1, SCP2, SCP3, and SCP4 can be provided only at one end of each of the scanning signal lines and the data signal lines, and one storage capacitance portion can be provided for each of the scanning signal lines or the data signal lines.

[0040] Second Embodiment FIG. 15 is a plan view showing a schematic configuration of a display panel 1c according to a second embodiment.

[0041] As shown in FIG. 15 , the first auxiliary capacitance-forming counter electrode SCE1″ included in each of the plurality of auxiliary capacitance sections including the auxiliary capacitance sections SCP1″, SCP2″, SCP3″, and SCP4″ provided in the display panel 1c may be formed in an island shape. That is, the first auxiliary capacitance-forming counter electrode SCE1″ included in each of the plurality of auxiliary capacitance sections including the auxiliary capacitance sections SCP1″, SCP2″, SCP3″, and SCP4″ provided in the display panel 1c may be electrically separated from each other. With this configuration, by connecting each of the plurality of island-shaped first auxiliary capacitance-forming counter electrodes SCE1″ to the node of an adjacent pixel, the potential of each of the plurality of first auxiliary capacitance-forming counter electrodes SCE1″ can be individually controlled. Furthermore, the potential of some of the island-shaped first auxiliary capacitance-forming counter electrodes SCE1″ can be controlled to be different from the potential of the remaining electrodes.

[0042] [Embodiment 3] Fig. 16 is a plan view showing a schematic configuration of a display panel 1d of embodiment 3. Fig. 17 is a cross-sectional view taken along line CC' of the display panel 1d of embodiment 3 shown in Fig. 16, showing a schematic configuration of a storage capacitance unit SCP3.

[0043] 16 includes, in the second frame area NDA, a plurality of emission signal line drive circuits including emission signal line drive circuits EC1, EC2, EC3, and EC4, and a plurality of emission signal lines including emission signal lines EML1, EML2, EML3, and EML4 electrically connected to the plurality of emission signal line drive circuits, respectively. That is, the display panel 1d includes, for example, an emission signal line EML2 provided between a longer scanning signal line (first scanning signal line) SL1 and a shorter scanning signal line (second scanning signal line) SL2, and spaced apart from each of the scanning signal line SL1 and the scanning signal line SL2.

[0044] 16 , the plurality of emission signal lines, including the emission signal lines EML1, EML2, EML3, and EML4, also have different lengths, similar to the scanning signal lines SL1, SL2, SL3, and SL4 described above. Since these lines are electrically connected to a plurality of pixel circuits, including emission signal lines different from the pixel circuit GC shown in FIG. 3 , differences in their load capacitances occur. Therefore, similar to the scanning signal lines SL1, SL2, SL3, and SL4 described above, each of the plurality of emission signal lines, including the emission signal lines EML1, EML2, EML3, and EML4, may be provided with an auxiliary capacitance section to reduce the difference in load capacitance. However, because the influence of the difference in load capacitance is often not a problem for signals supplied to the emission signal lines, in this embodiment, an auxiliary capacitance section to reduce the difference in load capacitance is not provided for each of the plurality of emission signal lines, including the emission signal lines EML1, EML2, EML3, and EML4.

[0045] 17, in an auxiliary capacitance section SCP3 which is an example of a plurality of auxiliary capacitance sections provided in the display panel 1d shown in FIG. 16, the emission signal line EML3 includes a first portion EML3a, a second portion EML3b, and a third portion EML3c. The first portion EML3a is electrically connected to the emission signal line drive circuit EC3, the first portion EML3a and the third portion EML3c are electrically connected via a conductive member CNP2", the second portion EML3b and the third portion EML3c are electrically connected via a conductive member CNP1", and the second portion EML3b extends in the direction of the display area DA. The line width of the third portion EML3c is formed to be approximately the same as the line widths of the first portion EML3a and the second portion EML3b. A capacitance is formed by the first auxiliary capacitance forming counter electrode SCE1′, the first insulating layer INS1, and the third portion EML3c, but this capacitance has the same magnitude for each of the multiple emission signal lines including the emission signal lines EML1, EML2, EML3, and EML4, and therefore does not contribute to reducing the difference in load capacitance.

[0046] [Additional Notes] The present disclosure is not limited to the above-described embodiments, and various modifications are possible within the scope of the claims. Embodiments obtained by appropriately combining the technical means disclosed in different embodiments are also included in the technical scope of the present disclosure. Furthermore, new technical features can be formed by combining the technical means disclosed in each embodiment.

[0047] The present disclosure can be used in a display panel.

[0048] 1, 1a to 1d display panel SL1 to SL4, Sl, Ss, SL scanning signal lines D1 to D15, Dl, Ds data signal lines SL1' to SL4', SL' extensions of scanning signal lines EML1 to EML4, EML3a to EML3c emission signal lines SCP1 to SCP4, SCP3', SCPa to SCPd storage capacitance section SCE1 first storage capacitance electrode SCE1', SCE1'' counter electrode for forming first storage capacitance SLSCP storage capacitance section of scanning signal line SCE2, SCE2', SCE2'' second storage capacitance electrode DLSCP storage capacitance section of data signal line CNP1, CNP2, CNP1', CNP2' conductive member CNP1'', CNP2'' conductive member PIX pixel GC pixel circuit E1 pixel electrode E2 Counter electrode SC1 to SC4 Scanning signal line drive circuit EC1 to EC4 Emission signal line drive circuit DA Display area SCPR, SCPR1, SCPR2 First frame area NDA Second frame area PSU Power supply circuit INS1 First insulating layer INS2 Second insulating layer INS3 Third insulating layer

Claims

a first scanning signal line electrically connected to M (M is a natural number greater than or equal to 2) pixel circuits of the plurality of pixel circuits that are provided in a first region; a second scanning signal line electrically connected to less than M pixel circuits of the plurality of pixel circuits that are provided in a second region; a first data signal line electrically connected to N (N is a natural number greater than or equal to 2) pixel circuits of the plurality of pixel circuits that are provided in a third region; a second data signal line electrically connected to less than N pixel circuits of the plurality of pixel circuits that are provided in a fourth region; an auxiliary capacitance section of the second scanning signal line including a first auxiliary capacitance electrode electrically connected to the second scanning signal line and a first auxiliary capacitance-forming opposing electrode facing the first auxiliary capacitance electrode; and an auxiliary capacitance section of the second data signal line including a second auxiliary capacitance electrode electrically connected to the second data signal line and the first auxiliary capacitance-forming opposing electrode facing the second auxiliary capacitance electrode.

2. The display panel according to claim 1, wherein one of the second scanning signal line and the first auxiliary capacitance electrode is provided as a layer above the other of the second scanning signal line and the first auxiliary capacitance electrode.

3. The display panel according to claim 1, wherein the second scanning signal line and the first auxiliary capacitance electrode are provided in the same layer, and the second scanning signal line and the first auxiliary capacitance electrode are each electrically connected to a conductive member provided in a layer different from that of the second scanning signal line and the first auxiliary capacitance electrode.

4. The display panel according to any one of claims 1 to 3, comprising: a third scanning signal line electrically connected to less than M pixel circuits provided in a fifth region among the plurality of pixel circuits; a third data signal line electrically connected to less than N pixel circuits provided in a sixth region among the plurality of pixel circuits; an auxiliary capacitance section of the third scanning signal line including a third auxiliary capacitance electrode electrically connected to the third scanning signal line and a second auxiliary capacitance-forming opposing electrode facing the third auxiliary capacitance electrode; and an auxiliary capacitance section of the third data signal line including a fourth auxiliary capacitance electrode electrically connected to the third data signal line and the second auxiliary capacitance-forming opposing electrode facing the fourth auxiliary capacitance electrode.

5. The display panel according to claim 4, wherein the first auxiliary capacitance forming opposing electrode and the second auxiliary capacitance forming opposing electrode are connected to each other.

6. The display panel according to claim 4, wherein the first auxiliary capacitance forming opposing electrode and the second auxiliary capacitance forming opposing electrode are each formed in an island shape.

7. A display panel according to any one of claims 4 to 6, wherein the number of pixel circuits electrically connected to the third scanning signal line is smaller than the number of pixel circuits electrically connected to the second scanning signal line, and the overlapping area between the third auxiliary capacitance electrode and the second auxiliary capacitance forming opposing electrode in a planar view is larger than the overlapping area between the first auxiliary capacitance electrode and the first auxiliary capacitance forming opposing electrode in a planar view.

8. A display panel according to any one of claims 4 to 7, wherein the number of pixel circuits electrically connected to the third data signal line is smaller than the number of pixel circuits electrically connected to the second data signal line, and the overlapping area between the fourth auxiliary capacitance electrode and the second auxiliary capacitance forming opposing electrode in a planar view is larger than the overlapping area between the second auxiliary capacitance electrode and the first auxiliary capacitance forming opposing electrode in a planar view.

9. A display panel according to any one of claims 1 to 8, further comprising an emission signal line provided between the first scanning signal line and the second scanning signal line and spaced apart from the first scanning signal line and the second scanning signal line.

10. A display panel as claimed in any one of claims 1 to 9, wherein each of the plurality of pixel circuits includes a pixel electrode, and in a display area including the plurality of pixel electrodes, the number of pixel electrodes in a portion of the area along the vertical direction is different from the number of pixel electrodes in another portion of the area along the vertical direction, and the number of pixel electrodes in a portion of the area along the horizontal direction is different from the number of pixel electrodes in another portion of the area along the horizontal direction.

Images