Semiconductor package and method for manufacturing same

Abstract

This semiconductor package comprises: a package substrate having a main surface that includes a first electrode; a semiconductor chip component having an outer peripheral surface and a circuit surface that includes a second electrode; an underfill; a sealing layer; and an intermediate resin part. The underfill includes a portion that is interposed between the package substrate and the semiconductor chip component. The sealing layer includes a portion that surrounds the semiconductor chip component on the package substrate. The intermediate resin part is provided so as to be interposed between the underfill and the sealing layer and to be in contact with the outer peripheral surface of the semiconductor chip component.

Description

Semiconductor package and manufacturing method thereof

[0001] The present disclosure relates to a semiconductor package and a method for manufacturing the same.

[0002] In recent years, the rapid advancement in the functionality of electronic devices, such as AI and HPC, has led to a rapid increase in the size and density of semiconductor packages. Regarding semiconductor package structure, not only has the density of surface mounting increased, but the packaging process has also become more complex and diverse, driven by inorganic (silicon) interposer or organic interposer (Bridge die / RDL) technology, as well as 2.xD packaging using these and 3D packaging technology (HBM / Chiplet) that applies TSV. For example, Resonac Inc., based at its "Packaging Solutions Center," is developing next-generation semiconductor packaging process technology that combines packaging processes and materials from the perspective of its customers (semiconductor manufacturers).

[0003] In a semiconductor package in which a semiconductor chip component is mounted on a package substrate, an underfill is sometimes provided to fill the gap between the semiconductor chip component and the package substrate (see Patent Document 1).

[0004] Japanese Patent Application Laid-Open No. 2017-005175

[0005] In order to sufficiently fill the narrow gaps between electrodes such as bumps between a semiconductor chip component and a package substrate with underfill, it is desirable for the underfill material to have high fluidity. However, if the underfill formed from an underfill material with high fluidity protrudes from between the semiconductor chip component and the package substrate to form a fillet, cracks may easily occur around the fillet.

[0006] The present disclosure relates to a semiconductor package having an underfill interposed between a semiconductor chip component and a package substrate, and relates to ensuring sufficient filling by the underfill and suppressing the occurrence of cracks.

[0007] The present disclosure includes the following: [1] A semiconductor package comprising: a package substrate having a main surface including a plurality of first electrodes; a semiconductor chip component having a circuit surface including a plurality of second electrodes and an outer peripheral surface surrounding the circuit surface; an underfill; a sealing layer; and an intermediate resin part, wherein the semiconductor chip component is mounted on the package substrate with the circuit surface facing the main surface of the package substrate and the first electrodes and the second electrodes are electrically connected; the underfill has a portion interposed between the package substrate and the semiconductor chip component; the sealing layer has a portion surrounding the semiconductor chip component on the package substrate; and the intermediate resin part is interposed between the underfill and the sealing layer and is provided so as to contact the outer peripheral surface of the semiconductor chip component. [2] The semiconductor package according to [1], wherein the intermediate resin part is provided so as to contact the outer peripheral surface of the semiconductor chip component and the main surface of the package substrate. [3] The semiconductor package according to [1] or [2], wherein, when the maximum height of the semiconductor chip component from the main surface of the package substrate is H0 and the maximum height of the intermediate resin portion from the main surface of the package substrate is H2, H2 / H0 is 0.6 or more and less than 1.0. [4] The semiconductor package according to any of [1] to [3], wherein the underfill does not include a fillet portion protruding from between the package substrate and the semiconductor chip component. [5] The semiconductor package according to any of [1] to [4], wherein the underfill further includes a fillet portion protruding from between the package substrate and the semiconductor chip component, and the intermediate resin portion is interposed between the fillet portion and the sealing layer. [6] The linear expansion coefficient of the underfill is α １ The linear expansion coefficient of the intermediate resin part is α ２ and α １ and α ２ The relation is: α １ >α ２ [7] The semiconductor package according to any one of [1] to [5], wherein the linear expansion coefficient of the sealing layer is α ３ and α １ , α ２and α ３ The relation is: α １ >α ２ >α ３ [8] The semiconductor package according to [6], wherein the underfill may contain an inorganic filler, the intermediate resin portion contains an inorganic filler, and a content of the inorganic filler in the underfill is X based on the mass of the underfill. １ The content of the inorganic filler in the intermediate resin portion is X% by mass based on the mass of the intermediate resin portion. ２ is mass %, and X １ and X ２ The relation is: X １ <X ２ [9] The semiconductor package according to any one of [1] to [7], wherein the sealing layer contains an inorganic filler, and the content of the inorganic filler in the sealing layer is X based on the mass of the sealing layer. ３ is mass %, and X １ , X ２ and X ３ The relation is: X １ <X ２ <X ３

[10] The semiconductor package according to any one of [1] to [9], wherein the underfill, the intermediate resin part, and the sealing layer contain an inorganic filler, and the average particle size of the inorganic filler contained in the underfill is smaller than the average particle size of the inorganic filler contained in the intermediate resin part and the average particle size of the inorganic filler contained in the sealing layer.

[11] A method for manufacturing a semiconductor package, comprising: preparing a connection body having a package substrate having a main surface including a plurality of first electrodes, and a semiconductor chip component having a circuit surface including a plurality of second electrodes and an outer peripheral surface surrounding the circuit surface, wherein the semiconductor chip component is mounted on the package substrate with the circuit surface facing the main surface of the package substrate, and the first electrodes and the second electrodes are electrically connected; filling a liquid underfill material between the package substrate and the semiconductor chip component, and subsequently thermally curing the underfill material to form an underfill including a portion interposed between the package substrate and the semiconductor chip component; providing an intermediate resin portion in contact with the outer peripheral surface of the semiconductor chip component; and providing a sealing layer on the package substrate including a portion surrounding the semiconductor chip component, such that the intermediate resin portion is interposed between the underfill and the sealing layer.

[0008] In a semiconductor package having an underfill interposed between a semiconductor chip component and a package substrate, sufficient filling by the underfill can be ensured, and the occurrence of cracks can be suppressed. Warping of the semiconductor package can also be suppressed.

[0009] Fig. 1 is a plan view showing an example of a semiconductor package; Fig. 2 is a partial cross-sectional view showing an example of a semiconductor package; Fig. 3 is a partial cross-sectional view showing an example of a semiconductor package; Fig. 4 is a partial cross-sectional view showing an example of a semiconductor package; Fig. 5 is a process diagram showing an example of a method for manufacturing a semiconductor package; Fig. 6 is a process diagram showing an example of a method for manufacturing a semiconductor package.

[0010] The present invention is not limited to the following examples.

[0011] FIG. 1 is a plan view showing an example of a semiconductor package. FIG. 2 is a partial cross-sectional view taken along dashed line II in FIG. 1 . The semiconductor package 101 shown in FIGS. 1 and 2 includes a package substrate 1 having a rectangular main surface S1A including a plurality of first electrodes 21, a semiconductor chip component 3 having a circuit surface S3A including a plurality of second electrodes 22 and an outer peripheral surface S3C surrounding the circuit surface S3A, an underfill 5, a sealing layer 7, and an intermediate resin portion 10. The semiconductor chip component 3 is mounted on the package substrate 1 with the circuit surface S3A facing the main surface S1A of the package substrate 1. The semiconductor package 101 also includes a bump portion 25 interposed between the first electrode 21 and the second electrode 22 and electrically connecting them, thereby electrically connecting the first electrode 21 and the second electrode 22. The bump portion 25 can be, for example, a conductive portion derived from a solder bump provided on the first electrode 21, a solder bump provided on the second electrode 22, or both.

[0012] 1, four semiconductor chip components 3 and a semiconductor chip component 2 different from the semiconductor chip component 3 are mounted on a package substrate 1. The type, number, and arrangement of the semiconductor chip components in one semiconductor package are not limited to the example of FIG. 1 and can be changed as desired.

[0013] The package substrate 1 is a plate-shaped member (wiring board) having two rectangular main surfaces S1A and S1B, and includes wiring connected to the semiconductor chip components 2 and 3. One main surface S1A of the package substrate 1 includes the surface of the main body of the package substrate 1 and the surface of the first electrode 21. The package substrate 1 may be, for example, a wiring board having a plate-shaped core material including a fiber base material and an insulating resin, and build-up layers including wiring provided on both sides of the core material. The first electrode 21 may be a connection pad connected to the wiring in the build-up layer. The package substrate 1 may have a solder resist provided around the first electrode 21. A conductive through-hole may be provided through the core material. An electrode (connection pad) for connection to a motherboard or the like may be provided in the main surface S1B on the back side of the main surface S1A of the package substrate 1.

[0014] The thickness of the package substrate 1 may be, for example, 0.3 mm or more and 20 mm or less. The lengths of at least two of the four sides constituting the rectangular main surfaces S1A and S1B of the package substrate 1 may be, for example, 30 mm or more and 100 mm or less.

[0015] The semiconductor chip component 3 includes one or more semiconductor chips. The semiconductor chip component 3 may include multiple semiconductor chips that are stacked with adhesive layers interposed therebetween. The circuit surface S3A is the main surface of the semiconductor chip component 3, and includes the surface of the main body of the semiconductor chip component 3 and the surface of the second electrode 22. The semiconductor chip component 3 may further include a sealing layer that seals the semiconductor chips, an interposer on which the multiple semiconductor chips are mounted, and the like.

[0016] The thickness of the semiconductor chip component 3 may be, for example, 0.2 mm or more and 1.5 mm or less. The width of one semiconductor chip component 3 may be, for example, 5 mm or more and 50 mm or less at maximum.

[0017] The underfill 5 has a portion interposed between the package substrate 1 and the semiconductor chip component 3. The underfill 5 fills the spaces between the plurality of first electrodes 21 and second electrodes 22 between the package substrate 1 and the semiconductor chip component 3, thereby sealing the connection portion including these electrodes. The underfill 5 can be a cured product of a thermosetting underfill material. The thickness of the underfill 5 may be, for example, 5 μm or more and 400 μm or less.

[0018] 2 , the underfill 5 does not protrude from between the package substrate 1 and the semiconductor chip component 3 when viewed from the thickness direction D of the package substrate 1. In other words, the underfill 5 does not have a fillet portion that protrudes from between the package substrate 1 and the semiconductor chip component 3.

[0019] The encapsulating layer 7 has a portion that surrounds the semiconductor chip component 3 on the main surface S1A of the package substrate 1, thereby encapsulating the semiconductor chip component 3. The encapsulating layer 7 may be in contact with the outer peripheral surface S3C of the semiconductor chip component 3. The thickness of the encapsulating layer 7 may be substantially the same as the height H0 of the semiconductor chip component 3 from the main surface S1A of the package substrate 1. In other words, the encapsulating layer 7 and the back surface S3B of the semiconductor chip component (the surface behind the circuit surface S3A) may form a flat surface. The encapsulating layer 7 may be a cured product of a typical thermosetting encapsulant.

[0020] The intermediate resin portion 10 is interposed between the underfill 5 and the encapsulating layer 7 and is provided so as to contact the outer peripheral surface S3C of the semiconductor chip component 3. The intermediate resin portion 10 is in contact with the underfill 5 and the encapsulating layer 7. When the underfill 5 forms a fillet portion and the fillet portion is in contact with the encapsulating layer 7, cracks may easily occur near the fillet portion and the outer peripheral surface S3C of the semiconductor chip component 3. One cause of crack occurrence is thought to be the significant difference in properties such as the linear expansion coefficient and elastic modulus between the fillet portion formed by the underfill 5 and the encapsulating layer 7. By providing the intermediate resin portion 10 in contact with the outer peripheral surface S3C of the semiconductor chip component 3, crack occurrence can be suppressed, particularly near the outer peripheral surface S3C of the semiconductor chip component 3, compared to when the fillet portion formed by the underfill 5 is in direct contact with the encapsulating layer 7. The intermediate resin portion 10 can be formed from a material selected to suppress crack occurrence, without the need to consider fillability. The intermediate resin portion 10, which does not require filling, can easily have high rigidity. The intermediate resin portion 10 having high rigidity can contribute to suppressing warpage of the semiconductor package.

[0021] 2, the intermediate resin part 10 is provided so as to be in contact with the main surface S1A of the package substrate 1. In other words, the intermediate resin part 10 is continuously interposed between the underfill 5 and the sealing layer 7 from the main surface S1A of the package substrate 1 to the outer peripheral surface S3C of the semiconductor chip component 3. If the intermediate resin part 10 is also in contact with the main surface S1A of the package substrate 1, the occurrence of cracks in the vicinity of the main surface S1A can also be suppressed.

[0022] Cracks can be more effectively suppressed when the proportion of the portion of the outer peripheral surface S3C of the semiconductor chip component 3 that is in contact with the intermediate resin part 10 is large. Therefore, when the maximum height of the semiconductor chip component 3 from the main surface S1A of the package substrate 1 is H0 and the maximum height of the intermediate resin part 10 from the main surface S1A of the package substrate 1 is H2, H2 / H0 may be 0.6 or more and less than 1.0. H2 / H0 may also be 0.7 or more, or 0.8 or more.

[0023] FIG. 3 is a partial cross-sectional view showing another example of a semiconductor package. The semiconductor package 102 shown in FIG. 3 differs from the semiconductor package 101 shown in FIG. 2 in that the underfill 5 has a fillet portion 5a that protrudes from between the package substrate 1 and the semiconductor chip component 3. Even when the underfill 5 forms the fillet portion 5a, the intermediate resin portion 10 interposed between the fillet portion 5a and the sealing layer 7 can suppress the occurrence of cracks caused by the fillet portion 5a. The fillet portion 5a may be in contact with the outer peripheral surface S3C of the semiconductor chip component 3. When the maximum height of the fillet portion 5a from the main surface S1A of the package substrate 1 is H1, H1 / H0 may be less than 0.6.

[0024] Fig. 4 is a partial cross-sectional view showing another example of a semiconductor package. The semiconductor package 103 shown in Fig. 4 differs from the semiconductor package 102 shown in Fig. 3 in that the intermediate resin part 10 is not in contact with the main surface S1A of the package substrate 1. In this case as well, the occurrence of cracks near the outer peripheral surface S3C of the semiconductor chip component 3 can be suppressed.

[0025] Fig. 5 is also a partial cross-sectional view showing another example of a semiconductor package. The semiconductor package 104 shown in Fig. 5 differs from the semiconductor package 101 of Fig. 1 in that the underfill 5 is provided inside the outer peripheral surface S3C of the semiconductor chip component 3 when viewed from the thickness direction D of the package substrate 1. The intermediate resin portion 10 contacts the underfill 5 between the package substrate 1 and the semiconductor chip component 3, inside the outer peripheral surface S3C. In this case, too, the occurrence of cracks near the outer peripheral surface S3C and near the main surface S1A can be suppressed.

[0026] 6 and 7 are process diagrams showing an example of a method for manufacturing the semiconductor package 101 of Fig. 1. The method shown in Fig. 6 and 7 includes preparing a connector 50 (Fig. 6(a)) having a package substrate 1 with a main surface S1A including a plurality of first electrodes 21 and a semiconductor chip component 3 with a circuit surface S3A including a plurality of second electrodes 22 and an outer peripheral surface S3C surrounding the circuit surface S3A, filling a liquid underfill material between the package substrate 1 and the semiconductor chip component 3 and subsequently thermally curing the underfill material to form an underfill 5 (Fig. 6(b)) having a portion interposed between the package substrate 1 and the semiconductor chip component 3, providing an intermediate resin part 10 (Fig. 7(a)) in contact with the outer peripheral surface S3C of the semiconductor chip component 3, and providing a sealing layer 7 (Fig. 7(b)) including a portion surrounding the semiconductor chip component 3 on the package substrate 1 so that the intermediate resin part 10 is interposed between the underfill 5 and the sealing layer 7. After forming the sealing layer 7 that completely buries the semiconductor chip component 3, a portion of the sealing layer 7 may be removed from the side opposite the package substrate 1 to form a flat surface including the semiconductor chip component 3 and the sealing layer 7.

[0027] The connector 50, in which the first electrode 21 and the second electrode 22 are electrically connected, can be prepared by a conventional method such as alignment and reflow. To form the underfill 5, a liquid thermosetting underfill material is injected between the package substrate 1 and the semiconductor chip component 3. The main surface S1A of the package substrate 1 may be pre-treated with plasma. Heated underfill material may also be injected. An underfill 5 having no fillet or a small fillet can be formed, for example, by weakening the intensity of plasma treatment of the main surface S1A, lowering the temperature of the injected underfill material, or a combination of these. The fillet formed by the underfill 5 may also be removed.

[0028] The underfill material can be, for example, a thermosetting resin composition containing a thermosetting component. The underfill material and the underfill 5 formed therefrom may contain an inorganic filler. The underfill material and the underfill 5 formed therefrom may be substantially free of inorganic filler. If the content of inorganic filler is low, the underfill material has high filling properties, which can suppress the occurrence of voids, for example. From these viewpoints, the content X of inorganic filler in the underfill material and the underfill 5 １ However, it may be 0 mass % or more and 63 mass % or less based on the mass of the underfill material or underfill 5. １ may be 60% by mass or less, or 55% by mass or less.

[0029] When the underfill material and the underfill 5 contain an inorganic filler, if the particle size of the inorganic filler is small, it is easier to fill the spaces between multiple electrodes provided at a narrow pitch with the underfill 5. From this perspective, the average particle size of the inorganic filler contained in the underfill material or the underfill 5 may be 0 μm or more and 20 μm or less, 5 μm or less, or 1 μm or less.

[0030] In the present disclosure, the average particle size of the inorganic filler can be a cumulative 50% diameter on a volume basis, determined from a particle size distribution measured by a laser diffraction method.

[0031] The thermosetting component contained in the underfill material may include, for example, an epoxy resin and its curing agent.

[0032] The underfill material filled between the package substrate 1 and the semiconductor chip component 3 is thermally cured to form an underfill 5, which is a cured product of the underfill material.

[0033] The intermediate resin part 10 can be formed by a method including supplying a resin material selected in consideration of, for example, the linear expansion coefficient and mechanical properties onto the package substrate 1. The resin material for forming the intermediate resin part 10 may be thermosetting or photosetting.

[0034] The resin material and the intermediate resin part 10 formed therefrom may contain inorganic filler. A resin material and intermediate resin part 10 containing a large amount of inorganic filler tend to have a lower coefficient of linear expansion and a larger modulus of elasticity than the underfill 5. For example, when the content X of the inorganic filler in the resin material and the intermediate resin part 10 is ２ However, it may be 50% by mass or more and 80% by mass or less based on the mass of the resin material or the intermediate resin part 10. ２ However, the average particle size of the inorganic filler contained in the underfill material or underfill 5 may be smaller than the average particle size of the inorganic filler contained in the resin material or intermediate resin portion 10.

[0035] The thermosetting resin material for forming the intermediate resin portion 10 may include a thermosetting component. The thermosetting component may include, for example, an epoxy resin and a curing agent thereof.

[0036] The encapsulating layer 7 can be formed by a conventional molding method such as compression molding using a thermosetting encapsulating material used to encapsulate electronic components such as semiconductor components. The encapsulating material may be, for example, a thermosetting resin composition containing a thermosetting component and an inorganic filler. The thermosetting component may include, for example, an epoxy resin and its curing agent. The content X of the inorganic filler in the encapsulating material and the encapsulating layer 7 is ３ However, it may be 63 mass % or more and 90 mass % or less based on the mass of the sealing material or sealing layer 7. ３ However, the average particle size of the inorganic filler contained in the underfill material or underfill 5 may be smaller than the average particle size of the inorganic filler contained in the sealing material or sealing layer 7.

[0037] The inorganic filler contained in the underfill 5, the intermediate resin part 10, the sealing layer 7, or the materials for forming these may be, for example, silica particles.

[0038] The underfill material, the resin material for forming the intermediate resin portion, and the sealing material may further contain other components as needed, such as a surfactant, a coupling agent, a curing accelerator, and an ion trapping agent.

[0039] By appropriately adjusting the thermal and mechanical properties of the underfill 5, the intermediate resin portion 10, and the sealing layer 7, it is possible to suppress cracking and warpage while maintaining good filling properties of the underfill 5. For example, the linear expansion coefficient α of the underfill 5 １ , and the linear expansion coefficient α of the intermediate resin portion 10 ２ But the relation: α １ >α ２ In this case, the linear expansion coefficient of the sealing layer may be α ３ and α １ , α ２ and α ３ The relation is: α １ >α ２ >α ３ The linear expansion coefficient α of the intermediate resin portion 10 may be satisfied. ２is the linear expansion coefficient α of the underfill 5 １ , the linear expansion coefficient α of the intermediate resin portion 10 can contribute to achieving both good filling properties of the underfill 5 and crack suppression. ２ is the linear expansion coefficient α of the underfill 5 １ and the linear expansion coefficient of the sealing layer 7 is α ３ and α １ and α ３ Cracks caused by a large difference between the thickness and the thickness can be particularly effectively suppressed.

[0040] In this specification, the linear expansion coefficient can be the slope of the tangent to the thermal expansion curve showing the relationship between the dimensions of a test piece and the temperature measured by thermomechanical analysis in a temperature range lower than the glass transition region, or the slope of the line connecting two points on the curve in a temperature range lower than the glass transition temperature. The glass transition region is usually observed as a portion where the slope of the thermal expansion curve changes significantly.

[0041] The magnitude relationship of the linear expansion coefficient can be adjusted by, for example, the content of the inorganic filler and the chemical structure of the thermosetting component. For example, １ Mass %, content X of inorganic filler in resin material or intermediate resin portion 10 ２ mass %, and the content X of the inorganic filler in the sealing material or sealing layer 7 ３ The mass % is expressed by the following formula: X １ <X ２ <X ３ may be satisfied.

[0042] 1...package substrate, 2, 3...semiconductor chip component, S3C...outer peripheral surface, 5...underfill, 5a...fillet portion, 7...sealing layer, 10...intermediate resin portion, 21...first electrode, 22...second electrode, 50...connector, 101, 102, 103, 104...semiconductor package, S1A, S1B...main surface of package substrate, S3A...circuit surface of semiconductor chip component, S3C...outer peripheral surface of semiconductor chip component.

Claims

1. A semiconductor package comprising: a package substrate having a main surface including a plurality of first electrodes; a semiconductor chip component having a circuit surface including a plurality of second electrodes and an outer peripheral surface surrounding the circuit surface; an underfill; a sealing layer; and an intermediate resin portion, wherein the semiconductor chip component is mounted on the package substrate with the circuit surface facing the main surface of the package substrate, and the first electrodes and the second electrodes are electrically connected; the underfill has a portion interposed between the package substrate and the semiconductor chip component; the sealing layer has a portion that surrounds the semiconductor chip component on the package substrate; and the intermediate resin portion is interposed between the underfill and the sealing layer and is provided so as to contact the outer peripheral surface of the semiconductor chip component.

2. The semiconductor package according to claim 1, wherein the intermediate resin portion is provided so as to contact the outer peripheral surface of the semiconductor chip component and the main surface of the package substrate.

3. The semiconductor package of claim 1, wherein when the maximum height of the semiconductor chip component from the main surface of the package substrate is H0 and the maximum height of the intermediate resin portion from the main surface of the package substrate is H2, H2 / H0 is 0.6 or more and less than 1.

0.

4. The semiconductor package according to claim 1, wherein the underfill does not have a fillet portion that protrudes from between the package substrate and the semiconductor chip component.

5. The semiconductor package according to claim 1, wherein the underfill further has a fillet portion that protrudes from between the package substrate and the semiconductor chip component, and the intermediate resin portion is interposed between the fillet portion and the sealing layer.

6. The coefficient of linear expansion of the underfill is α １ The linear expansion coefficient of the intermediate resin part is α ２ and α １ and α ２ The relation is: α １ >α ２ The semiconductor package according to claim 1 , wherein 7. The linear expansion coefficient of the sealing layer is α ３ and α １ , α ２ and α ３ The relation is: α １ >α ２ >α ３ The semiconductor package according to claim 6 , which satisfies the above.

8. The underfill may contain an inorganic filler, the intermediate resin portion may contain an inorganic filler, and the content of the inorganic filler in the underfill may be X based on the mass of the underfill. １ The content of the inorganic filler in the intermediate resin portion is X% by mass based on the mass of the intermediate resin portion. ２ is mass %, and X １ and X ２ The relation is: X １ <X ２ The semiconductor package according to claim 1 , wherein 9. The sealing layer contains an inorganic filler, and the content of the inorganic filler in the sealing layer is X based on the mass of the sealing layer. ３ is mass %, and X １ , X ２ and X ３ The relation is: X １ <X ２ <X ３ The semiconductor package according to claim 8 , which satisfies the above.

10. The semiconductor package of claim 1, wherein the underfill, the intermediate resin portion, and the sealing layer contain an inorganic filler, and the average particle size of the inorganic filler contained in the underfill is smaller than the average particle size of the inorganic filler contained in the intermediate resin portion and the average particle size of the inorganic filler contained in the sealing layer.

11. A method for manufacturing a semiconductor package, comprising: preparing a connection body having a package substrate having a main surface including a plurality of first electrodes, and a semiconductor chip component having a circuit surface including a plurality of second electrodes and an outer peripheral surface surrounding the circuit surface, wherein the semiconductor chip component is mounted on the package substrate with the circuit surface facing the main surface of the package substrate, and the first electrodes and the second electrodes are electrically connected; filling the gap between the package substrate and the semiconductor chip component with a liquid underfill material, and subsequently heat-curing the underfill material to form an underfill including a portion interposed between the package substrate and the semiconductor chip component; providing an intermediate resin portion in contact with the outer peripheral surface of the semiconductor chip component; and providing an encapsulation layer on the package substrate including a portion surrounding the semiconductor chip component, such that the intermediate resin portion is interposed between the underfill and the encapsulation layer.

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