Nitride semiconductor device and nitride semiconductor wafer

Abstract

A nitride semiconductor device (1) is provided with a base layer, and an n-type nitride semiconductor layer (20) provided above the base layer and having n-type conductivity. The n-type nitride semiconductor layer (20) includes a plurality of regions (21) arranged along a direction orthogonal to the thickness direction of the base layer. Each of the plurality of regions (21) includes a high-concentration region (22) and a low-concentration region (23) having a lower carrier concentration than the high-concentration region (22). The high-concentration region (22) and the low-concentration region (23) are arranged along the direction orthogonal to the thickness direction of the base layer.

Description

Nitride semiconductor device and nitride semiconductor wafer

[0001] FIELD OF THE DISCLOSURE The present disclosure relates to nitride semiconductor devices and nitride semiconductor wafers.

[0002] Group III nitride semiconductors are used in optical devices such as semiconductor lasers and light-emitting diodes, but are also used in the field of high-frequency or high-power electronic devices, etc. Devices made using Group III nitride semiconductors have attracted particular attention in recent years because they are expected to reduce switching loss during power conversion compared to silicon-based devices.

[0003] In order to fabricate high-frequency or high-power electronic devices, it is necessary to suppress the occurrence of crystal defects in device layers. For example, there is a need to fabricate devices using high-quality Group III nitride semiconductor substrates, and many attempts have been made to control the threading dislocation density. For example, Patent Document 1 aims to reduce leakage current by controlling the threading dislocation density.

[0004] Japanese Patent Application Laid-Open No. 2007-227790

[0005] T. Kachi et al., “Evaluation of GaN Substrate for Vertical GaN Power Device Applications”, Sensors and Materials, 2013, Vol. 25, No. 3, pp. 219-227I. C. Kiziyalli et al., “Reliability studies of vertical GaN devices based on bulk GaN substrates”, Microelectronics Reliability, Vol. 55, Iss. 9, Jul. 2015, pp. 1654-1661D. D. Koleske et al., “Growth Model for GaN with Comparison to Structural, Optical, and Electrical Properties”, J. Appl. Phys., Aug. 1998, Vol. 84, pp. 1998-2010K. Shiojima et al., “Effect of Wafer Off-Angles on Defect Formation in Drift Layers Grown on Free-Standing GaN Phys. Stat. Sol., Nov. 2019, Vol. 257, No. 4, 1900561

[0006] An object of the present disclosure is to provide a nitride semiconductor device and a nitride semiconductor wafer that can reduce leakage current.

[0007] A nitride semiconductor device according to one aspect of the present disclosure includes an underlayer and a nitride semiconductor layer having n-type conductivity provided above the underlayer, the nitride semiconductor layer including a plurality of regions aligned along a direction perpendicular to a thickness direction of the underlayer, each of the plurality of regions including a first region and a second region having a carrier concentration lower than that of the first region, the first region and the second region being aligned along a direction perpendicular to the thickness direction of the underlayer.

[0008] According to the present disclosure, it is possible to obtain a nitride semiconductor device capable of reducing leakage current.

[0009] FIG. 1 is a cross-sectional view of a nitride semiconductor device according to an embodiment. FIG. 2A is a diagram showing a differential interference microscope image of the surface of a nitride semiconductor layer having small surface roughness. FIG. 2B is a diagram showing a differential interference microscope image of the surface of a nitride semiconductor layer having large surface roughness. FIG. 3 is a diagram showing an atomic force microscope image of the surface of a nitride semiconductor layer having large surface roughness. FIG. 4A is a diagram showing a scanning microwave microscope image of the surface of an n-type nitride semiconductor layer having a flat surface. FIG. 4B is a diagram showing a scanning microwave microscope image of the surface of an n-type nitride semiconductor layer having a ridge structure on its surface. FIG. 5 is a diagram showing the relationship between breakdown voltage and carrier concentration ratio. FIG. 6 is a diagram showing the relationship between breakdown voltage and area ratio. FIG. 7 is a diagram showing the reverse IV characteristics of a pn diode according to an example. FIG. 8 is a diagram showing a scanning capacitance microscope image of a cross section of a pn diode according to an example. FIG. 9 is a cross-sectional view of a nitride semiconductor wafer according to a modified example of the embodiment.

[0010] (Summary of the Present Disclosure) A nitride semiconductor device according to a first aspect of the present disclosure includes an underlayer and a nitride semiconductor layer having n-type conductivity provided above the underlayer, the nitride semiconductor layer including a plurality of regions aligned along a direction perpendicular to a thickness direction of the underlayer, each of the plurality of regions including a first region and a second region having a carrier concentration lower than that of the first region, the first region and the second region being aligned along a direction perpendicular to the thickness direction of the underlayer.

[0011] This makes it possible to reduce the leakage current.

[0012] A nitride semiconductor device according to a second aspect of the present disclosure is the nitride semiconductor device according to the first aspect of the present disclosure, wherein in at least one of the plurality of regions, a value obtained by dividing the carrier concentration of the first region by the carrier concentration of the second region is 2 or less.

[0013] This reduces the ratio of carrier concentrations, thereby making it possible to further reduce leakage current.

[0014] A nitride semiconductor device according to a third aspect of the present disclosure is the nitride semiconductor device according to the first or third aspect of the present disclosure, wherein in at least one of the plurality of regions, the value obtained by dividing the area of ​​the second region in a planar view by the area of ​​the first region in a planar view is 1.5 or less.

[0015] This reduces the area ratio, thereby further reducing the leakage current.

[0016] A nitride semiconductor device according to a fourth aspect of the present disclosure is the nitride semiconductor device according to any one of the first to third aspects of the present disclosure, wherein the average carrier concentration of the nitride semiconductor layer is 1×10 １８ cm －３ The following is the result.

[0017] This prevents the carrier concentration from being too high, thereby increasing the breakdown voltage.

[0018] A nitride semiconductor device according to a fifth aspect of the present disclosure is the nitride semiconductor device according to any one of the first to fourth aspects of the present disclosure, wherein the underlayer is a substrate made of a nitride semiconductor.

[0019] This facilitates lattice matching between the underlayer and the nitride semiconductor layer, making it easier to form a nitride semiconductor layer with good film quality, thereby further reducing leakage current.

[0020] A nitride semiconductor device according to a sixth aspect of the present disclosure is the nitride semiconductor device according to any one of the first to fifth aspects of the present disclosure, further comprising an electrode provided on the lower surface of the underlayer.

[0021] A nitride semiconductor wafer according to a seventh aspect of the present disclosure comprises a substrate and a nitride semiconductor layer having n-type conductivity provided above the substrate, the nitride semiconductor layer including a plurality of regions aligned along a direction perpendicular to a thickness direction of the substrate, each of the plurality of regions including a first region and a second region having a carrier concentration lower than that of the first region, the first region and the second region being aligned along a direction perpendicular to the thickness direction of the substrate.

[0022] This makes it possible to manufacture devices with reduced leakage current using nitride semiconductor wafers.

[0023] A nitride semiconductor wafer according to an eighth aspect of the present disclosure is the nitride semiconductor wafer according to the seventh aspect of the present disclosure, wherein an upper surface of the nitride semiconductor layer is exposed.

[0024] As a result, the upper surface of the nitride semiconductor layer is exposed, and other semiconductor layers can be formed by epitaxial growth directly or after simple surface treatment, thereby simplifying the device manufacturing process.

[0025] Hereinafter, embodiments of the present disclosure will be described with reference to examples. However, the present disclosure is not limited in any way by the use of numerical values ​​or specific elements used in the following description.

[0026] The embodiments described below are all comprehensive or specific examples. The numerical values, shapes, materials, components, component placement and connection configurations, steps, and step order shown in the following embodiments are merely examples and are not intended to limit the present disclosure. Furthermore, among the components in the following embodiments, components not described in the independent claims are described as optional components.

[0027] Furthermore, each figure is a schematic diagram and is not necessarily an exact illustration. Therefore, for example, the scales of the figures do not necessarily match. Furthermore, in each figure, substantially the same components are given the same reference numerals, and redundant explanations are omitted or simplified.

[0028] Furthermore, in this specification, terms indicating the relationship between elements, such as parallel or perpendicular, terms indicating the shape of elements, and numerical ranges are not expressions that only express a strict meaning, but are expressions that also include a substantially equivalent range, for example, a difference of about a few percent.

[0029] In this specification, the "thickness direction" of a substrate refers to the direction perpendicular to the main surface of the substrate. The thickness direction is the same as the stacking direction of the semiconductor layers, and is also referred to as the "vertical direction." The direction parallel to the main surface of the substrate may be referred to as the "lateral direction." A "vertical" semiconductor device refers to a device in which the main path of current, such as drain current or forward current, is vertical, i.e., a device in which the main current passes vertically through the substrate. A "lateral" semiconductor device refers to a device in which the main path of current, such as drain current or forward current, is horizontal, i.e., a device in which the main current does not pass through the substrate.

[0030] Furthermore, in this specification, the terms "above" and "below" do not refer to the upward direction (vertically upward) and downward direction (vertically downward) in absolute spatial recognition, but are used as terms defined by a relative positional relationship based on the stacking order in a stacked configuration. Furthermore, the terms "above" and "below" are applied not only to a case where two components are arranged with a gap between them and another component exists between the two components, but also to a case where two components are arranged closely together and the two components are in contact with each other.

[0031] Furthermore, in this specification, ordinal numbers such as "first" and "second" do not refer to the number or order of components unless otherwise specified, but are used for the purpose of avoiding confusion and distinguishing between components of the same type.

[0032] (Embodiment) [Configuration] The configuration of a nitride semiconductor device according to an embodiment of the present disclosure will now be described with reference to Fig. 1. Fig. 1 is a cross-sectional view showing the configuration of a nitride semiconductor device 1 according to the present embodiment.

[0033] The nitride semiconductor device 1 is a device including a nitride semiconductor layer made of a nitride semiconductor. In the nitride semiconductor device 1, a main current flows through the nitride semiconductor layer during operation. Note that, when the nitride semiconductor device 1 is a diode such as a Schottky diode or a pn diode, the main current during operation is a forward current. When the nitride semiconductor device 1 is a transistor, the main current during operation is a drain current flowing between the drain electrode and the source electrode.

[0034] In this embodiment, a vertical pn diode is used as an example of the nitride semiconductor device 1. As shown in Fig. 1, the nitride semiconductor device 1 includes a substrate 10, an n-type nitride semiconductor layer 20, a p-type nitride semiconductor layer 30, and electrodes 40 and 50.

[0035] The substrate 10 is an example of an underlayer. The substrate 10 is a substrate made of a nitride semiconductor. The material of the substrate 10 is not particularly limited, and can be appropriately selected depending on the characteristics of the n-type nitride semiconductor layer 20 having n-type conductivity. For example, the substrate 10 is a single crystal substrate having the same element composition ratio as the n-type nitride semiconductor layer 20. Alternatively, examples of the material of the substrate 10 include sapphire, silicon, silicon carbide, and ScAlMgO ４ , Group III nitride, LiAlO ２ , or ZnO, etc.

[0036] The n-type nitride semiconductor layer 20 is a semiconductor layer having n-type conductivity, and is provided above the substrate 10. Specifically, the n-type nitride semiconductor layer 20 contacts and covers the upper surface of the substrate 10. The n-type nitride semiconductor layer 20 is made of a nitride semiconductor containing at least one element of Ga, Al, and In, for example. The n-type nitride semiconductor layer 20 is doped with silicon (Si), for example, as an n-type impurity. The upper surface 20a of the n-type nitride semiconductor layer 20 is not flat, but has a ridge structure. A specific example of the ridge structure will be described later with reference to FIG. 3 .

[0037] 1 , the n-type nitride semiconductor layer 20 includes a plurality of regions 21. The plurality of regions 21 are aligned in a direction perpendicular to the thickness direction of the substrate 10. Each of the plurality of regions 21 includes a high-concentration region 22 and a low-concentration region 23. The high-concentration region 22 is an example of a first region. The low-concentration region 23 is an example of a second region, and is a region having a lower carrier concentration than the high-concentration region 22. The boundary between the high-concentration region 22 and the low-concentration region 23 within a region 21 and the boundary between two adjacent regions 21 correspond to the ridges or valleys of the ridge structure of the n-type nitride semiconductor layer 20, respectively.

[0038] The high-concentration regions 22 and the low-concentration regions 23 are aligned in a direction perpendicular to the thickness direction of the substrate 10. In this embodiment, the alignment direction of the multiple regions 21 and the alignment direction of the high-concentration regions 22 and the low-concentration regions 23 within a region 21 are the same. Therefore, as shown in FIG. 1 , the high-concentration regions 22 and the low-concentration regions 23 are aligned alternately. The high-concentration regions 22 and the low-concentration regions 23 are striped in a plan view of the substrate 10, but may be island-shaped or have various other shapes. The shapes of the high-concentration regions 22 and the low-concentration regions 23 are not particularly limited, but are often striped under crystal growth conditions that form a high-quality n-type nitride semiconductor layer 20.

[0039] In at least one of the plurality of regions 21, the carrier concentration ratio obtained by dividing the carrier concentration of the high-concentration region 22 by the carrier concentration of the low-concentration region 23 is equal to or less than 2. Furthermore, for example, the closer the carrier concentration ratio is to 1, the greater the effect of reducing leakage current, as will be described later. In the nitride semiconductor device 1 according to the present embodiment, the carrier concentration ratio in all of the regions 21 is equal to or less than 2.

[0040] Furthermore, in at least one of the plurality of regions 21, the area ratio obtained by dividing the area of ​​the low-concentration region 23 in a plan view by the carrier concentration of the high-concentration region 22 in a plan view is 1.5 or less. The area ratio may be less than 1. That is, the area of ​​the low-concentration region 23 may be smaller than the area of ​​the high-concentration region 22. Since narrow high-concentration regions 22 do not exist locally, electric field concentration in the high-concentration region 22 can be suppressed, and the effect of reducing leakage current is enhanced. In the nitride semiconductor device 1 according to the present embodiment, the area ratio in all of the regions 21 is 1.5 or less.

[0041] As described above, the n-type nitride semiconductor layer 20 of the nitride semiconductor device 1 has a structure in which high-concentration regions 22 and low-concentration regions 23 are repeatedly provided, and in each region 21, the carrier concentration ratio is 2 or less and the area ratio is 1.5 or less. This enables the nitride semiconductor device 1 to suppress to a low value the leakage current that flows when a reverse bias is applied. The relationship between the carrier concentration ratio and the area ratio and the leakage current will be described later.

[0042] The nitride semiconductor device 1 according to the present disclosure is expected to be used as a device for controlling power. The average carrier concentration of the n-type nitride semiconductor layer 20 is, for example, 1×10 １８ cm －３ This allows the breakdown voltage of the nitride semiconductor device 1 to be increased, making the nitride semiconductor device 1 useful as a power control device. The average carrier concentration of the n-type nitride semiconductor layer 20 is, for example, 1×10 １５ cm －３ This is the end. As a result, the resistance during operation of the nitride semiconductor device 1 can be reduced, and the reverse leakage current can be kept low. The average carrier concentration can be estimated from the impurity concentration measured by, for example, Hall effect measurement or secondary ion mass spectrometry (SIMS).

[0043] The multiple regions 21 may include regions with different shapes or sizes. Alternatively, the multiple regions 21 may have the same shape and size. Furthermore, the high-concentration region 22 included in one region 21 may have the same or different shape, size, and carrier concentration as the high-concentration region 22 included in another region 21. The same applies to the low-concentration region 23.

[0044] The thickness of the n-type nitride semiconductor layer 20 is, for example, 1 μm or more and 15 μm or less, for example, about 7 μm to 8 μm. The width of the regions 21 is, for example, 10 μm or more and 100 μm or less. The width of the regions 21 is the length in the arrangement direction of the regions 21.

[0045] The n-type nitride semiconductor layer 20 is formed by growing a nitride semiconductor crystal on the upper surface of the substrate 10 by epitaxial growth such as MOVPE (Metal Organic Vapor Phase Epitaxy). By adjusting the growth conditions such as the temperature and the supply amount of gases that are material supply sources, the n-type nitride semiconductor layer 20 having a distribution of carrier concentrations can be formed. That is, a plurality of regions 21 including high-concentration regions 22 and low-concentration regions 23 can be formed in the n-type nitride semiconductor layer 20.

[0046] The p-type nitride semiconductor layer 30 is a semiconductor layer having p-type conductivity, and is provided above the n-type nitride semiconductor layer 20. Specifically, the p-type nitride semiconductor layer 30 is in contact with and covers the upper surface 20a of the n-type nitride semiconductor layer 20. The p-type nitride semiconductor layer 30 is made of a nitride semiconductor containing at least one element of Ga, Al, and In, for example. The p-type nitride semiconductor layer 30 is doped with, for example, magnesium (Mg) as a p-type impurity.

[0047] There are no particular limitations on the thickness, carrier concentration, etc. of the p-type nitride semiconductor layer 30. In addition, another layer, such as an undoped nitride semiconductor layer, may be provided between the p-type nitride semiconductor layer 30 and the n-type nitride semiconductor layer 20.

[0048] The electrode 40 is provided above the p-type nitride semiconductor layer 30 and is electrically connected to the p-type nitride semiconductor layer 30. Specifically, the electrode 40 contacts and covers the upper surface of the p-type nitride semiconductor layer 30. The electrode 40 functions as an anode electrode of the pn diode. The electrode 40 is formed using a conductive material such as a metal. For example, the electrode 40 is formed using a metal that is ohmic-connected to the p-type nitride semiconductor layer 30. As an example, the electrode 40 has a single-layer or multilayer structure of a conductive film containing a metal such as palladium (Pd), gold (Au), or nickel (Ni).

[0049] The electrode 50 is provided below the n-type nitride semiconductor layer 20 and is electrically connected to the n-type nitride semiconductor layer 20. Specifically, the electrode 50 contacts and covers the lower surface of the substrate 10. The electrode 50 functions as a cathode electrode of the pn diode. The electrode 50 is formed using a conductive material such as a metal. For example, the electrode 50 is formed using a metal that is ohmic-connected to the n-type nitride semiconductor layer 20. As an example, the electrode 50 has a single-layer or multilayer structure of a conductive film containing a metal such as titanium (Ti) or aluminum (Al).

[0050] In the present embodiment, an example in which the nitride semiconductor device 1 is a pn diode has been described, but the present invention is not limited to this. For example, the nitride semiconductor device 1 may not include the p-type nitride semiconductor layer 30, and the electrode 40 may be Schottky-connected to the n-type nitride semiconductor layer 20. That is, the nitride semiconductor device 1 may be a Schottky diode. Alternatively, the nitride semiconductor device 1 may be a vertical transistor that uses the n-type nitride semiconductor layer 20 as a current path. For example, the nitride semiconductor device 1 may be a vertical field effect transistor (FET) that includes a gate electrode and a source electrode instead of the electrode 40, and uses the electrode 50 as a drain electrode.

[0051] Furthermore, although the substrate 10 is used as the base layer in contact with the n-type nitride semiconductor layer 20, the base layer may be a layer other than the substrate 10. For example, a buffer layer provided between the substrate 10 and the n-type nitride semiconductor layer 20 may be used as the base layer. The buffer layer is a layer for alleviating strain that may occur when the layer is formed on a base material such as the substrate 10. The provision of the buffer layer can improve the quality of the n-type nitride semiconductor layer 20. The buffer layer has a single layer or a multilayer structure of layers made of nitride semiconductors such as AlN and AlGaN, for example.

[0052] As described above, in the nitride semiconductor device 1 according to the present embodiment, the n-type nitride semiconductor layer 20 has a structure in which the high-concentration regions 22 and the low-concentration regions 23 are repeatedly provided. This makes it possible to reduce the leakage current that flows through the n-type nitride semiconductor layer 20 compared to when the carrier concentration of the n-type nitride semiconductor layer 20 is uniform.

[0053] It should be noted that the leakage current can also be reduced by sufficiently lowering the carrier concentration of the n-type nitride semiconductor layer 20. However, lowering the carrier concentration of the n-type nitride semiconductor layer 20 increases the resistance during operation of the nitride semiconductor device 1. In the nitride semiconductor device 1 according to the present embodiment, the high-concentration regions 22 and the low-concentration regions 23 are provided alternately, thereby making it possible to reduce the leakage current while suppressing an increase in resistance during operation.

[0054] [Carrier Concentration Distribution] Next, the carrier concentration distribution of the n-type nitride semiconductor layer 20 will be described based on the studies of the present inventors. The present inventors have studied the relationship between the carrier concentration distribution and the leakage current, and have found a carrier concentration ratio and an area ratio that can reduce the leakage current and increase the breakdown voltage.

[0055] First, leakage current flowing through the n-type nitride semiconductor layer 20 includes leakage current that flows when an electric field is applied in the reverse direction to the pn junction formed by the p-type nitride semiconductor layer 30 and the n-type nitride semiconductor layer 20 .

[0056] For example, Non-Patent Document 1 states that pure screw dislocations in III-nitride semiconductor devices cause leakage current when an electric field is applied in the reverse direction. However, other types of dislocations have not been confirmed to cause leakage current, and it is difficult to explain all causes of leakage current solely in terms of pure screw dislocations. Therefore, it is necessary to clarify other causes of leakage current.

[0057] Next, Non-Patent Document 2 investigates reverse leakage current in pn diodes and describes the relationship between surface flatness and leakage current. Specifically, it states that data has been obtained showing that the rougher the surface, the more likely leakage is to occur. Therefore, in recent years, attention has been focused on the influence of surface roughness as one of the causes of leakage.

[0058] However, simply considering the shape of the nitride semiconductor device 1, which is characterized by large surface roughness, it is not possible to explain why a large leakage current flows when an electric field is applied in the reverse direction. For example, it is expected that the large leakage current in the reverse direction can be explained as being caused by the concentration of the electric field, but when the surface roughness is on the order of nanometers and the n-type nitride semiconductor layer 20 has a thickness on the order of micrometers, the effect is small. In other words, it is not expected that the electric field concentration will occur due to the physical shape.

[0059] Therefore, the present inventors considered the possibility that the surface roughness may cause distribution in minute regions regarding the incorporation of impurities, and that the distribution of carrier concentration in the nitride semiconductor layer may affect the reverse leakage current.

[0060] First, we will explain why a carrier concentration distribution occurs in a microscopic region when the surface roughness is large. Here, we will focus on the case of nitride semiconductors, mainly gallium nitride.

[0061] 2A and 2B are both differential interference microscope images of the surface of a nitride semiconductor layer. Fig. 2A shows a case where the surface roughness is small, and Fig. 2B shows a case where the surface roughness is large. When the surface roughness is small, the surface of the nitride semiconductor layer is very flat, as shown in Fig. 2A. On the other hand, when the surface roughness is large, the surface of the nitride semiconductor layer has many ridge structures, as shown in Fig. 2B.

[0062] FIG. 3 is a diagram showing an atomic force microscope (AFM) image of the surface of a nitride semiconductor layer. Specifically, FIG. 3 shows an image obtained by observing the surface of a nitride semiconductor layer with significant surface roughness corresponding to FIG. 2B using an atomic force microscope. The observed range is enlarged in the order of (a) → (b) → (c) and (d) in FIG. 3. The thin white regions extending diagonally in FIG. 3(a) correspond to the ridges of the ridge structure. The dark regions located between two adjacent thin white regions correspond to the valleys of the ridge structure. In other words, in the ridge structure, ridges and valleys extending in approximately the same direction are alternately formed. (c) and (d) in FIG. 3 show one surface and the other surface of the ridge (or valley) of the ridge structure, respectively.

[0063] As shown by comparing (c) and (d) in Figure 3, it was found that the terrace widths of the atomic steps differ between one side and the other side of the ridge structure, and that the ridge structure is not caused by step bunching. Generally, when a line of distinguishable ridge structures is seen in a microscope image such as a differential interference microscope image, it is often thought that the ridge structure is caused by the occurrence of step bunching. However, it was found that the surface roughness, which is the focus of attention in this disclosure and whose relationship with reverse leakage current in nitride semiconductor layers is attracting attention, is a different phenomenon.

[0064] Furthermore, the AFM image shown in Figure 3 indicates that the terrace widths of the atomic steps on the two surfaces forming the ridge structure are different, which means that the off-angles on each surface are slightly different. That is, two surfaces are alternately present: a surface with a large off-angle where the steps are closely spaced as shown in Figure 3(c), and a surface with a small off-angle where the steps are widely spaced as shown in Figure 3(d). For example, the off-angle on the surface shown in Figure 3(c) is greater than 0.2°, e.g., 0.35°. The off-angle on the surface shown in Figure 3(d) is less than 0.2°, e.g., 0.1°.

[0065] A ridge or valley occurs at the boundary between the two planes, forming a ridgeline structure. However, the difference in off-angle is very small, for example, in a very small area of ​​about 100 μm or less. Therefore, in measurements using X-ray diffraction, which is widely used to estimate the off-angle, the measurement area is large, making it difficult to identify that the two planes constituting the ridge or valley have two different off-angles. Therefore, no attention has been paid to ridgeline structures resulting from differences in off-angles in very small areas.

[0066] The reason why two planes with different off angles are formed is thought to be the existence of a plane with a stable off angle under the crystal growth conditions of the nitride semiconductor layer. Non-Patent Document 3 describes the diffusion length of Ga on the gallium nitride surface under various conditions. Although it depends on the crystal growth method, it is estimated that a line of atomic steps with a terrace width comparable to the diffusion distance of Ga is stable. This is expected to result in the formation of an energetically stable plane.

[0067] On the other hand, because the nitride semiconductor layer as a whole inherits the off-angle of the underlayer, planes with different off-angles are also formed to match the average off-angle with that of the underlayer. For example, if the off-angle of a plane stable under the crystal growth conditions of the nitride semiconductor layer is larger than that of the underlayer, planes with smaller off-angles than that of the underlayer are also formed, so that the average off-angle of the nitride semiconductor layer is equal to that of the underlayer. Furthermore, the spacing between the ridges or valleys of the ridgeline structure means that the growth rate at the ridges is faster than that at the valleys, meaning that the growth rate, i.e., the driving force for crystal growth, has a periodic distribution within the plane. Therefore, in the case of vapor phase growth, for example, the spacing between the ridges or valleys can be expected to be changed by the formation conditions of the nitride semiconductor layer in relation to the diffusion distance of the raw material species in the vapor phase.

[0068] Incidentally, Non-Patent Document 4 shows that the incorporation of carbon impurities into a nitride semiconductor layer increases rapidly when the off-angle becomes small to a certain extent. In other words, it was found that, between the two faces constituting the edge, the face with the smaller off-angle has a higher carbon concentration, and the carbon concentrations on the two faces are likely to be different. Furthermore, the carbon impurity concentration in Non-Patent Document 4 is close to the carrier concentration of an n-type nitride semiconductor layer in a nitride semiconductor device for power control. Furthermore, carbon impurities may be contained in the equipment or raw material gases used to form the nitride semiconductor layer, and cannot be easily removed.

[0069] Here, when carbon is incorporated into an n-type nitride semiconductor layer, it compensates for n-type carriers, reducing the n-type carrier concentration. Therefore, the inventors have come to consider the possibility that the carrier concentration may differ between the two faces that make up the edge.

[0070] However, for an n-type nitride semiconductor layer with a large surface roughness, in the Hall effect measurement generally used for carrier concentration measurement or the SIMS used for impurity concentration measurement, for example, the measurement area is narrowed to a range of 100 μm or less and the measurement area is 1×10 １８ cm －３In the case of relatively low carrier or impurity concentrations, it is difficult to detect differences in carrier concentration. Therefore, it is not possible to distinguish between regions with high and low carrier concentrations. In other words, due to problems with the measurement range and measurement accuracy, it is not possible to examine the distribution of carrier or impurity concentrations in a small area.

[0071] In response to this, the present inventors used a scanning microwave microscope (SMM) to investigate whether a carrier concentration distribution exists on the surface of a nitride semiconductor layer having n-type properties and a large surface roughness. Figures 4A and 4B are both SMM images of the surface of a nitride semiconductor layer. Figure 4A shows the carrier concentration distribution of an n-type nitride semiconductor layer having a flat surface, and Figure 4B shows the carrier concentration distribution of an n-type nitride semiconductor layer having a ridge structure on the surface. While no widespread regions of different carrier concentrations were observed on the flat surface of Figure 4A, the inventors discovered that widespread regions of different carrier concentrations exist on the flat surface with the ridge structure of Figure 4B.

[0072] Therefore, the present inventors performed a simulation of reverse leakage current using the carrier concentration ratio and area ratio as variables based on the nitride semiconductor device 1 shown in Fig. 1. As a result, it was found that when multiple pairs of high-concentration regions 22 with high carrier concentrations and low-concentration regions 23 with low carrier concentrations exist in the n-type nitride semiconductor layer 20, the leakage current decreases as the carrier concentration ratio decreases, and the leakage current decreases as the area ratio increases.

[0073] If the leakage current in the nitride semiconductor device 1 increases, it becomes difficult to control the current flowing through the device. Here, as an example, from a practical standpoint, when a reverse bias of 750 V is applied, the leakage current is assumed to be 1×10 －７ When the resistance is less than 1 A, it is considered that the leakage current of the nitride semiconductor device 1 can be made lower.

[0074] Below, the leakage current is 1×10 －７The reverse bias at A was regarded as the breakdown voltage of the nitride semiconductor device 1, and the carrier concentration ratio and area ratio were used as variables to summarize the simulation results. Fig. 5 is a diagram showing the relationship between the breakdown voltage and the carrier concentration ratio. In Fig. 5, the vertical axis represents the breakdown voltage, and the horizontal axis represents the carrier concentration ratio. As shown in Fig. 5, the smaller the carrier concentration ratio becomes and the closer it approaches 1, the higher the breakdown voltage becomes.

[0075] Furthermore, to ensure a breakdown voltage of 750 V, the carrier concentration ratio, which is the value obtained by dividing the carrier concentration of the high-concentration region 22 by the carrier concentration of the low-concentration region 23, is 2 or less. In other words, if the carrier concentration ratio exceeds 2, the breakdown voltage will be lower than 750 V. This is thought to be because, in areas with high carrier concentrations, the depletion layer does not easily expand, and the electric field concentrates, resulting in the generation of areas where the leakage current is large. Thus, if the carrier concentration ratio is 2 or less, the breakdown voltage of the nitride semiconductor device 1 can be made higher.

[0076] 6 is a diagram showing the relationship between breakdown voltage and area ratio. In FIG. 6, the vertical axis represents breakdown voltage and the horizontal axis represents area ratio. As shown in FIG. 6, it can be seen that the breakdown voltage increases as the area ratio decreases.

[0077] Furthermore, in order to ensure a breakdown voltage of 750 V, the area ratio, which is the value obtained by dividing the area of ​​the low concentration region 23 by the area of ​​the high concentration region 22, is 1.5 or less. In other words, if the area ratio exceeds 1.5, the breakdown voltage will be lower than 750 V. This is thought to be because, when the area of ​​the high concentration region 22 is small, the electric field will concentrate in the small area, resulting in the generation of locations where the leakage current will be large.

[0078] However, it is difficult to completely identify the mechanism described above, and it is merely based on the inferences of the present inventors.

[0079] Specific examples of the nitride semiconductor device 1 will be described below.

[0080] In this example, a gallium nitride substrate was used as substrate 10, which is an underlying layer, and a buffer layer 15 made of n-type gallium nitride was formed. Then, an n-type gallium nitride layer having high-concentration regions 22 and low-concentration regions 23 was formed as n-type nitride semiconductor layer 20. The average carrier concentrations were set to decrease in the order of substrate 10, buffer layer 15, and n-type nitride semiconductor layer 20.

[0081] Furthermore, a p-type gallium nitride layer was formed as a p-type nitride semiconductor layer 30 on the n-type nitride semiconductor layer 20. That is, the nitride semiconductor device 1 according to this example is a pn diode. Both gallium nitride layers were obtained by metal organic chemical vapor deposition. Silicon was added to the n-type nitride semiconductor layer 20, and Mg was added to the p-type nitride semiconductor layer 30, to give them their respective polarities.

[0082] Furthermore, by controlling the off-angle of the substrate 10 and the conditions for forming the n-type nitride semiconductor layer 20, the carrier concentration was relatively uniform, while the carrier concentration distribution was formed, thereby forming the high-concentration region 22 and the low-concentration region 23. Specifically, a ridge structure was generated by slightly shifting the diffusion distance of gallium (Ga) during the surface reaction in epitaxial growth and the spacing between atomic steps. This allowed for periodicity in the incorporation of carbon (C), resulting in the formation of a carrier concentration distribution. The periodicity is determined by the diffusion distance of the Ga precursor in the gas phase and is adjusted by the growth temperature or the V / III ratio, etc. The V / III ratio is the ratio of a group V element (specifically, N) to a group III element (specifically, Ga). For example, in the epitaxial growth for forming the n-type nitride semiconductor layer 20, the growth temperature is set to 1000°C or higher and 1200°C or lower. Alternatively, the supply rate of ammonia gas, which is a raw material for GaN, is set to 1 slm or more and 50 slm or less, thereby forming an n-type nitride semiconductor layer 20 in which high concentration regions 22 and low concentration regions 23 are alternately provided.

[0083] The reverse bias leakage current of the formed pn diode was examined, and then the cross section was analyzed using a scanning capacitance microscope (SCM) to investigate the carrier concentration ratio. Note that while SCM measurement allows comparison of carrier concentrations within the range of individual measurement results, it is difficult to compare carrier concentrations between different measurements due to the principles of measurement. In other words, it is not possible to compare carrier concentrations between examples and comparative examples. However, in this disclosure, we want to clarify the carrier concentration variations within each measurement range, so this SCM measurement is sufficient.

[0084] 7 shows the relationship between the reverse bias voltage and the current of the pn diode obtained in this example. The leakage current is 1×10 －７ A or less. That is, it was confirmed that the pn diode has good breakdown voltage performance, that is, a high breakdown voltage.

[0085] 8 is a diagram showing an SCM image of a cross section of a pn diode according to an example. In the n-type gallium nitride layer, the carrier concentration ratio, which is the value obtained by dividing the carrier concentration of the high-concentration region 22 by the carrier concentration of the low-concentration region 23, was 1.2. Furthermore, the carrier concentrations obtained by SCM measurement were generally uniform. Thus, in a nitride semiconductor device with a sufficiently high breakdown voltage, the carrier concentration ratio of the n-type nitride semiconductor layer was a value lower than 2.

[0086] [Modification] Next, a modification of the embodiment will be described with reference to FIG.

[0087] Fig. 9 is a cross-sectional view of a nitride semiconductor wafer 100 according to this modification. As shown in Fig. 9, the nitride semiconductor wafer 100 includes a substrate 10 and an n-type nitride semiconductor layer 20. The nitride semiconductor wafer 100 is also called an epitaxial wafer. By forming a p-type nitride semiconductor layer and various electrodes on the nitride semiconductor wafer 100, it is also possible to create a diode structure, a transistor structure, and the like.

[0088] 9 , the upper surface 20 a of the n-type nitride semiconductor layer 20 is exposed, but this is not limiting. For example, a protective film formed of an inorganic material such as SiN or an organic material such as a resin may be formed on the upper surface 20 a of the n-type nitride semiconductor layer 20. The protective film may be completely or partially removed when a device is manufactured using the nitride semiconductor wafer 100.

[0089] Furthermore, the substrate 10 may be thickened on the assumption that it will be polished. Furthermore, the nitride semiconductor wafer 100 may include a buffer layer provided between the substrate 10 and the n-type nitride semiconductor layer 20.

[0090] While nitride semiconductor devices and nitride semiconductor wafers according to one or more aspects have been described above based on embodiments, the present disclosure is not limited to these embodiments. As long as they do not deviate from the gist of the present disclosure, various modifications that would occur to a person skilled in the art to the present embodiments and configurations constructed by combining components of different embodiments are also included within the scope of the present disclosure.

[0091] For example, in the above embodiment, an example has been shown in which the carrier concentration ratio is 2 or less and the area ratio is 1.5 or less in all regions 21 included in n-type nitride semiconductor layer 20, but this is not limiting. The multiple regions 21 included in n-type nitride semiconductor layer 20 may include one or more regions with a carrier concentration ratio greater than 2 or an area ratio greater than 1.5.

[0092] Furthermore, various modifications, substitutions, additions, omissions, etc. can be made to the above-described embodiments within the scope of the claims or their equivalents.

[0093] The present disclosure can be used in high-frequency or high-power electronic devices, etc.

[0094] REFERENCE SIGNS LIST 1 nitride semiconductor device 10 substrate 15 buffer layer 20 n-type nitride semiconductor layer 20a upper surface 21 region 22 high concentration region 23 low concentration region 30 p-type nitride semiconductor layer 40, 50 electrode 100 nitride semiconductor wafer

Claims

1. A nitride semiconductor device comprising: an underlayer; and a nitride semiconductor layer having n-type conductivity provided above the underlayer, wherein the nitride semiconductor layer includes a plurality of regions aligned along a direction perpendicular to a thickness direction of the underlayer, each of the plurality of regions including: a first region and a second region having a carrier concentration lower than that of the first region, and the first region and the second region are aligned along a direction perpendicular to the thickness direction of the underlayer.

2. The nitride semiconductor device according to claim 1, wherein in at least one of said plurality of regions, a value obtained by dividing the carrier concentration of said first region by the carrier concentration of said second region is 2 or less.

3. The nitride semiconductor device according to claim 1, wherein in at least one of said plurality of regions, the value obtained by dividing the area of ​​said second region in a plan view by the area of ​​said first region in a plan view is 1.5 or less.

4. The average carrier concentration of the nitride semiconductor layer is 1×10 １８ cm －３ The nitride semiconductor device according to claim 1 , wherein:

5. The nitride semiconductor device according to any one of claims 1 to 3, wherein the underlayer is a substrate made of a nitride semiconductor.

6. The nitride semiconductor device according to claim 1, further comprising an electrode provided on a lower surface of the underlayer.

7. A nitride semiconductor wafer comprising: a substrate; and a nitride semiconductor layer having n-type conductivity provided above the substrate, wherein the nitride semiconductor layer includes a plurality of regions aligned along a direction perpendicular to the thickness direction of the substrate, each of the plurality of regions including: a first region and a second region having a carrier concentration lower than that of the first region, and the first region and the second region aligned along the direction perpendicular to the thickness direction of the substrate.

8. The nitride semiconductor wafer according to claim 7, wherein an upper surface of the nitride semiconductor layer is exposed.

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