Semiconductor device and method for producing same

Abstract

This semiconductor device comprises: a first impurity region (11); a drift layer (12) that is disposed on the first impurity region (11); a body layer (13) that is formed on the drift layer (12); a second impurity region (14) that is formed in a surface layer portion of the body layer (13); a gate trench (15) that penetrates the second impurity region (14) and the body layer (13); a breakdown voltage trench (18) that is different from the gate trench (15) and penetrates the body layer (13); and second conductivity type breakdown voltage enhancement layers (19, 20) that are formed along the breakdown voltage trench (18) and have a portion that is positioned closer to the first impurity region (11) than the lower surface of the gate trench (15). This semiconductor device also comprises a first conductivity type high concentration layer (21) which is in contact with the breakdown voltage enhancement layers (19, 20) at a position that is closer to the first impurity region (11) than the lower surface of the gate trench (15), and which has a higher impurity concentration than the drift layer (12).

Description

Semiconductor device and manufacturing method thereof CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application is based on Japanese Patent Application No. 2024-123446, filed on July 30, 2024, the contents of which are incorporated herein by reference.

[0002] The present disclosure relates to a semiconductor device and a method for manufacturing the same.

[0003] Conventionally, a semiconductor device made of silicon carbide (hereinafter simply referred to as SiC) on which a MOSFET (an abbreviation for metal oxide semiconductor field effect transistor) having a trench gate structure has been proposed (see, for example, Patent Document 1). ＋ An n-type drift layer is formed on an n-type drain layer, and a p-type body layer is formed on the drift layer. ＋ A source region of a first conductivity type is formed. In this semiconductor device, a trench gate structure is formed so as to penetrate the source region and the body layer and reach the drift layer. The trench gate structure is configured by disposing a gate electrode in a gate trench via a gate insulating film. In this semiconductor device, a first electrode is disposed connected to the source region and the body layer, and a second electrode is disposed connected to the drain layer. In this semiconductor device, a deep layer of a second conductivity type is formed below the trench gate structure and connected to the body layer (i.e., the first electrode).

[0004] In such a semiconductor device, a deep layer is formed at a position deeper than the trench gate structure, and therefore, in the off state, a depletion layer formed between the deep layer and the drift layer suppresses the rise of equipotential lines due to the influence of the drain voltage, making it difficult for a high electric field to penetrate into the gate insulating film. This prevents the gate insulating film from being destroyed, and increases the DS breakdown voltage between the drain and source.

[0005] Japanese Patent Application Laid-Open No. 2019-46908

[0006] The present inventors have been studying a semiconductor device in which a voltage-resistant trench is formed separately from the gate trench, and a p-type voltage-resistant layer is formed along the voltage-resistant trench and electrically connected to the first electrode to improve the DS breakdown voltage. The voltage-resistant layer is formed to have a portion located below the gate trench. However, in such a semiconductor device, the p-type voltage-resistant layer is formed within the n-type drift layer, which may cause a depletion layer between the drift layer and the voltage-resistant layer to expand, narrowing the current path and potentially increasing the on-resistance.

[0007] An object of the present disclosure is to provide a semiconductor device capable of reducing on-resistance and a method for manufacturing the same.

[0008] According to one aspect of the present disclosure, a semiconductor device includes a first impurity region of a first conductivity type or a second conductivity type, a drift layer of the first conductivity type disposed on the first impurity region and having a lower impurity concentration than the first impurity region, a body layer of the second conductivity type formed on the drift layer, a second impurity region of the first conductivity type formed in a surface layer portion of the body layer, a gate trench penetrating the second impurity region and the body layer, a gate insulating film formed on an inner wall surface of the gate trench, a gate electrode formed on the gate insulating film, and a gate the gate trench is different from the gate trench and includes a voltage-resistant trench penetrating the body layer; a second conductivity-type voltage-resistant improvement layer formed along the voltage-resistant trench and having a portion located closer to the first impurity region than the bottom surface of the gate trench; a first electrode electrically connected to the second impurity region, the body layer, and the voltage-resistant improvement layer; and a second electrode electrically connected to the first impurity region, and includes a first conductivity-type high-concentration layer that is in contact with the voltage-resistant improvement layer closer to the first impurity region than the bottom surface of the gate trench and has a higher impurity concentration than the drift layer.

[0009] According to this, the high concentration layer having a higher impurity concentration than the drift layer is arranged so as to be in contact with the breakdown voltage improving layer arranged closer to the first impurity region than the gate trench, and therefore, in the on-state, it is possible to prevent the depletion layer caused by the breakdown voltage improving layer from extending too much, thereby reducing the on-resistance.

[0010] According to one aspect of the present disclosure, the above-described method for manufacturing a semiconductor device includes preparing a semiconductor substrate having an epitaxial layer grown on a first impurity region, forming a high-concentration layer in the semiconductor substrate, and, after forming the high-concentration layer, forming a gate trench and a voltage-resistant trench.

[0011] According to this, since the gate trench and the voltage-resistant trench are formed after the high-concentration layer is formed, alignment is easier than when the high-concentration layer is formed after the gate trench and the voltage-resistant trench are formed, and the manufacturing process can be simplified.

[0012] 1 is a plan view showing a semiconductor device according to a first embodiment; FIG. 2 is a cross-sectional view taken along line II-II in FIG. 1; FIG. 3 is a diagram showing the relationship between the impurity concentration of a high-concentration layer, on-resistance, and DS breakdown voltage; FIG. 4 is a cross-sectional view showing a semiconductor device without a high-concentration layer; FIG. 5 is a cross-sectional view showing a semiconductor device according to a modification of the first embodiment; FIG. 6 is a cross-sectional view showing a semiconductor device according to a second embodiment; FIG. 7 is a cross-sectional view showing a semiconductor device according to a modification of the second embodiment; FIG. 8 is a cross-sectional view showing a semiconductor device according to a modification of the second embodiment; FIG. 9 is a cross-sectional view showing a semiconductor device according to a modification of the second embodiment; FIG. 10 is a cross-sectional view showing a semiconductor device according to a modification of the second embodiment; FIG. 11 is a cross-sectional view showing a semiconductor device according to a modification of the second embodiment; FIG. 12 is a cross-sectional view showing a semiconductor device according to a modification of the fourth embodiment; FIG. 13 is a cross-sectional view showing a semiconductor device according to a modification of the fourth embodiment; FIG. 14 is a cross-sectional view showing a semiconductor device according to a modification of the fourth embodiment; FIG. 15 is a cross-sectional view showing a semiconductor device according to a modification of the fourth embodiment; FIG. 10 is a cross-sectional view showing a semiconductor device according to a modification of the fifth embodiment. FIG. 11 is a cross-sectional view showing a semiconductor device according to the sixth embodiment. FIG. 12 is a cross-sectional view showing a semiconductor device according to the seventh embodiment. FIG. 13 is a cross-sectional view showing a semiconductor device according to a modification of the seventh embodiment. FIG. 14 is a cross-sectional view showing a semiconductor device according to a modification of the seventh embodiment. FIG. 15 is a cross-sectional view showing a semiconductor device according to a modification of the seventh embodiment.

[0013] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. In the following embodiments, identical or equivalent parts will be denoted by the same reference numerals.

[0014] First Embodiment A first embodiment will be described with reference to the drawings. In this embodiment, a semiconductor device made of SiC will be described as an example of a semiconductor device. Note that the following description will be given by taking a semiconductor device including a MOSFET as an example.

[0015] 1, the semiconductor device has an active region Ra and a peripheral region Rb surrounding the active region Ra. The active region Ra is a region in which a MOSFET is formed and current flows, as will be described later. The peripheral region Rb is disposed to surround the active region Ra, and is a region in which a FLR (Field Limiting Ring) structure and the like are formed, although a detailed configuration thereof will be omitted. The peripheral region Rb is also formed with a pad portion 1 and the like that is connected to a gate electrode 17, as will be described later.

[0016] As shown in FIG. 2, the semiconductor device is configured using a semiconductor substrate 10 having one surface 10a and another surface 10b. Note that FIG. 2 is a cross-sectional view taken along line II-II in FIG. 1, and is a cross-sectional view of the active region Ra. Hereinafter, the depth (i.e., thickness) direction of the semiconductor substrate 10 will be referred to as the Z-axis direction, a direction parallel to the one surface 10a of the semiconductor substrate 10 (i.e., a direction perpendicular to the Z-axis direction) will be referred to as the X-axis direction, and a direction perpendicular to the X-axis and Z-axis directions will be referred to as the Y-axis direction. Hereinafter, the length in the Z-axis direction from the one surface 10a of the semiconductor substrate 10 to the other surface 10b will also be referred to simply as the depth. The Z-axis direction can also be considered the stacking direction of the substrate 11 and the drift layer 12, which will be described later. Furthermore, hereinafter, the portion of each of the components, which will be described later and which is located on the other surface 10b side, will also be referred to as the bottom surface.

[0017] In this embodiment, the semiconductor substrate 10 is made of SiC. However, the semiconductor substrate 10 may be made of gallium nitride, gallium oxide, or the like. The semiconductor substrate 10 is made of SiC. ＋In this embodiment, the substrate 11 has an off-angle of 0 to 8° with respect to the (0001) Si plane, and an n-type impurity concentration of nitrogen, phosphorus, or the like of 1.0×10 １９ / cm ３ The substrate 11 has a thickness of about 300 μm. In this embodiment, the substrate 11 constitutes a drain region, and corresponds to a first impurity region.

[0018] On the surface of the substrate 11, for example, an n-type impurity concentration of 8.5×10 １５ / cm ３ and the n-type semiconductor layer 11 has a lower impurity concentration than the substrate 11. － An n-type drift layer 12 is formed on the semiconductor substrate 10. The n-type buffer layer may be provided between the substrate 11 and the drift layer 12. The n-type buffer layer has a lower impurity concentration than the substrate 11 and a higher impurity concentration than the drift layer 12. For example, a p-type buffer layer having a p-type impurity concentration of 5.0×10 １６ ~2.0 x 10 １９ / cm ３ On the body layer 13, for example, an n-type impurity concentration (i.e., surface concentration) of 1.0×10 ２１ / cm ３ and the n ＋ A source region 14 of the type is formed on the semiconductor substrate 10. In this embodiment, the semiconductor substrate 10 has one surface 10a on the source region 14 side and another surface 10b on the substrate 11 side. In this embodiment, the source region 14 corresponds to a second impurity region.

[0019] Gate trenches 15 are formed in the semiconductor substrate 10, penetrating from one surface 10a through the source region 14 and the body layer 13. In this embodiment, the gate trenches 15 extend with their longitudinal direction in the Y-axis direction. Although only one gate trench 15 is shown in FIG. 1, in reality, a plurality of gate trenches 15 extend with their longitudinal direction in the Y-axis direction, and are arranged at equal intervals in the X-axis direction to form a stripe pattern.

[0020] The inner wall surface of the gate trench 15 is covered with a gate insulating film 16, and a gate electrode 17 is disposed on the gate insulating film 16. Each gate electrode 17 is insulated from the semiconductor substrate 10 by the gate insulating film 16. In this manner, the trench gate structure of this embodiment is formed.

[0021] Furthermore, in the semiconductor substrate 10, breakdown voltage trenches 18 are formed, which extend from the one surface 10a through the source region 14 and the body layer 13 to reach the drift layer 12. Similar to the gate trenches 15, the breakdown voltage trenches 18 are extended in the Y-axis direction as their longitudinal direction, and a plurality of them are formed in a stripe pattern along the X-axis direction. Furthermore, the breakdown voltage trenches 18 are formed such that the gate trenches 15 are disposed between adjacent breakdown voltage trenches 18 in the X-axis direction.

[0022] The voltage trench 18 of this embodiment is formed so that its lower surface is located closer to the other surface 10b than the lower surface of the gate trench 15. In other words, the voltage trench 18 of this embodiment is formed so that its lower surface is deeper than the lower surface of the gate trench 15. The lower surface of the gate trench 15 refers to the surface of the gate trench 15 facing the other surface 10b, and the lower surface of the voltage trench 18 refers to the surface of the voltage trench 18 facing the other surface 10b. The inner wall surface of the voltage trench 18 is covered with an insulating film 25 made of an oxide film or the like.

[0023] A p-type trench lower layer 19 is formed in the semiconductor substrate 10 so as to face the lower surface of the breakdown voltage trench 18. When the semiconductor substrate 10 is viewed from the one surface 10a side, the trench lower layer 19 is formed so as to extend elongate along the longitudinal direction of the corresponding breakdown voltage trench 18 (i.e., the Y-axis direction in this embodiment). However, the trench lower layer 19 may be formed so as to have a divided portion between one end and the other end of the longitudinal direction of the breakdown voltage trench 18. Furthermore, although the trench lower layer 19 is formed so as to contact the lower surface of the breakdown voltage trench 18 in this embodiment, it may also be formed slightly away from the lower surface of the breakdown voltage trench 18. Note that when the semiconductor substrate 10 is viewed from the one surface 10a side, it can also be referred to as when viewed from the Z-axis direction or in the stacking direction of the substrate 11 and the drift layer 12.

[0024] The semiconductor substrate 10 also includes a p-type trench-side layer 20 formed along the side surface of the breakdown voltage trench 18, the p-type trench-side layer 20 being connected to the trench lower layer 19. The breakdown voltage trench 18 of this embodiment has a portion protruding from the source region 14 that is covered with the trench lower layer 19 and the trench-side layer 20. The semiconductor substrate 10 also includes a contact region 26 formed on the opposite side of the source region 14 from the gate trench 15 and connected to the trench-side layer 20. The trench-side layer 20 is formed from the lower surface of the contact region 26 along the side surface of the breakdown voltage trench 18. The specific shape of the contact region 26 can be changed as needed, as long as the trench lower layer 19, the trench-side layer 20, and the body layer 13 are electrically connected to an upper electrode 23 (described later) and the potential is fixed. For example, the contact region 26 may be formed to extend elongatedly in the Y-axis direction, or may be divided and selectively formed. The contact region 26 may be formed above the body layer 13. The lower surface of the contact region 26 refers to the surface of the contact region 26 on the other surface 10b side.

[0025] The trench-side layer 20 in this embodiment is selectively formed in the Y-axis direction. In the portion where the trench-side layer 20 is not formed, the body layer 13 is in contact with the side surface of the breakdown-voltage trench 18. However, the trench-side layer 20 may be formed so as to extend long along the longitudinal direction of the gate trench 15 (i.e., the Y-axis direction in this embodiment). Furthermore, although the trench-side layer 20 is formed so as to be in contact with the side surface of the breakdown-voltage trench 18 in this embodiment, it may be formed slightly away from the side surface of the breakdown-voltage trench 18.

[0026] As described above, the breakdown voltage trench 18 is formed so that its lower surface is located closer to the other surface 10b than the lower surface of the gate trench 15. Therefore, it can be said that the trench lower layer 19 is formed closer to the other surface 10b (i.e., at a deeper position) than the lower surface of the gate trench 15. It can also be said that the trench-side layer 20 has a portion formed closer to the other surface 10b (i.e., at a deeper position) than the lower surface of the gate trench 15. In this embodiment, the trench lower layer 19 and the trench-side layer 20 correspond to breakdown voltage improving layers.

[0027] Furthermore, in the semiconductor substrate 10, an n-type high-concentration layer 21 having a higher n-type impurity concentration than the drift layer 12 is formed in the trench lower layer 19 and the trench-side layer 20 at a position closer to the other surface 10b than the lower surface of the gate trench 15 (i.e., a deeper position). In this embodiment, the high-concentration layer 21 is formed to be in contact with the lower surface of the body layer 13, cover the trench lower layer 19 and the trench-side layer 20, and further cover the portion of the gate trench 15 that protrudes from the body layer 13 toward the other surface 10b. In other words, the high-concentration layer 21 is formed over the entire area between the drift layer 12 and the body layer 13. The high-concentration layer 21 is formed so that its lower surface is approximately parallel to the other surface 10b. Note that the lower surface of the body layer 13 refers to the surface of the body layer 13 facing the other surface 10b, and the lower surface of the high-concentration layer 21 refers to the surface of the high-concentration layer 21 facing the other surface 10b.

[0028] The n-type impurity concentration of the high-concentration layer 21 is higher than that of the drift layer 12, but is set to be half or less of the p-type impurity concentration of the p-type trench lower layer 19 and the p-type trench-side layer 20. The trench lower layer 19 and the trench-side layer 20 have a p-type impurity concentration of, for example, 2.0×10 １７ ~5.0 x 10 １８ / cm ３ It is said to be about that level.

[0029] An interlayer insulating film 22 is disposed on the one surface 10a of the semiconductor substrate 10 so as to cover the gate electrode 17. The interlayer insulating film 22 is made of BPSG (an abbreviation for borophosphosilicate glass) or the like. Contact holes 22a are formed in the interlayer insulating film 22 to expose the source region 14 and the breakdown voltage trench 18.

[0030] An upper electrode 23 is disposed on the interlayer insulating film 22. Specifically, the upper electrode 23 is formed so as to be electrically connected to the source region 14 and the contact region 26 through a contact hole 22a formed in the interlayer insulating film 22. The upper electrode 23 is also disposed in the voltage-resistant trench 18. However, because an insulating film 25 is disposed in the voltage-resistant trench 18, the upper electrode 23 disposed in the voltage-resistant trench 18 is not directly electrically connected to the trench lower layer 19 and the trench-side layer 20. This configuration can suppress the occurrence of breakdown and an increase in drain-source DS leakage. The trench-side layer 20 is electrically connected to the upper electrode 23 via the contact region 26, and the trench lower layer 19 and the body layer 13 are electrically connected to the upper electrode 23 via the trench-side layer 20 and the contact region 26. In this embodiment, the upper electrode 23 corresponds to a first electrode.

[0031] The upper electrode 23 of this embodiment is made of a plurality of metals, such as Ni / Al. The portion of the plurality of metals that contacts the portion that constitutes the n-type SiC (i.e., the source region 14) is made of a metal that can make ohmic contact with the n-type SiC. Furthermore, the portion of the plurality of metals that contacts at least the p-type SiC (i.e., the contact region 26) is made of a metal that can make ohmic contact with the p-type SiC.

[0032] A lower electrode 24 electrically connected to the substrate 11 is formed on the other surface 10b of the semiconductor substrate 10. In this embodiment, the lower electrode 24 corresponds to the second electrode.

[0033] The above is the configuration of the semiconductor device in this embodiment. In this embodiment, n-type corresponds to the first conductivity type, and p-type corresponds to the second conductivity type. As described above, the semiconductor device has an active region Ra and a peripheral region Rb surrounding the active region Ra. The high-concentration layer 21 in this embodiment is formed only in the active region Ra. Next, the operation and effects of the semiconductor device will be described.

[0034] In the semiconductor device of this embodiment, in the off state before a gate voltage equal to or greater than the threshold voltage is applied to the gate electrode 17, no inversion layer is formed in the body layer 13. Therefore, even if a positive voltage, for example, 1600 V, is applied to the bottom electrode 24, electrons do not flow from the source region 14 into the body layer 13, and the semiconductor device is in the off state where no current flows between the top electrode 23 and the bottom electrode 24.

[0035] When the semiconductor device is in an off state, an electric field is applied between the gate and drain, which can cause electric field concentration on the underside of the gate insulating film 16. However, in the semiconductor device of this embodiment, the trench lower layer 19 and a portion of the trench-side layer 20 are formed closer to the other surface 10b (i.e., at a deeper position) than the gate trench 15. Therefore, the depletion layer formed between the p-type trench lower layer 19 and trench-side layer 20 and the n-type high-concentration layer 21 suppresses the rise of equipotential lines due to the influence of the drain voltage, making it difficult for a high electric field to penetrate the gate insulating film 16. Therefore, in this embodiment, it is possible to suppress breakdown of the gate insulating film 16 and improve the DS breakdown voltage between the drain and source.

[0036] When a gate voltage equal to or higher than the threshold voltage, for example, 20 V, is applied to the gate electrode 17, an inversion layer (i.e., a channel) is formed on the surface of the body layer 13 that is in contact with the gate trench 15. As a result, electrons flow from the source region 14 to the substrate 11 via the inversion layer, the high-concentration layer 21, and the drift layer 12, resulting in an on-state.

[0037] In this case, if the depletion layer resulting from the trench lower layer 19 and the trench-side layer 20 extends too far at a position closer to the other surface 10b than the gate trench 15, the current path narrows and the on-resistance increases. For this reason, in this embodiment, the high-concentration layer 21 is formed so as to contact the trench lower layer 19 and the trench-side layer 20 at a position closer to the other surface 10b than the gate trench 15. This makes it possible to prevent the depletion layer from extending too far, thereby reducing the on-resistance.

[0038] Here, when the high-concentration layer 21 is formed as in this embodiment, the depletion layer resulting from the trench lower layer 19 and the trench-side layer 20 is less likely to extend, which raises concerns about a decrease in the DS breakdown voltage. For this reason, the inventors conducted extensive research into the relationship between the n-type impurity concentration of the high-concentration layer 21, the on-resistance Ron, and the DS breakdown voltage, and obtained the results shown in Fig. 3. Note that the "no impurity concentration in the high-concentration layer 21" in Fig. 3 refers to a semiconductor device in which the high-concentration layer 21 is not formed and the drift layer 12 is in contact with the trench lower layer 19 and the trench-side layer 20, as shown in Fig. 4.

[0039] 3, it has been confirmed that increasing the impurity concentration of the high-concentration layer 21 reduces the on-resistance Ron, but also reduces the DS breakdown voltage. However, when the n-type impurity concentration of the high-concentration layer 21 is increased to, for example, 5×10 １６ / cm ３ It is confirmed that when the n-type impurity concentration of the high-concentration layer 21 is 5×10, the on-resistance Ron can be reduced by about 30% compared to when the high-concentration layer 21 is not provided. １６ / cm ３ In this case, it was confirmed that the DS breakdown voltage was approximately 11% lower than when the high-concentration layer 21 was not provided. In other words, it was confirmed that forming the high-concentration layer 21 lowered the DS breakdown voltage, but also reduced the on-resistance Ron. In other words, it was confirmed that forming the high-concentration layer 21 reduced the on-resistance Ron more than the DS breakdown voltage. However, if the impurity concentration of the high-concentration layer 21 is too high, the depletion layer becomes difficult to extend, which may significantly reduce the DS breakdown voltage. Furthermore, according to the inventors' studies, it was confirmed that the n-type impurity concentration of the high-concentration layer 21 is preferably equal to or less than half the p-type impurity concentration of the trench-lower layer 19 and the trench-side layer 20. Therefore, in this embodiment, the n-type impurity concentration of the high-concentration layer 21 is equal to or less than half the p-type impurity concentration of the p-type trench-lower layer 19 and the p-type trench-side layer 20. This allows the rate of reduction in on-resistance Ron to be greater than the rate of reduction in DS breakdown voltage.

[0040] Such a semiconductor device is manufactured, for example, as follows. First, an epitaxial layer constituting the drift layer 12 and the like is grown on the substrate 11 to form the semiconductor substrate 10. Next, n-type impurities are ion-implanted to form the high-concentration layer 21. The high-concentration layer 21 is formed from the surface 10a of the semiconductor substrate 10 to a deep position by, for example, ion-implanting n-type impurities while changing the acceleration voltage. At this time, the maximum acceleration voltage is set to approximately 2500 KeV. The high-concentration layer 21 may be formed by increasing the impurity concentration of the portion that will become the high-concentration layer 21 when growing the epitaxial layer. That is, the ion-implantation to form the high-concentration layer 21 may be omitted. Next, the body layer 13, the source region 14, and the contact region 26 are formed, and then the gate trench 15, the breakdown voltage trench, and the like are formed. Then, a mask is appropriately positioned to implant p-type impurities to form the trench lower layer 19 and the trench-side layer 20, and the gate insulating film 16, the gate electrode 17, and the like are formed in sequence. The trench lower layer 19 and the trench side layer 20 are formed along the voltage-resistant trench 18 by ion-implanting p-type impurities into the wall surfaces of the voltage-resistant trench 18. Thereafter, the upper electrode 23 and the lower electrode 24 are manufactured, thereby completing the manufacturing of the semiconductor device.

[0041] According to the present embodiment described above, the n-type high-concentration layer 21, which has a higher impurity concentration than the drift layer 12, is arranged so as to be in contact with the p-type trench lower layer 19 and trench-side layer 20, which are arranged at a position deeper than the gate trench 15. Therefore, in the on-state, it is possible to prevent the depletion layer caused by the trench lower layer 19 and the trench-side layer 20 from extending too much, and it is possible to reduce the on-resistance.

[0042] (1) In this embodiment, the breakdown voltage improving layer is configured to include the trench lower layer 19. This makes it easier to dispose the p-type layer at a position deeper than the gate trench 15, making it easier to increase the DS breakdown voltage.

[0043] (2) In this embodiment, the high-concentration layer 21 is formed in contact with the lower surface of the body layer 13, covering the portion of the gate trench 15 protruding from the body layer 13, the trench-lower layer 19, and the trench-side layer 20. Such a high-concentration layer 21 is formed by ion-implanting n-type impurities throughout the gate trench 15 or by adjusting the n-type impurity concentration during epitaxial layer growth. This simplifies the manufacturing process compared to when the high-concentration layer 21 is selectively formed. Furthermore, because the high-concentration layer 21 is formed to cover the trench-lower layer 19 and the trench-side layer 20, excessive extension of the depletion layer resulting from the trench-lower layer 19 and the trench-side layer 20 in the surface direction and the depth direction can be suppressed. This further reduces the on-resistance.

[0044] (3) In this embodiment, the bottom surface of the breakdown voltage trench 18 is formed so as to be located closer to the other surface 10b than the bottom surface of the gate trench 15. This makes it easier to form the trench lower layer 19, which is formed so as to face the bottom surface of the breakdown voltage trench 18, at a deeper position. This makes it easier to increase the DS breakdown voltage.

[0045] (4) In this embodiment, the portion of the high-concentration layer 21 on the substrate 11 side (i.e., the portion on the other surface 10b side) is parallel to the surface direction of the substrate 11. This makes it easier for the depletion layer to spread evenly toward the substrate 11 side during off-state operation, making it easier to increase the DS breakdown voltage.

[0046] (5) In this embodiment, the high-concentration layer 21 is formed only in the active region Ra. This makes it easier to prevent the equipotential lines from rising due to the influence of the drain voltage from the peripheral region Rb. This makes it possible to prevent a decrease in the DS breakdown voltage.

[0047] (6) In this embodiment, the n-type impurity concentration of the high-concentration layer 21 is set to be equal to or less than half the p-type impurity concentration of the trench lower layer 19 and the trench-side layer 20. This can prevent a significant decrease in the DS breakdown voltage.

[0048] (7) In this embodiment, the gate trenches 15 and the breakdown voltage trenches 18 are formed after the high concentration layer 21 is formed. This makes alignment easier and simplifies the manufacturing process compared to when the high concentration layer 21 is formed after the gate trenches 15 and the breakdown voltage trenches 18 are formed.

[0049] (Modification of First Embodiment) A modification of the first embodiment will be described. In the first embodiment, the detailed shape of the body layer 13 can be changed as appropriate as long as it is electrically connected to the upper electrode 23. For example, the body layer 13 may be formed so as to be exposed from the one surface 10a of the semiconductor substrate 10 together with the source region 14, and may be electrically connected to the upper electrode 23 on the one surface 10a side. Furthermore, in the first embodiment, a portion of the trench-side layer 20 is located closer to the other surface 10b than the lower surface of the gate trench 15, and this portion can also improve the DS breakdown voltage. Therefore, the trench lower layer 19 does not need to be formed.

[0050] In the first embodiment, as shown in FIG. 5 , the high-concentration layer 21 may be configured by stacking a first high-concentration layer 21 a and a second high-concentration layer 21 b in the Z-axis direction (i.e., the depth direction), and the n-type impurity concentrations of the first high-concentration layer 21 a and the second high-concentration layer 21 b may be different. That is, the n-type impurity concentration of the high-concentration layer 21 may not be constant in the depth direction. Furthermore, although not particularly shown, the n-type impurity concentration of the high-concentration layer 21 may not be constant in the surface direction of the semiconductor substrate 10 (i.e., the X-axis direction and the Y-axis direction). Furthermore, although not particularly shown, the n-type impurity concentration of the high-concentration layer 21 may be higher in the portion in contact with the trench lower layer 19 and the trench-side layer 20 than in the portion not in contact with the trench lower layer 19 and the trench-side layer 20. Even when the n-type impurity concentration is made different in parts, it is preferable that the n-type impurity concentration of the highest part of the high-concentration layer 21 be equal to or less than half the p-type impurity concentration of the trench lower layer 19 and the trench-side layer 20.

[0051] Furthermore, in the first embodiment, the n-type impurity concentration of the high-concentration layer 21 may be set to be higher than half the p-type impurity concentration of the p-type trench lower layer 19 and the p-type trench-side layer 20. With such a semiconductor device, the on-resistance can also be reduced.

[0052] Second Embodiment A second embodiment will be described. This embodiment is different from the first embodiment in that the shape of the high-concentration layer 21 is changed. As the rest of the configuration is the same as the first embodiment, a description thereof will be omitted here.

[0053] 6 , in the semiconductor device of this embodiment, the high-concentration layer 21 is formed along the breakdown voltage trenches 18. In other words, the high-concentration layer 21 is formed along the trench lower layer 19 and the trench-side layer 20. The high-concentration layer 21 has a divided portion covering each breakdown voltage trench 18. The lower surface of the gate trench 15 is exposed from the high-concentration layer 21, and the exposed portion is in contact with the drift layer 12.

[0054] Such a high-concentration layer 21 is manufactured by growing an epitaxial layer that constitutes the drift layer 12, etc. on the substrate 11 to form the semiconductor substrate 10, and then performing ion implantation using a mask to form the high-concentration layer 21.

[0055] According to the present embodiment described above, the high-concentration layer 21 is formed so as to be in contact with the p-type trench lower layer 19 and the trench-side layer 20, which are located deeper than the gate trench 15. Therefore, the same effects as those of the first embodiment can be obtained.

[0056] (1) In this embodiment, the gate trench 15 is exposed from the high-concentration layer 21. That is, compared to the first embodiment, the area where the high-concentration layer 21 is formed is reduced. This makes it easier to prevent the DS breakdown voltage from decreasing.

[0057] (Modification of Second Embodiment) A modification of the second embodiment will be described. In the second embodiment, as shown in FIG. 7A , the high-concentration layer 21 may be formed so as to contact only the trench-side layer 20, and not so as to contact the trench lower layer 19. In this case, as shown in FIG. 7B , the high-concentration layer 21 may be formed so as to contact only a portion of the trench-side layer 20 located on the other surface 10b side of the gate trench 15. Alternatively, as shown in FIG. 7C , the high-concentration layer 21 may be formed so as to contact only a portion of the trench-side layer 20 located on the other surface 10b side of the gate trench 15, and further on the other surface 10b side. Furthermore, as shown in FIG. 7D , unlike the first embodiment, the high-concentration layer 21 may not have a portion in contact with the trench lower layer 19. 7E , the high-concentration layer 21 may be formed in contact with only a portion of the trench-side layer 20 located closer to the other surface 10b than the gate trench 15, as compared to the configuration of FIG. 7D , so that the lower surface of the gate trench 15 is exposed from the high-concentration layer 21. Alternatively, the high-concentration layer 21 may be formed in contact with a portion of the trench-side layer 20 located below the gate trench 15 and in contact with the trench lower layer 19, as shown in FIG. 7F , so that the lower surface of the gate trench 15 is exposed from the high-concentration layer 21. In this case, as shown in FIG. 7G , the high-concentration layer 21 may be connected to adjacent trench lower layers 19 and trench-side layers 20 in the X-axis direction. In other words, as shown in FIG. 7G , the high-concentration layer 21 may be formed in contact with only a portion of the trench-side layer 20 located closer to the other surface 10b than the gate trench 15, as compared to the configuration of FIG. 7D , so that the lower surface of the gate trench 15 is exposed from the high-concentration layer 21.

[0058] Third Embodiment A third embodiment will be described. This embodiment is different from the first embodiment in that the depth of the breakdown voltage trench 18 is changed. As the rest of the third embodiment is the same as the first embodiment, a description thereof will be omitted here.

[0059] 8 , in the semiconductor device of this embodiment, the bottom surface of the voltage trench 18 has the same depth as the bottom surface of the gate trench 15. In other words, the depth of the voltage trench 18 and the depth of the gate trench 15 are the same. However, the trench lower layer 19 is formed so as to face the bottom surface of the voltage trench 18, and is formed deeper than the gate trench 15. The trench lower layer 19 and the trench-side layer 20 are formed along the voltage trench 18, similar to the first embodiment.

[0060] Such a semiconductor device is manufactured by forming the gate trenches 15 and the voltage-resistant trenches 18 to the same depth.

[0061] According to the present embodiment described above, the high-concentration layer 21 is formed so as to be in contact with the p-type trench lower layer 19 and the trench-side layer 20, which are located deeper than the gate trench 15. Therefore, the same effects as those of the first embodiment can be obtained.

[0062] (1) In this embodiment, the bottom surface of the voltage-resistant trench 18 has the same depth as the bottom surface of the gate trench 15. This allows the voltage-resistant trench 18 and the gate trench 15 to be formed in the same process, thereby simplifying the manufacturing process.

[0063] (Modification of Third Embodiment) A modification of the third embodiment will be described. In the third embodiment, as shown in FIG. 9 , the high-concentration layer 21 has a configuration in which a first high-concentration layer 21a and a second high-concentration layer 21b are stacked in the Z-axis direction (i.e., the depth direction), similar to the modification of the first embodiment, and the n-type impurity concentrations of the first high-concentration layer 21a and the second high-concentration layer 21b may be different. In other words, the n-type impurity concentration of the high-concentration layer 21 does not have to be constant in the depth direction. Furthermore, although not particularly shown, the n-type impurity concentration of the high-concentration layer 21 does not have to be constant in the surface direction of the semiconductor substrate 10 (i.e., the X-axis direction and the Y-axis direction).

[0064] Furthermore, in the above third embodiment, if the trench lower layer 19 has a portion located closer to the other surface 10b than the gate trench 15, the lower surface of the voltage-resistant trench 18 may be located closer to the one surface 10a than the lower surface of the gate trench 15.

[0065] Fourth Embodiment A fourth embodiment will be described. This embodiment is different from the third embodiment in that the shape of the high-concentration layer 21 is changed. As the rest of the fourth embodiment is the same as the third embodiment, a description thereof will be omitted here.

[0066] 10 , in the semiconductor device of this embodiment, similarly to the second embodiment, the high-concentration layer 21 is formed along the breakdown voltage trenches 18. In other words, the high-concentration layer 21 is formed along the trench lower layer 19 and the trench-side layer 20. The high-concentration layer 21 has a divided portion covering each breakdown voltage trench 18. The lower surface of the gate trench 15 is exposed from the high-concentration layer 21, and the exposed portion is in contact with the drift layer 12.

[0067] According to the present embodiment described above, the high-concentration layer 21 is formed so as to be in contact with the p-type trench lower layer 19 and the trench-side layer 20, which are located deeper than the gate trench 15. Therefore, the same effects as those of the first embodiment can be obtained.

[0068] (1) In this embodiment, the gate trench 15 is exposed from the high-concentration layer 21. That is, compared to the third embodiment, the area where the high-concentration layer 21 is formed is reduced. This makes it easier to prevent the DS breakdown voltage from decreasing.

[0069] (Modification of Fourth Embodiment) A modification of the fourth embodiment will be described. In the fourth embodiment, the shape of the high-concentration layer 21 may be changed as in the modification of the second embodiment. That is, as shown in FIG. 11A , the high-concentration layer 21 may be formed so as to contact only the trench-side layer 20, and not so as to contact the trench lower layer 19. In this case, the high-concentration layer 21 may be formed so as to contact only a portion of the trench-side layer 20 located on the other surface 10b side of the gate trench 15, as shown in FIG. 11B . Alternatively, the high-concentration layer 21 may be formed so as to contact only a portion of the trench-side layer 20 located on the other surface 10b side of the gate trench 15, as shown in FIG. 11C . Furthermore, as shown in FIG. 11D , unlike the fourth embodiment, the high-concentration layer 21 may not have a portion in contact with the trench lower layer 19. 11E , the high-concentration layer 21 may be formed in contact with only a portion of the trench-side layer 20 located on the other surface 10b side of the gate trench 15, as compared to the configuration of FIG. 11D , so that the lower surface of the gate trench 15 is exposed from the high-concentration layer 21. Alternatively, as shown in FIG. 11F , the high-concentration layer 21 may be formed in contact with a portion of the trench-side layer 20 located below the gate trench 15 and in contact with the trench lower layer 19, so that the lower surface of the gate trench 15 is exposed from the high-concentration layer 21. In this case, as shown in FIG. 11G , the high-concentration layer 21 may be connected to the trench lower layer 19 and the trench-side layer 20 adjacent to each other in the X-axis direction. In other words, as shown in FIG. 11G , the high-concentration layer 21 may be formed in contact with only a portion of the trench-side layer 20 located on the other surface 10b side of the gate trench 15, as compared to the configuration of FIG. 11D , so that the lower surface of the gate trench 15 is exposed from the high-concentration layer 21.

[0070] Fifth Embodiment A fifth embodiment will be described. In this embodiment, the source region 14 is disposed only on one side of the gate trench 15, as compared to the first embodiment. As the rest of the configuration is the same as the first embodiment, a description thereof will be omitted here.

[0071] 12 , in the semiconductor device of this embodiment, a drift layer 12 is formed on a substrate 11, and a body layer 13 is formed on the drift layer 12. A source region 14 is formed in a surface layer portion of the body layer 13.

[0072] Gate trenches 15 are formed in the semiconductor substrate 10, penetrating from one surface 10a through the source region 14 and the body layer 13. As in the first embodiment, a plurality of gate trenches 15 are provided extending longitudinally in the Y-axis direction and are arranged at equal intervals in the X-axis direction to form a stripe pattern. In this embodiment, no breakdown voltage trenches 18 are formed in the semiconductor substrate 10. The source region 14 and the body layer 13 are formed to contact only one of the opposing side surfaces of the gate trench 15.

[0073] In addition, the semiconductor substrate 10 has a p-type silicon nitride film formed in contact with the other side surface of the gate trench 15 and deeper than the gate trench 15. ＋ 12, the source region 14 and the body layer 13 are formed so as to contact the side surface of the gate trench 15 on the left side of the page, and the breakdown voltage improving layer 30 is formed so as to contact the side surface of the gate trench 15 on the right side of the page.

[0074] An n-type high-concentration layer 21 having a higher impurity concentration than the drift layer 12 is formed in the semiconductor substrate 10 so as to contact the end of the lower surface of the breakdown voltage improvement layer 30 opposite the gate trench 15 with which the breakdown voltage improvement layer 30 is in contact. In this embodiment, the high-concentration layer 21 is formed so as to contact the lower surface of the body layer 13 and cover the portions of the breakdown voltage improvement layer 30 and the gate trench 15 that protrude from the body layer 13 toward the other surface 10b. The high-concentration layer 21 is also formed so that its lower surface is approximately parallel to the other surface 10b. In other words, the portion of the high-concentration layer 21 on the substrate 11 side is parallel to the surface direction of the substrate 11. Note that the high-concentration layer 21 has a higher impurity concentration than the drift layer 12, but the n-type impurity concentration is preferably equal to or less than half the p-type impurity concentration of the breakdown voltage improvement layer 30. The breakdown voltage improvement layer 30 has a p-type impurity concentration of, for example, 2.0×10 １７ ~5.0 x 10 １８ / cm ３ It is said to be about that level.

[0075] As in the first embodiment, an interlayer insulating film 22 is disposed on the one surface 10a of the semiconductor substrate 10 so as to cover the gate electrode 17. In addition, a contact hole 22b is formed in the interlayer insulating film 22 to expose the source region 14 and the breakdown voltage improving layer 30.

[0076] An upper electrode 23 is disposed on the interlayer insulating film 22. Specifically, the upper electrode 23 is formed so as to be electrically connected to the source region 14 and the breakdown voltage improving layer 30 through a contact hole 22b formed in the interlayer insulating film 22. The body layer 13 is electrically connected to the upper electrode 23 via the breakdown voltage improving layer 30.

[0077] The upper electrode 23 of this embodiment is made of a plurality of metals, such as Ni / Al. The portion of the plurality of metals that contacts the portion that constitutes the n-type SiC (i.e., the source region 14) is made of a metal that can make ohmic contact with the n-type SiC. Furthermore, the portion of the plurality of metals that contacts at least the p-type SiC (i.e., the breakdown voltage improving layer 30) is made of a metal that can make ohmic contact with the p-type SiC.

[0078] A lower electrode 24 electrically connected to the substrate 11 is formed on the other surface 10b of the semiconductor substrate 10. In this embodiment, the lower electrode 24 corresponds to the second electrode.

[0079] The above is the configuration of the semiconductor device in this embodiment. In this embodiment, n-type corresponds to the first conductivity type, and p-type corresponds to the second conductivity type. As in the first embodiment, the semiconductor device has an active region Ra and a peripheral region Rb surrounding the active region Ra. The high-concentration layer 21 in this embodiment is formed only in the active region Ra. Next, the operation and effects of the semiconductor device will be described.

[0080] In the semiconductor device of this embodiment, the breakdown voltage improving layer 30 is formed at a position deeper than the gate trench 15, and therefore in the off state, a depletion layer formed between the p-type breakdown voltage improving layer 30 and the n-type high concentration layer 21 suppresses the rise of equipotential lines due to the influence of the drain voltage, making it difficult for a high electric field to penetrate into the gate insulating film 16. Therefore, in this embodiment, it is possible to suppress breakdown of the gate insulating film 16 and improve the DS breakdown voltage between the drain and the source.

[0081] Furthermore, when a gate voltage equal to or greater than the threshold voltage is applied to the gate electrode 17 to turn it on, an inversion layer (i.e., a channel) is formed on the surface of the body layer 13 that contacts the gate trench 15, and electrons flow from the source region 14 to the substrate 11 via the inversion layer, the high-concentration layer 21, and the drift layer 12. At this time, if the depletion layer caused by the breakdown voltage improving layer 30 extends too far at a position closer to the other surface 10b than the gate trench 15, the current path narrows and the on-resistance increases. In particular, if the depletion layer extends in the portion of the lower surface of the breakdown voltage improving layer 30 opposite the gate trench 15, the current path is likely to narrow. For this reason, in this embodiment, the high-concentration layer 21 is formed so as to contact the portion of the lower surface of the breakdown voltage improving layer 30 opposite the gate trench 15 with which the breakdown voltage improving layer 30 contacts. Therefore, the depletion layer can be prevented from extending in the portion that serves as the current path, and the on-resistance can be prevented from increasing.

[0082] Such a semiconductor device is manufactured, for example, as follows. First, an epitaxial layer constituting the drift layer 12 and the like is grown on the substrate 11 to form the semiconductor substrate 10. Next, n-type impurities are ion-implanted to form the high-concentration layer 21. The high-concentration layer 21 is formed from the surface 10a of the semiconductor substrate 10 to a deep position by, for example, ion-implanting n-type impurities while changing the acceleration voltage. At this time, the maximum acceleration voltage is set to about 2500 KeV. The high-concentration layer 21 may be formed by increasing the impurity concentration of the portion that will become the high-concentration layer 21 when growing the epitaxial layer. In other words, the ion-implantation to form the high-concentration layer 21 may be omitted. Next, the body layer 13, the source region 14, the breakdown voltage improvement layer 30, and the like are formed, and then the gate trench 15 is formed, and the gate insulating film 16, the gate electrode 17, and the like are formed in this order. Thereafter, the upper electrode 23 and the lower electrode 24 are fabricated, thereby manufacturing the semiconductor device.

[0083] According to the embodiment described above, the n-type high-concentration layer 21 is disposed on the underside of the p-type breakdown voltage improving layer 30, which is disposed at a position deeper than the gate trench 15, so as to contact the portion of the p-type breakdown voltage improving layer 30 on the opposite side of the gate trench 15 with which the breakdown voltage improving layer 30 is in contact. Therefore, in the on-state, excessive extension of the depletion layer caused by the breakdown voltage improving layer 30 can be suppressed, and the on-resistance can be reduced. Furthermore, in recent years, miniaturization has been achieved by narrowing the spacing between adjacent gate trenches 15 in the X-axis direction. However, the semiconductor device of this embodiment can adequately accommodate miniaturization because the extension of the depletion layer caused by the breakdown voltage improving layer 30 is suppressed.

[0084] (1) In this embodiment, the high-concentration layer 21 is formed so as to contact the lower surface of the body layer 13 and cover the portion of the gate trench 15 that protrudes from the body layer 13 and the breakdown voltage improvement layer 30. Such a high-concentration layer 21 is formed by ion-implanting n-type impurities throughout the entire structure or by adjusting the n-type impurity concentration during epitaxial layer growth. This simplifies the manufacturing process compared to when the high-concentration layer 21 is selectively formed. Furthermore, because the lower surface of the gate trench 15 is also in contact with the high-concentration layer 21, extension of a depletion layer from the breakdown voltage improvement layer 30 downward into the gate trench 15 can be suppressed, allowing this portion to also serve as a current path. This allows for an expansion of the channel width and a reduction in on-resistance.

[0085] (2) In this embodiment, the portion of the high-concentration layer 21 on the substrate 11 side (i.e., the portion on the other surface 10b side) is parallel to the surface direction of the substrate 11. This makes it easier for the depletion layer to spread evenly toward the substrate 11 side when the device is off, thereby improving the breakdown voltage.

[0086] (3) In this embodiment, the high-concentration layer 21 is formed only in the active region Ra. This makes it easier to prevent the equipotential lines from rising due to the influence of the drain voltage from the peripheral region Rb. This makes it possible to prevent a decrease in the DS breakdown voltage.

[0087] (4) In this embodiment, the n-type impurity concentration of the high-concentration layer 21 is set to be equal to or less than half the p-type impurity concentration of the breakdown voltage improving layer 30. This makes it possible to prevent the DS breakdown voltage from decreasing significantly.

[0088] (5) In this embodiment, the gate trench 15 is formed after the high-concentration layer 21, the breakdown voltage improving layer 30, etc. are formed. Therefore, compared to the case where the high-concentration layer 21 is formed after the gate trench 15 is formed, alignment is easier and the manufacturing process can be simplified.

[0089] (Modification of Fifth Embodiment) A modification of the fifth embodiment will be described. In the fifth embodiment, the detailed shape of the body layer 13 can be modified as appropriate as long as it is electrically connected to the upper electrode 23. For example, the body layer 13 may be formed so as to be exposed from the one surface 10a of the semiconductor substrate 10 together with the source region 14, and may be electrically connected to the upper electrode 23 on the one surface 10a side.

[0090] 13A , the high-concentration layer 21 may be configured by stacking a first high-concentration layer 21a and a second high-concentration layer 21b in the Z-axis direction (i.e., the depth direction), and the n-type impurity concentrations of the first high-concentration layer 21a and the second high-concentration layer 21b may be different. That is, the n-type impurity concentration of the high-concentration layer 21 may not be constant in the depth direction. Furthermore, although not specifically shown, the n-type impurity concentration of the high-concentration layer 21 may not be constant in the surface direction of the semiconductor substrate 10 (i.e., the X-axis direction and the Y-axis direction). Even when the n-type impurity concentration is partially different, the highest n-type impurity concentration of the high-concentration layer 21 is preferably equal to or less than half the p-type impurity concentration of the breakdown voltage improvement layer 30.

[0091] Furthermore, the high concentration layer 21 may be formed so as to expose the lower surface of the gate trench 15, as shown in FIG. 13B.

[0092] Furthermore, in the fifth embodiment, the n-type impurity concentration of the high-concentration layer 21 may be set to be higher than half the p-type impurity concentration of the breakdown voltage improving layer 30. With such a semiconductor device, the on-resistance can also be reduced.

[0093] Sixth Embodiment A sixth embodiment will be described. This embodiment is different from the fifth embodiment in that the shape of the high-concentration layer 21 is changed. As the other features are the same as those of the fifth embodiment, a description thereof will be omitted here.

[0094] 14 , in the semiconductor device of this embodiment, the high-concentration layer 21 is formed along the breakdown voltage improving layer 30. The high-concentration layer 21 has divided portions covering the respective breakdown voltage improving layers 30. The lower surface of the gate trench 15 is exposed from the high-concentration layer 21 on the side opposite to the breakdown voltage improving layer 30 side that is in contact with the gate trench 15, and the exposed portion is in contact with the drift layer 12.

[0095] Such a high-concentration layer 21 is manufactured by growing an epitaxial layer that constitutes the drift layer 12, etc. on the substrate 11 to form the semiconductor substrate 10, and then performing ion implantation using a mask to form the high-concentration layer 21.

[0096] According to the present embodiment described above, the high-concentration layer 21 is disposed on the lower surface of the breakdown voltage improving layer 30, which is disposed at a position deeper than the gate trench 15, so as to be in contact with the portion opposite to the gate trench 15 that is in contact with the breakdown voltage improving layer 30. Therefore, the same effects as those of the fifth embodiment can be obtained.

[0097] (1) In this embodiment, the gate trench 15 is exposed from the high-concentration layer 21. That is, compared to the fifth embodiment, the area where the high-concentration layer 21 is formed is reduced. This makes it easier to prevent the DS breakdown voltage from decreasing.

[0098] (Modification of the Sixth Embodiment) A modification of the sixth embodiment will be described. In the sixth embodiment, as in the fifth embodiment, the n-type impurity concentration of the high-concentration layer 21 may be varied in different portions. In the semiconductor device of this embodiment, between two gate trenches 15 adjacent to each other in the X-axis direction, the source region 14 and the body layer 13 are disposed so as to contact one of the gate trenches 15, and the breakdown voltage improving layer 30 is disposed so as to contact the other gate trench 15. When the semiconductor device is in an on-state, a current flows from the source region 14 that contacts one of the gate trenches 15 between the two gate trenches 15 adjacent to each other in the X-axis direction. Therefore, if a depletion layer extends from the other gate trench 15 to the one gate trench 15 between two gate trenches 15 adjacent to each other in the X-axis direction, the current path narrows, which tends to increase the on-resistance. Therefore, when the n-type impurity concentration of the high-concentration layer 21 is varied in different portions, the high-concentration layer 21 is preferably configured as follows. That is, the high-concentration layer 21 preferably has a higher concentration in a portion of the voltage-resistance improving layer 30 that contacts the portion of the voltage-resistance improving layer 30 opposite the gate trench 15 with which the voltage-resistance improving layer 30 contacts than in a portion of the voltage-resistance improving layer 30 that contacts the lower surface of the voltage-resistance improving layer 30 and the portion of the voltage-resistance improving layer 30 that contacts the gate trench 15. Adjusting the n-type impurity concentration of the high-concentration layer 21 in this manner makes it difficult for a depletion layer to extend to the gate trench 15 side located opposite the gate trench 15 with which the voltage-resistance improving layer 30 contacts, thereby further reducing the narrowing of the current path and the increase in on-resistance. Adjusting the n-type impurity concentration of the high-concentration layer 21 in this manner also makes it difficult for a high electric field to penetrate the gate insulating film 16, thereby reducing the reduction in the DS breakdown voltage. Note that when the n-type impurity concentrations of the high-concentration layer 21 are varied in the fifth embodiment, the same effect can be achieved by maintaining the relationship between the n-type impurity concentrations of the high-concentration layer 21 as described above.

[0099] Seventh Embodiment A seventh embodiment will be described. This embodiment is different from the fifth embodiment in that the shape of the high-concentration layer 21 is changed. As the rest of the configuration is the same as the fifth embodiment, a description thereof will be omitted here.

[0100] 15 , in the semiconductor device of this embodiment, the high-concentration layer 21 is a portion of the voltage-resistance improving layer 30 that is located closer to the other surface 10b than the gate trench 15, and is arranged so as to be in contact with a portion of the voltage-resistance improving layer 30 on the opposite side of the gate trench 15 with which the voltage-resistance improving layer 30 is in contact. However, the high-concentration layer 21 is formed so as not to be in contact with the bottom surface of the voltage-resistance improving layer 30 and the portion of the voltage-resistance improving layer 30 on the gate trench 15 side with which the voltage-resistance improving layer 30 is in contact. In other words, the bottom surface of the voltage-resistance improving layer 30 and the portion of the voltage-resistance improving layer 30 on the gate trench 15 side with which the voltage-resistance improving layer 30 is in contact with the drift layer 12.

[0101] According to the present embodiment described above, the high-concentration layer 21, which has a higher impurity concentration than the drift layer 12, is arranged so as to be in contact with the portion of the breakdown voltage improving layer 30 that is located closer to the other surface 10b than the gate trench 15. Therefore, in the on-state, it is possible to prevent the depletion layer caused by the breakdown voltage improving layer 30 from extending too much, and it is possible to reduce the on-resistance.

[0102] (1) In this embodiment, the high-concentration layer 21 is disposed so as to be in contact with a portion of the voltage-resistant improving layer 30 that is located closer to the other surface 10b than the gate trench 15 and that is located on the opposite side of the gate trench 15 that is in contact with the voltage-resistant improving layer 30. This makes it easier to prevent a depletion layer from extending from the gate trench 15 side that is in contact with the voltage-resistant improving layer 30 to the gate trench 15 side that is in contact with the source region 14 between two gate trenches 15 that are adjacent in the X-axis direction, making it easier to reduce the on-resistance.

[0103] (Modification of Seventh Embodiment) A modification of the seventh embodiment will be described. In the seventh embodiment, as shown in FIG. 16A , the high-concentration layer 21 may be formed so as to contact only a portion of the breakdown voltage improving layer 30 on the side opposite the gate trench 15 with which the breakdown voltage improving layer 30 is in contact, that is, a portion located closer to the other surface 10b than the gate trench 15. Alternatively, as shown in FIG. 16B , the high-concentration layer 21 may be formed so as to contact only a portion of the breakdown voltage improving layer 30 on the side of the gate trench 15 with which the breakdown voltage improving layer 30 is in contact. In other words, the high-concentration layer 21 may be formed so that the lower surface and a portion of the breakdown voltage improving layer 30 on the side opposite the gate trench 15 with which the breakdown voltage improving layer 30 is in contact with the drift layer 12.

[0104] 16C , the high-concentration layer 21 may be formed so that the lower surface of the breakdown voltage improving layer 30 is in contact with the drift layer 12, and so that the high-concentration layer 21 is in contact only with the portion of the breakdown voltage improving layer 30 opposite the gate trench 15 and the portion of the breakdown voltage improving layer 30 on the gate trench 15 side. In this case, the high-concentration layer 21 may be arranged so as to connect between adjacent breakdown voltage improving layers 30 in the X-axis direction, as shown in FIG. 16D . In other words, compared to the fifth embodiment, the high-concentration layer 21 may be formed so that the lower surface of the breakdown voltage improving layer 30 is exposed. In this configuration, the high-concentration layer 21 may be formed away from the lower surface of the body layer 13 and the lower surface of the gate trench 15, as shown in FIG. 16E .

[0105] (Other Embodiments) While the present disclosure has been described with reference to the embodiments, it is understood that the present disclosure is not limited to the embodiments or structures. The present disclosure also encompasses various modifications and modifications within the scope of equivalents. In addition, various combinations and forms, as well as other combinations and forms including only one element, more than one element, or less than one element, are also within the scope and spirit of the present disclosure.

[0106] For example, in each of the above embodiments, a semiconductor device has been described in which an n-channel MOSFET is formed, with the first conductivity type being n-type and the second conductivity type being p-type. However, the semiconductor device may also have a p-channel MOSFET formed in which the conductivity types of each component are inverted relative to the n-channel type. Furthermore, the semiconductor device may also have a configuration in which an IGBT having a similar structure is formed in addition to the MOSFET. In the case of an IGBT, the n-channel MOSFET in each of the above embodiments may have a p-channel MOSFET formed in which the conductivity types of each component are inverted relative to the n-channel type. ＋ The substrate 11 is ＋ Except for the change to the substrate 11, the MOSFET is the same as that described in each of the above embodiments.

[0107] In each of the above embodiments, the high-concentration layer 21 may also be formed in the outer periphery region Rb.

[0108] [Disclosure of the Present Invention] The above-described disclosure can be understood from the following aspects, for example. [First Aspect] A semiconductor device comprising: a first impurity region (11) of a first conductivity type or a second conductivity type; a drift layer (12) of the first conductivity type arranged on the first impurity region and having a lower impurity concentration than the first impurity region; a body layer (13) of a second conductivity type formed on the drift layer; a second impurity region (14) of the first conductivity type formed in a surface layer portion of the body layer; a gate trench (15) penetrating the second impurity region and the body layer; a gate insulating film (16) formed on an inner wall surface of the gate trench; a gate electrode (17) formed on the gate insulating film; a voltage-resistant trench (18) that is a trench different from the gate trench and penetrates the body layer; and a second conductivity-type voltage-resistant improvement layer (19, 20) formed along the voltage-resistant trench and having a portion located closer to the first impurity region than a bottom surface of the gate trench. a semiconductor device comprising: a first electrode (23) electrically connected to the second impurity region, the body layer, and the voltage improvement layer; and a second electrode (24) electrically connected to the first impurity region, and a first conductivity type high-concentration layer (21) in contact with the voltage improvement layer on a side closer to the first impurity region than a bottom surface of the gate trench, the high-concentration layer having a higher impurity concentration than the drift layer. [Second Aspect] The semiconductor device according to the first aspect, wherein the voltage improvement layer includes a trench lower layer (19) arranged opposite to a bottom surface of the voltage trench. [Third Aspect] The semiconductor device according to the first or second aspect, wherein a bottom surface of the voltage trench is deeper than a bottom surface of the gate trench. [Fourth Aspect] The semiconductor device according to any one of the first to third aspects, wherein the high-concentration layer is in contact with a bottom surface of the body layer and is formed to cover a portion of the gate trench protruding from the body layer and the voltage improvement layer. Fifth Aspect The semiconductor device according to any one of the first to fourth aspects, wherein the high concentration layer is formed so that the gate trench is in contact with the drift layer.[Sixth Aspect] The semiconductor device according to any one of the first to fifth aspects, wherein the high-concentration layer has a first conductivity type impurity concentration that is equal to or less than half of the second conductivity type impurity concentration in the breakdown voltage improvement layer. [Seventh Aspect] The semiconductor device according to any one of the first to sixth aspects, wherein the semiconductor device has an active region (Ra) in which the gate trench is disposed and through which a current flows by controlling a voltage applied to the gate electrode, and an outer periphery region (Rb) surrounding the active region, and the high-concentration layer is formed only in the active region. a first impurity region (11) of a first conductivity type or a second conductivity type; a drift layer (12) of the first conductivity type disposed on the first impurity region and having a lower impurity concentration than the first impurity region; a body layer (13) of a second conductivity type formed on the drift layer; a second impurity region (14) of the first conductivity type formed in a surface layer portion of the body layer; a gate trench (15) penetrating the second impurity region and the body layer; a gate insulating film (16) formed on an inner wall surface of the gate trench; a gate electrode (17) formed on the gate insulating film; a voltage-resistant trench (18) that is a trench different from the gate trench and penetrates the body layer; and a voltage-resistant improvement layer (19, 20) of a second conductivity type formed along the voltage-resistant trench and having a portion located closer to the first impurity region than a bottom surface of the gate trench. a first electrode (23) electrically connected to the second impurity region, the body layer, and the voltage improvement layer; and a second electrode (24) electrically connected to the first impurity region, and a first conductivity type high concentration layer (21) in contact with the voltage improvement layer on a side closer to the first impurity region than a lower surface of the gate trench, the high concentration layer having a higher impurity concentration than the drift layer, the method comprising: preparing a semiconductor substrate (10) on which an epitaxial layer is grown on the first impurity region; forming the high concentration layer in the semiconductor substrate; and, after forming the high concentration layer, forming the gate trench and the voltage improvement trench.

Claims

1. A semiconductor device comprising: a first impurity region (11) of a first conductivity type or a second conductivity type; a drift layer (12) of the first conductivity type disposed on the first impurity region and having a lower impurity concentration than the first impurity region; a body layer (13) of a second conductivity type formed on the drift layer; a second impurity region (14) of the first conductivity type formed in a surface layer portion of the body layer; a gate trench (15) penetrating the second impurity region and the body layer; a gate insulating film (16) formed on an inner wall surface of the gate trench; a gate electrode (17) formed on the gate insulating film; a voltage-resistant trench (18) that is a trench different from the gate trench and penetrates the body layer; and a second conductivity-type voltage-resistant improvement layer (19, 20) formed along the voltage-resistant trench and having a portion located closer to the first impurity region than a bottom surface of the gate trench. a first electrode (23) electrically connected to the second impurity region, the body layer, and the breakdown voltage improvement layer; and a second electrode (24) electrically connected to the first impurity region, wherein the semiconductor device has a first conductivity type high concentration layer (21) that is in contact with the breakdown voltage improvement layer on a side closer to the first impurity region than a bottom surface of the gate trench, and has an impurity concentration higher than that of the drift layer.

2. The semiconductor device according to claim 1, wherein the breakdown voltage improving layer includes a trench lower layer (19) disposed opposite to the lower surface of the breakdown voltage trench.

3. The semiconductor device according to claim 1, wherein the bottom surface of the voltage-resistant trench is deeper than the bottom surface of the gate trench.

4. The semiconductor device according to claim 1, wherein the high-concentration layer is formed so as to contact the lower surface of the body layer and to cover the portion of the gate trench protruding from the body layer and the breakdown voltage improving layer.

5. The semiconductor device according to claim 1, wherein the high concentration layer is formed so that the gate trench is in contact with the drift layer.

6. The semiconductor device according to claim 1, wherein the high concentration layer has a first conductivity type impurity concentration that is equal to or less than half the second conductivity type impurity concentration in the breakdown voltage improving layer.

7. A semiconductor device according to any one of claims 1 to 6, comprising an active region (Ra) in which the gate trench is disposed and through which current flows by controlling the voltage applied to the gate electrode, and an outer peripheral region (Rb) surrounding the active region, wherein the high concentration layer is formed only in the active region.

8. A first impurity region (11) of a first conductivity type or a second conductivity type; a drift layer (12) of the first conductivity type disposed on the first impurity region and having a lower impurity concentration than the first impurity region; a body layer (13) of a second conductivity type formed on the drift layer; a second impurity region (14) of the first conductivity type formed in a surface layer portion of the body layer; a gate trench (15) penetrating the second impurity region and the body layer; a gate insulating film (16) formed on an inner wall surface of the gate trench; a gate electrode (17) formed on the gate insulating film; a voltage-resistant trench (18) which is a trench different from the gate trench and penetrates the body layer; a voltage-resistant improvement layer (19, 20) of a second conductivity type formed along the voltage-resistant trench and having a portion located closer to the first impurity region than a bottom surface of the gate trench; and a first electrode (23) electrically connected to the second impurity region, the body layer, and the voltage-resistant improvement layer. a second electrode (24) electrically connected to the first impurity region, and a high-concentration layer of a first conductivity type in contact with the voltage-resistant improvement layer on a side closer to the first impurity region than a bottom surface of the gate trench, the high-concentration layer having a higher impurity concentration than the drift layer, the method comprising: preparing a semiconductor substrate (10) on which an epitaxial layer is grown on the first impurity region; forming the high-concentration layer in the semiconductor substrate; and, after forming the high-concentration layer, forming the gate trench and the voltage-resistant trench.

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