Memory system and operation method and system therefor, and storage medium

Abstract

Embodiments of the present disclosure provide a memory system and an operation method and system therefor, and a storage medium. The memory system comprises a memory and a memory controller coupled to the memory; the memory controller is configured to control the memory to perform partitioned storage on the basis of regions, wherein the storage space of a single region is configured to support sequential writing; the memory controller is configured with a first interface that is used for being coupled to a system unit, and receives a first command from the system unit by means of the first interface, wherein the first command comprises the identifier of a specified region and mode switching information of the specified region; the memory controller is further configured to switch, on the basis of the mode switching information, a storage mode of the specified region to a target storage mode indicated by the mode switching information.

Description

Memory system and operating method, system and storage medium thereof TECHNICAL FIELD

[0001] Embodiments of the present disclosure relate to the technical field of semiconductor technology, and particularly relate to a memory system and an operating method, system and storage medium thereof. BACKGROUND

[0002] Memory and its system are storage devices used for saving information in modern information technology. With the increasing demand for storage devices, there is much room for improvement in memory and its system.

[0003] SUMMARY

[0004] Embodiments of the present disclosure provide a memory system and an operating method, system and storage medium thereof.

[0005] In a first aspect, embodiments of the present disclosure provide a memory system, comprising: a memory and a memory controller coupled with the memory, the memory controller being configured to control the memory to store data in a partitioned manner by region, wherein a storage space of a single region is configured to support sequential writing; wherein the memory controller is configured with a first interface for coupling with a host, and receives a first command from the host through the first interface, the first command comprising identification of a specified region and mode switching information of the specified region; the memory controller is further configured to switch a storage mode of the specified region to a target storage mode indicated in the mode switching information according to the mode switching information.

[0006] In the above scheme, the memory controller is configured to: determine a current storage mode of the specified region, and in a case where the current storage mode is different from the target storage mode indicated in the mode switching information, switch the current storage mode to the target storage mode according to the mode switching information.

[0007] In the above scheme, the storage mode comprises a first storage mode and a second storage mode; when the region is in the first storage mode, each of the storage units corresponding to the storage space of the region can be written with N-bit data; when the region is in the second storage mode, each of the storage units corresponding to the storage space of the region can be written with M-bit data, M and N are integers greater than or equal to 1, and M is greater than N.

[0008] In the above scheme, the memory controller is configured to: determine the specified region according to the identification of the specified region; switch the specified region from the first storage mode to the second storage mode according to the mode switching information; or switch the specified region from the second storage mode to the first storage mode according to the mode switching information.

[0009] In the above scheme, the memory controller is further configured to receive a region write request and write data through the first interface, and if the write data is hot data, the region write request is used to instruct to write the write data to a region with a first storage mode, and if the write data is non-hot data, the region write request is used to instruct to write the write data to a region with a second storage mode; and write the write data into the storage space of the corresponding region according to the region write request.

[0010] In the above scheme, the memory controller is configured to reset the state of the specified region to the empty state according to the first command.

[0011] In the above scheme, the first command includes a reset write pointer command, and the mode switching information occupies two bit fields in the reset write pointer command.

[0012] In the above scheme, the region is a region in a zone namespace (ZNS).

[0013] In the above scheme, the memory controller is further configured to receive a second command through the first interface, the second command includes mode recovery information, the mode recovery information is used to indicate whether the storage mode information needs to be returned, and generate report region parameter data meeting the indication of the mode recovery information according to the second command.

[0014] In the above scheme, the memory controller is configured to generate report region parameter data including storage mode information according to the second command in the case that the mode recovery information indicates that the storage mode information needs to be returned.

[0015] In the above scheme, the storage mode information is located in a region descriptor in the report region parameter data.

[0016] In the above scheme, the storage mode information occupies four bit fields in the region descriptor.

[0017] In the above scheme, the report region parameter data includes a region descriptor list and a common descriptor; the region descriptor list includes at least one region descriptor, and the region descriptor is used to indicate the self attribute of the corresponding region, and the common descriptor is used to indicate the common attribute of multiple regions.

[0018] In the above scheme, the region descriptor further includes a region type field, a region state field, a region length field, a region start logical block address field, and a write pointer logical block address field.

[0019] In the above scheme, the common descriptor includes a region list length field, a same field, and a maximum logical block address field.

[0020] In the above scheme, the second command includes a report region command.

[0021] In a second aspect, the embodiments of the present disclosure provide a system, comprising a memory system and a host, the memory system comprising: a memory and a memory controller coupled with the memory, the memory controller being configured to control the memory to store data in regions, wherein a storage space of a single region is configured to support sequential writing; wherein the memory controller is configured with a first interface for coupling with the host, and receives a first command from the host through the first interface, the first command comprising an identification of a specified region and mode switching information of the specified region; the host comprising a host controller and a second interface for coupling with the memory controller, the host controller being configured to generate the first command and send the first command to the memory controller through the second interface.

[0022] In the above solution, the memory controller is further configured to switch the storage mode of the specified region to a target storage mode indicated in the mode switching information according to the mode switching information.

[0023] In the above solution, the memory controller is configured to determine a current storage mode of the specified region, and in a case where the current storage mode is different from a target storage mode indicated in the mode switching information, switch the current storage mode to the target storage mode according to the mode switching information.

[0024] In the above solution, the storage mode comprises a first storage mode and a second storage mode; when the region is in the first storage mode, each of the storage units corresponding to the storage space of the region can be written with N-bit data; when the region is in the second storage mode, each of the storage units corresponding to the storage space of the region can be written with M-bit data, M and N are integers greater than or equal to 1, and M is greater than N.

[0025] In the above solution, the memory controller is configured to determine the specified region according to the identification of the specified region; switch the specified region from the first storage mode to the second storage mode according to the mode switching information; or switch the specified region from the second storage mode to the first storage mode according to the mode switching information.

[0026] In the above solution, the host is configured with a file system; the host controller is configured to determine a cold and hot attribute of the write data through the file system, generate a corresponding region write request according to the cold and hot attribute of the write data, and send the write data and the region write request to the memory controller through the second interface; if the write data is hot data, the region write request is used to instruct to write the write data to a region with the first storage mode; if the write data is non-hot data, the region write request is used to instruct to write the write data to a region with the second storage mode; and the memory controller is configured to write the write data into the storage space of the corresponding region according to the region write request.

[0027] In the scheme, the host controller is configured to send the second command to the memory controller through the second interface, the second command comprising mode reply information, the mode reply information being used to indicate whether the storage mode information needs to be returned; the memory controller is configured to receive the second command through the first interface, and generate and send the report area parameter data meeting the indication of the mode reply information to the host controller according to the second command.

[0028] In the scheme, the memory controller is configured to, when the mode reply information is used to indicate the case where the storage mode information needs to be returned, generate and send the report area parameter data comprising the storage mode information to the host controller according to the second command.

[0029] In the scheme, the storage mode information is located in the area descriptor in the report area parameter data.

[0030] In the scheme, the report area parameter data comprises an area descriptor list and a common descriptor; the area descriptor list comprises at least one area descriptor, the area descriptor being used to indicate the self attribute of the corresponding area, and the common descriptor being used to indicate the common attribute of multiple areas.

[0031] In the scheme, the area descriptor further comprises an area type field, an area state field, an area length field, an area start logical block address field, and a write pointer logical block address field.

[0032] In the scheme, the common descriptor comprises an area list length field, a SAME field, and a maximum logical block address field.

[0033] In the scheme, the host is configured with a file system; the host processor is configured to: establish a target area data structure through the file system, the target area data structure being used to store the information of the target area, the target area being an area with the first storage mode; obtain the information of the target area according to the report area parameter data comprising the storage mode information; and store the information of the target area to the target area data structure.

[0034] In the scheme, the target area data structure is used to store the number of target areas, a target area linked list list, and the identifier of the currently used target area; the area linked list list comprises at least one area linked list, and the target area linked list comprises the identifier of the target area, the state of the target area, and the linked list pointer of the next target area linked list.

[0035] In the scheme, the host processor is configured to: send the first command to the memory controller through the second interface in a preset scenario; the preset scenario comprises at least one of the following: a file system initialization stage, a case where the information of the target area is not obtained through the second command, and a case where the state of the currently used target area in the target area data structure is a full state.

[0036] In the above solution, the host processor is configured to: acquire a remaining space of the memory in a case that a state of a target area currently used in the target area data structure is a full state; and send a first command to the memory controller according to a maximum continuous space in the remaining space satisfying a preset condition.

[0037] In the above solution, the information of the target area includes an identifier of the target area, a state of the target area, and an identifier of the target area currently used.

[0038] In the above solution, the file system includes a flash friendly file system (F2FS).

[0039] In the above solution, the first command includes a reset write pointer command, and the mode switching information occupies two bit fields in the reset write pointer command.

[0040] In the above solution, the memory controller is configured to reset the state of the specified area to an empty state according to the first command.

[0041] In the above solution, the second command includes a report area command.

[0042] In the above solution, the storage mode information occupies four bit fields in the area descriptor.

[0043] In the above solution, the area is an area in a zone namespace (ZNS).

[0044] In a third aspect, an operation method of a memory system is provided, the memory system including a memory and a memory controller coupled with the memory, the memory controller being configured with a first interface for coupling with a host, the method including: receiving a first command through the first interface; wherein the first command includes an identifier of a specified area and mode switching information of the specified area, the area corresponding to a storage space of the memory, and a storage space of a single area being configured to support sequential writing; and switching, by the memory controller, a storage mode of the specified area to a target storage mode indicated in the mode switching information according to the mode switching information.

[0045] In the above solution, the switching of the storage mode of the specified area to the target storage mode indicated in the mode switching information according to the mode switching information includes: determining a current storage mode of the specified area, and switching, in a case that the current storage mode is different from the target storage mode indicated in the mode switching information, the current storage mode to the target storage mode according to the mode switching information.

[0046] The storage mode includes a first storage mode and a second storage mode; when the region is in the first storage mode, each of the storage units corresponding to the storage space of the region can be written with N-bit data; when the region is in the second storage mode, each of the storage units corresponding to the storage space of the region can be written with M-bit data, M and N are integers greater than or equal to 1, and M is greater than N.

[0047] The mode switching information is used to switch the storage mode of the specified region to a target storage mode indicated in the mode switching information, including: determining the specified region according to the identifier of the specified region; switching the specified region from the first storage mode to the second storage mode according to the mode switching information; or, switching the specified region from the second storage mode to the first storage mode according to the mode switching information.

[0048] The method further includes: receiving a region write request and write data through the first interface, if the write data is hot data, the region write request is used to instruct to write the write data to a region with the first storage mode, if the write data is non-hot data, the write data is written to a region with the second storage mode; and writing the write data into the storage space of the corresponding region according to the region write request.

[0049] The method further includes: receiving a second command through the first interface, the second command including mode recovery information, the mode recovery information being used to indicate whether to return storage mode information; and generating report region parameter data satisfying the indication of the mode recovery information according to the second command.

[0050] When the mode recovery information is used to indicate a case of needing to return the storage mode information, the generating of the report region parameter data satisfying the indication of the mode recovery information according to the second command includes: generating the report region parameter data including the storage mode information according to the second command.

[0051] The storage mode information is located in a region descriptor in the report region parameter data.

[0052] The storage mode information occupies four bit fields in the region descriptor.

[0053] The report region parameter data includes a region descriptor list and a common descriptor; the region descriptor list includes at least one region descriptor, the region descriptor being used to indicate the self attribute of the corresponding region, and the common descriptor being used to indicate the common attribute of multiple regions.

[0054] The region descriptor further includes a region type field, a region state field, a region length field, a region start logical block address field, and a write pointer logical block address field.

[0055] In the foregoing solution, the public descriptor includes a region list length field, a same field, and a maximum logical block address field.

[0056] In the foregoing solution, the first command includes a reset write pointer command, and the mode switching information occupies two bit fields in the reset write pointer command.

[0057] In the foregoing solution, the second command includes a report region command.

[0058] In the foregoing solution, the region is a region in a zone namespace (ZNS).

[0059] In the foregoing solution, the method further includes resetting a state of the specified region to an empty state according to the first command.

[0060] In a fourth aspect, an embodiment of the present disclosure provides a computer readable storage medium, and the computer readable storage medium stores a computer program. When the computer program is executed, the method in any one of the third aspect is implemented. BRIEF DESCRIPTION OF DRAWINGS

[0061] In the drawings, like reference numerals refer to like elements throughout the various drawings. The drawings are not necessarily to scale, the emphasis instead being placed on the relations between the various elements. It should be understood that the drawings only depict some embodiments in accordance with the present disclosure and should not be considered limiting of the scope of the disclosure.

[0062] FIG. 1 is a schematic diagram of an exemplary system having a memory system according to an embodiment of the present disclosure;

[0063] FIG. 2A is a schematic diagram of an exemplary memory card having a memory system according to an embodiment of the present disclosure;

[0064] FIG. 2B is a schematic diagram of an exemplary solid state drive having a memory system according to an embodiment of the present disclosure;

[0065] FIG. 3A is a schematic diagram of a distribution of memory cells of a three-dimensional NAND type memory according to an embodiment of the present disclosure;

[0066] FIG. 3B is a schematic diagram of an exemplary memory device including a peripheral circuit according to an embodiment of the present disclosure;

[0067] FIG. 4 is a schematic diagram of a cross-section of an array of memory cells including NAND memory strings according to an embodiment of the present disclosure;

[0068] FIG. 5A is a schematic diagram of an exemplary memory device including an array of memory cells and a peripheral circuit according to an embodiment of the present disclosure;

[0069] FIG. 5B is a schematic diagram of a memory controller according to an embodiment of the present disclosure;

[0070] FIG. 6 is a diagram illustrating a structure of a reset write pointer command in the ZBC according to an embodiment of the present disclosure;

[0071] FIG. 7 is a diagram illustrating a structure of a report region command in the ZBC according to an embodiment of the present disclosure;

[0072] FIG. 8A is a diagram illustrating a structure of report region parameter data in the ZBC according to an embodiment of the present disclosure;

[0073] FIG. 8B is a diagram illustrating a structure of a region descriptor in the report region parameter data according to an embodiment of the present disclosure;

[0074] FIG. 9 is a diagram illustrating an interaction flow between a memory system and a host according to an embodiment of the present disclosure;

[0075] FIG. 10A is a block diagram of a host according to an embodiment of the present disclosure;

[0076] FIG. 10B is a block diagram of a host according to an embodiment of the present disclosure;

[0077] FIG. 11 is a diagram illustrating an interaction flow between a memory system and a host according to an embodiment of the present disclosure;

[0078] FIG. 12 is a diagram illustrating a target region data structure according to an embodiment of the present disclosure;

[0079] FIG. 13 is a flowchart illustrating a method of operating a host according to an embodiment of the present disclosure;

[0080] FIG. 14 is a flowchart illustrating a method of operating a host according to an embodiment of the present disclosure;

[0081] FIG. 15 is a flowchart illustrating a method of operating a memory system according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0082] Example embodiments of the present disclosure will be described more fully hereinafter with reference to the accompanying drawings; however, these embodiments are not intended to limit the scope of the present disclosure, but rather, the present disclosure can be implemented in various forms. Rather, the present disclosure will provide a more complete understanding of the present disclosure by describing the embodiments in more detail, and will fully convey the scope of the present disclosure to those skilled in the art.

[0083] In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present disclosure. However, it will be apparent to one skilled in the art that the present disclosure can be practiced without one or more of these specific details. In other instances, well-known features have not been described in detail in order to avoid unnecessarily complicating the present disclosure.

[0084] In the drawings, the size of layers, regions, elements, and the like can be exaggerated for clarity. Like reference numbers in different drawings can indicate like elements.

[0085] It will be understood that when an element or layer is referred to as being "on" or "connected to" another element or layer, it can be directly on or connected to the other element or layer or intervening elements or layers can be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element or layer, there are no intervening elements or layers present. It will also be understood that, although the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms since such terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section.

[0086] Spatially relative terms, such as "beneath", "below", "lower", "under", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" or "over" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. The device can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0087] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising", when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. The terms "root", "strip" or "piece" of transmission line all represent the same meaning.

[0088] In order to enable a person skilled in the art to more fully understand the features and technical contents of the embodiments of the present disclosure, the implementation of the embodiments of the present disclosure is described in detail below with reference to the accompanying drawings, which are only used for reference and do not limit the embodiments of the present disclosure.

[0089] The memory in the embodiments of the present disclosure includes but is not limited to a three-dimensional NAND type memory, and for the convenience of understanding, the three-dimensional NAND type memory is taken as an example for description.

[0090] FIG. 1 is a block diagram of an exemplary system 100 having a memory, according to an embodiment of the present disclosure. The system 100 can be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a memory therein. As shown in FIG. 1, the system 100 can include a host 108 and a memory system 102 having one or more memories 104 and a memory controller 106. The host 108 can be a processor (e.g., a central processing unit (CPU)) or a system on chip (SoC) (e.g., an application processor (AP)) of an electronic device. The host 108 can be configured to send data to or receive data from the memory 104. The host 108 includes a host controller and a second interface for coupling with the memory controller 106, that is, the second interface can also be an interface through which the host and the memory controller communicate.

[0091] In some embodiments, the memory controller 106 is coupled to the memory 104 and the host 108 and is configured to control the memory 104. The memory controller 106 can manage data stored in the memory 104 and communicate with the host 108. In some embodiments, the memory controller 106 is designed for operation in a low duty cycle environment, such as a secure digital (SD) card, compact flash (CF) card, universal serial bus (USB) flash drive, or other media for use in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some embodiments, the memory controller 106 is designed for operation in a high duty cycle environment, such as an SSD or embedded multimedia card (eMMC), which is used as data storage for mobile devices such as smartphones, tablet computers, laptop computers, etc. and enterprise storage arrays.

[0092] The memory controller 106 can be configured to control operations of the memory 104, such as read, erase, and program operations. The memory controller 106 can also be configured to manage various functions with respect to data stored in or to be stored in the memory 104, including but not limited to bad block management, garbage collection, logical to physical address translation, wear leveling, etc. In some embodiments, the memory controller 106 is also configured to handle error correction codes (ECC) with respect to data read from or written to the memory 104. The memory controller 106 can also perform any other suitable functions, such as formatting the memory 104. The memory controller 106 can communicate with external devices (e.g., the host 108) according to a particular communication protocol. For example, the memory controller 106 can communicate with external devices through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a peripheral component interconnect (PCI) protocol, a PCI express (PCI-E) protocol, an advanced technology attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer small interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, a Firewire protocol, etc. These interfaces can also be referred to as first interfaces (also referred to as front-end interfaces). The first interface here is the interface that is coupled to the second interface of the aforementioned host. In some embodiments, the memory controller 106 interacts with the memory 104 for commands / data through a plurality of channels configured. These channels are also referred to as back-end interfaces.

[0093] The memory controller 106 and one or more memories 104 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an eMMC package). That is, the memory system 102 can be implemented and packaged into different types of end electronic products. In one example as shown in FIG. 2A, the memory controller 106 and a single memory 104 can be integrated into a memory card 202. The memory card 202 can include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), a UFS, etc. The memory card 202 can also include a memory card connector 204 that couples the memory card 202 with a host (e.g., the host 108 in FIG. 1). In another example as shown in FIG. 2B, the memory controller 106 and multiple memories 104 can be integrated into an SSD 206. The SSD 206 can also include an SSD connector 208 that couples the SSD 206 with a host (e.g., the host 108 in FIG. 1). In some implementations, the storage capacity and / or operating speed of the SSD 206 is greater than that of the memory card 202.

[0094] FIG. 3A is a schematic diagram of a structure of a memory cell array of a three-dimensional NAND memory according to an embodiment of the present disclosure. As shown in FIG. 3A, the memory cell array of the three-dimensional NAND memory is composed of a plurality of rows of memory cells that are parallel and staggered with respect to gate isolation structures and upper select gate isolation structures. Each two rows of memory cells are separated by a gate isolation structure and an upper select gate isolation structure. Each row of memory cells includes a plurality of memory strings. The gate isolation structures can include first gate isolation structures and second gate isolation structures. The first gate isolation structures divide the memory cell array into a plurality of memory blocks. The second gate isolation structures divide the memory blocks into a plurality of finger regions. The upper select gate isolation structures disposed in the middle of each finger region divide the finger region into two portions, thereby dividing the finger region into two strings. One memory block shown in FIG. 3A contains six strings. In actual applications, the number of strings in a memory block is not limited to this.

[0095] It should be noted that the number of rows of memory cells between the gate isolation structures and the upper select gate isolation structures shown in FIG. 3A is only exemplary and is not intended to limit the number of rows of memory cells included in one finger region of the three-dimensional NAND memory according to the present disclosure. In actual applications, the number of rows of memory cells included in one finger region can be adjusted according to actual conditions, such as 2, 4, 8, 16, etc.

[0096] Figure 3B is a schematic circuit diagram of an exemplary memory 300 including peripheral circuitry in accordance with an embodiment of the present disclosure. The memory 300 can be an example of the memory 104 in Figure 1. The memory 300 can include an array of memory cells 301 and peripheral circuitry 302 coupled to the array of memory cells 301. By way of example, the array of memory cells 301 is described as a three-dimensional NAND type array of memory cells 306 provided in the form of an array of NAND memory strings 308, each of which extends vertically above a substrate (not shown). In some implementations, each NAND memory string 308 includes a plurality of memory cells 306 coupled in series and stacked vertically. Each memory cell 306 can hold a continuous analog value, e.g., a voltage or charge, that depends on the number of electrons captured within a region of the memory cell 306. Each memory cell 306 can be a floating gate type of memory cell that includes a floating gate transistor, or a charge trap type of memory cell that includes a charge-trapping transistor.

[0097] In some implementations, each memory cell 306 is a single-level cell (SLC) that has two possible memory states and thus can store one bit of data. For example, a first memory state “0” can correspond to a first voltage range, and a second memory state “1” can correspond to a second voltage range. In some implementations, each memory cell 306 is a multi-level cell (MLC) that can store more than a single bit of data in more than four memory states. For example, a MLC can store two bits per cell, three bits per cell (also referred to as triple-level cells (TLC)), or four bits per cell (also referred to as quad-level cells (QLC)). Each MLC can be programmed to take on a range of possible nominal storage values. In one example, if each MLC stores two bits of data, the MLC can be programmed to take on one of three possible programmed levels from an erased state by writing one of three possible nominal storage values to the cell. A fourth nominal storage value can be used for the erased state.

[0098] As shown in FIG. 3B, each NAND memory string 308 can include a lower select gate (BSG) 310 at its source end and an upper select gate (TSG) 312 at its drain end. The BSG 310 and TSG 312 can be configured to activate a selected NAND memory string 308 during read and program operations. In some implementations, the sources of the NAND memory strings 308 in the same memory block 304 are coupled through the same source line (SL) 314 (e.g., a common SL). In other words, according to some implementations, all NAND memory strings 308 in the same memory block 304 have an array common source (ACS). According to some implementations, the TSG 312 of each NAND memory string 308 is coupled to a respective bit line (BL) 316 from which data can be read or written via an output bus (not shown). In some implementations, each NAND memory string 308 is configured to be selected or deselected by applying a select voltage (e.g., higher than the threshold voltage of the transistor with the TSG 312) or a deselect voltage (e.g., 0 V) to the respective TSG 312 via one or more TSG lines 313 and / or by applying a select voltage (e.g., higher than the threshold voltage of the transistor with the BSG 310) or a deselect voltage (e.g., 0 V) to the respective BSG 310 via one or more BSG lines 315.

[0099] As shown in FIG. 3B, the NAND memory strings 308 can be organized into a plurality of memory blocks 304, each of which can have a common source line 314 (e.g., coupled to ground). In some implementations, each memory block 304 is a basic unit of data for erase operations, i.e., all memory cells 306 on the same memory block 304 are erased at the same time. To erase the memory cells 306 in a selected memory block, the source lines 314 coupled to the selected memory block and to unselected memory blocks in the same face as the selected memory block can be biased with an erase voltage (Vers) (e.g., a high positive voltage (e.g., 20 V or higher)). It should be appreciated that in some examples, erase operations can be performed at a half memory block level, at a quarter memory block level, or at a level having any suitable number of memory blocks or any suitable fraction of a memory block. The memory cells 306 of adjacent NAND memory strings 308 can be coupled through word lines 318 that select which row of memory cells 306 is affected by read and program operations.

[0100] FIG. 4 is a cross-sectional schematic diagram of an exemplary memory cell array 301 including a NAND memory string 308 according to an embodiment of the present disclosure. As shown in FIG. 4, the NAND memory string 308 can include a layer stack 410 including a plurality of gate layers 411 and a plurality of insulating layers 412 alternately stacked in sequence, and the memory string 308 vertically penetrating the gate layers 411 and the insulating layers 412. The gate layers 411 and the insulating layers 412 can be alternately stacked, and two adjacent gate layers 411 are separated by one insulating layer 412. The number of pairs of the gate layers 411 and the insulating layers 412 in the layer stack 410 can determine the number of memory cells included in the memory cell array 301.

[0101] The constituent material of the gate layers 411 can include a conductive material. The conductive material includes, but is not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate layer 411 includes a metal layer, for example, a tungsten layer. In some embodiments, each gate layer 411 includes a doped polysilicon layer. Each gate layer 411 can include a control gate surrounding a memory cell. The gate layers 411 at the top of the layer stack 410 can laterally extend as upper select gate lines, the gate layers 411 at the bottom of the layer stack 410 can laterally extend as lower select gate lines, and the gate layers 411 laterally extending between the upper select gate lines and the lower select gate lines can serve as word line layers.

[0102] In some embodiments, the layer stack 410 can be disposed on a semiconductor layer 401. The semiconductor layer 401 can include silicon (e.g., single-crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), germanium on insulator (GOI), or any other suitable material.

[0103] In some embodiments, the NAND memory string 308 includes a channel structure that extends vertically through the stack structure 410. In some embodiments, the channel structure includes a channel hole that is filled with a semiconductor material(s) (e.g., as a semiconductor channel) and a dielectric material(s) (e.g., as a memory film). In some embodiments, the semiconductor channel includes silicon, e.g., polysilicon. In some embodiments, the memory film is a composite dielectric layer that includes a tunneling layer, a storage layer (also referred to as a “charge-trapping / storage layer”), and a blocking layer. The channel structure can have a cylindrical shape (e.g., a column shape). According to some embodiments, the semiconductor channel, the tunneling layer, the storage layer, and the blocking layer are arranged radially from the center of the column toward the outer surface of the column in this order. The tunneling layer can include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer can include silicon nitride, silicon oxynitride, or any combination thereof. The blocking layer can include silicon oxide, silicon oxynitride, a high-k dielectric, or any combination thereof. In one example, the memory film can include a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0104] Referring back to FIG. 3B, the peripheral circuitry 302 can be coupled to the memory cell array 301 through the bit lines 316, the word lines 318, the source lines 314, the BSG lines 315, and the TSG lines 313. The peripheral circuitry 302 can include any suitable analog, digital, and mixed-signal circuitry for facilitating the operation of the memory cell array 301 by applying voltage signals and / or current signals to and sensing voltage signals and / or current signals from each target memory cell 306 through the bit lines 316, the word lines 318, the source lines 314, the BSG lines 315, and the TSG lines 313. The peripheral circuitry 302 can include various types of peripheral circuitry formed using metal-oxide-semiconductor (MOS) technology. FIG. 5A is a schematic diagram of an example memory device including a memory cell array and peripheral circuitry according to an embodiment of the disclosure, the peripheral circuitry 302 including a page buffer / sense amplifier 504, a column decoder / bit line driver 506, a row decoder / word line driver 508, a voltage generator 510, control logic 512, registers 514, an interface 516, and a data bus 518. It should be understood that additional peripheral circuitry not shown in FIG. 5A can also be included in some examples.

[0105] Control logic 512 can be coupled to each of the peripheral circuits described above and configured to control the operation of each of the peripheral circuits. Registers 514 can be coupled to control logic 512 and include status registers, command registers, and address registers to store status information, command operation codes (OP codes), and command addresses used to control the operation of each of the peripheral circuits. Interface 516 can be coupled to control logic 512 and act as a control buffer to buffer and relay control commands received from a host (not shown) to control logic 512, and to buffer and relay status information received from control logic 512 to the host. Interface 516 can also be coupled to column decoder / bit line driver 506 via data bus 518 and act as a data I / O interface and data buffer to buffer and relay data to or from memory cell array 301. That is, interface 516 here is the interface that couples with the back end interface of the aforementioned memory controller, that is, interface 516 can also be the interface through which the memory communicates with the memory controller.

[0106] In some embodiments, page buffer / sense amplifier 504 can be configured to read data from and program (write) data to memory cell array 301 according to control signals from control logic 512. In one example, page buffer / sense amplifier 504 can store program data (write data) to be programmed to memory cells 306 of memory cell array 301. In another example, page buffer / sense amplifier 504 can perform a program verify operation to ensure that data has been correctly programmed to memory cells 306 coupled to a selected word line 318. Column decoder / bit line driver 506 can be configured to be controlled by control logic 512 and select one or more NAND memory strings 308 by applying bit line voltages generated from voltage generator 510.

[0107] Row decoders / word line drivers 508 can be configured to be controlled by control logic 512 and to select / deselect memory blocks 304 of memory cell array 301 and to select / deselect word lines 318 of memory blocks 304. Row decoders / word line drivers 508 can also be configured to drive word lines 318 using word line voltages generated from voltage generator 510. In some embodiments, row decoders / word line drivers 508 can also select / deselect and drive BSG lines 315 and TSG lines 313. As described in detail below, row decoders / word line drivers 508 are configured to perform program operations on memory cells 306 coupled to selected word line(s) 318. Voltage generator 510 can be configured to be controlled by control logic 512 and to generate word line voltages (e.g., read voltages, program voltages, pass voltages, channel boost voltages, verify voltages, etc.), bit line voltages, and source line voltages to be supplied to memory cell array 301.

[0108] FIG. 5B is a schematic diagram of a memory controller 106 according to an embodiment of the present disclosure. The memory controller 106 can include one or more processors 522 and a storage module including a cache 524. The memory controller 106 can also include an interface (I / F) 528 (i.e., a first interface) coupled to the host 108 and an interface (I / F) 530 (i.e., a back-end interface) coupled to the memory 104. The first interface here is the interface coupled to the second interface of the aforementioned host. The processor 522 can include an arithmetic logic unit (ALU) for performing arithmetic and logic operations. The interface 528 can receive instructions and data from the host 108 and buffer the instructions and data to the processor 522 and the cache 524, respectively. The interface 530 can transmit control signals and data from the processor 522 and the cache 524 to the memory 104, respectively.

[0109] The embodiments of the present disclosure provide a memory system. Herein, the specific structure and components of the memory system can refer to the related structure and components of the memory system 102 in FIG. 1, FIG. 2A, and FIG. 2B. For brevity, the detailed description is not repeated herein. The memory system includes a memory and a memory controller coupled to the memory, the memory controller is configured to control the memory to store data in a region-by-region manner, wherein a storage space of a single region is configured to support only sequential writing; the memory controller is configured with a first interface for coupling to a host and receives a first command from the host through the first interface; the first command includes identification of a specified region and mode switching information of the specified region; the memory controller is further configured to switch a storage mode of the specified region to a target storage mode indicated in the mode switching information according to the mode switching information.

[0110] The embodiments of the present disclosure can realize the switching of the target storage mode of the specified region in the memory through the first command.

[0111] In some embodiments, the memory controller is configured to determine the current storage mode of the specified region, and in the case that the current storage mode is different from the target storage mode indicated in the mode switching information, switch the current storage mode to the target storage mode according to the mode switching information.

[0112] In some other embodiments, the memory controller is configured to determine the current storage mode of the specified region, and in the case that the current storage mode is the same as the target storage mode indicated in the mode switching information, not to switch the storage mode of the specified region.

[0113] In some embodiments, the storage mode includes a first storage mode and a second storage mode, and when the region is in the first storage mode, each of the storage units corresponding to the storage space of the region can be written with N-bit data; and when the region is in the second storage mode, each of the storage units corresponding to the storage space of the region can be written with M-bit data, M and N are integers greater than or equal to 1, and M is greater than N.

[0114] As described above, in the NAND type memory, the storage units can be divided into single-level cells (SLC) and multi-level cells (MLC) according to the difference in storage density. Correspondingly, the first storage mode can be a single-level cell (SLC) storage mode, i.e., N = 1, and the second storage mode can be a multi-level cell (MLC) storage mode, i.e., M is an integer greater than 1. The storage density of the first storage mode is less than that of the second storage mode, i.e., N is less than M. The multi-level cell (MLC) storage mode can be at least one of a two-level cell storage mode, a three-level cell (TLC) storage mode, and a four-level cell (QLC) storage mode. When M = 2, the second storage mode is a two-level cell storage mode; when M = 3, the second storage mode is a TLC storage mode; and when M = 4, the second storage mode is a QLC storage mode.

[0115] In some embodiments, the memory controller is configured to determine the specified region according to the identification of the specified region in the first command, switch the specified region from the first storage mode to the second storage mode according to the mode switching information, or switch the specified region from the second storage mode to the first storage mode according to the mode switching information.

[0116] Here, the region to be switched in storage mode can be determined according to the identification of the specified region in the first command. The switching of the specified region between the first storage mode and the second storage mode can be realized according to the mode switching information in the first command. That is, only one command needs to be transmitted between the host and the memory system to realize the function of switching the storage mode between the first storage mode and the second storage mode.

[0117] In a specific example, the first storage mode is an SLC storage mode, and the second storage mode is a TLC storage mode. The first command can be used to switch the specified region between the SLC storage mode and the TLC storage mode.

[0118] In some embodiments, the region is a region in a zone namespace (ZNS). The ZNS includes a plurality of zones. A zone is a fixed size sub-interval within the ZNS, and each zone has a range of logical block addresses (LBAs). The number of logical block addresses corresponding to each zone can be the same. In some embodiments, each of the plurality of zones in the ZNS can have the same configuration. Typically, in a ZNS, an external device (e.g., a host) provides a definition of logical block addresses to the memory system. For example, the host can indicate a range of LBAs corresponding to a first zone, a range of LBAs corresponding to a second zone, and so on. The memory system then maps each zone in the ZNS to a physical block in the memory. For example, the memory system can map the LBAs corresponding to the first zone to a first physical block, the LBAs corresponding to the second zone to a second physical block, and so on.

[0119] In some embodiments, the storage capacity of a single zone is less than the storage capacity corresponding to a physical block of the memory. In this context, the storage capacity can refer to how much storage space the memory provides.

[0120] In some embodiments, a zone namespace (ZNS) can have a preset or adjustable storage capacity. A memory system supporting a zone namespace (ZNS) can establish a plurality of zones, so that the memory controller can control the memory to store in zones. For example, data transmitted by the host can be stored in a zone, and the memory system can allocate at least one storage block or a portion of a storage block to each zone. The memory system can sequentially store the data transmitted by the host in the corresponding LBA-specified zone.

[0121] In a memory system supporting a zone namespace ZNS, a zone in the zone namespace ZNS only supports sequential writing and does not support random writing, and a zone in the zone namespace ZNS can support random reading and sequential reading.

[0122] In some embodiments, in addition to the zone namespace ZNS, the memory system can also include one or more conventional namespaces (CNS).

[0123] In some embodiments, the first command comprises a Zoned Block Command (ZBC). For example, the first command can be a command in the ZBC for switching the state of a zone. In a specific example, the first command can be a Reset Write Pointer Command in the ZBC. Here, the first command is a command in a format complying with a Zoned UFS (Zoned Universal Flash Storage) protocol.

[0124] FIG. 6 is a structural diagram of a Reset Write Pointer Command in the ZBC according to an embodiment of the present disclosure. Referring to FIG. 6, the Reset Write Pointer Command can further include an OPERATION CODE field, a SERVICE ACTION field, an ALL bit, a CONTROL byte, and a Reserved field, etc. The various fields and information included in the Reset Write Pointer Command can be understood with reference to the ZBC specification. In the example of FIG. 6, the ZONE ID is an identifier of a specified zone, and the ZONE MODE is mode switching information.

[0125] In some embodiments, the Reset Write Pointer Command sent by the host can request the memory controller to perform a reset operation of the write pointer. The reset operation of the write pointer is an operation of resetting the write pointer to an initial value. The initial value of the write pointer can be 0.

[0126] Here, the write pointer is used to indicate a starting LBA of a write operation to be started. The write pointer can be determined by the memory controller and can be assigned to each of the ZNS zones. For example, the memory controller can determine an initial value of the write pointer to indicate a starting point of a write for each zone. For example, when the initial value of the write pointer is 0 (i.e., WP = 0), it can indicate that the starting point of the write for the zone is the starting LBA of the zone.

[0127] When data is written to a zone, the write pointer is advanced or updated to point to or indicate a next LBA in the zone for writing data, so as to track a next write starting point (i.e., a completion point of a previous write equals a starting point of a subsequent write). Therefore, the write pointer can be used to indicate where a subsequent write to the zone will start.

[0128] In some embodiments, the zone state includes an Empty state, an Open state, and a Full state. In the Empty state, there is no valid data in the zone, and the write pointer of the zone is set to the start LBA in the zone (i.e., WP = 0). After the zone state is switched from the Empty state to the Open state, the zone can be used for data writing. In the Open state, there can be no valid data in the zone or there can be valid data in the zone, the write pointer points to a position between the start LBA and the end of the last LBA in the zone (i.e., WP > 0), and the storage space corresponding to the zone can receive write data for data writing through a write command. In addition, the host can reset the zone to clear or erase the valid data stored in the zone, so that the zone is reset to the Empty state. Once the storage space corresponding to the zone is full, the zone is switched to the Full state. In the Full state, the storage space corresponding to the zone is full, and the zone cannot be opened to receive write data. At this time, the write pointer points to the LBA of the next zone. If each zone in the ZNS is full, the write pointer points to the end of the last LBA of the zone (i.e., WP = ZCAP). Here, ZCAP is the capacity of the zone.

[0129] In some embodiments, the memory controller is configured to reset the state of the specified zone to the Empty state according to the first command.

[0130] Since the reset write pointer command can reset the write pointer to the initial value, that is, the write pointer points to the start LBA of the zone, the state of the specified zone can be reset to the Empty state through the first command.

[0131] In some embodiments, referring to FIG. 6, the ZONE MODE is the mode switching information, and the mode switching information can be contained in the unused reserved field in the reset write pointer command based on the existing ZBC specification. In some embodiments, the mode switching information occupies two bit fields in the reset write pointer command. In a specific example, the mode switching information occupies the first bit to the second bit of the fourteenth byte in the reset write pointer command.

[0132] In a specific example, the mode switching information can be used to indicate the target storage mode of the specified zone. When the mode switching information is 01h, it represents that the target storage mode is the first storage mode; when the mode switching information is 02h, it represents that the target storage mode is the second storage mode.

[0133] In a specific example, when the mode switching information is 00h, it represents that the storage mode of the specified zone is not switched.

[0134] In a specific example, when the storage mode information is 01h, if the current storage mode of the specified region is the first storage mode, which is the same as the target storage mode indicated in the mode switching information, the storage mode of the specified region is not switched; if the current storage mode of the specified region is the second storage mode, which is different from the target storage mode indicated in the mode switching information, the specified region is switched from the second storage mode to the first storage mode. When the storage mode information is 02h, if the current storage mode of the specified region is the second storage mode, which is the same as the target storage mode indicated in the mode switching information, the storage mode of the specified region is not switched; if the current storage mode of the specified region is the first storage mode, which is different from the target storage mode indicated in the mode switching information, the specified region is switched from the first storage mode to the second storage mode.

[0135] It should be noted that when the value of the ALL bit in the reset write pointer command is 1, the storage mode information in the reset write pointer command is ignored.

[0136] In some embodiments, when the memory controller receives the reset write pointer command, it is configured to reset the state of the specified region to the empty state according to the first command, and if the current storage mode of the specified region is different from the target storage mode indicated in the mode switching information, the specified region is configured to the target storage mode.

[0137] In the embodiments of the present disclosure, the reset write pointer command is used to switch the storage mode of the specified region. Since the reset write pointer command can reset the specified region to the empty state, it ensures that the memory system has a writable region for storage mode switching, i.e., there is no need to use other commands to confirm whether there is a writable region, and only one command can realize the function of switching the storage mode between the first storage mode and the second storage mode. Therefore, the interaction process between the host and the memory system is simple and time-consuming.

[0138] In some embodiments, the memory controller is further configured to receive a region write request and write data through the first interface, and if the write data is hot data, the region write request is used to indicate that the write data is written to a region with the first storage mode, and if the write data is non-hot data, the region write request is used to indicate that the write data is written to a region with the second storage mode; and write the write data into the storage space of the corresponding region according to the region write request.

[0139] In the embodiments of the present disclosure, the host selectively allocates a region with a storage mode of a first storage mode to hot data and a region with a storage mode of a second storage mode to non-hot data based on the cold-hot attribute of the write data. Thus, after the memory system receives the region write request and the write data sent by the host, the write data can be written into the corresponding region based on the region write request. The non-hot data refers to data with an access frequency lower than a reference value set by the memory and a relatively long predetermined storage duration. The hot data refers to data with an access frequency higher than the reference value set by the memory and a relatively short predetermined storage duration. The non-hot data includes cold data and warm data. The access frequency of the warm data is higher than that of the cold data but lower than that of the hot data. Therefore, the region with the storage mode of the first storage mode can be used to store the hot data with a relatively short predetermined storage duration, and the region with the storage mode of the second storage mode can be used to store the non-hot data with a relatively long predetermined storage duration. In this way, the hot data is allocated to the region with the corresponding storage mode based on the cold-hot attribute of the write data, so that the write speed and the read speed of the hot data can be improved.

[0140] In some embodiments, the memory controller is further configured to receive, through the first interface, a second command, the second command including mode reply information indicating whether storage mode information of the region needs to be returned, and generate, according to the second command, the report region parameter data satisfying the indication of the mode reply information.

[0141] In some embodiments, the memory controller is configured to send, to the host according to the second command, the report region parameter data satisfying the indication of the mode reply information, specifically including: in a case where the mode reply information indicates that the storage mode information of the region needs to be returned, the memory controller sends, to the host through the first interface, the report region parameter data including the storage mode information of the region; in a case where the mode reply information indicates that the storage mode information of the region does not need to be returned, the memory controller sends, to the host through the first interface, the report region parameter data not including the storage mode information of the region. For example, the memory controller can generate the corresponding report region parameter data based on the mode reply information in the second command.

[0142] In some embodiments, the second command includes Zoned Block Commands (ZBC). For example, the second command can be a command in the ZBC that can be used to obtain the report region parameter data. In a specific example, the second command can be a REPORT ZONES command in the ZBC. Here, the second command is a command in compliance with the format of the Zoned Universal Flash Storage (Zoned UFS) protocol.

[0143] In some embodiments, the report zones command includes mode return information, the mode return information indicating whether the storage mode information of the zone needs to be returned.

[0144] FIG. 7 is a structure diagram of the report zones command in ZBC according to an embodiment of the present disclosure. Referring to FIG. 7, the report zones command can further include an operation code (OPERATION CODE) field, a service action (SERVICE ACTION) field, a zone start logical block address (ZONE START LBA) field, an allocation length (ALLOCATION LENGTH) field, a partial bit, a reporting options (REPORTING OPTIONS) field, a control (CONTROL) byte, and a reserved (Reserved) field, etc. The various fields and information included in the report zones command can be understood with reference to the ZBC specification.

[0145] In some embodiments, the mode return information is contained in an unused reserved field in the report zones command based on the existing ZBC specification. In some embodiments, referring to FIG. 7, the mode return information occupies three bit fields in the report zones command. In a specific example, the mode return information occupies the sixth bit to the eighth bit of the second byte in the report zones command. In a specific example, when the mode return information is 01h, it indicates that the storage mode information of the zone needs to be returned; when the mode return information is 02h, it indicates that the storage mode information of the zone does not need to be returned.

[0146] In some embodiments, the mode return information can be 01h by default. In other embodiments, the mode return information can also be fixed as 01h.

[0147] In some embodiments, the storage controller is configured to generate, according to the second command, report zones parameter data (REPORT ZONES parameter data) including the storage mode information when the mode return information is used to indicate that the storage mode information needs to be returned.

[0148] In some embodiments, the storage controller is configured to generate, according to the second command, report zones parameter data (REPORT ZONES parameter data) including the storage mode information when the mode return information is 01h.

[0149] In other embodiments, the storage controller is configured to generate, according to the second command, report zones parameter data (REPORT ZONES parameter data) not including the storage mode information when the mode return information is used to indicate that the storage mode information of the zone does not need to be returned.

[0150] In some embodiments, the memory controller is configured to generate the reporting zone parameter data without the storage mode information when the mode recovery information is 02h. Here, the reporting zone parameter data without the storage mode information is the reporting zone parameter data based on the existing ZBC specification.

[0151] FIG. 8A is a schematic diagram of a structure of the reporting zone parameter data in the ZBC according to an embodiment of the present disclosure. Referring to FIG. 8A, the reporting zone parameter data can include a zone descriptor list, a common descriptor, and a reserved field, etc. The zone descriptor list includes at least one zone descriptor, and the zone descriptor is used to indicate the self attribute of the corresponding zone. The common descriptor is used to indicate the common attribute of a plurality of zones. The common descriptor includes a zone list length (ZONE LIST LENGTH) field, a same (SAME) field, a maximum logical block address (MAXIMUM LBA) field, and a reserved field, etc.

[0152] In some embodiments, the storage mode (NAND MODE) information can be located in the zone descriptor in the reporting zone parameter data. Since each zone corresponds to a zone descriptor, the storage mode information is set in the zone descriptor of each zone, so that the storage mode of each zone can be obtained based on the storage mode information in each zone descriptor.

[0153] FIG. 8B is a schematic diagram of a structure of the zone descriptor in the reporting zone parameter data according to an embodiment of the present disclosure. It is to be noted that FIG. 8B shows the zone descriptor including the storage mode information. Referring to FIG. 8B, the zone descriptor can further include a zone type (ZONE TYPE) field, a zone condition (ZONE CONDITION) field, a zone length (ZONE LENGTH) field, a zone start logical block address (ZONE START LBA) field, a write point logical block address (WRITE POINT LBA) field, and a reserved field, etc. The fields and information included in the reporting zone parameter data and the fields and information included in the zone descriptor can be understood with reference to the ZBC specification. For example, the zone type field can define the access type of the zone namespace, and the zone type field being 02h indicates that the zone namespace needs to be written in order. For another example, the same field can define the zone type (ZONE TYPE) and the zone length (ZONE LENGTH) in each zone descriptor in the zone descriptor list, and the same field being 1h indicates that the zone type (ZONE TYPE) and the zone length (ZONE LENGTH) in each zone descriptor in the zone descriptor list are the same.

[0154] In some embodiments, the storage mode information can be stored in a reserved field in the zone descriptor in the reporting area parameter based on the existing ZBC specification. In some embodiments, the storage mode information occupies a four-bit field in the zone descriptor. In a specific example, referring to FIG. 8B, the storage mode information occupies the first to fourth bits of the second byte in the zone descriptor.

[0155] In some embodiments, the storage mode information is used to indicate the storage mode of the zone. In a specific example, when the storage mode information is 01h, it indicates that the storage mode of the zone is the first storage mode; when the storage mode information is 02h, it indicates that the storage mode of the zone is the second storage mode. Here, the first storage mode is the SLC storage mode, and the second storage mode is the TLC storage mode.

[0156] In some embodiments, the storage mode information can also be used to indicate the number of bits of the data stored in the storage unit included in the storage space of the zone. In a specific example, when the storage mode information is 01h, it indicates that the number of bits of the data stored in the storage unit included in the storage space of the zone is N; when the storage mode information is 02h, it indicates that the number of bits of the data stored in the storage unit included in the storage space of the zone is M, where N = 1 and M = 3.

[0157] In the embodiments of the present disclosure, on the host side: by adding mode switching information in the reset write pointer command, the mode switching information can be set based on actual needs, so that the target storage mode of the specified zone can be controlled. Correspondingly, on the memory system side: based on the mode switching information in the reset write pointer command, the storage mode of the specified zone can be switched to the target storage mode indicated in the mode switching information. In the embodiments of the present disclosure, the existing ZBC command can be used to realize the switching of the specified zone between the first storage mode and the second storage mode.

[0158] In the embodiments of the present disclosure, the storage mode information of each zone in the zone namespace (ZNS) can be obtained through the reporting area command, so that the storage mode of each zone can be obtained. In this way, when data is written, the hot data can be selectively allocated to the zone with the first storage mode, and the non-hot data can be allocated to the zone with the second storage mode based on the hot and cold attributes of the written data. In this way, the writing speed and reading speed of the hot data can be improved.

[0159] The embodiment of the present disclosure provides a system, wherein the specific structure and composition of the system can refer to the related structure and composition of the foregoing figure 1. For the sake of brevity, the details are not repeated here. Figure 9 is a schematic diagram of the interaction process between the memory system and the host according to an embodiment of the present disclosure, and the working process of the system is described in combination with figure 9 and figure 1. The system comprises: a memory system and a host; wherein the memory system comprises: a memory and a memory controller coupled with the memory, the memory controller is configured to control the memory to store by area, wherein the storage space of a single area is configured to support only sequential writing; the host comprises a host controller and a second interface for coupling with the memory controller, at step 901: the host controller is configured to generate a first command; at step 902: the first command is sent to the memory controller through the second interface, the first command comprises the identification of the specified area and the mode switching information of the specified area; and the memory controller is configured with a first interface for coupling with the host, and the memory controller receives the first command from the host through the first interface; at step 903: the memory controller switches the storage mode of the specified area to the target storage mode indicated in the mode switching information according to the first command.

[0160] Specifically, the memory controller switches the storage mode of the specified area to the target storage mode indicated in the mode switching information according to the mode switching information.

[0161] In some embodiments, the first command comprises a reset write pointer command, and the mode switching information occupies two bit fields in the reset write pointer command. The reset write pointer command can refer to the foregoing figure 6, and the details are not repeated here.

[0162] In some embodiments, step 903 specifically comprises: the memory controller is configured to determine the current storage mode of the specified area, and in the case that the current storage mode is different from the target storage mode indicated in the mode switching information, the current storage mode is switched to the target storage mode according to the mode switching information.

[0163] The storage mode comprises a first storage mode and a second storage mode. When the area is in the first storage mode, each of the storage units corresponding to the storage space of the area can be written N-bit data; when the area is in the second storage mode, each of the storage units corresponding to the storage space of the area can be written M-bit data, and specifically, N is 1 and M is 3. That is, the first storage mode can be an SLC storage mode, and the second storage mode can be an MLC storage mode.

[0164] In some embodiments, the step 903 specifically comprises: the memory controller is configured to: determine the specified region according to the identification of the specified region; switch the specified region from the first storage mode to the second storage mode according to the mode switching information; or, switch the specified region from the second storage mode to the first storage mode according to the mode switching information.

[0165] In some embodiments, at the step 904: the host controller is configured to generate a second command, at the step 905: the second command is sent to the memory controller through the second interface, the second command comprises mode reply information, the mode reply information is used to indicate whether the storage mode information needs to be returned; at the step 906: the memory controller is configured to receive the second command through the first interface, generate the reporting region parameter data satisfying the indication of the mode reply information according to the second command and send to the host controller.

[0166] In some embodiments, the second command comprises a reporting region command, and the mode reply information occupies three bit fields in the reporting region command. The reporting region command can be understood with reference to the aforementioned FIG. 7, which will not be described here again.

[0167] In some embodiments, the host is configured with a file system; at the step 907: the host controller is configured to determine the hot-cold attribute of the write data through the file system, generate a corresponding region write request according to the hot-cold attribute of the write data, at the step 908: the write data and the region write request are sent to the memory controller through the second interface; if the write data is hot data, the region write request is used to indicate that the write data is written to the region whose storage mode is the first storage mode, if the write data is non-hot data, the region write request is used to indicate that the write data is written to the region whose storage mode is the second storage mode; at the step 909: the memory controller is configured to write the write data into the storage space of the corresponding region according to the region write request.

[0168] Specifically, if the write data is hot data, the region write request is used to indicate that the write data is written to the region whose storage mode is the first storage mode, at this time the memory controller writes the write data into the storage space of the region whose storage mode is the first storage mode according to the region write request; if the write data is non-hot data, the region write request is used to indicate that the write data is written to the region whose storage mode is the second storage mode, at this time the memory controller writes the write data into the storage space of the region whose storage mode is the second storage mode according to the region write request.

[0169] FIG. 10A is a block diagram of a host according to an embodiment of the present disclosure. Referring to FIG. 10A, the host 108 includes a cache 111 and a host processor 112. The cache 111 can be a random access memory (RAM), which can be used to store instructions and data and can be directly accessed by the host processor 112. For example, the cache 111 can be configured to store a target region data structure 113. The host processor 112 is the operation and control core of the host 108, and is the final execution unit of information processing and program running.

[0170] FIG. 10B is a block diagram of a host according to an embodiment of the present disclosure. Referring to FIG. 10B, in the embodiment of the present disclosure, the host 108 is further configured with a file system 114. The file system 114 processes input data so that the input data is stored in a specific logical or physical location in the memory system. That is, when the host 108 receives data through a user application (not shown), the host 108 can process the data using the file system 114 and then store the data in the memory system.

[0171] In some embodiments, the file system 114 can include a log-structured file system (LFS), for example, a flash friendly file system (F2FS) designed for the Linux kernel based on flash characteristics, or a journal flash file system (JFFS) as a Linux LFS related to a NOR flash device. The F2FS can separate hot data, warm data, and cold data of user write data according to the access frequency of the user write data. For example, the F2FS can separate the user write data into hot data, warm data, and cold data according to the access frequency of the user write data. The warm data and the cold data are both non-hot data.

[0172] In the embodiment of the present disclosure, the file system 114 can create a target region data structure, which can be stored in the cache 111.

[0173] In some embodiments, referring to FIG. 9, step 906 specifically comprises that the memory controller is configured to generate and send, according to the second command, report region parameter data including the storage mode information to the host controller in the case that the mode return information indicates that the storage mode information of the region needs to be returned. Specifically, the storage mode information can be located in a region descriptor in the report region parameter data, and the storage mode information occupies four bit fields in the region descriptor. The report region parameter data and the region descriptor can be understood with reference to the aforementioned FIG. 8A and FIG. 8B, which will not be repeated here. The storage mode information is used to indicate the storage mode of the region. In a specific example, the storage mode information occupies the first bit to the fourth bit of the second byte in the region descriptor. When the storage mode information is 01h, it indicates that the storage mode of the region is the first storage mode; when the storage mode information is 02h, it indicates that the storage mode of the region is the second storage mode.

[0174] In some embodiments, the host is configured with a file system; and the host processor is configured to: establish, by the file system, a target region data structure, the target region data structure being used to store information of a target region, the target region being a region with the first storage mode; obtain, according to the report region parameter data including the storage mode information, the information of the target region; and store the information of the target region to the target region data structure.

[0175] FIG. 11 is a schematic diagram of an interaction flow between a memory system and a host according to an embodiment of the present disclosure. It should be understood that not all steps in the interaction between the memory system and the host shown in FIG. 9 and FIG. 11 need to be performed, and the operation steps shown in FIG. 9 and FIG. 11 can not be exhaustive, and other operation steps can also be performed before, after or between any of the operation steps shown. In addition, some of the operation steps can be performed simultaneously, or in a different order from that shown in FIG. 9 and FIG. 11. The working flow of the system will be described in combination with FIG. 11, FIG. 9 and FIG. 1. Referring to FIG. 11, the system comprises: a memory system and a host; wherein the memory system comprises: a memory and a memory controller coupled with the memory, the memory controller being configured to control the memory to store data in regions, wherein the storage space of a single region is configured to support only sequential writing; the host comprises a host controller and a second interface for coupling with the memory controller, at step 901: the host controller is configured to generate a first command; at step 902: the first command is sent to the memory controller through the second interface, the first command including identification of a specified region and mode switching information of the specified region; and the memory controller is configured with a first interface for coupling with the host, and the memory controller receives the first command from the host through the first interface; at step 903: the memory controller switches the storage mode of the specified region to the target storage mode indicated in the mode switching information according to the first command.

[0176] At step 904, the host controller is configured to generate a second command, at step 905, the second command is sent to the memory controller through the second interface, the second command includes mode reply information, the mode reply information is used to indicate whether the storage mode information needs to be returned; step 906 specifically includes: the memory controller is configured to generate report region parameter data including storage mode information according to the second command and send to the host controller in the case that the mode reply information is used to indicate that the storage mode information of the region needs to be returned; at step 1101, the host processor is configured to obtain the information of the target region according to the report region parameter data including the storage mode information; the information of the target region is stored to the target region data structure.

[0177] In some embodiments, the target region is a region whose storage mode is SLC storage mode, hereinafter referred to as “SLC region”, the host processor obtains the information of the SLC region according to the report region parameter data including the storage mode information, and stores the information of the SLC region to the target region data structure. The non-target region is a region whose storage mode is TLC storage mode, hereinafter referred to as “TLC region”.

[0178] In some embodiments, in the case that the mode reply information is used to indicate that the storage mode information of the region needs to be returned, the host can obtain the report region parameter data including the information of each region through the second command, that is, the report region parameter data includes the information of the SLC region and the information of the TLC region, but the host only stores the information of the SLC region to the target region data structure. In the embodiment of the present disclosure, a target region data structure is added in the host, which is used to manage the information of the SLC region in the memory system, so that the host processor can write the hot data to the SLC region, thereby effectively improving the writing speed of the hot data.

[0179] In some embodiments, the target region data structure is used to store the number of target regions, a target region linked list list and an identifier of a currently used target region; wherein the region linked list list includes at least one region linked list, the target region linked list includes an identifier of a target region, a state of the target region and a linked list pointer of a next target region linked list.

[0180] FIG. 12 is a target region data structure provided by an embodiment of the present disclosure, and it is to be noted that FIG. 12 takes the target region as an SLC region as an example for illustration. Referring to FIG. 12, a target region data structure named struct f2fs_SLC_ZONE_info is created in F2FS, and in the target region data structure, slc_zone_count represents the number of SLC regions in the memory. current_slc_zone_id represents the identification of the SLC region used by the current hot data. struct SLC_NAND slc_nand_zone represents an SLC region linked list list, and the SLC region linked list list records the information of all SLC regions. In the target region linked list, ZONE_ID represents the identification of the SLC region, and ZONE_CONDITION represents the state of the SLC region. Specifically, the state of the SLC region includes an empty state (1h: EMPTY), an open state (2h: OPEN), and a full state (Eh: FULL). SLC_NAND*next represents a linked list pointer of the next SLC region linked list.

[0181] In some embodiments, the host processor is configured to: send the first command to the memory controller through the second interface in a preset scenario; the preset scenario includes at least one of the following: a file system initialization stage, a case where information of the target region is not acquired through the second command, and a case where a state of a currently used target region in the target region data structure is a full state.

[0182] FIG. 13 is a flowchart of a method for operating a host according to an embodiment of the present disclosure. Referring to FIG. 13, in an embodiment of the present disclosure, at step S1201, F2FS is initialized. At step S1302, the host processor can be configured to send a second command to the memory system. In this way, the host processor can obtain information of each region in the memory through the second command. At step S1303, whether there is a target region in the memory is determined according to the reporting region parameter data including the storage mode information. Exemplarily, the target region is an SLC region. If there is an SLC region in the memory, the host processor records the information of the target region in the target region data structure at step S1304. If there is no SLC region in the memory, the host processor is configured to send a first command to the memory system to instruct the memory processor to configure at least one region in the memory as an SLC region through the first command at step S1305. Here, since the memory controller can be instructed to switch the storage mode of a specified region to a target storage mode through the first command, the mode switching information generated by the host can indicate that the target storage mode is the first storage mode, and the first command carrying the identifier of the specified region and the mode switching information of the specified region can instruct the memory controller to switch the storage mode of the specified region to the first storage mode, so that the target region can be configured through the first command.

[0183] At step S1306, the host processor sends the second command to the memory system again to obtain the reporting region parameter data including the storage mode information again. Since the SLC region has been configured through the first command before step 1306, the reporting region parameter data obtained through step 1306 has information of the SLC region, based on which, at step S1307, the information in the target region data structure is updated according to the latest information of the target region. That is, the information of the SLC region configured through step 1305 is updated to the target region data structure.

[0184] At step S1308, when the host needs to write data to the memory, the host processor can determine the hotness attribute of the write data through F2FS. Then, the host processor generates a corresponding region write request according to the hotness attribute of the write data, and sends the write data and the region write request to the memory system at step S1309. At this time, if the write data is determined to be hot data, the region write request instructs to write the write data to the SLC region. If the write data is determined to be non-hot data, the region write request instructs to write the write data to a non-target region. Exemplarily, the non-target region is a TLC region.

[0185] In a specific embodiment, when the host processor determines that the write data is hot data through the F2FS, the host processor can send the write data and a region write request to the memory system according to the current_slc_zone_id in the target region data structure, to instruct writing the write data to the SLC region corresponding to the identifier. In other words, if the host processor determines that the write data is hot data through the F2FS, the host processor sends the hot data and a region write request to the memory system, wherein the region write request includes the identifier of the SLC region in a non-full state (e.g., empty state or open state) currently used by the hot data. For example, if the host processor determines that the write data is hot data through the F2FS for the first time, the region write request includes the identifier of the first SLC region in a non-full state pointed to after the F2FS is initialized.

[0186] In the embodiments of the present disclosure, after the current hot data is written into the memory, if the SLC region used by the current hot data is in a full state, the current_slc_zone_id in the target region data structure points to the next SLC region in a non-full state for writing the next hot data. It should be noted that at this time, if there is no SLC region in a non-full state in the memory that can be used to write hot data, the host processor needs to send a first command to the memory system to configure at least one region in a non-full state as an SLC region.

[0187] When the host processor determines that the write data is non-hot data through the F2FS, the host processor can sequentially select a region in a non-full state and traverse the SLC region linked list in the target region data structure to determine whether the currently selected region is an SLC region. If it is determined that the region is an SLC region, the region is skipped and the next region is selected until a TLC region, i.e., a region in the second storage mode, is found. Then, at step S1309, the write data and a region write request are sent to instruct writing the write data to the TLC region.

[0188] FIG. 14 is a flowchart of a second method of operating a host according to an embodiment of the present disclosure. As shown in FIG. 14, in step S1401, the F2FS is initialized. In step S1402, the host processor can send a first command to the memory system. Here, the first command can be used to instruct to configure at least one region in the memory as a target region, so that there is at least one target region in the memory, and the target region is an SLC region, for example. In an example, the first command can be used to instruct to configure a first third of the plurality of regions in the memory as SLC regions. That is, the specified region is the first third of the plurality of regions in the memory, so that the memory controller can configure the first third of the plurality of regions in the memory as SLC regions based on the identification of the specified region in the first command.

[0189] In step S1403, the host processor sends a second command to the memory system to obtain information of the SLC region in the memory. In step S1404, the information of the SLC region is updated in the target region data structure.

[0190] In another embodiment of the present disclosure, in the case that the state of the SLC region currently used in the target region data structure is full, the host processor can send a first command to the memory system to instruct to configure at least one region in the memory as an SLC region. Then, the host processor sends a second command to the memory system to obtain information of all regions in the memory. According to the information of the SLC region in all regions obtained, the data in the target region data structure is updated.

[0191] It should be noted that in the embodiment of the present disclosure, after the host processor sends the first command to the memory system each time, the host processor also needs to send a second command to the memory system to update the data in the target region data structure.

[0192] In step S1405, the hotness attribute of the write data is determined. In the case that the write data is hot data, it is determined whether there is a writable SLC region in the region data structure. In the case that there is a writable SLC region in the region data structure, step S1406 is entered, that is, the write data and a first region write request are sent to the memory system to instruct the memory system to write the hot data to the SLC region. Here, the first region write request is used to instruct to write the write data to the SLC region.

[0193] If there is no writable SLC region in the region data structure, i.e., the state of the currently used SLC region is full, then step S1407 is entered. At step S1407, it is determined whether the largest continuous storage space in the remaining storage space of the memory system satisfies a preset condition. For example, the preset condition can be that the largest continuous storage space in the remaining storage space of the memory system is greater than or equal to the storage space occupied by two non-target regions, for example, the non-target regions are TLC regions. If the largest continuous storage space in the remaining storage space of the memory system satisfies the preset condition, then step S1408 is entered, and the host processor sends a first command to the memory system to configure at least one region of the largest continuous storage space in the remaining storage space as an SLC region. For example, half of the largest continuous storage space in the remaining storage space can be configured as an SLC region. Then, the host processor can send a second command to the memory system to update and maintain the target region data structure. In step S1409, the write data and the first region write request are sent to the memory system to instruct the memory system to write the hot data to the SLC region. If the largest continuous storage space in the remaining storage space of the memory system does not satisfy the preset condition, since the preset condition is not satisfied, the SLC region cannot be configured, and thus the host cannot allocate a writable SLC region for the hot data, so step S1410 is entered, and the write data and the second region write request are sent to the memory system to instruct the memory system to write the hot data to the TLC region.

[0194] If it is determined at step S1405 that the write data is non-hot data, then step S1411 is entered. At step S1411, the write data and the second region write request are sent to the memory system to instruct the memory system to write the non-hot data to the TLC region.

[0195] The above description of the system embodiments is similar to the description of the above memory system embodiments, and has similar beneficial effects as the memory system embodiments. For technical details not disclosed in the system embodiments of the present disclosure, please refer to the description of the memory system embodiments of the present disclosure for understanding.

[0196] FIG. 15 is a flowchart of an operation method of a memory system according to an embodiment of the present disclosure. Here, the specific structure and composition of the memory system can refer to the related structure and composition of the memory system 102 in FIGS. 1, 2A, and 2B. For brevity, the details are not repeated here. It should be understood that the operation steps shown in FIG. 15 can not be exhaustive, and other operation steps can also be performed before, after, or between any of the operation steps shown. In addition, some of the operation steps can be performed simultaneously, or in a different order from that shown in FIG. 15.

[0197] At step 1501, a first command is received through a first interface, wherein the first command comprises identification of a specified region and mode switching information of the specified region, and the region corresponds to a storage space of a memory, and the storage space of a single region is configured to support sequential writing.

[0198] At step 1502, the storage mode of the specified region is switched to a target storage mode indicated in the mode switching information according to the mode switching information through a memory controller.

[0199] In some embodiments, step 1502 comprises determining a current storage mode of the specified region, and in a case where the current storage mode is different from the target storage mode indicated in the mode switching information, switching the current storage mode to the target storage mode according to the mode switching information.

[0200] In some embodiments, the storage mode comprises a first storage mode and a second storage mode; when the region is in the first storage mode, each of the storage units corresponding to the storage space of the region is capable of being written with N-bit data; when the region is in the second storage mode, each of the storage units corresponding to the storage space of the region is capable of being written with M-bit data, M and N are integers greater than or equal to 1, and M is greater than N.

[0201] In some embodiments, step 1502 comprises determining the specified region according to the identification of the specified region, switching the specified region from the first storage mode to the second storage mode according to the mode switching information, or switching the specified region from the second storage mode to the first storage mode according to the mode switching information.

[0202] In some embodiments, at step 1503, a region write request and write data are received through the first interface, if the write data is hot data, the region write request is used to indicate that the write data is written to a region with the first storage mode, if the write data is non-hot data, the write data is written to a region with the second storage mode, and the write data is written to the storage space of the corresponding region according to the region write request.

[0203] In some embodiments, at step 1504, a second command is received through the first interface, the second command comprises mode recovery information, the mode recovery information is used to indicate whether the storage mode information needs to be returned, and report region parameter data satisfying the indication of the mode recovery information is generated according to the second command. It should be noted that there is no obvious sequence relationship between step 1504 and step 1503, and step 1504 can occur before step 1501 or after step 1501.

[0204] In some embodiments, the mode reply information is used to indicate a case where the stored mode information needs to be returned, and step 1504 comprises: generating, according to the second command, report area parameter data comprising the stored mode information.

[0205] In some embodiments, the stored mode information is located in an area descriptor in the report area parameter data.

[0206] In some embodiments, the stored mode information occupies a four-bit field in the area descriptor.

[0207] In some embodiments, the report area parameter data comprises an area descriptor list and a common descriptor; the area descriptor list comprises at least one area descriptor, and the area descriptor is used to indicate the self attribute of the corresponding area; and the common descriptor is used to indicate the common attribute of multiple areas.

[0208] In some embodiments, the area descriptor further comprises an area type field, an area state field, an area length field, an area start logical block address field, and a write pointer logical block address field.

[0209] In some embodiments, the common descriptor comprises an area list length field, a same field, and a maximum logical block address field.

[0210] In some embodiments, the first command comprises a reset write pointer command, and the mode switching information occupies a two-bit field in the reset write pointer command.

[0211] In some embodiments, the second command comprises a report area command.

[0212] In some embodiments, the area is an area in a zone namespace (ZNS).

[0213] In some embodiments, before step 1502, the method further comprises step 1505: resetting, according to the first command, the state of the specified area to an empty state.

[0214] The above description of the operation method of the memory system embodiments is similar to the description of the above memory system embodiments, and has similar beneficial effects as the memory system embodiments. For technical details not disclosed in the operation method of the memory system embodiments of the present disclosure, please refer to the description of the memory system embodiments of the present disclosure for understanding.

[0215] In the embodiments of the present disclosure, on the host side: by adding mode switching information in the reset write pointer command, the mode switching information can be set based on actual needs, so as to control the target storage mode of the specified area. Correspondingly, on the memory system side: based on the mode switching information in the reset write pointer command, the storage mode of the specified area can be switched to the target storage mode indicated in the mode switching information. In the embodiments of the present disclosure, the existing ZBC command can be used to realize the switching of the specified area between the first storage mode and the second storage mode.

[0216] In the embodiments of the present disclosure, the storage mode information of each area in the zone namespace (ZNS) can be obtained through the report area command, so that the storage mode of each area can be obtained. In this way, when data is written, the hot data can be selectively allocated to the area with the first storage mode based on the hot attribute of the written data, and the non-hot data can be allocated to the area with the second storage mode. In this way, the writing speed and reading speed of the hot data can be improved.

[0217] In the embodiments of the present disclosure, the target area data structure is provided in the host, and the target area data structure can be used to manage the information of the target area with the first storage mode. Meanwhile, the host can obtain the information of each area of the ZNS (including the storage mode information) through the first command, so as to obtain the information of the target area and maintain the target area data structure based on the information of the target area.

[0218] The embodiments of the present disclosure also provide a computer readable storage medium, and the computer readable storage medium stores a computer program. When the computer program is executed, the operation method of the memory system is realized.

[0219] In some embodiments, the computer-readable storage medium can be a ferromagnetic random access memory (FRAM), a read only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a flash memory, a magnetic surface storage, an optical disc, or a compact disc read-only memory (CD-ROM), and the like. It can also be various devices including one or any combination of the above memories.

[0220] In some embodiments, the computer program can be in the form of a program, software, a software module, a script, or code, written in any form of programming language, including compiled or interpreted languages, or declarative or procedural languages, and it can be deployed in any form, including as a stand-alone program or as a module, component, subroutine, or other unit suitable for use in a computing environment.

[0221] As an example, a computer program can, but need not, correspond to a file in a file system. A program can be stored in a portion of a file that holds other programs or data, e.g., one or more scripts stored in a markup language document, in a single file dedicated to the program in question, or in multiple coordinated files, e.g., files that store one or more modules, sub programs, or portions of code.

[0222] As an example, a computer program can be deployed for execution on one computer, or on multiple computers of a system or grid, or across multiple locations and multiple computers via a communications network, for example.

[0223] It should be understood that the reference herein to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the disclosure. The appearances of "in one embodiment" or "in an embodiment" in various places in the specification are not necessarily all referring to the same embodiment. Furthermore, various specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that the sequence of the processes described above does not mean the order of execution, and the execution order of the processes should be determined according to the functions and inherent logic, and should not constitute any limitation on the implementation process of the embodiments of the disclosure. The sequence of the above embodiments of the disclosure is only for description, and does not represent the advantages or disadvantages of the embodiments.

[0224] The preferred embodiments of the disclosure described above are merely preferred but not limitative of the patent scope of the disclosure, and any equivalent structural changes made according to the disclosure, or directly / indirectly applied to other related technical fields, are included in the patent protection scope of the disclosure.

Claims

1. A memory system, comprising: a memory and a memory controller coupled with the memory, the memory controller configured to control the memory to store by zone, wherein a storage space of a single zone is configured to support sequential write; wherein the memory controller is configured with a first interface for coupling with a host and receives a first command from the host through the first interface, the first command comprising an identification of a specified zone and mode switching information of the specified zone; the memory controller is further configured to switch a storage mode of the specified zone to a target storage mode indicated in the mode switching information according to the mode switching information.

2. The memory system of claim 1, wherein, the memory controller is configured to determine a current storage mode of the specified zone, and in a case that the current storage mode is different from the target storage mode indicated in the mode switching information, switch the current storage mode to the target storage mode according to the mode switching information.

3. The memory system according to claim 1 or 2, wherein the storage mode comprises a first storage mode and a second storage mode; when the zone is in the first storage mode, each of storage units corresponding to the storage space of the zone is capable of being written with N-bit data; when the zone is in the second storage mode, each of storage units corresponding to the storage space of the zone is capable of being written with M-bit data, M and N are integers greater than or equal to 1, and M is greater than N.

4. The memory system of claim 3, wherein, the memory controller is configured to determine the specified zone according to the identification of the specified zone; switch the specified zone from the first storage mode to the second storage mode according to the mode switching information, or switch the specified zone from the second storage mode to the first storage mode according to the mode switching information.

5. The memory system of claim 3, wherein, the memory controller is further configured to receive a zone write request and write data through the first interface, wherein if the write data is hot data, the zone write request is used to indicate that the write data is written to a zone with a first storage mode, and if the write data is non-hot data, the zone write request is used to indicate that the write data is written to a zone with a second storage mode; and write the write data into a storage space of a corresponding zone according to the zone write request.

6. The memory system of claim 1, wherein, the memory controller is configured to reset a state of the specified zone to an empty state according to the first command.

7. The memory system of claim 1, wherein, the first command comprises a reset write pointer command, and the mode switching information occupies two bit fields in the reset write pointer command.

8. The memory system of claim 1, wherein, the zone is a zone in a zone namespace (ZNS).

9. The memory system of claim 1, wherein, the memory controller is further configured to receive a second command through the first interface, the second command comprising mode recovery information, the mode recovery information being used to indicate whether storage mode information needs to be returned; and generate report zone parameter data satisfying an indication of the mode recovery information according to the second command.

10. The memory system of claim 9, wherein, The memory controller is configured to generate the report area parameter data including the storage mode information according to the second command in a case where the mode recovery information indicates that the storage mode information needs to be returned.

11. The memory system of claim 10, wherein, The storage mode information is located in a region descriptor in the report area parameter data.

12. The memory system of claim 11, wherein, The storage mode information occupies four bit fields in the region descriptor.

13. The memory system of claim 11, wherein, The report area parameter data includes a region descriptor list and a common descriptor; the region descriptor list includes at least one region descriptor, and the region descriptor is used to indicate the self attribute of the corresponding region; and the common descriptor is used to indicate the common attribute of a plurality of regions.

14. The memory system of claim 11, wherein, The region descriptor further includes a region type field, a region state field, a region length field, a region start logical block address field, and a write pointer logical block address field.

15. The memory system of claim 13, wherein, The common descriptor includes a region list length field, a same field, and a maximum logical block address field.

16. The memory system of claim 9, wherein, The second command includes a report region command.

17. A system comprising a memory system and a host, wherein The memory system comprises: a memory and a memory controller coupled with the memory, the memory controller being configured to control the memory to store in a region-by-region manner, wherein the storage space of a single region is configured to support sequential writing; wherein the memory controller is configured with a first interface for coupling with the host and receives a first command from the host through the first interface, the first command including the identification of a specified region and the mode switching information of the specified region; The host includes a host controller and a second interface for coupling with the memory controller, and the host controller is configured to generate the first command and send the first command to the memory controller through the second interface.

18. The system of claim 17, wherein, The memory controller is further configured to switch the storage mode of the specified region to the target storage mode indicated in the mode switching information.

19. The system of claim 18, wherein, The memory controller is configured to: determine the current storage mode of the specified region, and in a case where the current storage mode is different from the target storage mode indicated in the mode switching information, switch the current storage mode to the target storage mode according to the mode switching information.

20. The system of claim 17 or 18, wherein, The storage mode includes a first storage mode and a second storage mode; when the region is in the first storage mode, each of the storage units corresponding to the storage space of the region can be written with N-bit data; When the region is in the second storage mode, each of the storage units corresponding to the storage space of the region can be written with M-bit data, M and N are integers greater than or equal to 1, and M is greater than N.

21. The system of claim 20, wherein, The memory controller is configured to: determine the specified region according to the identification of the specified region; switch the specified region from the first storage mode to the second storage mode according to the mode switching information, or switch the specified region from the second storage mode to the first storage mode according to the mode switching information.

22. The system of claim 20, wherein, The host is configured with a file system; The host controller is configured to determine the hotness attribute of the write data through the file system, generate a corresponding area write request according to the hotness attribute of the write data, and send the write data and the area write request to the memory controller through the second interface; if the write data is hot data, the area write request is used to instruct writing the write data to an area with the first storage mode, and if the write data is non-hot data, the area write request is used to instruct writing the write data to an area with the second storage mode; The memory controller is configured to write the write data into the storage space of the corresponding area according to the area write request.

23. The system of claim 20, wherein, The host controller is configured to send a second command to the memory controller through the second interface, the second command including mode return information, the mode return information being used to indicate whether storage mode information needs to be returned; The memory controller is configured to receive the second command through the first interface, and generate and send report area parameter data satisfying the indication of the mode return information to the host controller according to the second command.

24. The system of claim 23, wherein, The memory controller is configured to: The mode return information is used to indicate that the storage mode information needs to be returned, and the memory controller is configured to generate and send the report area parameter data including the storage mode information to the host controller according to the second command.

25. The system of claim 24, wherein, The storage mode information is located in an area descriptor in the report area parameter data.

26. The system of claim 25, wherein, The report area parameter data includes an area descriptor list and a common descriptor; the area descriptor list includes at least one area descriptor, and the area descriptor is used to indicate the self attribute of the corresponding area; and the common descriptor is used to indicate the common attribute of the plurality of areas.

27. The system of claim 25, wherein, The area descriptor further includes an area type field, an area state field, an area length field, an area start logical block address field, and a write pointer logical block address field.

28. The system of claim 26, wherein, The common descriptor includes an area list length field, a SAME field, and a maximum logical block address field.

29. The system of claim 24, wherein, The host is configured with a file system; and the host processor is configured to establish a target area data structure through the file system, the target area data structure being used to store information of a target area, the target area being an area with the first storage mode; According to the report area parameter data including the storage mode information, the information of the target area is obtained; The information of the target area is stored into the target area data structure.

30. The system of claim 29, wherein, The target area data structure is used to store the number of target areas, a target area linked list list, and the identification of the currently used target area; wherein the area linked list list includes at least one area linked list, and the target area linked list includes the identification of the target area, the state of the target area, and the linked list pointer of the next target area linked list.

31. The system of claim 29, wherein, The host processor is configured to: In a preset scenario, the first command is sent to the memory controller through the second interface; the preset scenario includes at least one of the following: a file system initialization stage, a case where the information of the target area is not acquired through the second command, and a case where the state of the currently used target area in the target area data structure is a full state.

32. The system of claim 31, wherein, The host processor is configured to: determine that the state of the currently used target area in the target area data structure is a full state, and acquire the remaining space of the memory; according to the fact that the maximum continuous space in the remaining space meets a preset condition, send the first command to the memory controller.

33. The system of claim 29, wherein, The information of the target area includes the identification of the target area, the state of the target area, and the identification of the currently used target area.

34. The system of claim 22 or 29, wherein, The file system includes a flash-friendly file system (F2FS).

35. The system of claim 17, wherein, The first command includes a reset write pointer command, and the mode switching information occupies two bit fields in the reset write pointer command.

36. The system of claim 18, wherein, The memory controller is configured to: reset the state of the specified area to an empty state according to the first command.

37. The system of claim 23, wherein, The second command includes a report area command.

38. The system of claim 25, wherein, The storage mode information occupies four bit fields in the area descriptor.

39. The system of claim 17, wherein, The area is an area in an area namespace (ZNS).

40. An operating method of a memory system, the memory system including a memory and a memory controller coupled with the memory, the memory controller being configured with a first interface for coupling with a host, the method comprising: receiving a first command through the first interface; wherein the first command includes identification of a specified area and mode switching information of the specified area, the area corresponding to a storage space of the memory, and the storage space of a single area being configured to support sequential writing; switching, by the memory controller, a storage mode of the specified area to a target storage mode indicated in the mode switching information according to the mode switching information.

41. The method of claim 40, wherein, The switching of the storage mode of the specified area to the target storage mode indicated in the mode switching information according to the mode switching information includes: determining a current storage mode of the specified area, and switching the current storage mode to the target storage mode according to the mode switching information in a case where the current storage mode is different from the target storage mode indicated in the mode switching information.

42. The method of claim 40 or 41, wherein: the storage mode includes a first storage mode and a second storage mode; when the area is in the first storage mode, each of the storage units corresponding to the storage space of the area can be written with N-bit data; when the area is in the second storage mode, each of the storage units corresponding to the storage space of the area can be written with M-bit data, M and N being integers greater than or equal to 1, and M greater than N.

43. The method of claim 42, wherein, The switching of the storage mode of the specified area to the target storage mode indicated in the mode switching information according to the mode switching information includes: determining the specified region according to the identification of the specified region; switching the specified region from the first storage mode to the second storage mode according to the mode switching information, or switching the specified region from the second storage mode to the first storage mode according to the mode switching information.

44. The method of claim 42, wherein, The method further comprises: receiving a region write request and write data through the first interface, wherein if the write data is hot data, the region write request is used to indicate that the write data is written to a region with a first storage mode, and if the write data is non-hot data, the write data is written to a region with a second storage mode; writing the write data into a storage space of a corresponding region according to the region write request.

45. The method of claim 42, wherein, The method further comprises: receiving a second command through the first interface, wherein the second command comprises mode recovery information used to indicate whether storage mode information needs to be returned, and generating report region parameter data satisfying an indication of the mode recovery information according to the second command.

46. The method of claim 45, wherein, If the mode recovery information is used to indicate that the storage mode information needs to be returned, the generating the report region parameter data satisfying the indication of the mode recovery information according to the second command comprises generating the report region parameter data comprising the storage mode information according to the second command.

47. The method of claim 46, wherein, The storage mode information is located in a region descriptor in the report region parameter data.

48. The method of claim 47, wherein, The storage mode information occupies four bit fields in the region descriptor.

49. The method of claim 46, wherein, The report region parameter data comprises a region descriptor list and a common descriptor, wherein the region descriptor list comprises at least one region descriptor used to indicate self attributes of a corresponding region, and the common descriptor is used to indicate common attributes of the plurality of regions.

50. The method of claim 46, wherein, The region descriptor further comprises a region type field, a region state field, a region length field, a region start logical block address field, and a write pointer logical block address field.

51. The method of claim 49, wherein, The common descriptor comprises a region list length field, a same field, and a maximum logical block address field.

52. The method of claim 40, wherein, The first command comprises a reset write pointer command, and the mode switching information occupies two bit fields in the reset write pointer command.

53. The method of claim 45, wherein, The second command comprises a report region command.

54. The method of claim 40, wherein, The region is a region in a region namespace (ZNS).

55. The method of claim 40, wherein, The method further comprises: resetting a state of the specified region to an empty state according to the first command. 56.A computer readable storage medium, wherein a computer program is stored on the computer readable storage medium, and the computer program is executed to implement the method in any one of claims 40 to 55.

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