Storage array and manufacturing method therefor, memory, and electronic device

Abstract

Embodiments of the present application relate to the technical field of semiconductors, and disclose a storage array and a manufacturing method therefor, a memory, and an electronic device. The storage array comprises a ferroelectric capacitor. The ferroelectric capacitor comprises a first electrode layer, a second electrode layer, a first ferroelectric layer, a first electric-dipole interlayer, and electron-injection interlayers. The second electrode layer is disposed opposite to the first electrode layer. The first ferroelectric layer is located between the first electrode layer and the second electrode layer. The first electric-dipole interlayer is located between the first ferroelectric layer and the second electrode layer. The electron-injection interlayers are located between the first ferroelectric layer and the first electric-dipole interlayer. The resistivity of the material of the electron-injection interlayers is less than the resistivity of the material of the first electric-dipole interlayer. On the basis of using the first electric-dipole interlayer to increase a storage window and reduce an operating voltage and power consumption, the electron-injection interlayers can be used to introduce a large number of free electrons, thereby improving the imprint, retention, and endurance characteristics of the storage array and the memory to which the storage array is applied.

Description

Storage array and preparation method thereof, memory, and electronic device

[0001] The present application claims priority from the Chinese patent application No. 202411083454.X, filed on August 7, 2024, and entitled "Storage array and preparation method thereof, memory, and electronic device", the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] The present application relates to the technical field of semiconductor technology, and in particular to a storage array and a preparation method thereof, a memory, and an electronic device. BACKGROUND

[0003] Ferroelectric random access memory (FeRAM) is a new type of memory, which has been widely concerned due to its fast read-write speed, non-volatile storage of data, low power consumption, and compatibility with CMOS (complementary metal-oxide semiconductor) process.

[0004] However, during the cyclic use of FeRAM, problems such as imprint, retention, and endurance deterioration are prone to occur. SUMMARY

[0005] Embodiments of the present application provide a storage array and a preparation method thereof, a memory, and an electronic device, which are used to improve the imprint of the storage array and the memory applied thereto, and to improve the retention and endurance of the storage array and the memory applied thereto.

[0006] To achieve the above-mentioned purpose, embodiments of the present application adopt the following technical solutions:

[0007] In a first aspect, a storage array is provided, which can be a two-dimensional structure or a three-dimensional structure. Furthermore, the storage array can be applied to FeRAM, ferroelectric field effect transistor memory, or ferroelectric tunnel junction (FTJ) memory to realize reading and writing of data.

[0008] The ferroelectric capacitor includes a first electrode layer, a second electrode layer, a first ferroelectric layer, a first electric dipole interlayer, and an electron injection interlayer. The second electrode layer is disposed opposite to the first electrode layer. The first ferroelectric layer is located between the first electrode layer and the second electrode layer. The first electric dipole interlayer is located between the first ferroelectric layer and the second electrode layer. The electron injection interlayer is located between the first ferroelectric layer and the first electric dipole interlayer. The resistivity of the material of the electron injection interlayer is less than the resistivity of the material of the first electric dipole interlayer. That is, the free electron concentration in the electron injection interlayer is higher than the free electron concentration in the first electric dipole interlayer.

[0009] The storage array provided by some embodiments of the present application can increase the polarization charge amount, the remanent polarization intensity, and the storage window by providing the first electric dipole interlayer between the first ferroelectric layer and the second electrode layer. In this way, the electric dipoles in the first electric dipole interlayer can migrate in response to the flipping of the applied electric field generated by the first electrode layer and the second electrode layer, and contribute to the polarization charge amount, thereby increasing the polarization charge amount, the remanent polarization intensity, and the storage window. In addition, the electric field generated by the electric dipoles in the first electric dipole interlayer can assist the flipping of the ferroelectric domains of the first ferroelectric layer, thereby reducing the coercive field, the operating voltage, and the power consumption.

[0010] Further, the electron injection interlayer provided between the first electric dipole interlayer and the first ferroelectric layer can introduce more free electrons. In this way, the ferroelectric capacitor can be provided with shielding charges, and the depolarization field generated in the first ferroelectric layer can be weakened or even shielded, thereby improving the retention characteristics of the storage array and the memory applied thereto. In addition, the free electrons in the electron injection interlayer can combine with the positively charged oxygen vacancies at the interface, thereby weakening the built-in electric field in the first ferroelectric layer and improving the imprint impression. Furthermore, the defect energy level provided by the electron injection interlayer is shallow, which can reduce the number of trapped and accumulated electrons, suppress the charge trapping caused by the interface defects, and improve the durability of the retention characteristics of the storage array and the memory applied thereto.

[0011] In a possible design of the first aspect, the ferroelectric capacitor further includes a second ferroelectric layer located between the electron injection interlayer and the first electric dipole interlayer. The first ferroelectric layer and the second ferroelectric layer can be, for example, a complete ferroelectric film, and the electron injection interlayer can be, for example, an interlayer embedded in the ferroelectric film. In this case, the electron injection interlayer can effectively improve the retention characteristics and the durability of the memory, and effectively alleviate the imprint impression problem.

[0012] In a possible design of the first aspect, the ferroelectric capacitor further includes a second electric dipole interlayer between the electron injection interlayer and the first ferroelectric layer. The resistivity of the material of the electron injection interlayer is less than the resistivity of the material of the second electric dipole interlayer. The second electric dipole interlayer and the first electric dipole interlayer may, for example, be a complete electric dipole film, and the electron injection interlayer may, for example, be an interlayer embedded in the electric dipole film. In this case, the free electrons in the electron injection interlayer can be injected into the second electric dipole interlayer, not only effectively shielding the depolarization field in the first ferroelectric layer and improving the poor retention characteristics of the memory, but also enabling the free electrons to combine with oxygen vacancies at the contact interface between the first ferroelectric layer and the second electric dipole interlayer, effectively alleviating the imprint problem.

[0013] In a possible design of the first aspect, the number of electron injection interlayers is multiple. The ferroelectric capacitor further includes a second ferroelectric layer and / or a second electric dipole interlayer between any two adjacent electron injection interlayers. The resistivity of the material of the electron injection interlayer is less than the resistivity of the material of the second electric dipole interlayer.

[0014] In a possible design of the first aspect, the material of the second electric dipole interlayer is the same as that of the first electric dipole interlayer. This facilitates simplification of the preparation process of the memory array and the memory applied thereto, and improves the preparation efficiency of the memory array and the memory applied thereto.

[0015] In a possible design of the first aspect, the resistivity of the material of the electron injection interlayer is less than or equal to 200 μΩ·cm. This ensures a high concentration of free electrons in the electron injection interlayer, ensures that the electron injection interlayer can provide more free electrons, and ensures the improvement effect on the imprint problem and the poor retention characteristics and durability.

[0016] In a possible design of the first aspect, the material of the electron injection interlayer includes at least one of a metal material, a metal nitride material, or a metal oxide material.

[0017] In a possible design of the first aspect, the material of the electron injection interlayer includes at least one of aluminum, molybdenum, tungsten, nickel, platinum, titanium, tantalum, titanium nitride, zirconium nitride, hafnium nitride, niobium nitride, indium tin oxide, antimony tin oxide, or indium gallium zinc oxide.

[0018] In a possible design of the first aspect, the thickness of the electron injection interlayer ranges from 0.1 nm to 2 nm. This not only reduces the impact on the thickness of the ferroelectric memory, but also ensures that the electron injection interlayer can improve a large number of free electrons.

[0019] In a possible design of the first aspect, the first electrode layer and the second electrode layer are both planar electrodes. The first electrode layer, the first ferroelectric layer, the electron injection interlayer, the first electric dipole interlayer, and the second electrode layer are sequentially stacked along a thickness direction of the first electrode layer. In this case, the ferroelectric capacitor has a two-dimensional planar structure, and is easy to manufacture, which is conducive to reducing the manufacturing difficulty of the storage array or the memory.

[0020] In a possible design of the first aspect, the first electrode layer is a planar electrode, and the second electrode layer is a columnar electrode. The second electrode layer penetrates through the first electrode layer, the first electric dipole interlayer surrounds the second electrode layer, the electron injection interlayer surrounds the first electric dipole interlayer, and the first ferroelectric layer surrounds the electron injection interlayer. In this case, the ferroelectric capacitor has a three-dimensional structure, which can reduce the occupied area and is conducive to improving the storage density of the storage array or the memory.

[0021] In a possible design of the first aspect, the material of the first electric dipole interlayer includes at least one of tantalum oxide, aluminum oxide, titanium oxide, niobium oxide, lanthanum oxide, molybdenum oxide, tungsten oxide, or tantalum nitride.

[0022] In a second aspect, a preparation method of a storage array is provided, including: forming a first electrode layer; forming a first ferroelectric layer on one side of the first electrode layer; forming an electron injection interlayer on a side of the first ferroelectric layer away from the first electrode layer; forming a first electric dipole interlayer on a side of the electron injection interlayer away from the first electrode layer; the resistivity of the material of the electron injection interlayer is less than the resistivity of the material of the first electric dipole interlayer; and forming a second electrode layer on a side of the first electric dipole interlayer away from the first electrode layer.

[0023] In a possible design of the second aspect, before the first electric dipole interlayer is formed on the side of the electron injection interlayer away from the first electrode layer, the preparation method further includes: forming a second ferroelectric layer on the side of the electron injection interlayer away from the first electrode layer.

[0024] In a possible design of the second aspect, before the electron injection interlayer is formed on the side of the first ferroelectric layer away from the first electrode layer, the preparation method further includes: forming a second electric dipole interlayer on the side of the first ferroelectric layer away from the first electrode layer. The resistivity of the material of the electron injection interlayer is less than the resistivity of the material of the second electric dipole interlayer.

[0025] In a third aspect, a memory is provided, including: a storage array and a controller electrically connected with the storage array. The storage array is the storage array in any of the embodiments of the first aspect.

[0026] In a fourth aspect, an electronic device is provided, comprising a memory and a circuit board electrically connected with the memory. The memory is any of the memories according to the third aspect.

[0027] The technical effects brought by any of the design manners of the second aspect to the fourth aspect can refer to the technical effects brought by different design manners of the first aspect, which will not be repeated here. BRIEF DESCRIPTION OF DRAWINGS

[0028] FIG. 1 is an architecture diagram of an electronic device according to an embodiment of the present application;

[0029] FIG. 2 is an architecture diagram of a memory according to an embodiment of the present application;

[0030] FIG. 3 is an architecture diagram of another memory according to an embodiment of the present application;

[0031] FIG. 4 is an architecture diagram of yet another memory according to an embodiment of the present application;

[0032] FIG. 5 is an equivalent circuit diagram of a memory cell according to an embodiment of the present application;

[0033] FIG. 6 is a structure diagram of a ferroelectric capacitor according to an embodiment of the present application;

[0034] FIG. 7 is a structure diagram of another ferroelectric capacitor according to an embodiment of the present application;

[0035] FIG. 8 is an equivalent circuit diagram of a memory array according to an embodiment of the present application;

[0036] FIG. 9 is a structure diagram of a memory array cell in the memory array shown in FIG. 8;

[0037] FIG. 10 is a structure diagram of another memory array cell in the memory array shown in FIG. 8;

[0038] FIG. 11 is a structure diagram of yet another memory array cell in the memory array shown in FIG. 8;

[0039] FIG. 12 is a structure diagram of yet another memory array cell in the memory array shown in FIG. 8;

[0040] FIG. 13 is a structure diagram of yet another memory array cell in the memory array shown in FIG. 8;

[0041] FIG. 14 is a structure diagram of yet another memory array cell in the memory array shown in FIG. 8;

[0042] FIG. 15 is an equivalent circuit diagram of another memory array according to an embodiment of the present application;

[0043] Fig. 16a is a partial plan view of the memory array shown in Fig. 15;

[0044] Fig. 16b is a cross-sectional view of the structure shown in Fig. 16a along M-M';

[0045] Fig. 17 is a flow chart of a method for fabricating a memory array according to an embodiment of the present application;

[0046] Fig. 18 is a series of cross-sectional views of a method for fabricating a memory array according to an embodiment of the present application;

[0047] Fig. 19 is a series of cross-sectional views of another method for fabricating a memory array according to an embodiment of the present application;

[0048] Figs. 20a-20g are a series of cross-sectional views of yet another method for fabricating a memory array according to an embodiment of the present application. DETAILED DESCRIPTION

[0049] The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all of the embodiments of the present application.

[0050] In the description of the present application, "a plurality of" means two or more than two, unless otherwise specified. "At least one" or similar expressions mean any combination of the items, including any combination of single or multiple. For example, at least one of a, b or c can mean a, b, c, a-b, a-c, b-c, or a-b-c, where a, b, and c can be single or multiple.

[0051] In addition, in order to clearly describe the technical solutions in the embodiments of the present application, "first", "second", and the like are used in the embodiments of the present application to distinguish the same items or similar items with basically the same function and effect. Those skilled in the art can understand that "first", "second", and the like do not limit the quantity and execution order, and "first", "second", and the like do not necessarily mean different. Meanwhile, in the embodiments of the present application, "exemplary" or "for example" means to serve as an example, illustration or description. Any embodiment or design scheme described as "exemplary" or "for example" in the embodiments of the present application should not be interpreted as more preferred or more advantageous than other embodiments or design schemes. Rather, "exemplary" or "for example" is used to specifically present the relevant concept, so as to be easy to understand.

[0052] In the embodiments of the present application, unless specifically defined and limited otherwise, the term "connection" can be a direct mechanical or electrical connection, or an indirect mechanical or electrical connection through an intermediate medium. The mechanical connection herein can not limit whether it is used for transmitting electrical signals, and the electrical connection is used for transmitting electrical signals.

[0053] In the embodiments of the present application, "vertical" and "parallel" respectively represent approximately vertical and approximately parallel within a certain error range, which can be a range of less than or equal to 5°, 8° or 10° deviation angle with respect to absolute vertical and absolute parallel, which is not specifically limited here.

[0054] The present application describes exemplary embodiments with reference to cross-sectional views and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and regions are exaggerated for clarity. Therefore, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, the exemplary embodiments should not be construed as limited to the precise shapes of regions illustrated in this application, but are to include deviations in shapes that result from, for example, manufacturing. For example, an etched region illustrated as a rectangle will typically have curved or jagged features. Thus, the regions illustrated in the figures are schematic and not intended to be limiting of the scope of the exemplary embodiments in terms of the shapes of the regions illustrated. The exemplary embodiments are described herein with reference to cross-sectional and / or plan views that are idealized illustrations. The cross-sectional and / or plan views illustrated herein using broken lines indicate that some portions thereof are shown greatly exaggerated in height or width to facilitate an understanding of the exemplary embodiments. The cross-sectional and / or plan views illustrated herein using unbroken lines indicate other portions thereof illustrated with a degree of precision that is not necessarily to scale, and are thus intended to facilitate an understanding of the exemplary embodiments. Thus, the cross-sectional and / or plan views are schematic illustrations of the regions of the devices, and are not intended to limit the scope of the exemplary embodiments to the precise shapes of the regions illustrated. The exemplary embodiments are not limited to the precise cross-sectional and / or plan views illustrated herein, but can include other shapes as is desired in other exemplary embodiments.

[0055] In addition, the architecture and scenarios described in the embodiments of the present application are used to more clearly illustrate the technical solutions of the embodiments of the present application, and do not constitute a limitation on the technical solutions provided by the embodiments of the present application. It can be known by those skilled in the art that, as the architecture evolves and new scenarios appear, the technical solutions provided by the embodiments of the present application are also applicable to similar technical problems.

[0056] The electronic device provided by the embodiments of the present application can be applied to various communication systems or communication protocols, such as: Bluetooth (BT) communication technology, global positioning system (GPS) communication technology, global system of mobile communication (GSM) communication technology, wireless fidelity (WiFi) communication technology, wideband code division multiple access wireless (WCDMA) communication technology, long term evolution (LTE), 5G communication technology, and other future communication technologies.

[0057] The electronic device in the embodiments of the present application can be a mobile phone, a pad, a notebook computer, a smart home, a smart wearable device (for example, a smart watch, a smart bracelet, smart glasses, a smart helmet), a virtual reality (VR) electronic device, an augmented reality (AR) electronic device, and the like. The electronic device can also be a handheld device, a computing device, or other processing device connected to a wireless modem having a wireless communication function, a vehicle-mounted device, an electronic device in a 5G network or an electronic device in a future evolved public land mobile network (PLMN), and the like, and the embodiments of the present application are not limited thereto.

[0058] FIG. 1 is an architecture diagram of an electronic device provided by the embodiments of the present application. As shown in FIG. 1, the electronic device 1000 can include a circuit board 100, a bus 200, and a processor 300. The bus 200 is located on the circuit board 100 and is electrically connected to the circuit board 100. The processor 300 is located on the circuit board 100 and is connected to the bus 200. The circuit board 100 is, for example, a printed circuit board (PCB), and the processor 300 is, for example, a system on chip (SoC) which can be used to process data, such as processing data of an application program, processing image data, and buffering temporary data. Optionally, the system on chip can include an application processor (AP) 310 for processing an application program, a graphics processing unit (GPU) 320 for processing image data, and a first RAM 330 for buffering high-speed data. The first RAM 330 can be a static random access memory (SRAM) or an embedded flash (eflash), and the like. The above-mentioned application processor 300, image processing unit 320, and first RAM 330 can be integrated in one die, or can be respectively arranged in multiple dies.

[0059] Continuing to refer to FIG. 1, the electronic device 1000 can further include a second RAM 400, which can be connected to the processor 300 through the bus 200. The second RAM 400 can be a DRAM. The second RAM 400 can be used to store volatile data, such as temporary data generated by the on-chip system described above. The storage capacity of the second RAM 400 can generally be greater than that of the first RAM 330, but the read speed of the second RAM 400 can generally be slower than that of the first RAM 330.

[0060] In addition, the electronic device 1000 can further include a communication chip 500 and a power management chip 600, both of which are connected to the processor 300 through the bus 200. The communication chip 500 can be used for processing of a protocol stack, or amplification, filtering, etc. of analog radio frequency signals, or both. The power management chip 600 can be used to power other chips. Illustratively, the on-chip system and the second RAM 400 can be packaged in the same packaging structure, such as a 2.5D or 3D packaging, etc. to package the on-chip system and the second RAM 400, so as to obtain a faster inter-chip data transmission rate.

[0061] Embodiments of the present application also provide a memory applied to the electronic device described above. In some embodiments, the memory can be used as the first RAM 330 in FIG. 1, or as the second RAM 400 in FIG. 1. Embodiments of the present application do not limit the application scenarios of the memory described above.

[0062] In some examples, as shown in FIGS. 2 and 3, the memory 700 described above can include a storage array 710 and a controller 720 for accessing the storage array 710, the controller 720 being electrically connected to the storage array 710, and the controller 720 can be used to control the read and write operations of the storage array 710. The number of storage arrays 710 can be one, two, three or even more. Both FIGS. 2 and 3 show four storage arrays 710.

[0063] Illustratively, as shown in FIG. 2, in the memory 700 described above, the storage array 710 and the controller 720 can be two independent chips from each other, and the storage array 710 and the controller 720 can be respectively arranged on a carrier board (such as a package transistor chain or a conversion board), and the storage array 710 and the controller 720 are respectively electrically connected to the carrier board. In this way, the storage array 710 and the controller 720 can realize signal transmission through the metal traces in the carrier board. Based on this, the memory 700 with the storage array 710 described above can be referred to as a stand-alone memory.

[0064] Alternatively, as an example, in the memory 700 described above, the memory array 710 and the controller 720 can be two independent chips, and the memory array 710 and the controller 720 are stacked on the carrier board. The memory array 710 and the controller 720 can be electrically connected through a through silicon via (TSV) or a redistribution layer (RDL), so that the memory array 710 and the controller 720 can transmit signals with the carrier board. Similarly, the memory 700 with the memory array 710 described above can be referred to as a stand-alone memory.

[0065] Alternatively, as another example, as shown in FIG. 3, in the memory 700 described above, the memory array 710 is stacked on the controller 720, and the memory array 710 and the controller 720 can be integrated into the same chip, and the integrated chip is electrically connected with the carrier board. Based on this, the memory 700 with the memory array 710 described above can be referred to as an embedded memory.

[0066] In some examples, as shown in FIG. 4, each memory array 710 in the memory 700 includes a plurality of memory cells 711 arranged in an array, where each memory cell 711 can be used to store 1 bit or multiple bits of data. The memory array 710 can also include signal lines such as word lines (WL) and bit lines (BL). Each memory cell 711 is electrically connected to a corresponding word line and bit line. Different memory cells 711 can be electrically connected through the word lines and the bit lines. One or more of the word lines and the bit lines are used to select the memory cell 711 to be read or written in the memory array 710 by receiving a control level output by a control circuit, so as to realize the read and write operations of data.

[0067] Continuing to refer to FIG. 4, the controller 720 in the memory 700 includes one or more circuit structures such as a decoder 721, a driver 722, a timing controller 723, a buffer 724, and an input-output driving circuit 725. The circuit structures in the controller 720 are electrically connected to the memory cells 711 in the memory array 710 through signal lines. The decoder 721 is configured to decode the address of the memory cells 711. The decoder 721 is configured to decode the received address to determine the memory cell 711 to be accessed. The driver 722 is configured to control the level of the signal lines according to the decoding result of the decoder 721, so as to realize the access to the specified memory cell 711. The buffer 724 is configured to buffer the read data, for example, a FIFO (first-in first-out) can be used for buffering. The timing controller 723 is configured to control the timing of the buffer 724, and control the driver 722 to drive the signal lines in the memory array 710. The input-output driving circuit 725 is configured to drive the transmission signal, for example, to drive the received data signal and drive the data signal to be sent, so that the data signal can be transmitted over a long distance.

[0068] The memory array 710, the decoder 721, the driver 722, the timing controller 723, the buffer 724, and the input-output driving circuit 725 can be integrated in one chip, or can be integrated in multiple chips respectively.

[0069] The type of the memory 700 provided in the embodiments of the present application includes multiple types. Optionally, the memory 700 includes but is not limited to FeRAM (also referred to as ferroelectric memory), ferroelectric field effect transistor memory, or ferroelectric tunnel junction memory, etc.

[0070] The memory 700 is taken as an example of FeRAM. The memory cell 711 of the memory array 710 can include ferroelectric material. The ferroelectric material can have spontaneous polarization, and the polarization direction of the ferroelectric material can change with the change of an applied electric field. Specifically, when an applied electric field is applied to the ferroelectric material, the central atoms stay in a low-energy state position along the direction of the electric field, and conversely, when an applied electric field is applied to the same ferroelectric material, the central atoms move in the crystal along the direction of the electric field and stay in another low-energy state position. A large number of central atoms move in the crystal cell to form ferroelectric domains, and the ferroelectric domains form polarization charges (also known as flip charges) under the action of an applied electric field. The flip charges formed by the flipping of the ferroelectric domains under the action of an applied electric field are relatively high, and the flip charges formed by the non-flipping of the ferroelectric domains under the action of an applied electric field are relatively low. The binary stable state of such ferroelectric material makes the ferroelectric material can be used as a memory, and the different flip charges generated by applying an electric field in the same direction can be used to store data "0" and "1" by using the difference in the direction of the residual polarization strength.

[0071] When an applied electric field is applied to the ferroelectric material crystal, the central atoms move in the crystal along the direction of the electric field. When the atoms move, they pass through an energy barrier, thereby causing charge breakdown. After the applied electric field is removed, the central atoms can remain in the same position, and the polarization state can be maintained. Therefore, the memory 700 formed by using the ferroelectric material has the characteristic of non-volatility, that is, the memory 700 will not lose the stored data when power is off.

[0072] The structure of the memory cell 711 in the memory array 710 includes a plurality of structures, and FIG. 5(a), (b), and (c) respectively show equivalent circuit diagrams of a memory cell 711. Of course, the structure of the memory cell 711 is not limited to the three structures shown in FIG. 5. In addition, FIG. 6 shows a structure diagram of a ferroelectric capacitor. As shown in FIG. 6, the ferroelectric capacitor C includes, for example, a first electrode layer 1 and a second electrode layer 2 arranged opposite to each other, and a ferroelectric material layer 3 located between the first electrode layer 1 and the second electrode layer 2. In the case where the materials of the first electrode layer 1 and the second electrode layer 2 both include metal materials, the ferroelectric capacitor C can constitute an MFM (metal ferroelectric metal) device structure.

[0073] In (a) of FIG. 5, the storage unit 711 includes one transistor Tr and one ferroelectric capacitor C. The gate of the transistor Tr is electrically connected with one electrode layer (e.g., the first electrode layer 1) of the ferroelectric capacitor C. During the operation of the memory 700, the storage state of the memory 700 can be determined by controlling the flipping of the ferroelectric domain in the ferroelectric capacitor C to regulate the high and low of the gate voltage of the transistor Tr, and then detecting the current of the transistor Tr. Thus, the structure shown in (a) of FIG. 5 can also be referred to as a 1T1C current sensing structure.

[0074] In (b) of FIG. 5, the storage unit 711 includes one transistor Tr and one ferroelectric capacitor C. The drain (or source) of the transistor Tr is electrically connected with one electrode layer (e.g., the first electrode layer 1) of the ferroelectric capacitor C. During the operation of the memory 700, the storage state of the memory 700 can be determined by detecting the current direction of the transistor Tr to determine the storage state of the ferroelectric capacitor C. The structure shown in (b) of FIG. 5 can also be referred to as a 1T1C charge sensing structure, which can be understood as replacing the capacitor in the traditional 1T1C DRAM (dynamic random access memory) with the ferroelectric capacitor C.

[0075] In (c) of FIG. 5, the storage unit 711 only includes one transistor Tr. The structure shown in (c) of FIG. 5 can also be referred to as a 1T0C structure, which can be understood as replacing the gate oxide dielectric in the traditional MOSFET (metal oxide semiconductor field effect transistor) with the ferroelectric material layer 3 or the composite dielectric layer containing the ferroelectric material layer 3. At this time, the gate of the transistor Tr can be the first electrode layer 1 or the second electrode layer 2, and the transistor Tr can be referred to as a FeFET (ferroelectric field effect transistor).

[0076] It can be understood that after the ferroelectric domain in the ferroelectric material flips multiple times, the remanent polarization Pr will decrease, the coercive field Ec will increase, and the amount of polarization charge will be less. This will cause the two storage states corresponding to “0” and “1” in the ferroelectric memory C to be closer and closer, reducing the memory window (MW) of the memory 700. Moreover, the increase of the coercive field Ec will also increase the external electric field required to flip the ferroelectric domain, and thus will increase the operating voltage and increase the power consumption.

[0077] Fig. 7 shows a structure diagram of another ferroelectric capacitor. As shown in Fig. 7, the ferroelectric capacitor C further comprises an electric dipole interlayer 4 disposed between the ferroelectric material layer 3 and the second electrode layer 2. Of course, the electric dipole interlayer 4 can also be disposed between the first electrode layer 1 and the ferroelectric material layer 3, which is not limited in the embodiments of the present application.

[0078] The material of the electric dipole interlayer 4 described above comprises an insulating material such as oxide and nitride, which comprises at least one of tantalum oxide (Ta2O5), aluminum oxide (Al2O3), titanium oxide (TiO2), niobium oxide (Nb2O5), lanthanum oxide (La2O3), molybdenum oxide (MoO3), tungsten oxide (WO3) or tantalum nitride (TaN). In the case that the material of the first electrode layer 1 and the second electrode layer 2 both comprises metal material, the ferroelectric capacitor C can constitute a MFIM (metal ferroelectric insulator semiconductor metal) device structure.

[0079] The electric dipole interlayer 4 comprises electric dipoles, which can generate electric field. In the case that the applied electric field generated by the first electrode layer 1 and the second electrode layer 2 is reversed, the electric dipoles in the electric dipole interlayer 4 can migrate in response to the reversal of the applied electric field, contribute part of the polarization charge amount, so that the total amount of the polarization induced current is equal to the sum of the induced current generated by the ferroelectric material polarization and the induced current of the electric dipoles, so as to increase the residual polarization strength, increase the distinction degree of the two storage states corresponding to "0" and "1" in the ferroelectric memory C, and increase the storage window of the memory 700.

[0080] In addition, the electric dipole interlayer 4 can also generate more electric dipoles in response to the applied electric field, and the ferroelectric domains are oriented and reversed under the action of the reversed applied electric field. The electric field generated by the electric dipoles can assist the reversal of the ferroelectric domains, so as to improve the efficiency of the reversal of the ferroelectric domains and reduce the coercive field Ec of the ferroelectric material, so as to reduce the applied electric field required for the reversal of the ferroelectric domains, and further reduce the operating voltage of the ferroelectric capacitor C, which is conducive to reducing the power consumption of the memory 700.

[0081] In the ferroelectric capacitor C shown in Fig. 6, there are more free charges (also referred to as free electrons) in the first electrode layer 1 and the second electrode layer 2, which can effectively shield the polarization charges in the ferroelectric material layer 3. However, in the ferroelectric memory C shown in Fig. 7, the material of the electric dipole interlayer 4 is an insulating material, and there are fewer free electrons in the electric dipole interlayer 4, so that the electric dipole interlayer 4 provides limited shield charges at the contact interface between the electric dipole interlayer 4 and the ferroelectric material layer 3, and it is difficult to effectively shield the polarization charges in the ferroelectric material layer 3, thereby resulting in a large depolarization field in the ferroelectric material layer 3. For example, in Fig. 7, the voltage applied to the first electrode layer 1 and the second electrode layer 2 forms an applied electric field Eapp, and there is a depolarization field Ed in the ferroelectric material layer 3. This will gradually weaken the storage state of the storage unit 711 over time, and reduce the retention characteristics of the memory 700.

[0082] Moreover, during the cyclic use of the memory 700, the existence of the large depolarization field Ed in the ferroelectric material layer 3 will cause a printing impression problem. That is, the interface charges will be separated from the interface oxygen vacancies, and charged oxygen vacancies will be formed on the surface of the ferroelectric material layer 3, thereby generating a persistent built-in electric field, which will cause the polarization direction of the ferroelectric material to be biased to a certain direction, resulting in one of the storage states being more obvious, and the other storage state being difficult to identify. In addition, the interface defects caused by the charged oxygen vacancies will also cause charge trapping, which will have a negative impact on the durability of the memory 700.

[0083] Based on this, embodiments of the present application further improve the structure of the ferroelectric capacitor. In which, Fig. 8 and Fig. 15 respectively show an equivalent circuit diagram of a storage array, Fig. 9 to Fig. 14 respectively show a structure diagram of a storage unit in the storage array shown in Fig. 8, Fig. 16a shows a partial top view structure diagram of the storage array shown in Fig. 15, and Fig. 16b shows a sectional structure diagram of the structure shown in Fig. 16a along the M-M' direction.

[0084] In some examples, as shown in FIG. 8 and FIG. 15, the storage array 710 includes ferroelectric capacitors C, and further includes transistors Tr electrically connected with the ferroelectric capacitors C. For example, as shown in FIG. 9 and FIG. 16a, the ferroelectric capacitor C includes a first electrode layer 1 and a second electrode layer 2 oppositely arranged, and the transistor Tr is electrically connected with the first electrode layer 1 (as shown in FIG. 9) or the second electrode layer 2 (as shown in FIG. 16b). In the embodiments of the present application, the source (or the drain) of the transistor Tr is electrically connected with the ferroelectric capacitor C as an example, and the electrical connection between the transistor Tr and the ferroelectric capacitor C is not limited thereto. For example, the ferroelectric capacitor C can be part of the transistor Tr, so that the transistor Tr constitutes a ferroelectric field effect transistor.

[0085] In some examples, as shown in FIG. 8 and FIG. 15, the number of the ferroelectric capacitors C and the number of the transistors Tr are both plural, and one transistor Tr can be electrically connected with one or more ferroelectric capacitors C.

[0086] For example, as shown in FIG. 8, one transistor Tr is electrically connected with one ferroelectric capacitor C to constitute a 1T1C structure storage unit 711. In this case, the ferroelectric capacitor C has a two-dimensional planar structure. As shown in FIG. 9, the first electrode layer 1 and the second electrode layer 2 are both planar electrodes, the first electrode layer 1 is electrically connected with the transistor Tr, and the second electrode layer 2 is located on the side of the first electrode layer 1 away from the transistor Tr. The plurality of ferroelectric capacitors C included in the storage array 710 are arranged in an array, and the plurality of ferroelectric capacitors C in the same row are arranged in sequence along a first direction X, and the plurality of ferroelectric capacitors C in the same column are arranged in sequence along a second direction Y. The first direction X and the second direction Y are perpendicular to each other.

[0087] The ferroelectric capacitor C has the above arrangement, which has a simpler structure and is easy to manufacture, thereby facilitating the manufacture of the storage array 710 and the memory 700.

[0088] For another example, as shown in FIG. 15, one transistor Tr is electrically connected with a plurality of ferroelectric capacitors C in parallel to constitute a 1TnC structure storage unit 711. In this case, the ferroelectric capacitor C has a three-dimensional structure. As shown in FIG. 16a and FIG. 16b, the first electrode layer 1 is a planar electrode, and the second electrode layer 2 is a columnar electrode, a plurality of first electrode layers 1 are stacked along a third direction Z, and the second electrode layer 2 penetrates the plurality of first electrode layers 1. The second electrode layer 2 can be a common electrode plate and be electrically connected with the transistor Tr, and the second electrode layer 2 and the plurality of first electrode layers 1 constitute a plurality of ferroelectric capacitors C in parallel, and the plurality of ferroelectric capacitors C in parallel can be arranged in sequence along the third direction Z. The third direction Z is perpendicular to the first direction X and the second direction Y.

[0089] The ferroelectric capacitor C is arranged in the above manner, so that the occupied area is reduced, and the number of ferroelectric capacitors C is increased, thereby facilitating the increase of the storage density of the storage array 710 and the memory 700.

[0090] In some examples, as shown in FIGS. 9, 16a and 16b, the ferroelectric capacitor C further includes a first ferroelectric layer 31, a first electric dipole interlayer 41 and an electron injection interlayer 5. The first ferroelectric layer 31 is located between the first electrode layer 1 and the second electrode layer 2, the first electric dipole interlayer 41 is located between the first ferroelectric layer 31 and the second electrode layer 2, and the electron injection interlayer 5 is located between the first ferroelectric layer 31 and the first electric dipole interlayer 41. In the case where the first electrode layer 1 and the second electrode layer 2 are both planar electrodes, as shown in FIG. 9, the first ferroelectric layer 31, the electron injection interlayer 5 and the first electric dipole interlayer 41 are all planar, and the first electrode layer 1, the first ferroelectric layer 31, the electron injection interlayer 5, the first electric dipole interlayer 41 and the second electrode layer 2 are sequentially stacked along the thickness direction (e.g., the third direction Z) of the first electrode layer 1. In the case where the first electrode layer 1 is a columnar electrode and the second electrode layer 2 is a planar electrode, as shown in FIGS. 16a and 16b, the first ferroelectric layer 31, the electron injection interlayer 5 and the first electric dipole interlayer 41 are all hollow tubular, the first electric dipole interlayer 41 surrounds the first electrode layer 1, the electron injection interlayer 5 surrounds the first electric dipole interlayer 41, and the first ferroelectric layer 31 surrounds the electron injection interlayer 5.

[0091] Optionally, the material of the first ferroelectric layer 31 includes a hafnium zirconium oxide (HZO) ferroelectric material, a hafnium zirconium titanium oxide (HZTO) ferroelectric material, or a hafnium oxide (HfO2) based ferroelectric material. The hafnium oxide based ferroelectric material includes, but is not limited to, a hafnium oxide material doped with at least one of zirconium, silicon, lanthanum, yttrium, strontium, gadolinium or aluminum. The hafnium oxide based ferroelectric material has a wide band gap, so that the storage unit 711 has the advantages of small leakage current, low power consumption, good cycle performance and microminiaturization, and still has ferroelectricity when the thickness of the first ferroelectric layer 31 is less than or equal to 10 nm.

[0092] Optionally, the band gap of the material of the first electric dipole interlayer 41 ranges from 2.1 eV to 6.2 eV. For example, the material of the first electric dipole interlayer 41 includes an insulating material such as an oxide or a nitride, which includes at least one of a tantalum oxide, an aluminum oxide, a titanium oxide, a niobium oxide, a lanthanum oxide, an oxide, a tungsten oxide or a tantalum nitride. The band gaps of various insulating materials are shown in Table 1 below.

[0093] Table 1

[0094] The first electric dipole interlayer 41 formed of the material shown in Table 1 can provide more electric dipoles. This can increase the storage window of the memory 700 including the storage array 710, reduce the operating voltage of the ferroelectric capacitor C, and reduce the power consumption of the memory 700. For details, refer to the above description of the electric dipole interlayer 4, which will not be repeated here.

[0095] In some examples, the resistivity of the material of the above-mentioned electron injection interlayer 5 is less than the resistivity of the material of the first electric dipole interlayer 41. Accordingly, there are more free electrons in the electron injection interlayer 5 than in the first electric dipole interlayer 41. The free electron concentration in the electron injection interlayer 5 is higher than the free electron concentration in the first electric dipole interlayer 41.

[0096] This can introduce more free electrons between the first ferroelectric layer 31 and the first electric dipole interlayer 41, provide a large amount of shielding charges for the ferroelectric capacitor C, weaken or even shield the depolarization field generated in the first ferroelectric layer 31, so that the storage state of the ferroelectric capacitor C remains substantially unchanged for a longer period of time, thereby improving the retention characteristics of the storage array 710 and the memory 700 to which it is applied.

[0097] Moreover, the free electrons in the electron injection interlayer 5 can combine with the positively charged oxygen vacancies at the interface, weaken the built-in electric field in the first ferroelectric layer 31, and improve the bias of the polarization direction of the ferroelectric material, so that the two storage states corresponding to "0" and "1" in the ferroelectric memory C can be well identified, thereby improving the imprint impression.

[0098] In addition, the defect energy level provided by the electron injection interlayer 5 is shallow, which can reduce the number of trapped and accumulated electrons, suppress the charge trapping caused by interface defects, and improve the durability of the storage array 710 and the memory 700 to which it is applied.

[0099] In some embodiments, the resistivity of the material of the above-mentioned electron injection interlayer 5 is less than or equal to 200 μΩ·cm.

[0100] Alternatively, the resistivity of the material of the electron injection interlayer 5 can be in the range of 1 μΩ·cm to 200 μΩ·cm, 50 μΩ·cm to 200 μΩ·cm, 100 μΩ·cm to 200 μΩ·cm, 80 μΩ·cm to 150 μΩ·cm, etc. The resistivity of the material of the electron injection interlayer 5 is, for example, 10 μΩ·cm, 30 μΩ·cm, 70 μΩ·cm, 110 μΩ·cm, 130 μΩ·cm, 180 μΩ·cm, 200 μΩ·cm, etc.

[0101] This ensures that the electron injection interlayer 5 has a large number of free electrons, which can provide sufficient shielding charges for the ferroelectric capacitor C, thereby effectively improving the retention characteristics, imprint impression, and durability of the storage array 710 and the memory 700 to which the storage array 710 is applied.

[0102] In some embodiments, the material of the electron injection interlayer 5 includes at least one of a metal material, a metal nitride material, or a metal oxide material. That is, the electron injection interlayer 5 can include one of a metal material, a metal nitride material, and a metal oxide material, or can be composed of at least two of a metal material, a metal nitride material, and a metal oxide material.

[0103] The metal material, the metal nitride material, the metal oxide material, and the like have a low resistivity. Forming the electron injection interlayer 5 using at least one of a metal material, a metal nitride material, or a metal oxide material ensures that the electron injection interlayer 5 has a large number of free electrons, which can provide sufficient shielding charges for the ferroelectric capacitor C, thereby effectively improving the retention characteristics, imprint impression, and durability of the storage array 710 and the memory 700 to which the storage array 710 is applied.

[0104] In some examples, the material of the electron injection interlayer 5 includes at least one of aluminum (Al), molybdenum (Mo), tungsten (W), nickel (Ni), platinum (Pt), titanium (Ti), tantalum (Ta), titanium nitride (TiN), zirconium nitride (ZrN), hafnium nitride (HfN), niobium nitride (NbN), indium tin oxide (ITO), antimony tin oxide (AZO), or indium gallium zinc oxide (IGZO). The resistivity of the aluminum, molybdenum, tungsten, nickel, platinum, titanium, tantalum, titanium nitride, zirconium nitride, hafnium nitride, niobium nitride, indium tin oxide, and the like is shown in Table 2 below.

[0105] Table 2

[0106] The electron injection interlayer 5 formed of the materials shown in Table 2 has a low resistivity and a large number of free electrons, which can provide sufficient shielding charges for the ferroelectric capacitor C, thereby effectively improving the retention characteristics, imprint impression, and durability of the storage array 710 and the memory 700 to which the storage array 710 is applied, and improving the reliability of the storage array 710 and the memory 700 to which the storage array 710 is applied.

[0107] Optionally, the electron injection interlayer 5 can be a single-layer thin film structure or a structure formed by stacking multiple thin films in a superlattice manner. In the case of the electron injection interlayer 5 being a single-layer thin film structure, the electron injection interlayer 5 can be formed of one of a plurality of materials including aluminum, molybdenum, tungsten, nickel, platinum, titanium, tantalum, titanium nitride, zirconium nitride, hafnium nitride, niobium nitride, indium tin oxide, antimony tin oxide, and indium gallium zinc oxide, or can be formed by mixing at least two of aluminum, molybdenum, tungsten, nickel, platinum, titanium, tantalum, titanium nitride, zirconium nitride, hafnium nitride, niobium nitride, indium tin oxide, antimony tin oxide, or indium gallium zinc oxide. In the case of the electron injection interlayer 5 being a structure formed by stacking multiple thin films in a superlattice manner, the materials of the thin films can be the same or different, and each thin film can be formed of one of a plurality of materials including aluminum, molybdenum, tungsten, nickel, platinum, titanium, tantalum, titanium nitride, zirconium nitride, hafnium nitride, niobium nitride, indium tin oxide, antimony tin oxide, and indium gallium zinc oxide, or can be formed by mixing at least two of aluminum, molybdenum, tungsten, nickel, platinum, titanium, tantalum, titanium nitride, zirconium nitride, hafnium nitride, niobium nitride, indium tin oxide, antimony tin oxide, or indium gallium zinc oxide.

[0108] In some examples, the thickness (i.e., the dimension in the third direction Z) of the electron injection interlayer 5 ranges from 0.1 nm to 2 nm. Optionally, the thickness of the electron injection interlayer 5 can be 0.1 nm, 0.5 nm, 0.8 nm, 1.1 nm, 1.5 nm, 2 nm, or the like.

[0109] This can not only reduce the impact of the introduction of the electron injection interlayer 5 on the thickness of the ferroelectric memory C, but also ensure that the electron injection interlayer 5 can improve a large number of free electrons.

[0110] The number of the above-mentioned electron injection interlayer 5 can be one or more. In the case of the number of the electron injection interlayer 5 being one or more, the film layers in the ferroelectric memory C have a plurality of setting modes, which will be described below with reference to the accompanying drawings.

[0111] In some possible embodiments, as shown in FIGS. 9, 10, and 11, the number of the electron injection interlayer 5 is one.

[0112] In some examples, as shown in FIG. 9, only one electron injection interlayer 5 is arranged between the first ferroelectric layer 31 and the first electric dipole interlayer 41.

[0113] In some examples, as shown in FIG. 10, the ferroelectric memory C further includes a second ferroelectric layer 32 located between the electron injection interlayer 5 and the first electric dipole interlayer 41. In the case where the first electrode layer 1 and the second electrode layer 2 are both planar electrodes, the second ferroelectric layer 32 is also planar, and the first electrode layer 1, the first ferroelectric layer 31, the electron injection interlayer 5, the second ferroelectric layer 32, the first electric dipole interlayer 41, and the second electrode layer 2 are sequentially stacked along the third direction Z.

[0114] In this case, the first ferroelectric layer 31 and the second ferroelectric layer 32 can be two independent film layers. Alternatively, the first ferroelectric layer 31 and the second ferroelectric layer 32 can be one complete ferroelectric material layer 3, and the electron injection interlayer 5 is inserted into the ferroelectric material layer 3.

[0115] In combination with FIGS. 7 and 10, a shielding electric field Es can be formed between the electron injection interlayer 5 and the first electrode layer 1 to weaken the depolarization field Ed in the first ferroelectric layer 1, thereby effectively improving the retention characteristics and poor durability of the memory and effectively alleviating the imprint impression problem.

[0116] In yet some examples, as shown in FIG. 11, the ferroelectric memory C further includes a second electric dipole interlayer 42 located between the electron injection interlayer 5 and the first ferroelectric layer 31. In the case where the first electrode layer 1 and the second electrode layer 2 are both planar electrodes, the second electric dipole interlayer 42 is also planar, and the first electrode layer 1, the first ferroelectric layer 31, the second electric dipole interlayer 42, the electron injection interlayer 5, the first electric dipole interlayer 41, and the second electrode layer 2 are sequentially stacked along the third direction Z.

[0117] In this case, the first electric dipole interlayer 41 and the second electric dipole interlayer 42 can be two independent film layers. Alternatively, the first electric dipole interlayer 41 and the second electric dipole interlayer 42 can be one complete electric dipole interlayer 4, and the electron injection interlayer 5 is inserted into the electric dipole interlayer 4.

[0118] In this case, the first electric dipole interlayer 41 and the second electric dipole interlayer 42 can be two independent film layers. Alternatively, the first electric dipole interlayer 41 and the second electric dipole interlayer 42 can be one complete electric dipole interlayer 4, and the electron injection interlayer 5 is inserted into the electric dipole interlayer 4.

[0119] Here, the free electrons in the electron injection interlayer 5 can be injected into the second electric dipole interlayer 42, so as to not only effectively shield the depolarization field in the first ferroelectric layer 31, improve the poor retention characteristics of the memory 700, but also make the free electrons combine with the oxygen vacancies located at the contact interface of the first ferroelectric layer 31 and the second electric dipole interlayer 42, effectively alleviate the imprint impression problem.

[0120] In some other possible embodiments, the number of the electron injection interlayer 5 is multiple. For example, the number of the electron injection interlayer 5 is two, three, four or even more. The multiple electron injection interlayers 5 are spaced and stacked along the third direction Z. In the case where the number of the electron injection interlayer 5 is three or more, the spacing between the adjacent two electron injection interlayers 5 can be equal or unequal.

[0121] In some examples, as shown in FIGS. 12, 13 and 14, the ferroelectric memory C further includes the second ferroelectric layer 32 and / or the second electric dipole interlayer 42 located between the adjacent two electron injection interlayers 5. Here, the resistivity of the material of the electron injection interlayer 5 is less than the resistivity of the material of the second electric dipole interlayer 42. The materials of the second electric dipole interlayer 42 and the first electric dipole interlayer 41 can be the same or different. In the case where the materials of the second electric dipole interlayer 42 and the first electric dipole interlayer 41 are the same, the preparation process of the memory array 710 and the memory 700 applied thereto can be simplified, and the preparation efficiency of the memory array 710 and the memory 700 applied thereto can be improved.

[0122] Optionally, as shown in FIG. 12, the ferroelectric memory C further includes the second ferroelectric layer 32 located between the adjacent two electron injection interlayers 5. Taking the case where the number of the electron injection interlayer 5 is two as an example, in the case where the first electrode layer 1 and the second electrode layer 2 are both planar electrodes, the second ferroelectric layer 32 is also planar, and the first electrode layer 1, the first ferroelectric layer 31, the electron injection interlayer 5, the second ferroelectric layer 32, the electron injection interlayer 5, the first electric dipole interlayer 41 and the second electrode layer 2 are sequentially stacked along the third direction Z.

[0123] Optionally, as shown in FIG. 13, the ferroelectric memory C further includes the second electric dipole interlayer 42 located between the adjacent two electron injection interlayers 5. Taking the case where the number of the electron injection interlayer 5 is two as an example, in the case where the first electrode layer 1 and the second electrode layer 2 are both planar electrodes, the second electric dipole interlayer 42 is also planar, and the first electrode layer 1, the first ferroelectric layer 31, the electron injection interlayer 5, the second electric dipole interlayer 42, the electron injection interlayer 5, the first electric dipole interlayer 41 and the second electrode layer 2 are sequentially stacked along the third direction Z.

[0124] Optionally, as shown in FIG. 14, the ferroelectric memory C further comprises a second ferroelectric layer 32 and a second electric dipole interlayer 42 between two adjacent electron injection interlayers 5. Taking the number of electron injection interlayers 5 as two for example, in the case where the first electrode layer 1 and the second electrode layer 2 are both planar electrodes, the second ferroelectric layer 32 and the second electric dipole interlayer 42 are also planar, and along the third direction Z, the first electrode layer 1, the first ferroelectric layer 31, the electron injection interlayer 5, the second ferroelectric layer 32, the second electric dipole interlayer 42, the electron injection interlayer 5, the first electric dipole interlayer 41 and the second electrode layer 2 are sequentially stacked.

[0125] Some embodiments of the present application also provide a preparation method of a memory array. The preparation method is used for preparing the memory array 710 in some embodiments described above, for example. Wherein, FIG. 17 schematically shows a flowchart of a preparation method of a memory array; FIG. 18(a), (b), (c), (d), (e), FIG. 19(a), (b), (c), (d), (e), (f) and FIG. 20a-20g respectively schematically show structure diagrams corresponding to respective steps in the preparation method of a memory array. It should be understood that the steps shown in FIG. 17 are not exclusive, and other steps can also be performed before, after or between any of the steps shown in FIG. 17. In addition, some of the steps can be performed simultaneously, or can be performed in an order different from that shown in FIG. 17.

[0126] The preparation method of a memory array is schematically described below with reference to the accompanying drawings. As shown in FIG. 17, the preparation method comprises S100-S500.

[0127] S100, forming a first electrode layer 1.

[0128] For example, as shown in FIG. 18(a) and FIG. 19(a), in the case where the first electrode layer 1 and the second electrode layer 2 are both planar electrodes, the embodiments of the present application can use a physical vapor deposition (PVD) process to form the first electrode layer 1 on the substrate 6. The material of the first electrode layer 1 is tungsten for example, the thickness of the first electrode layer 1 is 50 nm for example, and the material of the substrate 6 is silicon for example.

[0129] For example, as shown in FIG. 20a, in the case where the first electrode layer 1 is a planar electrode and the second electrode layer 2 is a columnar electrode, the embodiments of the present application can use a PVD process to form a stack structure composed of the first electrode layer 1 and the dielectric layer 7 which are alternately stacked on the substrate 6. The material of the dielectric layer 7 includes but is not limited to silicon oxide (SiO2).

[0130] S200, forming a first ferroelectric layer 31 on one side of the first electrode layer 1.

[0131] Exemplarily, as shown in (b) of FIG. 18 and (b) of FIG. 19, in the case where the first electrode layer 1 and the second electrode layer 2 are both planar electrodes, an atom layer deposition (ALD) process can be used to form the first ferroelectric layer 31 on the side of the first electrode layer 1 away from the substrate 6.

[0132] Exemplarily, as shown in FIG. 20b and FIG. 20c, in the case where the first electrode layer 1 is a planar electrode and the second electrode layer 2 is a columnar electrode, an etching process with a high aspect ratio can be used to etch the above-mentioned laminated structure to form a deep hole (or a columnar deep groove) penetrating through the laminated structure, and then an ALD process is used to form the first ferroelectric layer 31 on the sidewall of the deep hole.

[0133] The material of the first ferroelectric layer 31 is, for example, HZO with hafnium (Hf) and zirconium (Zr) in a ratio of 1:1, and the thickness of the first ferroelectric layer 31 is, for example, 8 nm.

[0134] S300, forming an electron injection interlayer 5 on the side of the first ferroelectric layer 31 away from the first electrode layer 1.

[0135] Exemplarily, as shown in (c) of FIG. 18, (c) of FIG. 19 and FIG. 20e, an ALD process can be used to form the electron injection interlayer 5. The thickness of the electron injection interlayer 5 is, for example, 0.5 nm, and the material of the electron injection interlayer 5 can refer to the related description above, which will not be repeated here. In the case where the first electrode layer 1 and the second electrode layer 2 are both planar electrodes, the electron injection interlayer 5 is planar; in the case where the first electrode layer 1 is a planar electrode and the second electrode layer 2 is a columnar electrode, the electron injection interlayer 5 is a hollow tube.

[0136] S400, forming a first electric dipole interlayer 41 on the side of the electron injection interlayer 5 away from the first electrode layer 1. The resistivity of the material of the electron injection interlayer 5 is less than the resistivity of the material of the first electric dipole interlayer 41.

[0137] Exemplarily, as shown in (d) of FIG. 18, (e) of FIG. 19 and FIG. 20f, an ALD process can be used to form the first electric dipole interlayer 41. The thickness of the first electric dipole interlayer 41 is, for example, 1.5 nm, and the material of the first electric dipole interlayer 41 can refer to the related description above, which will not be repeated here. In the case where the first electrode layer 1 and the second electrode layer 2 are both planar electrodes, the first electric dipole interlayer 41 is planar; in the case where the first electrode layer 1 is a planar electrode and the second electrode layer 2 is a columnar electrode, the first electric dipole interlayer 41 is a hollow tube.

[0138] S500, as shown in (e) of FIG. 18, (f) of FIG. 19 and (g) of FIG. 20, the second electrode layer 2 is formed on the side of the first electric dipole interlayer 41 away from the first electrode layer 1.

[0139] Optionally, the second electrode layer 2 can be a single-layer thin film structure, or a structure composed of multiple thin film layers. For example, the second electrode layer 2 is composed of two thin film layers, one of which is made of titanium nitride, and the other of which is made of tungsten.

[0140] For example, the ALD process is used to form a TiN layer on the side of the first electric dipole interlayer 41 away from the first electrode layer 1, and then the CVD process is used to form a W layer on the side of the TiN layer away from the first electrode layer 1, thereby obtaining the second electrode layer 2 composed of the TiN layer and the W layer. Then, the annealing process is performed by rapid thermal annealing, so that the first ferroelectric layer 31 forms a ferroelectric phase. The thickness of the TiN layer is, for example, 5 nm, and the thickness of the W layer is, for example, 30 nm.

[0141] In the preparation method of the storage array provided by some embodiments of the present application, in the process of preparing the ferroelectric capacitor, the first electric dipole interlayer 41 and the electron injection interlayer 5 are formed, and the resistivity of the material of the electron injection interlayer 5 is less than the resistivity of the material of the first electric dipole interlayer 41. On the one hand, the first electric dipole interlayer can increase the amount of polarization charge and assist the flipping of the ferroelectric domain of the first ferroelectric layer 31, so as to increase the storage window while reducing the operating voltage and power consumption. On the other hand, the electron injection interlayer 5 can introduce more free electrons to provide shielding charge for the ferroelectric capacitor, weaken or even shield the depolarization field generated in the first ferroelectric layer 31, and improve the retention characteristics of the storage array 710 and the memory 700 applied thereto. Moreover, the free electrons in the electron injection interlayer 5 can combine with the positively charged oxygen vacancies at the interface to weaken the built-in electric field in the first ferroelectric layer 31 and improve the imprint impression. In addition, the defect level provided by the electron injection interlayer 5 is shallow, which can reduce the number of captured and accumulated electrons, inhibit charge trapping caused by interface defects, and improve the durability of the retention characteristics of the storage array 710 and the memory 700 applied thereto.

[0142] In some embodiments, in combination with (d) and (e) of FIG. 19, before S400 described above, that is, before the first electric dipole interlayer 41 is formed on the side of the electron injection interlayer 5 away from the first electrode layer 1, the preparation method further includes S390.

[0143] S390, in combination with (c) and (d) in FIG. 19, a second ferroelectric layer 32 is formed on the side of the electron injection interlayer 5 away from the first electrode layer 1.

[0144] For example, as shown in (c) in FIG. 19, the ALD process can be used to form the electron injection interlayer 5. The material of the second ferroelectric layer 32 can be the same as or different from the material of the first ferroelectric layer 31. In this case, the electron injection interlayer 5 is located between the first ferroelectric layer 31 and the second ferroelectric layer 32, and the first electric dipole interlayer 41 is located on the side of the second ferroelectric layer 32 away from the electron injection interlayer 5.

[0145] Optionally, in the structure shown in (d) in FIG. 19, the thickness of the first ferroelectric layer 31 is, for example, 4 nm, and the thickness of the second ferroelectric layer 32 is, for example, 4 nm.

[0146] In other embodiments, in combination with FIG. 20d and FIG. 20e, before S300 described above, that is, before the electron injection interlayer 5 is formed on the side of the first ferroelectric layer 31 away from the first electrode layer 1, the preparation method further includes S290.

[0147] S290, in combination with FIG. 20c and FIG. 20d, a second electric dipole interlayer 42 is formed on the side of the first ferroelectric layer 31 away from the first electrode layer 1. The resistivity of the material of the electron injection interlayer 5 is less than the resistivity of the material of the second electric dipole interlayer 42.

[0148] For example, as shown in FIG. 20d, the ALD process can be used to form the second electric dipole interlayer 42. The material of the second electric dipole interlayer 42 can be the same as or different from the material of the first electric dipole interlayer 41. In this case, the electron injection interlayer 5 is located between the second electric dipole interlayer 42 and the first electric dipole interlayer 41, and the first ferroelectric layer 31 is located on the side of the second electric dipole interlayer 42 away from the electron injection interlayer 5.

[0149] Optionally, in the structure shown in FIG. 20f, the thickness of the first electric dipole interlayer 41 is, for example, 0.75 nm, and the thickness of the second electric dipole interlayer 42 is, for example, 0.75 nm.

[0150] Here, the preparation method described above is taken as an example with the number of the electron injection interlayer 5 being one. In the case where the number of the electron injection interlayer 5 is multiple, the second electric dipole interlayer 42 and / or the second ferroelectric layer 32 can be prepared between the first electrode layer 1 and the second electrode layer 2 by referring to S290 and / or S390 described above.

[0151] Illustratively, after the ferroelectric capacitor C is fabricated, the substrate 6 can be removed and the ferroelectric capacitor C can be connected to a transistor that is fabricated separately. Alternatively, the transistor can be formed on the substrate 6 before the ferroelectric capacitor C is fabricated. Alternatively, the transistor can be formed on the side of the ferroelectric capacitor C that is away from the substrate 6 after the ferroelectric capacitor C is fabricated.

[0152] The above description is only specific embodiments of the present application, but the protection scope of the present application is not limited thereto, and any person skilled in the art can think of changes or replacements within the technical range disclosed by the present application, which should be covered by the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A memory array comprising: The memory array comprises a ferroelectric capacitor; The ferroelectric capacitor comprises: a first electrode layer; a second electrode layer, disposed opposite to the first electrode layer; a first ferroelectric layer, located between the first electrode layer and the second electrode layer; a first electric dipole interlayer, located between the first ferroelectric layer and the second electrode layer; an electron injection interlayer, located between the first ferroelectric layer and the first electric dipole interlayer; The resistivity of the material of the electron injection interlayer is less than the resistivity of the material of the first electric dipole interlayer.

2. The storage array of claim 1, wherein, The ferroelectric capacitor further comprises a second ferroelectric layer, located between the electron injection interlayer and the first electric dipole interlayer.

3. The storage array of claim 1, wherein, The ferroelectric capacitor further comprises a second electric dipole interlayer, located between the electron injection interlayer and the first ferroelectric layer; The resistivity of the material of the electron injection interlayer is less than the resistivity of the material of the second electric dipole interlayer.

4. The storage array of claim 1, wherein, The number of the electron injection interlayers is multiple; The ferroelectric capacitor further comprises a second ferroelectric layer and / or a second electric dipole interlayer located between any two adjacent electron injection interlayers; The resistivity of the material of the electron injection interlayer is less than the resistivity of the material of the second electric dipole interlayer.

5. The storage array of claim 3 or 4, wherein, The material of the second electric dipole interlayer is the same as that of the first electric dipole interlayer.

6. The storage array of any of claims 1-5, wherein, The resistivity of the material of the electron injection interlayer is less than or equal to 200 μΩ·cm.

7. The storage array of any of claims 1-6, wherein, The material of the electron injection interlayer comprises at least one of a metal material, a metal nitride material or a metal oxide material.

8. The storage array of any of claims 1-7, wherein, The material of the electron injection interlayer comprises at least one of aluminum, molybdenum, tungsten, nickel, platinum, titanium, tantalum, titanium nitride, zirconium nitride, hafnium nitride, niobium nitride, indium tin oxide, antimony tin oxide or indium gallium zinc oxide.

9. The storage array of any of claims 1-8, wherein, The thickness of the electron injection interlayer ranges from 0.1 nm to 2 nm.

10. The storage array of any of claims 1-9, wherein, The first electrode layer and the second electrode layer are both planar electrodes; The first electrode layer, the first ferroelectric layer, the electron injection interlayer, the first electric dipole interlayer and the second electrode layer are sequentially stacked along the thickness direction of the first electrode layer.

11. The storage array of any of claims 1-9, wherein, The first electrode layer is a planar electrode, and the second electrode layer is a columnar electrode; The second electrode layer penetrates through the first electrode layer, the first electric dipole interlayer surrounds the second electrode layer, the electron injection interlayer surrounds the first electric dipole interlayer, and the first ferroelectric layer surrounds the electron injection interlayer.

12. The storage array of any of claims 1-11, wherein, The material of the first electric dipole interlayer comprises at least one of tantalum oxide, aluminum oxide, titanium oxide, niobium oxide, lanthanum oxide, molybdenum oxide, tungsten oxide or tantalum nitride.

13. The storage array of any of claims 1-12, wherein, The memory array further comprises a transistor; The transistor is electrically connected with the first electrode layer or the second electrode layer.

14. A method of fabricating a memory array, comprising: The preparation method comprises: forming a first electrode layer; forming a first ferroelectric layer on one side of the first electrode layer; forming an electron injection interlayer on the side of the first ferroelectric layer away from the first electrode layer; forming a first electric dipole interlayer on the side of the electron injection interlayer away from the first electrode layer; the resistivity of the material of the electron injection interlayer is less than the resistivity of the material of the first electric dipole interlayer; A second electrode layer is formed on a side of the first electric dipole interlayer distal from the first electrode layer.

15. The method of claim 14, wherein, The preparation method further comprises, before the forming of the first electric dipole interlayer on a side of the electron injection interlayer distal from the first electrode layer: A second ferroelectric layer is formed on a side of the electron injection interlayer distal from the first electrode layer.

16. The method of claim 14, wherein, The preparation method further comprises, before the forming of the electron injection interlayer on a side of the first ferroelectric layer distal from the first electrode layer: A second electric dipole interlayer is formed on a side of the first ferroelectric layer distal from the first electrode layer; and the resistivity of the material of the electron injection interlayer is less than the resistivity of the material of the second electric dipole interlayer.

17. A memory, comprising: The memory comprises: The memory array according to any one of claims 1-13; The controller is electrically connected with the memory array.

18. An electronic device, comprising: The electronic device comprises: The memory according to claim 17; The circuit board is electrically connected with the memory.

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