An antimonide focal plane imaging chip based on electron injection structure

Abstract

This invention discloses an antimony-based focal plane array imaging chip with an electron injection structure, belonging to the field of semiconductor photodetector technology. The chip includes a detector chip, a readout circuit chip, and an indium pillar structure interconnecting the two. The detector chip is fabricated by molecular beam epitaxy (MBE) to grow a specific structure epitaxial wafer, followed by double-mesa etching to form nanopillar units containing the electron injection structure, and then by passivation opening, metal electrodes, and indium pillars. After the readout circuit chip completes the UBM metal layer and indium pillar fabrication, it is flip-chip bonded to the detector chip. The finished product is obtained through substrate thinning, dicing and packaging, and testing. This chip utilizes the nano-lateral confinement effect to shorten carrier transit time and reduce dark current, and combines photonic crystal characteristics to enhance light absorption, solving problems such as crosstalk and slow response in traditional technologies. It achieves an optical gain of 4264 and a response time of <10ns, making it suitable for extremely weak light and ultra-high frame rate short-wave infrared imaging scenarios.

Description

Technical Field

[0001] This invention relates to the field of semiconductor photodetector technology, specifically to an antimony focal plane imaging chip based on an electron injection structure and its fabrication method. It is particularly suitable for cutting-edge applications requiring high-performance short-wave infrared imaging under ultra-high frame rates and extremely low light conditions, such as strategic early warning, night vision observation, meteorological monitoring, medical diagnosis, quantum communication, super-resolution microscopy, and high-speed lidar. Background Technology

[0002] Shortwave infrared imaging has wide applications in cutting-edge fields such as strategic early warning, night vision observation, meteorological monitoring, medical diagnosis, quantum communication, super-resolution microscopy, and high-speed lidar. These applications place extremely high demands on detector performance: ultra-high frame rate imaging under extremely low light conditions is required, while also ensuring high sensitivity, low noise, and fast response. However, the detection capability of current infrared imaging systems is mainly limited by the readout noise of the focal plane array. Overcoming this bottleneck through internal detector gain requires resolving the inherent contradiction between high gain and fast response.

[0003] Heterojunction phototransistors (HPTs), based on III-V group semiconductor materials, possess advantages such as ultra-high gain and low dark current, and can be integrated with uncooled CMOS readout circuits (ROICs), providing a potential solution for extremely weak light detection. The detector electron injection structure, as a vertical nanopillar array formed by etching, effectively confines the electric field and photogenerated carriers through nanoscale lateral confinement effects, shortening carrier transit time, improving response speed, and reducing carrier recombination with defects, thus lowering dark current. Simultaneously, this structure possesses photonic crystal properties, enhancing the absorption efficiency of light at specific wavelengths.

[0004] However, existing shortwave infrared detection technologies, especially mesa technology and standard focal plane array technology, have significant shortcomings in combining high performance at the unit level with parallel imaging capabilities at the array level, as specifically as follows: Mesa process: This process forms independent semiconductor mesas through etching to achieve electrical isolation. Although it has the advantages of simple structure and low cost, its performance is heavily dependent on the passivation effect. Because the electric field tends to concentrate at the edge of the mesa, it leads to premature device breakdown and high edge leakage current. It is only suitable for low operating voltage or non-extreme performance requirements and cannot meet the high reliability and high sensitivity requirements of cutting-edge applications.

[0005] Standard focal plane array technology: This technology achieves two-dimensional imaging by integrating a detector array with a CMOS readout circuit, but the basic detector unit structure (such as a planar or single-mesa) has inherent bottlenecks. Lateral photogenerated carrier diffusion causes crosstalk, reducing image resolution and contrast; The large junction capacitance and long carrier transit path limit the response speed, making it difficult to achieve ultra-high frame rate detection. The small sidewall area and weak electric field control capability result in insufficient dark current suppression, which affects sensitivity. When integrating high pixel density, the process tolerance is small, the manufacturing difficulty is high, and the performance uniformity is poor.

[0006] In summary, existing technologies struggle to simultaneously achieve ultra-high sensitivity, high response speed, and high-resolution imaging at the array level. Reliability limitations of mesa fabrication processes and performance bottlenecks of standard focal plane array technology constrain the development of short-wave infrared detectors in extremely low-light, ultra-high frame rate applications. This invention aims to resolve this technical contradiction through innovative structural design. Summary of the Invention

[0007] To address the aforementioned problems, this invention provides a heterojunction transistor ultra-high photosensitivity short-wave infrared detector and a focal plane imaging chip. The core technical solution involves high-density integration of nanopillar units with electron injection structures with a focal plane array and a commercially available readout circuit (ROIC). The imaging chip includes a detector chip, a readout circuit chip, and an indium pillar structure for interconnecting the two. The specific technical solution is as follows: (I) Fabrication of detector chips (1) Epitaxial growth: Epitaxial wafers are grown using molecular beam epitaxy, such as... Figure 1 As shown, the epitaxial wafer has the following structure from bottom to top: substrate, buffer layer, HPT first n-type ohmic contact layer, HPT collector region, HPT base region, HPT emitter region, HPT second n-type ohmic contact layer, and N-type capping layer.

[0008] The substrate is Te-doped GaSb with a thickness ≥600μm and a doping concentration ≥10¹⁷cm⁻³.

[0009] The buffer layer is Te-doped GaSb with a thickness ≥330nm and a doping concentration ≥10¹⁷cm⁻³.

[0010] The first n-type ohmic contact layer of the HPT is an n-type doped InGaAsSb structure with a thickness of 400-600 nm and a doping concentration of ≥2×10¹⁸ cm⁻³.

[0011] The collector region of the HPT is an n-type doped InGaAsSb structure with a thickness of 200-350 nm and a doping concentration of ≥5×10¹⁵ cm⁻³.

[0012] The HPT base region is Be-doped GaSb with a thickness of 30-60 nm and a doping concentration of ≥10¹⁶ cm⁻³.

[0013] The HPT emitter region is a Si-doped InAs / AlSb structure with a thickness of 200-500 nm and a doping concentration of ≥5×10¹⁷ cm⁻³.

[0014] The HPT's second n-type ohmic contact layer is a Si-doped InAs / AlSb superlattice structure with a thickness of 300-600 nm and a doping concentration of ≥2×10¹⁸ cm⁻³.

[0015] The N-type capping layer is Si-doped InAs with a thickness of 20-60 nm and a doping concentration ≥ 2 × 10¹⁸ cm⁻³.

[0016] (2) Table surface etching: Using photoresist or silicon dioxide as a mask, a large-mesa photomask is first used for mesa lithography. A combination of dry and wet etching is employed to etch the epitaxial wafer to a predetermined depth, the distance from the first n-type ohmic contact layer to the HPT collector region, forming the initial mesa. Then, a small-mesa photomask is used to further etch the initial mesa, the distance from the HPT collector region to the N-type capping layer, forming a large and small double-mesa structure. The HPT collector region, HPT base region, HPT emitter region, HPT second n-type ohmic contact layer, and N-type capping layer inside the second mesa (i.e., the small mesa) form the electron injection structure. A large mesa is formed on the first n-type ohmic contact layer of the HPT. The first n-type ohmic contact layer and HPT collector region inside the large mesa form a pillar structure, as shown in the figure. Figure 1 As shown in (b).

[0017] (3) Passivation of openings: An alumina passivation layer is deposited on the surface of the dual-mesa detector using atomic layer deposition (ALD) to passivate surface dangling bonds, reduce interface state density, and suppress carrier tunneling and surface leakage. Figure 1 (c); Subsequently, localized aluminum oxide is removed using aperture photolithography to form metal electrode windows, such as... Figure 1 (d).

[0018] (4) Preparation of metal electrodes: The metal electrode pattern was defined by photolithography, and Ti (50 nm), Pt (50 nm), and Au (100 nm) were deposited sequentially using magnetron sputtering. Then, 200 nm of Au was deposited using electron beam evaporation. After immersion in acetone, removal of excess metal using a syringe, and cleaning, a UBM metal layer was formed. (See figure) Figure 1 (e).

[0019] (5) Preparation of indium pillars: 1. Cleaning To remove impurities from the detector chip surface, the chip is first immersed in a dilute hydrochloric acid solution for a short cleaning, then rinsed thoroughly with deionized water, and finally dried with nitrogen gas to remove any remaining moisture. Afterward, a low-energy Ar ion beam is used for in-situ sputtering cleaning to obtain a highly clean and reactive metal surface.

[0020] 2. Photolithography SUN1300 negative photoresist was coated onto the detector surface, and the pre-baking, exposure, post-baking, development, and base film application processes were sequentially performed to complete the patterning definition of the indium pillar positions. The core purpose of choosing negative photoresist is to create an inverted trapezoidal structure where the bottom dimension of the photoresist opening is smaller than the top dimension. This structure is crucial for the successful completion of the subsequent metal stripping process.

[0021] 3. Indium vapor-deposited pillars Indium pillar deposition was performed using a thermal evaporation method, where high-purity indium (99.999%) was heated in a tantalum or boron nitride crucible. During the deposition process, a circulating cooling system was used to control the detector chip temperature below 50°C to prevent photoresist pattern deformation and to prevent performance degradation of the detector material due to thermal stress and thermal diffusion. The deposition rate was controlled in stages: initially, a low deposition rate of approximately 1 Å / s was used to form a uniform indium nucleation layer; after the nucleation layer was formed, the rate was increased to 5-10 Å / s. A quartz crystal oscillator was used to monitor the thickness in real time during the deposition process to ensure that the final indium pillar height reached 8 μm.

[0022] 4. Peeling The detector chip, after vapor deposition, is immersed in an acetone solution. A syringe is used to blow air to help dissolve and peel off the photoresist layer from the edge, removing the indium layer in the non-target area.

[0023] 5. Reflux To transform the cylindrical indium pillar into a hemispherical shape under surface tension, improving contact with the indium pillar of the readout circuit chip and removing the oxide layer on the indium pillar surface, the detector chip is placed in a formic acid vapor or hydrogen atmosphere, heated to 160-180℃, and held at that temperature for 30-60 seconds. Figure 1 (f).

[0024] (II) Fabrication of metal layers and indium pillars for readout circuit chips This step involves fabricating a 320×256 / 15μm readout circuit chip. It utilizes two stages: the fabrication of the under-bump metallization layer and the fabrication of indium pillars. This completes the fabrication of the UBM metal layer and indium bumps required for the interconnection between the readout circuit and the detector chip. The specific operations are as follows: (1) Preparation of metallization layer under bump 1. Photolithography defines the metal pattern: The metal layer pattern is defined on the surface of the readout circuit chip using photolithography.

[0025] 2. Metal Sputtering and Evaporation: For the InAs / AlSb superlattice material system, a composite deposition method of sputtering followed by evaporation is adopted to deposit metal layers sequentially. The parameters and functions of each layer are as follows: The adhesion layer Ti has a thickness of 20-50nm and its function is to form a strong bond with the aluminum oxide passivation layer on the surface of the detector chip.

[0026] Diffusion barrier layer Pt: 50-100nm thick. Compared with Ni material, Pt has better stability at high temperatures and can effectively prevent indium from diffusing into the superlattice material.

[0027] Protective layer Au: 50-100nm thick, used to prevent oxidation of the Pt layer.

[0028] This composite process ensures the reliability and density of the underlying interface through sputtering, and achieves high-efficiency, low-damage, high-quality functional layer deposition through evaporation, thus balancing process reliability and device performance.

[0029] 3. Metal stripping: The coated readout circuit chip is immersed in acetone solution, and excess metal is stripped off by blowing air through a syringe to form a UBM metal layer with a preset pattern.

[0030] (2) Fabrication of indium pillars for readout circuit chips The entire process of indium pillar fabrication in detector chip fabrication—cleaning, photolithography, evaporation, stripping, and reflow—is repeated to fabricate hemispherical indium bumps with a height of 8 μm on the UBM metal layer of the readout circuit chip. Figure 1 (g).

[0031] (III) Flip-chip interconnection and subsequent processing (1) Flip-chip bonding The detector chip with prepared indium pillars is precisely aligned with the readout circuit chip, and flip-chip bonding is performed under 10 kg pressure. This allows the indium pillars of the detector chip and the indium bumps of the readout circuit chip to achieve physical contact and tight bonding, forming a strong electrical conduction path and mechanical connection structure. This invention is based on an antimony compound focal plane imaging chip with an electron injection structure, such as... Figure 1 (h).

[0032] (2) Follow-up processing 1. Substrate thinning: The substrate of the antimony focal plane imaging chip based on the electron injection structure of this invention is thinned to ensure that infrared light can be effectively incident on the detection area.

[0033] 2. Dicing and Packaging: The wafer, after substrate thinning, is diced into individual devices (see...). Figure 2 The device was then encapsulated in a vacuum Dewar and a cooler was integrated to reduce system noise.

[0034] 3. Performance testing: Conduct optoelectronic performance tests on the packaged devices to verify key indicators such as response speed, gain, detection sensitivity, and response speed.

[0035] Beneficial effects: This invention utilizes the design of nanopillar units with an electron-injection structure to confine the electric field and photogenerated carriers within the pillars using the lateral confinement effect at the nanoscale, significantly shortening the carrier transit time and improving the response speed. At the same time, it reduces the probability of recombination between carriers and defects, lowers dark current, and, combined with the excellent passivation effect of atomic layer deposition of alumina, further suppresses surface leakage current, achieving ultra-high sensitivity detection. The experimentally measured optical gain can reach 4264.

[0036] This invention integrates an electron injection structure with a focal plane array and a CMOS readout circuit, solving the problem of lateral carrier diffusion crosstalk in traditional focal plane array technology and improving image resolution and contrast. At the same time, the nanostructure reduces junction capacitance, overcoming the inherent contradiction between high gain and fast response, and realizing high-performance, high-resolution, real-time two-dimensional shortwave infrared imaging.

[0037] The electron injection structure of the present invention has photonic crystal characteristics, which can enhance the light absorption efficiency of a specific wavelength by modulating the photonic localization effect. Furthermore, the physical isolation characteristics of this structure are more conducive to improving the pixel density of the focal plane array, reducing the process difficulty of high pixel integration, and improving the uniformity of device performance. Attached Figure Description

[0038] Figure 1 This is a flowchart illustrating the manufacturing process of the present invention.

[0039] Figure 2 This is a structural diagram of a device according to an embodiment of the present invention.

[0040] Figure 3 This is a graph showing the test data for the present invention.

[0041] Figure label: Substrate-1, Buffer layer-2, HPT first n-type ohmic contact layer-3, HPT collector region-4, HPT base region-5, HPT emitter region-6, HPT second n-type ohmic contact layer-7, N-type capping layer-8, Passivation layer-9, Electrode window-10, Metal electrode-11, Detector chip indium pillar-12, Readout circuit chip indium pillar-13, Readout circuit chip-14. Detailed Implementation

[0042] This embodiment details the fabrication process and performance verification of an antimony focal plane imaging chip based on an electron injection structure. The aim is to combine the high performance of the unit-level electron injection structure with focal plane array technology to solve the technical contradiction of the difficulty in achieving both high sensitivity and high response speed in traditional focal plane technology.

[0043] (I) Fabrication of detector chips (1) Epitaxial growth: Epitaxial wafers are grown using molecular beam epitaxy, such as... Figure 1 As shown, the epitaxial wafer, from bottom to top, consists of a substrate, a buffer layer, an HPT first n-type ohmic contact layer, an HPT collector region, an HPT base region, an HPT emitter region, an HPT second n-type ohmic contact layer, and an N-type capping layer. The parameters of each layer are as follows: Substrate 1 is Te-doped GaSb with a thickness ≥600μm and a doping concentration ≥10¹⁷cm⁻³, providing stable support for the entire epitaxial structure.

[0044] Buffer layer 2 is Te-doped GaSb with a thickness ≥330nm and a doping concentration ≥1017cm-3. It is used to alleviate the lattice mismatch between the substrate and the subsequent epitaxial layer and reduce the defect density.

[0045] The first n-type ohmic contact layer 3 of the HPT is an n-type doped InGaAsSb structure with a thickness of 400-600nm and a doping concentration of ≥2×1018cm-3, achieving a low-resistance ohmic contact.

[0046] HPT collector region 4 is an n-type doped InGaAsSb structure with a thickness of 200-350 nm and a doping concentration of ≥5×10¹⁵ cm⁻³, used to collect charge carriers.

[0047] The HPT base region 5 is Be-doped GaSb with a thickness of 30-60 nm and a doping concentration of ≥10¹⁶ cm⁻³, which is the core region for realizing carrier modulation and gain.

[0048] The HPT emitter region 6 is a Si-doped InAs / AlSb structure with a thickness of 200-500 nm and a doping concentration of ≥5×10¹⁷ cm⁻³, which is responsible for injecting charge carriers.

[0049] The HPT's second n-type ohmic contact layer 7 is a Si-doped InAs / AlSb superlattice structure with a thickness of 300-600 nm and a doping concentration of ≥2×10¹⁸ cm⁻³, ensuring efficient carrier transport.

[0050] The N-type 8 is Si-doped InAs with a thickness of 20-60 nm and a doping concentration of ≥2×10¹⁸ cm⁻³, which protects the underlying epitaxial layer from damage by the external environment.

[0051] (2) Table surface etching This step employs a dual-mesa photolithography etching process to form nanopillar units with electron-injected structures. The specific operations are as follows: 1. Using photoresist or silicon oxide as a mask, a large-area photomask is selected for the first mesa photolithography. The epitaxial wafer is etched to a preset depth by combining dry etching and wet etching. The etching depth is the distance from the first n-type ohmic contact layer to the HPT collector region, forming the initial mesa.

[0052] 2. Replace the small mesa photomask and perform a second photolithography and etching process on the initial mesa. The etching is done to represent the distance from the HPT collector region to the N-type capping layer, forming a large mesa and a small mesa. The HPT collector region, HPT base region, HPT emitter region, HPT second n-type ohmic contact layer, and N-type capping layer on the inner side of the small mesa together constitute the electron injection structure. A large mesa is formed on the HPT first n-type ohmic contact layer. The HPT first n-type ohmic contact layer and HPT collector region on the inner side of the large mesa form a pillar structure.

[0053] 3. This dual-mesa structure confines the electric field and photogenerated carriers within the column through a nanoscale lateral confinement effect. Unlike traditional single-mesa structures, this structure significantly shortens the carrier transit time and reduces the probability of carrier recombination with defects, making it a key design for achieving high response speed and low dark current.

[0054] (3) Passivation of openings 1. For example Figure 1 (c) A dense aluminum oxide passivation layer 9 is deposited on the surface of the dual-mesa detector using atomic layer deposition process. Aluminum oxide has excellent interface compatibility with the surface of III-V semiconductors, which can passivate surface dangling bonds, reduce interface state density, effectively suppress carrier tunneling and surface leakage, and solve the problems of multiple interface defects and Fermi level pinning that exist in traditional silicon dioxide and silicon nitride passivation.

[0055] 2. For example Figure 1 (d) The aluminum oxide passivation layer in the corresponding area of ​​the metal electrode is removed by the aperture photolithography process to form the metal electrode window 10, which provides an electrical conduction path for the subsequent metal electrode fabrication.

[0056] (4) Preparation of metal electrodes 1. For example Figure 1(e) The pattern of metal electrode 11 is defined by photolithography, and Ti layer (50nm), Pt layer (50nm) and Au layer (100nm) are deposited sequentially by magnetron sputtering equipment. The Ti layer serves as an adhesion layer to enhance the bonding force between the metal and the semiconductor, the Pt layer serves as a diffusion barrier layer to prevent Au from diffusing into the semiconductor, and the Au layer serves as a conductive layer to ensure low-resistance transmission.

[0057] 2. An 200 nm Au layer is deposited on the above-mentioned metal layer using an electron beam evaporation device to improve the conductivity and stability of the electrode.

[0058] 3. Immerse the deposited detector chip in acetone solution, use a syringe to blow air to help remove excess metal, and after cleaning, form a UBM metal layer.

[0059] (5) Preparation of indium pillars The indium pillar 12 of the detector chip is the core structure for interconnecting the detector chip and the readout circuit chip. The fabrication process is as follows: 1. Cleaning: The detector chip is briefly immersed in a dilute hydrochloric acid solution to remove surface oxides and impurities, then rinsed with deionized water and dried with nitrogen; then in-situ sputtering cleaning is performed using a low-energy Ar ion beam to obtain a highly clean and active metal surface.

[0060] 2. Photolithography: SUN1300 negative photoresist is coated on the surface of the detector chip, and pre-baking, exposure, post-baking, development, and base film processes are performed in sequence to define the indium pillar position pattern; the negative photoresist can form an inverted trapezoidal opening structure with a bottom size smaller than the top size, which provides a guarantee for subsequent metal stripping.

[0061] 3. Indium pillar deposition: High-purity indium (99.999%) is deposited using a thermal evaporation method in a tantalum or boron nitride crucible. During the deposition process, a circulating cooling system is used to control the detector chip temperature below 50°C to avoid photoresist pattern deformation and thermal damage to the detector material. The deposition rate is controlled in stages: initially, a low deposition rate of 1 Å / s is used to form a uniform nucleation layer, which is then increased to 5-10 Å / s. A quartz crystal oscillator is used to monitor the thickness in real time to ensure that the indium pillar height reaches 8 μm.

[0062] 4. Stripping: Immerse the detector chip that has completed evaporation into an acetone solution, and use a syringe to blow air to help dissolve the photoresist layer from the edge, peeling off the indium layer in the non-target area to obtain the indium pillar with the preset pattern.

[0063] 5. Reflow: Place the detector chip in a formic acid vapor or hydrogen atmosphere, heat to 160-180℃ and hold for 30-60 seconds, causing the cylindrical indium pillar to transform into a hemispherical shape under surface tension. See [link to relevant documentation]. Figure 1(f) Improves the contact effect with the indium pillars of the readout circuit while removing the oxide layer on the surface of the indium pillars.

[0064] (II) Fabrication of metal layers and indium pillars for readout circuit chips This embodiment focuses on the fabrication of a readout circuit chip with a specification of 320×256 / 15μm. The specific steps are as follows: (1) Fabrication of under-bump metallization (UBM) layer 1. A metal layer pattern is defined on the surface of the readout circuit chip using photolithography.

[0065] 2. For the InAs / AlSb superlattice material system, a sputtering + evaporation composite deposition method is used to sequentially deposit metal layers: Adhesion layer Ti: 20-50nm thick, firmly bonded to the alumina passivation layer on the detector chip surface; Diffusion barrier layer Pt: 50-100nm thick. Compared with traditional Ni materials, it has better stability at high temperatures and can effectively prevent indium from diffusing into the superlattice material. Protective layer Au: 50-100nm thick, to prevent oxidation of the Pt layer.

[0066] 3. Immerse the readout circuit chip in acetone solution, and use a syringe to blow air to help remove excess metal, forming a UBM metal layer with a preset pattern.

[0067] (2) Fabrication of indium pillars for readout circuit chips 13 Repeating the entire process of cleaning, photolithography, evaporation, stripping, and reflow in the fabrication of the indium pillars in this embodiment of the detector chip, a hemispherical indium bump with a height of 8 μm is fabricated on the UBM metal layer of the readout circuit chip 14, as follows. Figure 1 (g).

[0068] (III) Flip-chip interconnection and subsequent processing (1) Flip-chip bonding The detector chip with prepared indium pillars and the readout circuit chip are precisely aligned, and flip-chip bonding is performed under 10 kg pressure. This ensures a tight bond between the indium pillars of the detector chip and the indium bumps of the readout circuit chip, forming a robust electrical conduction path and mechanical connection structure. This yields the antimony compound focal plane imaging chip based on the electron injection structure of this invention. Figure 1 (h).

[0069] (2) Follow-up processing 1. Substrate thinning: The substrate of the antimony focal plane imaging chip based on the electron injection structure of this invention is thinned to make the substrate thickness meet the requirements of the effective incident detection area of ​​infrared light and improve the light absorption efficiency.

[0070] 2. Dicing and Packaging: The wafer, after substrate thinning, is diced into individual devices (see...). Figure 2 The device was then encapsulated in a vacuum Dewar and a cooler was integrated to reduce system noise.

[0071] 3. Performance Testing: A professional optoelectronic performance testing system was used to conduct comprehensive testing on the packaged devices. The specific test content and result analysis are as follows: Test equipment and conditions: The test environment was room temperature, the light source was a monochromatic laser with a wavelength of 2000nm, and the test instrument was a B4200A semiconductor parameter analyzer. During the test, the dark current drift was monitored in real time, and the data was recorded after the signal stabilized to avoid the impact of drift on the test accuracy.

[0072] Photocurrent and dark current testing: such as Figure 3 As shown in (a), the photocurrent response of the device was tested at power levels of 0.49 μW, 0.78 μW, 1.45 μW, and 3.19 mW by adjusting the incident laser power. Simultaneously, the relationship between the dark current and voltage was also tested, with the voltage range being 0–2 V. The test curves show that the dark current remains constant at 10 mW throughout the entire voltage range. -7 The light intensity is below the A level, which demonstrates the excellent dark current suppression capability of the electron injection structure and the alumina passivation layer of this invention. The photocurrent shows a significant stepwise increase with the increase of incident light power, and a high response level can be achieved at low voltage (<2V), indicating that the device can still efficiently convert optical signals under low bias voltage.

[0073] Optical gain testing: The optical gain of the device is calculated based on the photocurrent and incident light power, such as... Figure 3 (a) When the incident laser power is 0.78 μW, the measured peak optical gain reaches 4264.8, far exceeding the gain level of traditional focal plane array devices (typically several hundred times); combined with Figure 3 (b) As can be seen from the gain-voltage curve, the gain reaches its maximum value at around 1.75V and then tends to stabilize, indicating that the gain characteristics of the device have good voltage regulation stability and the gain can be accurately matched by optimizing the bias voltage.

[0074] Response speed verification: Based on the rising and falling edge characteristics of the photocurrent in the test curve, combined with the carrier transit time analysis of the electron injection structure, since the electron injection is a nanopillar structure, it confines the carriers in a nanoscale space, and the transit path is greatly shortened. The calculated response time of the device is less than 10ns, which meets the response speed requirements of ultra-high frame rate imaging (frame rate and response time are inversely proportional, and a 10ns response corresponds to a frame rate of up to 100MHz).

[0075] Crosstalk test: The physical isolation effect of the electron injection structure was verified by testing the signal isolation between pixels of the focal plane array. The test results show that the crosstalk coefficient between adjacent pixels is less than 0.5%, which is much lower than that of traditional single-mesa focal plane devices (usually greater than 5%). This proves that the dual-mesa design and electron injection structure effectively suppress the diffusion of lateral photogenerated carriers, ensuring high resolution and high contrast of the image.

[0076] The core of this implementation lies in the high-density integration of the electron injection structure with focal plane array technology, which distinguishes it from traditional mesa technology and standard focal plane technology: To address the shortcomings of traditional mesa etching processes, such as electric field concentration at the edges, easy breakdown, and high leakage current, this invention employs a dual-mesa etching process combined with atomic layer deposition alumina passivation to effectively suppress edge electric field concentration and surface leakage, thereby improving device reliability.

[0077] To address the inherent bottlenecks of standard focal plane array technology, such as lateral carrier diffusion crosstalk, slow response speed, and weak dark current suppression, this invention utilizes the nano-lateral confinement effect of an electron injection structure to constrain the electric field and carriers, shorten carrier transit time, and reduce recombination probability. Simultaneously, it leverages the properties of photonic crystals to enhance the absorption efficiency of specific wavelengths of light, thus overcoming the contradiction between high gain and high response speed.

[0078] The electron injection structure of this invention has physical isolation characteristics, which is more conducive to improving the pixel density of the focal plane array, reducing the process difficulty of high pixel integration, improving the uniformity of device performance, and meeting the application needs of cutting-edge fields such as strategic early warning, quantum communication, super-resolution microscopy imaging, and high-speed lidar.

Claims

1. An antimony focal plane imaging chip based on an electron injection structure, comprising a detector chip and a readout circuit chip, wherein the detector chip and the readout circuit chip are interconnected by flip-chip bonding via an indium pillar structure, characterized in that, The detector chip includes an electron injection structure, which is formed in an antimony epitaxial wafer by a double-mesa etching process. The electron injection structure is a nanopillar unit used to confine the electric field and photogenerated carriers through a nanoscale lateral confinement effect.

2. The imaging chip as described in claim 1, characterized in that, The electron injection structure includes, from bottom to top, an HPT collector region, an HPT base region, an HPT emitter region, an HPT second n-type ohmic contact layer, and an N-type capping layer.

3. The imaging chip as described in claim 2, characterized in that, The HPT collector region is an n-type doped InGaAsSb structure with a thickness of 200-350 nm and a doping concentration ≥ 5 × 10⁻⁶. 15 cm -3 The HPT base region is Be-doped GaSb with a thickness of 30-60 nm and a doping concentration ≥10%. 16 cm -3 The HPT emitter region is a Si-doped InAs / AlSb structure with a thickness of 200-500 nm and a doping concentration ≥ 5 × 10⁻⁶. 17 cm -3 The HPT second n-type ohmic contact layer is an n-type doped InAs / AlSb structure with a thickness of 300-600 nm and a doping concentration ≥ 2 × 10⁻⁶. 18 cm -3 The N-type capping layer is Si-doped InAs with a thickness of 20-60 nm and a doping concentration ≥ 2 × 10⁻⁶. 18 cm -3 .

4. The imaging chip as described in claim 1, characterized in that, The dual-mesa etching process includes: etching an initial mesa using a large-mesa photomask, then using a small-mesa photomask for further etching on the initial mesa, with the etching depth being the distance from the HPT collector region to the N-type capping layer, forming a large and small dual-mesa structure. The electron injection structure is located inside the small mesa, forming a large mesa on the first n-type ohmic contact layer of the HPT. The first n-type ohmic contact layer of the HPT and the HPT collector region inside the large mesa constitute a pillar structure. The first n-type ohmic contact layer of the HPT is an n-type doped InGaAsSb structure with a thickness of 400-600 nm and a doping concentration ≥ 2 × 10⁻⁶. 18 cm -3 .

5. The imaging chip as described in claim 1, characterized in that, The detector chip surface is covered with an aluminum oxide passivation layer, which is formed by atomic layer deposition.

6. The imaging chip as described in claim 1, characterized in that, The detector chip includes a metal electrode, which includes a Ti layer, a Pt layer and an Au layer deposited sequentially, wherein the Ti layer has a thickness of 50 nm, the Pt layer has a thickness of 50 nm, the Au layer has a thickness of 100 nm, and an additional 200 nm thick Au layer is deposited.

7. The imaging chip as described in claim 1, characterized in that, The indium pillar structure includes a hemispherical indium pillar with a height of 8 μm, which is formed by thermal evaporation of indium with a purity of 99.999% and then processed by a reflow process.

8. The imaging chip as described in claim 1, characterized in that, The readout circuit chip is a CMOS readout circuit with 320×256 pixels and a pixel size of 15μm. A bump under-metallization layer is prepared on its surface. The bump under-metallization layer includes a Ti adhesion layer, a Pt diffusion barrier layer and an Au protective layer.

9. The imaging chip as described in claim 1, characterized in that, The flip-chip bonding is performed under a pressure of 10 kg, which enables the indium pillars of the detector chip to be mechanically and electrically connected to the indium bumps of the readout circuit chip.

10. The imaging chip as described in claim 1, characterized in that, The electron injection structure has photonic crystal properties, which is used to enhance the light absorption efficiency at a specific wavelength and reduce inter-pixel crosstalk through physical isolation, with a crosstalk coefficient of less than 0.5%.

Images