Semiconductor package, imaging device, electronic device, and method for manufacturing semiconductor package

Abstract

The present invention achieves high-speed transmission in a wafer level package.　This semiconductor package is provided with a semiconductor chip, a first mold resin, a through via, and a rewiring layer. In the semiconductor package, the first mold resin covers the side surface of the semiconductor chip. In addition, in the semiconductor package, the through via penetrates the first mold resin. Further, the rewiring layer wires, as rewiring, a coplanar waveguide that connects a chip pad provided on the surface of the semiconductor chip and one end of the through via.

Description

Semiconductor package, imaging device, electronic device, and method for manufacturing semiconductor package

[0001] The present technology relates to a semiconductor package, and more particularly to a semiconductor package in which packaging is performed at a wafer level, an imaging device, an electronic device, and a method for manufacturing the semiconductor package.

[0002] Conventionally, semiconductor packages have been used in which a semiconductor chip having a semiconductor integrated circuit is mounted on a substrate and sealed, for the purpose of facilitating the handling of the semiconductor integrated circuit, etc. For example, a semiconductor package has been proposed in which a pad of a solid-state imaging element chip and one end of a through via that penetrates a molding resin around the chip are connected by rewiring in a rewiring layer (see, for example, Patent Document 1).

[0003] Japanese Patent Application Laid-Open No. 2008-211179

[0004] The above-mentioned conventional technology attempts to extend wiring to pads on the backside of a semiconductor package using rewiring and through-vias. However, the above-mentioned conventional technology has a problem in that the rewiring and other factors cause large reflections due to impedance mismatches, making it difficult to achieve high-speed transmission.

[0005] This technology was developed in light of these circumstances, and aims to achieve high-speed transmission in wafer-level packages.

[0006] The present technology has been made to solve the above-mentioned problems, and a first aspect thereof is a semiconductor package including a semiconductor chip, a first molding resin covering a side surface of the semiconductor chip, a through via penetrating the first molding resin, and a rewiring layer in which a coplanar waveguide is wired as a rewiring, the coplanar waveguide connecting a chip pad provided on a surface of the semiconductor chip to one end of the through via, thereby achieving an effect of realizing high-speed transmission.

[0007] In addition, in this first aspect, the through vias may include a pair of signal vias for transmitting differential signals and a plurality of ground vias formed around or on one side of the pair of signal vias, thereby providing an effect of facilitating impedance matching using the through vias.

[0008] In addition, in this first aspect, the rewiring may include a ground layer, a pair of ground lines formed between the ground layer and the first molding resin, and equal-length differential wiring for transmitting differential signals, the equal-length differential wiring being wired between the pair of ground lines, thereby providing an effect of facilitating impedance matching by the rewiring.

[0009] In addition, in the first aspect, a land pad connected to the other end of the through via may be further provided, thereby providing the effect of forming an LGA (Land Grid Array).

[0010] In addition, in the first aspect, an external terminal connected to the land pad may be further provided, thereby providing an effect that a BGA (Ball Grid Array) or the like is formed.

[0011] In addition, in this first aspect, a predetermined number of external terminals and an interposer connecting the external terminals to the other ends of the through vias may be further provided, thereby providing the effect of making it possible to arrange the external terminals in positions other than directly below the through vias.

[0012] In the first aspect, the diameter of the through via may be a value not exceeding 300 μm, thereby providing an effect of enabling the semiconductor package to be miniaturized.

[0013] In the first aspect, the resistivity of silicon of the semiconductor chip may be not less than 5000 Ω / cm, thereby reducing eddy current loss.

[0014] In the first aspect, the thickness of the semiconductor chip may be not less than 500 μm, thereby providing the effect of suppressing warpage of the semiconductor chip.

[0015] According to a second aspect of the present technology, there is provided an imaging device including: a semiconductor package including a semiconductor chip, a first molding resin covering a side surface of the semiconductor chip, a through via penetrating the first molding resin, and a rewiring layer in which a coplanar waveguide is wired as a rewiring, the coplanar waveguide connecting a chip pad provided on a surface of the semiconductor chip to one end of the through via; and an optical unit that focuses incident light and guides it to the semiconductor chip. This achieves high-speed transmission and improves the performance of the imaging device.

[0016] According to a third aspect of the present technology, there is provided an electronic device including a semiconductor package including: a transmitting unit that transmits a transmission wave; a receiving unit that receives a reception wave corresponding to the transmission wave; a semiconductor chip; a first molding resin that covers a side surface of the semiconductor chip; a through via that penetrates the first molding resin; and a rewiring layer in which a coplanar waveguide that connects a chip pad provided on a surface of the semiconductor chip to one end of the through via is wired as a rewiring. This achieves high-speed transmission, thereby improving the performance of the electronic device.

[0017] A fourth aspect of the present technology is a method for manufacturing a semiconductor package, the method including the steps of: forming a through via around a semiconductor chip; forming a first molding resin through which the through via penetrates and which covers a side surface of the semiconductor chip; and forming a rewiring layer in which a coplanar waveguide is wired as a rewiring, the coplanar waveguide connecting a chip pad provided on a surface of the semiconductor chip to one end of the through via. This produces the effect of manufacturing a semiconductor package capable of high-speed transmission.

[0018] In addition, in this first aspect, a resin frame may be further provided between the redistribution layer and the glass, thereby ensuring a sufficient distance from the light-receiving surface of the semiconductor chip to the glass.

[0019] The first side surface may further include a second molding resin that covers the side surface of the glass and the side surface of the resin frame, thereby improving the strength.

[0020] In addition, in this first aspect, a second molding resin may be further provided between the redistribution layer and the glass, thereby ensuring a sufficient distance from the light-receiving surface of the semiconductor chip to the glass.

[0021] In addition, in this first aspect, the semiconductor device may further include connection terminals that connect the redistribution layer and chip pads provided on the light-receiving surface of the semiconductor chip, and an underfill that covers the periphery of the connection terminals, thereby providing the effect of allowing the use of a process that does not damage the light-receiving surface of the semiconductor chip.

[0022] In addition, in the first aspect, a resin frame may be further provided between the rewiring layer and the glass, thereby ensuring a sufficient distance from the light-receiving surface of the semiconductor chip to the glass.

[0023] The first side surface may further include a second molding resin that covers the side surface of the glass and the side surface of the resin frame, thereby improving the strength.

[0024] In addition, in the first aspect, a second molding resin may be further provided between the redistribution layer and the glass, thereby ensuring a sufficient distance from the light-receiving surface of the semiconductor chip to the glass.

[0025] In the first aspect, the second molding resin may cover a side surface of the rewiring layer in the cavity, thereby suppressing light reflection on the side surface of the rewiring layer in the cavity.

[0026] In addition, in the first aspect, a rib may be further provided between the pixel portion of the semiconductor chip and the connection terminal, thereby preventing the underfill from entering the pixel portion.

[0027] In the first aspect, the underfill may further cover the periphery of the through via, thereby providing an effect of reducing the signal transmission distance and the package size.

[0028] In addition, in this first aspect, the distance between the light receiving surface of the semiconductor chip and one of the two surfaces of the glass facing the semiconductor chip may be no less than 300 micrometers, thereby suppressing flare and blemishes.

[0029] In addition, in this first aspect, a potting resin may be further provided between the redistribution layer and the glass, thereby ensuring a sufficient distance from the light-receiving surface of the semiconductor chip to the glass.

[0030] The first side surface may further include a second molding resin that covers the side surface of the glass and the side surface of the potting resin, thereby improving the strength.

[0031] In addition, in this first aspect, the semiconductor device may further include connection terminals that connect the redistribution layer and chip pads provided on the light-receiving surface of the semiconductor chip, and an underfill that covers the periphery of the connection terminals, thereby providing the effect of allowing the use of a process that does not damage the light-receiving surface of the semiconductor chip.

[0032] 1 is an example of a cross-sectional view of a semiconductor package according to a first embodiment of the present technology. FIG. 2 is a diagram showing a perspective view of rewiring according to the first embodiment of the present technology and a cross-sectional view of a rewiring layer and a mold resin according to the first embodiment of the present technology. FIG. 3 is a diagram showing a cross-sectional view of a mold resin according to the first embodiment of the present technology. FIG. 4 is a graph showing an example of a relationship between characteristic impedance and parameters according to the first embodiment of the present technology. FIG. 5 is an example of a cross-sectional view and a plan view of a CIS (CMOS Image Sensors) wafer according to the first embodiment of the present technology. FIG. 6 is a diagram for explaining a process up to singulation of a CIS wafer according to the first embodiment of the present technology. FIG. 7 is an example of a cross-sectional view and a plan view of a support wafer to which CIS chips are temporarily attached according to the first embodiment of the present technology. FIG. 8 is a diagram for explaining a process up to formation of rewiring according to the first embodiment of the present technology. FIG. 9 is a diagram for explaining a process up to removal of a protective film according to the first embodiment of the present technology. FIG. 10 is a diagram for explaining a process up to removal of a support wafer according to the first embodiment of the present technology. FIG. 11 is a diagram for explaining bonding of glass and singulation according to the first embodiment of the present technology. FIG. 12 is a flowchart showing an example of a method for manufacturing a semiconductor package according to the first embodiment of the present technology. FIG. 13 is an example of a cross-sectional view of a semiconductor package according to a second embodiment of the present technology. FIG. 10 is an example of a cross-sectional view of a semiconductor package according to a third embodiment of the present technology. FIG. 11 is a block diagram showing an example of a configuration of an imaging device according to a fourth embodiment of the present technology. FIG. 12 is a cross-sectional view showing an example of a configuration of an electronic device according to a fifth embodiment of the present technology. FIG. 13 is an example of a cross-sectional view of a semiconductor package according to a sixth embodiment of the present technology. FIG. 14 is an example of a cross-sectional view of a semiconductor package according to a modified example of the sixth embodiment of the present technology. FIG. 15 is an example of a cross-sectional view of a semiconductor package according to a seventh embodiment of the present technology. FIG. 16 is an example of a cross-sectional view of a semiconductor package according to an eighth embodiment of the present technology. FIG. 17 is an example of a cross-sectional view of a semiconductor package according to an eighth embodiment of the present technology. FIG. 18 is an example of a cross-sectional view of a semiconductor package according to an eighth embodiment of the present technology.13 is a diagram for explaining a process up to exposing one end of a through via in an eighth embodiment of the present technology. FIG. 14 is a diagram for explaining a process up to forming a back surface terminal in the eighth embodiment of the present technology. FIG. 15 is a diagram for explaining a process up to singulation in the eighth embodiment of the present technology. FIG. 16 is an example of a cross-sectional view of a semiconductor package in a first modified example of the eighth embodiment of the present technology. FIG. 17 is a diagram for explaining a process up to bonding a glass and a black resin frame in a first modified example of the eighth embodiment of the present technology. FIG. 18 is a diagram for explaining a process up to singulation in the first modified example of the eighth embodiment of the present technology. FIG. 19 is an example of a cross-sectional view of a semiconductor package in a second modified example of the eighth embodiment of the present technology. FIG. 19 is a diagram for explaining a process up to bonding a glass and a black resin frame in a second modified example of the eighth embodiment of the present technology. FIG. 19 is a diagram for explaining a process up to debonding a glass substrate in a second modified example of the eighth embodiment of the present technology. FIG. 19 is a diagram for explaining a process up to singulation in the second modified example of the eighth embodiment of the present technology. FIG. 19 is an example of a cross-sectional view of a semiconductor package in a third modified example of the eighth embodiment of the present technology. FIG. 19 is a diagram for explaining a molding process in a third modified example of the eighth embodiment of the present technology. 13 is a diagram for explaining a process up to flip chip connection in a third modified example of the eighth embodiment of the present technology. FIG. 14 is a diagram for explaining a process up to singulation in a third modified example of the eighth embodiment of the present technology. FIG. 15 is an example of a cross-sectional view of a semiconductor package in a fourth modified example of the eighth embodiment of the present technology. FIG. 16 is a diagram for explaining a molding process in a fourth modified example of the eighth embodiment of the present technology. FIG. 17 is a diagram for explaining a process up to flip chip connection in a fourth modified example of the eighth embodiment of the present technology. FIG. 18 is a diagram for explaining a process up to singulation in a fourth modified example of the eighth embodiment of the present technology. FIG. 19 is an example of a cross-sectional view of a semiconductor package in a fifth modified example of the eighth embodiment of the present technology. FIG. 19 is another example of a cross-sectional view of a semiconductor package in a sixth modified example of the eighth embodiment of the present technology. FIG. 19 is an example of a cross-sectional view of a semiconductor package in a ninth embodiment of the present technology.10 is a diagram for explaining a manufacturing process of a semiconductor package according to a ninth embodiment of the present technology. FIG. 11 is an example of a cross-sectional view of a semiconductor package according to a first modified example of the ninth embodiment of the present technology. FIG. 12 is a diagram for explaining a manufacturing process of a semiconductor package according to a first modified example of the ninth embodiment of the present technology. FIG. 13 is an example of a cross-sectional view of a semiconductor package according to a second modified example of the ninth embodiment of the present technology. FIG. 14 is a diagram for explaining a process up to application of potting resin and bonding of glass according to a second modified example of the ninth embodiment of the present technology. FIG. 15 is a diagram for explaining a process up to singulation according to a second modified example of the ninth embodiment of the present technology. FIG. 16 is an example of a cross-sectional view of a semiconductor package according to a third modified example of the ninth embodiment of the present technology. FIG. 17 is a diagram for explaining a process up to application of potting resin and bonding of glass according to a third modified example of the ninth embodiment of the present technology. FIG. 18 is a diagram for explaining a process up to debonding of a glass substrate according to a third modified example of the ninth embodiment of the present technology. FIG. 19 is a diagram for explaining a process up to singulation according to a third modified example of the ninth embodiment of the present technology. FIG. 19 is a block diagram showing an example of a schematic configuration of a vehicle control system. FIG. 19 is an explanatory diagram showing an example of installation positions of an outside-vehicle information detection unit and an imaging unit.

[0033] Hereinafter, modes for carrying out the present technology (hereinafter referred to as embodiments) will be described. The description will be made in the following order. 1. First embodiment (an example in which a coplanar waveguide is wired as a rewiring) 2. Second embodiment (an example in which a coplanar waveguide is wired as a rewiring and an external terminal is formed) 3. Third embodiment (an example in which a coplanar waveguide is wired as a rewiring and an external terminal is formed via an interposer) 4. Fourth embodiment (an example in which a semiconductor package in which a coplanar waveguide is wired as a rewiring is provided in an imaging device) 5. Fifth embodiment (an example in which a semiconductor package in which a coplanar waveguide is wired as a rewiring is provided in an electronic device) 6. Sixth embodiment (an example in which a coplanar waveguide is wired as a rewiring and a black resin frame is added) 7. Seventh embodiment (an example in which a coplanar waveguide is wired as a rewiring and a molding resin is added) 8. Eighth embodiment (an example in which a coplanar waveguide is wired as a rewiring and a non-open molding process is used) 9. Ninth embodiment (an example in which a coplanar waveguide is used as a rewiring and potting resin is added) 10. Application to a mobile object

[0034] 1 is an example of a cross-sectional view of a semiconductor package 200 according to a first embodiment of the present technology. The semiconductor package 200 is a fan-out wafer-level package (FOWLP) and includes glass 210, a CIS chip 220, a mold resin 230, and a redistribution layer 240.

[0035] The CIS chip 220 is, for example, a semiconductor chip having a CIS function. A pixel section 221 is formed on one of both surfaces of the CIS chip 220. In this pixel section 221, a plurality of pixels that photoelectrically convert incident light are arranged in a two-dimensional lattice pattern. Of the two surfaces of the CIS chip 220, the surface on which the pixel section 221 is formed will hereinafter be referred to as the "top surface" or "front surface," and the surface without the pixel section 221 will hereinafter be referred to as the "bottom surface" or "back surface." A predetermined number of chip pads 222 are formed around the pixel section 221 on the front surface of the CIS chip 220.

[0036] The CIS chip 220 is an example of a semiconductor chip described in the claims.

[0037] The optical axis perpendicular to the surface of the CIS chip 220 is referred to as the "Z-axis." A predetermined axis parallel to the surface of the CIS chip 220 is referred to as the "X-axis," and an axis perpendicular to the X-axis and Z-axis is referred to as the "Y-axis." The figure is a cross-sectional view seen from the Y-axis direction.

[0038] The mold resin 230 covers the periphery of the pixel section 221 on the surface of the CIS chip 220 and the side surfaces of the CIS chip 220, and seals the cavity. Here, the cavity is the space between the glass 210 and the CIS chip 220. The mold resin 230 is an example of a first mold resin described in the claims.

[0039] The mold resin 230 also includes a predetermined number of TMVs (Through Mold Vias) 260 that penetrate the mold resin 230 along the Z-axis direction. The upper ends of the TMVs 260 are connected to the rewiring layer 240, and the lower ends are connected to the land pads 271. The TMVs 260 are an example of the through vias described in the claims.

[0040] A predetermined number of land pads 271 are arranged on the lower surface of the mold resin 230, and these pads form an LGA.

[0041] The rewiring layer 240 is formed on top of the molding resin 230, and a predetermined number of rewirings 250 are wired in this layer. The rewirings 250 are coplanar waveguides, and connect the chip pads 222 and the upper ends of the TMVs 260.

[0042] The glass 210 is bonded to the top surface of the redistribution layer 240 .

[0043] [Configuration Example of Rewiring and TMV] Fig. 2 is a diagram showing a perspective view of a rewiring 250 according to the first embodiment of the present technology and a cross-sectional view of a rewiring layer 240 and a molding resin 230. In the same figure, "a" is a perspective view showing an example of the structure of the rewiring 250. In the same figure, "b" is a cross-sectional view of the rewiring layer 240 cut along line A-A' in Fig. 1 and seen from the Z-axis direction. In Fig. 2, "c" is a cross-sectional view of the molding resin 230 cut along line B-B' in Fig. 1 and seen from the Z-axis direction.

[0044] As illustrated in FIG. 2A, the rewiring 250 includes a ground layer 251, ground lines 252 and 253, and a differential equal-length wiring 254. The ground lines 252 and 253 are formed on the underside of the dielectric layer 241 in the rewiring layer 240. The differential equal-length wiring 254 is routed in the gap between these ground lines. This differential equal-length wiring 254 is composed of signal lines 254-1 and 254-2 of the same length and transmits differential signals. Transmitting differential signals can reduce noise during high-speed transmission compared to transmitting single-ended signals. The two-layer wiring illustrated in FIG. 2A is called a coplanar waveguide. Note that the rewiring 250 can also have three or more layers.

[0045] As shown in FIG. 1B, a predetermined number of rewirings 250 such as rewirings 250-1, 250-2, 250-3, etc. are wired in the rewiring layer 240. These structures are the same as those shown in FIG.

[0046] As shown in Fig. 3(c), the TMV 260 in the molded resin 230 includes signal vias 262 and 263 and a plurality of ground vias 261 formed around the signal vias 262 and 263. The signal vias 262 and 263 are TMVs that transmit differential signals. Alternatively, as shown in Fig. 3(c), the TMV 260 in the molded resin 230 includes signal vias 262 and 263 and a plurality of ground vias 261 formed on one side of the signal vias 262 and 263. The signal vias 262 and 263 are TMVs that transmit differential signals.

[0047] FIG. 4 is a graph showing an example of the relationship between the characteristic impedance and the parameters according to the first embodiment of the present technology.

[0048] When designing signal transmission lines such as wiring materials for electric circuits or printed circuit board patterns, it is necessary to take into account their characteristic impedance. Matching all characteristic impedances to the same value within a transmission line or electric circuit block, taking into account the input and output impedance of semiconductor devices, is generally called impedance matching.

[0049] If the impedance is not matched, the signal will be reflected and the transmission efficiency will be reduced. On the other hand, if the impedance is matched, the power transmission will be optimized and the energy will be used efficiently. Therefore, impedance matching can minimize the reflection.

[0050] In calculating impedance, an equivalent circuit having parameters R, L, G, and C is used. R is the resistance component per unit length, L is the inductance component per unit length, G is the conductance component per unit length, and C is the capacitance component per unit length. The characteristic impedance Z of this equivalent circuit is ０ is expressed by the following formula:

[0051] In the above equation, ω is the angular frequency of the AC current.

[0052] In Equation 1, R and G are very small, and if the transmission line can be approximated as lossless, then R=0 and G=0, and the following equation is obtained from Equation 1: Z ０ ≒ (L / C) １／２ ...Formula 2

[0053] The capacitance component C of the coplanar waveguide is expressed by the following equation: C=ε(S / d) Equation 3 In the above equation, ε is the dielectric constant of the dielectric layer 241, S is the overlap area between the ground layer 251 and the differential equal-length wiring 254, and d is the distance (in other words, the gap) between the ground layer 251 and the differential equal-length wiring 254.

[0054] From Equation 2 and Equation 3, if the parameters other than S are constant, the following relational expression is obtained: Z ０ ∝(1 / S) １／２ ...Formula 4

[0055] In the figure, a indicates the characteristic impedance Z of the rewiring 250, which is a coplanar waveguide. ０ 4 is a graph showing an example of the relationship between the overlap area S and the characteristic impedance Z ０ can be lowered.

[0056] Furthermore, from Equation 2 and Equation 3, if the parameters other than d are constant, the following relational expression is obtained: Z ０ ∝d １／２ ...Equation 5

[0057] In the figure, b indicates the characteristic impedance Z ０ 5 is a graph showing an example of the relationship between the distance (gap) d and the characteristic impedance Z ０ can be increased.

[0058] In addition, c in the same figure is the characteristic impedance Z of the rewiring 250 ０ 2 is a graph showing an example of the relationship between the signal line width W of the differential equal length wiring 254 and the characteristic impedance Z ０ can be increased.

[0059] For example, when polyimide is used as the dielectric layer 241, its dielectric constant ε is approximately 3.2. If the distance d is 10 μm and the pitch between the differential equal-length wiring 254 and the ground lines 252 and 253 is 120 μm, the characteristic impedance Z ０ can be about 100 Ω.

[0060] The impedance of the TMV 260 can be calculated in the same manner as for the rewiring 250. For example, when an epoxy resin is used as the molding resin 230, its dielectric constant is about 4.2. If the pitch between the signal vias 262 and 263 and the pitch of the ground vias 261 are both 200 μm, the characteristic impedance Z of the TMV 260 is ０ can be about 100 Ω.

[0061] As described above, by using the coplanar waveguide as the rewiring 250 and arranging multiple ground vias around the signal via (or on only one side of the signal via) for the TMV 260, it is possible to easily match the impedances of the two. This reduces transmission loss due to reflections on the paths (such as the rewiring 250 and the TMV 260) that transmit differential signals, enabling high-speed transmission.

[0062] For example, if a single layer of rewiring 250 that is not a coplanar waveguide is used, the maximum speed per lane is about 10 Gbps (Gigabits per second), but by using a coplanar waveguide, 20 Gbps per lane can be achieved.

[0063] Furthermore, it is preferable that the diameter of the TMVs 260 such as ground vias and signal vias is 300 μm or less, which allows the semiconductor package 200 to be miniaturized.

[0064] Furthermore, the resistivity of the silicon of the CIS chip 220 is preferably 5000 Ω / cm or more, which allows the eddy current loss in the CIS chip 220 to be reduced.

[0065] Furthermore, it is preferable that the thickness of the CIS chip 220, which is the size in the Z-axis direction, is 500 μm or more, which makes it possible to suppress warping of the CIS chip 220.

[0066] [Manufacturing Method of Semiconductor Package] Next, a manufacturing method of the semiconductor package 200 will be described with reference to FIGS.

[0067] 5A and 5B, a pixel portion 221 is formed for each CIS chip on the upper surface of the CIS wafer 201, and the chip thickness is adjusted by polishing the lower surface (i.e., the back surface). In the figure, "a" is an example of a cross-sectional view of the CIS wafer 201, and "b" is an example of a top view of the CIS wafer 201. The dotted lines in "a" indicate the boundary lines between the CIS chips separated by dicing.

[0068] For example, each pixel in the pixel section 221 is formed by forming a color filter on the photodiode and providing an OCL (On Chip Lens) on top of that.

[0069] 6A, a seed layer 301 made of Cu (copper), Ti (titanium), or the like is formed on the upper surface of the CIS wafer 201. Then, as shown in FIG. 6B, Cu pillars are formed around the pixel portions 221 by plating, and these Cu pillars are used as chip pads 222.

[0070] Then, as shown in FIG. 1C, the seed layer 301 is removed. Then, as shown in FIG. 1D, a protective film 302 is adhered to the pixel section 221. The protective film 302 is made of, for example, a silicone resin. Silicone resin is highly flexible, so it can be attached without damaging the pixel section 221. Then, as shown in FIG. 1E, dicing is performed along the dotted lines, and the CIS wafer 201 is divided into a plurality of CIS chips 220.

[0071] 7A and 7B, each of the CIS chips 220 is temporarily attached to the upper surface of the support wafer 303 along an alignment mark (not shown). Illustrated in FIG. 7A is an example of a cross-sectional view of the support wafer 303, and Illustrated in FIG. 7B is an example of a top view of the support wafer 303.

[0072] Next, as shown in FIG. 8A, Cu pillars are attached around the periphery of the CIS chip 220. These Cu pillars are used as TMVs 260. Then, as shown in FIG. 8B, a molding resin 230 is formed by a transfer molding method, a compression molding method, or the like. The upper part of the support wafer 303, which is integrated by filling with this molding resin 230, is used as a pseudo wafer 304. Then, as shown in FIG. 8C, the upper surface (front surface) of the support wafer 303 is polished by CMP (Chemical Mechanical Polishing) or the like until the chip pads 222 and the upper ends of the TMVs 260 are exposed.

[0073] Then, as illustrated in d in the figure, a dielectric layer 241 is formed, and the first layer of differential equal-length wiring 254 of the rewiring 250 is formed. The dielectric layer 241 is formed by, for example, processes of coating, pre-baking, exposure, development, curing, and descum treatment. The differential equal-length wiring 254 is formed by, for example, processes of forming a seed layer, forming wiring, and removing the seed layer.

[0074] Next, as illustrated in FIG. 9A, a dielectric layer 241 is further formed. Then, as illustrated in FIG. 9B, a second ground layer 251 of the rewiring 250 is formed. The steps of FIG. 9A and FIG. 9B are the same as the step of FIG. 8D. The thickness of each of the two dielectric layers is, for example, about 8 to 10 μm, and the thickness of the wiring (differential equal-length wiring 254 and ground layer 251) is, for example, 3 to 5 μm. Then, as illustrated in FIG. 9C, a dielectric layer 241 is further formed, and the rewiring layer 240 is obtained. Then, as illustrated in FIG. 9D, the protective film 302 is removed by air suction, and the pixel section 221 is cleaned.

[0075] 10A, the pseudo wafer 304 is removed from the support wafer 303, and the pseudo wafer 304 is turned upside down and reattached to the upper surface of the support wafer 303. Then, as shown in FIG. 10B, land pads 271 are formed on the back surface of the pseudo wafer 304 by plating. Then, as shown in FIG. 10C, the support wafer 303 is removed.

[0076] 11A, glass 210 is bonded to each semiconductor package 200. Then, as shown in FIG. 11B, dicing is performed along the dotted lines, and the pseudo wafer 304 is divided into a plurality of semiconductor packages 200.

[0077] 12 is a flowchart showing an example of a method for manufacturing a semiconductor package according to the first embodiment of the present technology. The back surface of the CIS wafer 201, on which the pixel portion 221 is formed on the front surface, is polished (step S901), and a seed layer 301 is formed (step S902). Then, Cu pillars are formed as chip pads 222 by plating (step S903), and the seed layer 301 is removed (step S904).

[0078] Next, the protective film 302 is adhered to the pixel portion 221 (step S905), and the CIS wafer 201 is divided into individual pieces (step S906). Then, the CIS chips 220 are temporarily attached to the upper surface of the support wafer 303 (step S907), and Cu pillars are attached as TMVs 260 (step S908).

[0079] Next, molding resin 230 is formed by a molding method (step S909), and the upper surface (front surface) of support wafer 303 is polished until chip pads 222 and the upper ends of TMVs 260 are exposed (step S910). Then, the first layer of rewiring 250 is formed (step S911), and the second layer is formed (step S912).

[0080] Next, the protective film 302 is removed, and the pixel section 221 is cleaned (step S913).Then, the pseudo wafer 304 is turned upside down, and the wafer is replaced (step S914).

[0081] Next, land pads 271 are formed on the back surface of the pseudo wafer 304 (step S915), and the support wafer 303 is removed (step S916). Then, glass 210 is bonded to each semiconductor package 200 (step S917), and the pseudo wafer 304 is divided into individual pieces (step S918). This completes the process of manufacturing the semiconductor package 200.

[0082] As described above, according to the first embodiment of the present technology, the coplanar waveguide is wired as the rewiring 250, and therefore, impedance matching can be easily performed by adjusting the parameters thereof. This reduces transmission loss due to reflection in the path through which the differential signal is transmitted, and enables high-speed transmission.

[0083] 2. Second Embodiment In the first embodiment described above, an LGA was formed on the lower surface (back surface) of the semiconductor package 200. However, a BGA can be formed instead of the LGA. The semiconductor package 200 in this second embodiment differs from the first embodiment in that a BGA is formed on the back surface.

[0084] 13 is an example of a cross-sectional view of a semiconductor package 200 according to a second embodiment of the present technology. The semiconductor package 200 according to the second embodiment differs from the first embodiment in that solder balls 272 are further provided on land pads 271 on the back surface. A BGA is formed by arranging the solder balls 272. The solder balls 272 are an example of external terminals as defined in the claims.

[0085] As described above, according to the second embodiment of the present technology, the solder balls 272 are provided on the back surface, and therefore, a BGA can be formed by arranging them.

[0086] 3. Third Embodiment In the second embodiment described above, the solder balls 272 are directly connected directly below the land pads 271, but it is preferable to form more solder balls 272. The semiconductor package 200 in this third embodiment differs from the second embodiment in that the solder balls 272 are arranged on an interposer.

[0087] 14 is an example of a cross-sectional view of a semiconductor package 200 according to the second embodiment of the present technology. The semiconductor package 200 according to the third embodiment differs from the second embodiment in that an interposer 270 is further provided.

[0088] The interposer 270 is formed on the rear surface of the CIS chip 220 and the mold resin 230, and a predetermined number of solder balls 272 are formed on the rear surface of the interposer 270. The interposer 270 connects the lower end of the TMV 260 to the solder balls 272. By using the interposer 270, the solder balls 272 can be arranged in places other than directly below the TMV 260.

[0089] As described above, according to the third embodiment of the present technology, since the interposer 270 is added, the solder balls 272 can be arranged in places other than directly below the TMV 260 .

[0090] 4. Fourth Embodiment The semiconductor package 200 of the first embodiment described above can be used in a variety of devices and equipment. In this fourth embodiment, the semiconductor package 200 is used in an imaging device.

[0091] 15 is a block diagram showing an example configuration of an imaging device 100 according to a fourth embodiment of the present technology. The imaging device 100 is a device for capturing image data, and includes an optical unit 110, a semiconductor package 200, and a DSP (Digital Signal Processing) circuit 120. The imaging device 100 further includes a display unit 130, an operation unit 140, a bus 150, a frame memory 160, a storage unit 170, and a power supply unit 180. The imaging device 100 is expected to be a camera mounted on a smartphone, an in-vehicle camera, or the like.

[0092] The optical unit 110 collects light from a subject and guides it to a CIS chip 220 (not shown) in a semiconductor package 200. The structure of this semiconductor package 200 is the same as that of the first embodiment. The CIS chip 220 generates image data by photoelectric conversion and supplies the image data to a DSP circuit 120 via a signal line 209.

[0093] The DSP circuit 120 performs predetermined signal processing on the image data, and outputs the processed image data to a frame memory 160 or the like via a bus 150.

[0094] The display unit 130 displays image data. For example, a liquid crystal panel or an organic EL (Electro Luminescence) panel is assumed as the display unit 130. The operation unit 140 generates an operation signal in accordance with a user's operation.

[0095] The bus 150 is a common path for the optical unit 110, semiconductor package 200, DSP circuit 120, display unit 130, operation unit 140, frame memory 160, storage unit 170, and power supply unit 180 to exchange data with one another.

[0096] The frame memory 160 holds image data. The storage unit 170 stores various data such as image data. The power supply unit 180 supplies power to the semiconductor package 200, the DSP circuit 120, the display unit 130, etc.

[0097] The semiconductor package 200 of the second and third embodiments can be applied to the fourth embodiment.

[0098] As described above, according to the fourth embodiment of the present technology, the semiconductor package 200 is disposed inside the imaging device 100, and thus high-speed transmission can be realized, thereby improving the performance of the imaging device 100.

[0099] 5. Fifth Embodiment The semiconductor package 200 of the first embodiment described above can be used in various devices and equipment. In this fifth embodiment, the semiconductor package 200 is used in an electronic device.

[0100] 16 is a cross-sectional view showing an example of a configuration of an electronic device 400 according to a fifth embodiment of the present technology. The electronic device 400 is a millimeter-wave radar used, for example, for sensing the interior of an automobile. The electronic device 400 includes a lens barrel 410, a semiconductor package 200, a transmitter 420, a receiver 430, and an interposer substrate 440.

[0101] The structure of semiconductor package 200 is the same as that of the first embodiment, and is disposed inside lens barrel 410. Inside lens barrel 410, a predetermined number of lenses are provided to guide images of the driver and passengers driving the automobile to semiconductor package 200.

[0102] The transmitter 420 transmits millimeter waves to the driver and passengers as transmission waves. The receiver 430 receives information on the driver's and passengers' heartbeats and pulses as reception waves. The interposer substrate 440 electrically connects the semiconductor package 200 to the transmitter 420 and receiver 430.

[0103] The CIS chip 220 (not shown) in the semiconductor package 200 has the function of calculating the heart rate and pulse information of the driver and passengers received by the receiving unit 430, and can therefore be used as sensor fusion to detect the state of a person that is difficult to understand from video alone.

[0104] The semiconductor package 200 of the second and third embodiments can be applied to the fifth embodiment.

[0105] As described above, according to the fifth embodiment of the present technology, the semiconductor package 200 is disposed in the electronic device 400, and thus high-speed transmission can be realized, thereby improving the performance of the electronic device 400.

[0106] 6. Sixth Embodiment In the first embodiment described above, the glass 210 is bonded to the upper surface of the rewiring layer 240. However, with this configuration, dust adhering to the upper or lower surface of the glass 210 may cause stains on image data. Furthermore, flare may occur due to the incidence of light reflected by the rewiring layer 240. The semiconductor package 200 in this sixth embodiment differs from the first embodiment in that a black resin frame is disposed between the glass 210 and the rewiring layer 240.

[0107] 17 is an example of a cross-sectional view of a semiconductor package 200 according to a sixth embodiment of the present technology. The semiconductor package 200 according to the sixth embodiment differs from the first embodiment in that it further includes a black resin frame 280. The black resin frame 280 is a black resin member molded into a frame shape and is disposed between the glass 210 and the rewiring layer 240. The upper surface of the black resin frame 280 is bonded to the lower surface of the glass 210 with an adhesive, and the lower surface of the black resin frame 280 is bonded to the upper surface of the rewiring layer 240 with an adhesive.

[0108] The thickness dZ2 of the redistribution layer 240 is, for example, 100 micrometers (μm) or less. In the first embodiment, in which the thickness of the adhesive is negligible and the black resin frame 280 is not provided, the distance dZ3 from the light-receiving surface (top surface) of the CIS chip 220 to the bottom surface of the glass 210 is 100 micrometers (μm) or less. In this configuration, the distance dZ3 is too short, which may result in the above-mentioned stains and flare.

[0109] In contrast, in the sixth embodiment, the black resin frame 280 is disposed between the glass 210 and the rewiring layer 240, so the distance dZ3 can be increased by the thickness of the black resin frame 280. This makes it possible to suppress the occurrence of stains and flare. The distance dZ3 is preferably, for example, 300 micrometers (μm) or more. To satisfy this condition, the thickness dZ1 of the black resin frame 280 is preferably 200 micrometers (μm) or more.

[0110] Next, a description will be given of a method for manufacturing the semiconductor package 200 according to the sixth embodiment. In the sixth embodiment, the steps illustrated in FIGS.

[0111] 18A, the lower surface of the black resin frame 280 is bonded to the upper surface of the rewiring layer 240. It is assumed that the glass 210 has been previously bonded to the upper surface of the black resin frame 280. The wafer in FIG. 18A is then divided into individual pieces, and the semiconductor packages 200 are obtained as shown in FIG. 18B.

[0112] In the figure, the black resin frame 280, which has been previously adhered to the glass 210, is adhered to the rewiring layer 240, but the process of adhering the black resin frame 280 to the glass 210 and the process of adhering the black resin frame 280 to the rewiring layer 240 may be performed in that order. Also, in order to meet the customer's request to eventually remove the glass 210, a thermoplastic adhesive may be used as the adhesive between the glass 210 and the black resin frame 280. Also, each of the second to fifth embodiments can be applied to the sixth embodiment.

[0113] As described above, according to the sixth embodiment of the present technology, the black resin frame 280 is disposed between the glass 210 and the redistribution layer 240, and therefore it is possible to ensure a sufficient distance from the light receiving surface (upper surface) of the CIS chip 220 to the lower surface of the glass 210. This makes it possible to suppress the occurrence of flare and spots.

[0114] [Modification] In the sixth embodiment described above, the black resin frame 280 is disposed between the glass 210 and the rewiring layer 240. However, it is preferable to further reduce the size of the glass 210 and the black resin frame 280, and in doing so, it is preferable to ensure sufficient strength. The semiconductor package 200 in this modification of the sixth embodiment differs from the sixth embodiment in that the side surfaces of the glass 210 and the black resin frame 280 are covered with mold resin.

[0115] 19 is an example of a cross-sectional view of a semiconductor package 200 according to a modification of the sixth embodiment of the present technology. The semiconductor package 200 according to the modification of the sixth embodiment differs from the sixth embodiment in that it further includes a mold resin 235. In addition, the sizes of the glass 210 and the black resin frame 280 in the X direction and the Y direction are smaller than the size of the rewiring layer 240.

[0116] The mold resin 235 is a black resin formed by a molding method such as transfer molding, and this resin covers the side surfaces of the glass 210 and the black resin frame 280. In the configuration shown in the figure, the size of the glass 210 and the black resin frame 280 can be reduced, thereby reducing costs. Furthermore, since the side surfaces of the glass 210 and the black resin frame 280 are covered with the mold resin 235, the glass 210 and the like can be protected from the external environment and strength can be improved.

[0117] The mold resin 230 is an example of a first mold resin as defined in the claims, and the mold resin 235 is an example of a second mold resin as defined in the claims.

[0118] Next, a description will be given of a method for manufacturing the semiconductor package 200 according to the modification of the sixth embodiment. In the modification of the sixth embodiment, the steps illustrated in FIGS.

[0119] 20 a, the lower surface of the black resin frame 280 is adhered to the upper surface of the rewiring layer 240. It is assumed that the glass 210 is adhered in advance to the upper surface of the black resin frame 280. Note that the step of adhering the black resin frame 280 to the glass 210 and the step of adhering the black resin frame 280 to the rewiring layer 240 can be performed in this order.

[0120] Then, as shown in b in the figure, a mold resin 235 is formed using a mold 305 by a transfer molding method or the like so as to cover the side surfaces of the glass 210 and the side surfaces of the black resin frame 280. Then, the wafer shown in b in the figure is divided into individual pieces, and the semiconductor packages 200 are obtained as shown in c in the figure.

[0121] It should be noted that each of the second to fifth embodiments can be applied to the modified example of the sixth embodiment.

[0122] As described above, according to the modification of the sixth embodiment of the present technology, the side surfaces of the glass 210 and the black resin frame 280 are covered with the mold resin 235, which makes it possible to reduce the size of the glass 210 and the black resin frame 280 and thereby reduce costs. In addition, the glass 210 and the like can be protected from the external environment and their strength can be improved.

[0123] 7. Seventh Embodiment In the first embodiment described above, glass 210 is bonded to the upper surface of rewiring layer 240, but this configuration can cause the above-mentioned stains and flares. Semiconductor package 200 in this sixth embodiment differs from the first embodiment in that a mold resin is disposed between glass 210 and rewiring layer 240.

[0124] 21 is an example of a cross-sectional view of a semiconductor package 200 according to a seventh embodiment of the present technology. The semiconductor package 200 according to the seventh embodiment differs from the first embodiment in that it further includes a molded resin 235. The molded resin 235 is a resin formed by a molding method such as a transfer molding method, and is disposed between the glass 210 and the rewiring layer 240. In order to set the distance dZ3 to 300 micrometers (μm) or more, it is preferable that the thickness dZ1 of the molded resin 235 be 200 micrometers (μm) or more.

[0125] Next, a description will be given of a method for manufacturing the semiconductor package 200 according to the seventh embodiment. In the seventh embodiment, the steps illustrated in FIGS.

[0126] 22 a, a mold resin 235 is molded using a mold 305 by a transfer molding method or the like. A portion of the mold 305 protrudes downward, and the size of the protrusion in the X and Y directions is slightly larger than the size of the side surface (in other words, the inner wall) of the rewiring layer 240 in the cavity. This allows the mold 305 to be supported by a portion of the upper surface of the rewiring layer 240. In addition, a step is created between the mold resin 235 and the rewiring layer 240.

[0127] 22 b, the individual pieces of glass 210 are bonded to the upper surface of the mold resin 235. The wafer in FIG. 22 b is then individualized to obtain semiconductor packages 200 as illustrated in FIG. 22 c.

[0128] In the seventh embodiment, the molding resin 235 for each of the multiple chips can be filled at once using a molding method, thereby improving the throughput during manufacturing compared to the sixth embodiment.

[0129] It should be noted that each of the second to fifth embodiments can be applied to the seventh embodiment.

[0130] As described above, according to the seventh embodiment of the present technology, since the molding resin 235 is disposed between the glass 210 and the redistribution layer 240, a sufficient distance can be secured between the light receiving surface (upper surface) of the CIS chip 220 and the lower surface of the glass 210. This makes it possible to suppress the occurrence of flare and stains. Furthermore, since the molding resin 235 can be filled all at once by the molding method, it is possible to improve throughput.

[0131] 8. Eighth Embodiment In the first embodiment described above, the semiconductor package 200 is manufactured using the open molding process illustrated in FIG. 8. In this process, the top surface of the CIS chip 220 (in other words, the image surface) is exposed to process damage through the protective film from molding to the formation of the redistribution layer 240. There are also concerns that the image surface may be damaged when the protective film is removed, and that residue of the protective film may remain after cleaning. The semiconductor package 200 in this eighth embodiment differs from the first embodiment in that a process is used that does not cause process damage to the image surface.

[0132] 23 is an example of a cross-sectional view of a semiconductor package 200 according to an eighth embodiment of the present technology. In this eighth embodiment, a predetermined number of chip pads 222 are provided around a pixel section 221 on the upper surface (light-receiving surface) of a CIS chip 220. The lower surface of the redistribution layer 240 and the chip pads 222 on the upper surface of the CIS chip 220 are connected by connection terminals 275. The periphery of this connection terminal 275 is covered with underfill 276. For example, a Cu pillar bump, a solder microbump, or an Au stud bump may be used as the connection terminal 275.

[0133] The bottom surface of the CIS chip 220 is covered with a photosensitive insulating film 277, and rear terminals 278 are provided in openings in the photosensitive insulating film 277. As the rear terminals 278, for example, solder microbumps or LGA lands are used.

[0134] Next, a method for manufacturing the semiconductor package 200 according to the eighth embodiment will be described.

[0135] As shown in FIG. 24A, a wafer-shaped glass substrate 211 is prepared. The dotted lines in the figure indicate the boundaries between CIS chips that are separated by dicing, which will be described later. This also applies to subsequent cross-sectional views. As shown in FIG. 24B, a photosensitive insulating film is formed, and a Cu-RDL (redistribution layer), the first layer of the rewiring layer 240, is formed by SAP (semi-additive process). This layer is referred to as RDL1. PI (polyimide) or PBO (polybenzoxazole) is used as the photosensitive insulating film.

[0136] Then, as shown in FIG. 1c, a second layer of Cu-RDL is formed by SAP. This layer is called RDL2. Note that ground lines are wired in RDL1, and differential equal-length wiring is wired in RDL2. Then, as shown in FIG. 1d, pads are opened by applying a photosensitive insulating film, exposing it to light, and developing it, exposing the Cu in the Cu-RDL. Then, as shown in FIG. 1e, Ni / Au is formed in the pad openings by electroless plating.

[0137] Next, as illustrated in FIG. 25A, the photosensitive insulating film in the rewiring layer 240 that overlaps with the pixel section 221 of the CIS chip 220 is removed by lithography and etching.

[0138] Then, as shown in FIG. 1B, a CIS chip 220 on which connection terminals 275 for flip-chip connection (such as Au stud bumps or solder microbumps) are pre-formed is flip-chip connected. The connection portion is filled with underfill 276. This underfill 276 may be added before flip-chip connection or after flip-chip connection.

[0139] Then, as illustrated in c in the figure, a Cu pillar used as a TMV 260 is attached to the rewiring layer 240, and a molding resin 230 is formed by a molding method. After the Cu pillar is erected in this process, an underfill 276 can also be filled from the outside.

[0140] Then, as shown in d in the figure, the molding resin 230 is thinned by back grinding until one end of the TMV 260 is exposed, and is then flattened by CMP.

[0141] 26A, a photosensitive insulating material is applied to the rear surfaces of the CIS chip 220 and the mold resin 230 to form a photosensitive insulating film 277. A portion of the photosensitive insulating film 277 above the TMV 260 is opened by exposure and development.

[0142] Then, as shown in FIG. 1B, a process for forming back surface terminals 278 is performed. In this process, a barrier metal (titanium, titanium nitride, or the like) and a seed metal (Cu, or the like) are formed by sputtering. Then, a photoresist 306 is applied, and the UBM (Under Bump Metal) and solder microbump locations are patterned by exposure and development. Then, Cu-solder microbumps are formed by electrolytic plating, and then Ni or SnAg is formed by electroless plating.

[0143] Then, as shown in Fig. 1C, the photoresist 306 is removed, and the barrier and seed metal are removed by wet etching. Reflow is then performed to form solder microbumps as the back surface terminals 278. Note that the back surface terminals 278 may not be solder microbumps, but may be LGA lands.

[0144] 27A, the protective film (not shown) on the rear surface of the glass substrate 211 is peeled off, and the wafer is placed on a dicing tape 307 and divided into individual pieces. Then, as shown in FIG. 27B, the semiconductor package 200 is picked up, completing the manufacturing process.

[0145] 24 to 27, the image surface of the CIS chip 220 is not exposed during molding, and this process is called a "non-open molding process." This process can prevent process damage to the image surface.

[0146] It should be noted that each of the second to fifth embodiments can be applied to the eighth embodiment.

[0147] As described above, according to the eighth embodiment of the present technology, the non-open molding process is used, and therefore process damage to the image plane can be prevented.

[0148] In the eighth embodiment described above, the glass 210 is bonded to the upper surface of the rewiring layer 240. However, this configuration can cause the above-mentioned stains and flares. The semiconductor package 200 in this first modification of the eighth embodiment differs from the eighth embodiment in that a black resin frame is disposed between the glass 210 and the rewiring layer 240.

[0149] 28 is an example of a cross-sectional view of a semiconductor package 200 in a first modified example of the eighth embodiment of the present technology. The semiconductor package 200 in this first modified example of the eighth embodiment differs from the eighth embodiment in that it further includes a black resin frame 280. The black resin frame 280 is a black resin member molded in a frame shape and is disposed between the glass 210 and the rewiring layer 240. The upper surface of the black resin frame 280 is bonded to the lower surface of the glass 210 with an adhesive, and the lower surface of the black resin frame 280 is bonded to the upper surface of the rewiring layer 240 with an adhesive. In order to set the distance dZ3 to 300 micrometers (μm) or more, it is preferable that the thickness dZ1 of the black resin frame 280 be 200 micrometers (μm) or more.

[0150] Next, a description will be given of a method for manufacturing the semiconductor package 200 according to the first modification of the eighth embodiment. In the first modification of the eighth embodiment, the steps illustrated in FIGS. 24 to 26 are performed.

[0151] 29a, a wafer-shaped glass substrate 212 provided with a release layer 308 for temporary bonding is attached to the back surface on which the back surface terminals 278 are provided. Then, the glass substrate 211 is debonded.

[0152] Then, as illustrated in FIG. 1B, the wafer is turned upside down, and the lower surface of the black resin frame 280 is bonded to the upper surface of the rewiring layer 240. It is assumed that the glass 210 has been bonded in advance to the upper surface of the black resin frame 280. Note that the step of bonding the black resin frame 280 to the glass 210 and the step of bonding the black resin frame 280 to the rewiring layer 240 can be performed in that order.

[0153] 30A, the glass substrate 212 is debonded, and any residue of the release layer 308 on the backside is washed away. Then, as shown in FIG. 30B, the wafer is placed on dicing tape 307 and separated into individual pieces. Then, as shown in FIG. 30C, the semiconductor packages 200 are picked up, completing the manufacturing process.

[0154] It should be noted that each of the second to fifth embodiments can be applied to the first modified example of the eighth embodiment.

[0155] As described above, according to the first modified example of the eighth embodiment of the present technology, the black resin frame 280 is disposed between the glass 210 and the redistribution layer 240, so that a sufficient distance can be secured between the light receiving surface (upper surface) of the CIS chip 220 and the lower surface of the glass 210. This makes it possible to suppress the occurrence of flare and spots.

[0156] [Second Modification] In the first modification of the eighth embodiment described above, the black resin frame 280 is disposed between the glass 210 and the rewiring layer 240. However, it is preferable to further reduce the size of the glass 210 and the black resin frame 280, and in doing so, it is preferable to ensure sufficient strength. The semiconductor package 200 in this second modification of the eighth embodiment differs from the first modification of the eighth embodiment in that the side surfaces of the glass 210 and the black resin frame 280 are covered with mold resin.

[0157] 31 is an example of a cross-sectional view of a semiconductor package 200 according to a second modified example of the eighth embodiment of the present technology. The semiconductor package 200 according to the second modified example of the eighth embodiment differs from the first modified example of the eighth embodiment in that it further includes a mold resin 235. In addition, the sizes of the glass 210 and the black resin frame 280 in the X direction and the Y direction are smaller than the size of the redistribution layer 240.

[0158] The mold resin 235 is a resin formed by a molding method such as transfer molding, and covers the side surfaces of the glass 210 and the black resin frame 280 .

[0159] Next, a description will be given of a method for manufacturing the semiconductor package 200 according to the second modification of the eighth embodiment. In the second modification of the eighth embodiment, the steps illustrated in FIGS. 24 to 26 are performed.

[0160] 32a, a wafer-shaped glass substrate 212 provided with a release layer 308 for temporary bonding is attached to the back surface on which the back surface terminals 278 are provided. Then, the glass substrate 211 is debonded.

[0161] Then, as illustrated in FIG. 1B, the wafer is turned upside down, and the lower surface of the black resin frame 280 is bonded to the upper surface of the rewiring layer 240. It is assumed that the glass 210 has been bonded in advance to the upper surface of the black resin frame 280. Note that the step of bonding the black resin frame 280 to the glass 210 and the step of bonding the black resin frame 280 to the rewiring layer 240 can be performed in that order.

[0162] 33A, a mold resin 235 is formed by a transfer molding method or the like using a mold 305 so as to cover the side surfaces of the glass 210 and the black resin frame 280. Then, as shown in FIG. 33B, the glass substrate 212 is debonded, and any residue of the release layer 308 on the back surface is washed away.

[0163] 34A, the wafer is placed on a dicing tape 307 and divided into individual pieces. Then, as shown in FIG. 34B, the semiconductor packages 200 are picked up, completing the manufacturing process.

[0164] It should be noted that each of the second to fifth embodiments can be applied to the second modified example of the eighth embodiment.

[0165] As described above, according to the second modified example of the eighth embodiment of the present technology, the side surfaces of the glass 210 and the black resin frame 280 are covered with the mold resin 235, which makes it possible to reduce the size of the glass 210 and the black resin frame 280 and thereby reduce costs. In addition, the glass 210 and the like can be protected from the external environment and their strength can be improved.

[0166] In the eighth embodiment described above, the glass 210 is bonded to the upper surface of the rewiring layer 240. However, this configuration may cause the above-mentioned stains and flares. The semiconductor package 200 in this third modification of the eighth embodiment differs from the eighth embodiment in that a mold resin is disposed between the glass 210 and the rewiring layer 240.

[0167] 35 is an example of a cross-sectional view of a semiconductor package 200 according to a third modified example of the eighth embodiment of the present technology. The semiconductor package 200 according to the third modified example of the eighth embodiment differs from the eighth embodiment in that it further includes a mold resin 235. The mold resin 235 is a resin formed by a molding method such as a transfer molding method, and is disposed between the glass 210 and the redistribution layer 240.

[0168] Next, a description will be given of a method for manufacturing the semiconductor package 200 in the third modified example of the eighth embodiment. In the third modified example of the eighth embodiment, the steps illustrated in FIG.

[0169] Then, as illustrated in FIG. 36A, the photosensitive resin in the rewiring layer 240 that overlaps with the pixel section 221 of the CIS chip 220 is removed by lithography and etching.

[0170] Then, as illustrated in b in the figure, a wafer-like glass substrate 212 provided with a release layer (not shown) for temporary bonding is attached to the rewiring layer 240. Then, the glass substrate 211 is debonded.

[0171] Then, as illustrated in c in the figure, the product is turned upside down, and molding resin 235 is molded by a transfer molding method or the like using a mold 305. A part of the mold 305 protrudes downward, and the size of the protrusion in the X and Y directions is set to be slightly larger than the size of the side surface (inner wall) of the rewiring layer 240 in the cavity.

[0172] 37A, a wafer-shaped glass substrate 213 provided with a release layer (not shown) for temporary bonding is attached to the molding resin 235. Then, the glass substrate 212 is debonded. A thermoplastic adhesive can be used as the adhesive between the glass substrate 213 and the molding resin 235.

[0173] The substrate is then turned upside down as shown in FIG. 2B, and the CIS chip 220 is flip-chip bonded as shown in FIG. 2C. A molding resin 230 is then formed by a molding method. The molding resin 230 is then thinned by back-grinding until one end of the TMV 260 is exposed, and is then planarized by CMP. For example, the steps shown in FIG. 25 are performed.

[0174] Then, rear surface terminals 278 are formed as shown in Fig. 38a. For example, the steps shown in Fig. 26 are used. Then, as shown in Fig. 38b, the wafer is placed on dicing tape 307 and separated into individual pieces. Then, as shown in Fig. 38c, the semiconductor packages 200 are picked up, completing the manufacturing process.

[0175] It should be noted that each of the second to fifth embodiments can be applied to the third modified example of the eighth embodiment.

[0176] As described above, according to the third modification of the eighth embodiment of the present technology, since the molding resin 235 is disposed between the glass 210 and the redistribution layer 240, a sufficient distance can be secured between the light receiving surface (upper surface) of the CIS chip 220 and the lower surface of the glass 210. This makes it possible to suppress the occurrence of flare and stains. Furthermore, since the molding resin 235 can be filled all at once by the molding method, it is possible to improve throughput.

[0177] In the third modification of the eighth embodiment described above, a mold resin is disposed between the glass 210 and the redistribution layer 240. However, in this configuration, flare may occur due to light reflected on the side surfaces (inner walls) of the redistribution layer 240 within the cavity. The semiconductor package 200 in this fourth modification of the eighth embodiment differs from the third modification of the eighth embodiment in that the inner walls of the redistribution layer 240 are covered with a mold resin 235.

[0178] 39 is an example of a cross-sectional view of a semiconductor package 200 according to a fourth modified example of the eighth embodiment of the present technology. The semiconductor package 200 according to the fourth modified example of the eighth embodiment differs from the third modified example of the eighth embodiment in that the side surfaces (inner walls) of the redistribution layer 240 in the cavity are covered with a molding resin 235. This makes it possible to prevent light reflection on the inner walls.

[0179] Next, a method for manufacturing the semiconductor package 200 according to the fourth modification of the eighth embodiment will be described. In the fourth modification of the eighth embodiment, the steps illustrated in FIG.

[0180] Then, as shown in FIG. 40A, the photosensitive resin in the rewiring layer 240 that overlaps with the pixel section 221 of the CIS chip 220 is removed by lithography and etching.

[0181] Then, as illustrated in b in the figure, a wafer-like glass substrate 212 provided with a release layer (not shown) for temporary bonding is attached to the rewiring layer 240. Then, the glass substrate 211 is debonded.

[0182] Then, as illustrated in FIG. 1C, the substrate is turned upside down, and a mold resin 235 is molded using a mold 305 by a transfer molding method or the like. A portion of the mold 305 protrudes downward, and the size of the protrusion in the X and Y directions is slightly smaller than the size of the side surface (inner wall) of the rewiring layer 240 in the cavity. By using such a mold 305, the inner wall of the rewiring layer 240 can be covered with the mold resin 235. This makes it possible to prevent light reflection on the inner wall of the rewiring layer 240.

[0183] Then, the steps illustrated in Figures 41 and 42 are carried out. The steps in Figures 41 and 42 are similar to the steps illustrated in Figures 37 and 38.

[0184] It should be noted that each of the second to fifth embodiments can be applied to the fourth modified example of the eighth embodiment.

[0185] Thus, according to the fourth variant of the eighth embodiment of the present technology, the side surfaces (inner walls) of the redistribution layer 240 in the cavity are covered with the molding resin 235, thereby preventing light reflection on the inner walls.

[0186] In the first modification of the eighth embodiment described above, the periphery of the connection terminals 275 in the non-open molding process is covered with underfill 276. However, it is preferable to further reduce the signal transmission distance and package size. The semiconductor package 200 in this fifth modification of the eighth embodiment differs from the first modification of the eighth embodiment in that the periphery of the TMV 260 is also covered with underfill 276 in addition to the periphery of the connection terminals 275.

[0187] 43 is an example of a cross-sectional view of a semiconductor package 200 according to a fifth modified example of the eighth embodiment of the present disclosure. The semiconductor package 200 according to the fifth modified example of the eighth embodiment differs from the first modified example of the eighth embodiment in that the periphery of the TMV 260 is also covered with an underfill 276 in addition to the periphery of the connection terminals 275. In the TMV 260, a base portion close to the glass 210 is covered with the underfill 276.

[0188] By covering the periphery of the TMV 260 with the underfill 276, the TMV 260 can be erected at a location closer to the CIS chip 220 than in the first modification of the eighth embodiment, thereby reducing the signal transmission distance and package size.

[0189] Note that the second to fifth embodiments, the eighth embodiment, and the second to fourth modifications of the eighth embodiment can be applied to the fifth modification of the eighth embodiment.

[0190] As described above, according to the fifth modified example of the eighth embodiment of the present technology, the periphery of the connection terminal 275 and the periphery of the TMV 260 are covered with the underfill 276, thereby making it possible to reduce the signal transmission distance and package size.

[0191] [Sixth Modification] In the first modification of the eighth embodiment described above, the periphery of the connection terminal 275 is covered with the underfill 276 in the non-open molding process, but it is preferable to prevent the underfill 276 from entering the pixel portion 221. The semiconductor package 200 in this sixth modification of the eighth embodiment differs from the first modification of the eighth embodiment in that a rib is provided between the connection terminal 275 and the pixel portion 221.

[0192] 44 is an example of a cross-sectional view of a semiconductor package 200 in a sixth modified example of the eighth embodiment of the present technology. The semiconductor package 200 in the sixth modified example of the eighth embodiment differs from the first modified example of the eighth embodiment in that a rib 279 is further disposed between the connection terminal 275 and the pixel portion 221. The rib 279 functions as a breakwater, thereby preventing the underfill 276 from penetrating into the pixel portion 221. This makes it possible to suppress degradation of imaging quality caused by the penetration of the underfill 276.

[0193] Note that the second to fifth embodiments, the eighth embodiment, and the second to fourth modifications of the eighth embodiment can be applied to the sixth modification of the eighth embodiment.

[0194] As shown in FIG. 45, the fifth modified example of the eighth embodiment in which the periphery of the TMV 260 is also covered with the underfill 276 can be applied to the sixth modified example of the eighth embodiment.

[0195] As described above, according to the sixth modification of the eighth embodiment of the present technology, the rib is disposed between the connection terminal 275 and the pixel portion 221, thereby preventing the underfill 276 from entering the pixel portion 221 and suppressing deterioration of imaging quality. 9. Ninth Embodiment In the first embodiment described above, the glass 210 is bonded to the upper surface of the redistribution layer 240, but this configuration may cause the above-mentioned stains and flare. The semiconductor package 200 in this ninth embodiment differs from the first embodiment in that a potting resin is disposed between the glass 210 and the redistribution layer 240.

[0196] 46 is an example of a cross-sectional view of a semiconductor package 200 according to a ninth embodiment of the present technology. The semiconductor package 200 according to the ninth embodiment differs from the first embodiment in that it further includes a potting resin 290. The potting resin 290 is a resin applied using a dispenser or the like and is disposed between the glass 210 and the rewiring layer 240. To set the distance dZ3 to 300 micrometers (μm) or more, the thickness dZ1 of the potting resin 290 is preferably 200 micrometers (μm) or more. Furthermore, the sizes of the glass 210 and the potting resin 290 in the X direction and the Y direction can be made smaller than the size of the rewiring layer 240.

[0197] Next, a description will be given of a method for manufacturing the semiconductor package 200 according to the ninth embodiment. In the ninth embodiment, the steps illustrated in FIGS.

[0198] 47A, a liquid potting resin 290 is applied to the upper surface of the rewiring layer 240 using a dispenser or the like. The individual pieces of glass 210 are bonded to the upper surface of the potting resin 290. The wafer in FIG. 47A is then individualized to obtain semiconductor packages 200, as shown in FIG. 47B.

[0199] It should be noted that each of the second to fifth embodiments can be applied to the ninth embodiment.

[0200] As described above, according to the ninth embodiment of the present technology, the potting resin 290 is disposed between the glass 210 and the redistribution layer 240, thereby ensuring a sufficient distance from the light receiving surface (upper surface) of the CIS chip 220 to the lower surface of the glass 210. This makes it possible to suppress the occurrence of flare and stains. [First Modification] In the above-described ninth embodiment, the potting resin 290 is disposed between the glass 210 and the redistribution layer 240, but it is preferable to ensure sufficient strength. The semiconductor package 200 in this first modification of the ninth embodiment differs from the ninth embodiment in that the side surfaces of the glass 210 and the potting resin 290 are covered with mold resin.

[0201] 48 is an example of a cross-sectional view of a semiconductor package 200 according to a first modified example of the ninth embodiment of the present technology. The semiconductor package 200 according to the first modified example of the ninth embodiment differs from the ninth embodiment in that it further includes a mold resin 235.

[0202] The mold resin 235 covers the side surfaces of the glass 210 and the potting resin 290. Since the side surfaces of the glass 210 and the potting resin 290 are covered with the mold resin 235, the glass 210 and the like can be protected from the external environment and strength can be improved.

[0203] Next, a description will be given of a method for manufacturing the semiconductor package 200 according to the first modification of the ninth embodiment. In the first modification of the ninth embodiment, the steps illustrated in FIGS. 5 to 10 are performed.

[0204] 49A, a liquid potting resin 290 is applied by a dispenser or the like to the upper surface of the rewiring layer 240. The individual pieces of glass 210 are bonded to the upper surface of the potting resin 290.

[0205] Then, as shown in b in the figure, a mold resin 235 is formed using a mold 305 by a transfer molding method or the like so as to cover the side surfaces of the glass 210 and the side surfaces of the potting resin 290. Then, the wafer shown in b in the figure is divided into individual pieces, and the semiconductor packages 200 are obtained as shown in c in the figure.

[0206] It should be noted that each of the second to fifth embodiments can be applied to the first modified example of the ninth embodiment.

[0207] Thus, according to the first variant of the ninth embodiment of the present technology, the side surfaces of the glass 210 and the potting resin 290 are covered with the mold resin 235, thereby protecting the glass 210 and the like from the external environment and improving their strength.

[0208] [Second Modification] In the above-described ninth embodiment, the semiconductor package 200 is manufactured using the open molding process illustrated in FIG. 8 . In this process, the upper surface (image surface) of the CIS chip 220 is exposed to process damage through the protective film. There are also concerns that the image surface may be damaged when the protective film is removed, and that residue of the protective film may remain after cleaning. The semiconductor package 200 in this second modification of the ninth embodiment differs from the ninth embodiment in that a process that does not cause process damage to the image surface is used.

[0209] 50 is an example of a cross-sectional view of a semiconductor package 200 in a second modified example of the ninth embodiment of the present technology. In this second modified example of the ninth embodiment, a predetermined number of chip pads 222 are provided around a pixel unit 221 on the upper surface (light-receiving surface) of a CIS chip 220. The lower surface of the redistribution layer 240 and the chip pads 222 on the upper surface of the CIS chip 220 are connected by connection terminals 275 (e.g., Cu pillar bumps). The periphery of each connection terminal 275 is covered with an underfill 276.

[0210] The bottom surface of the CIS chip 220 is covered with a photosensitive insulating film 277 , and rear surface terminals 278 (solder microbumps or the like) are provided in openings of the photosensitive insulating film 277 .

[0211] Next, a description will be given of a method for manufacturing the semiconductor package 200 according to the second modification of the ninth embodiment. In the second modification of the ninth embodiment, the steps illustrated in FIGS. 24 to 26 are performed.

[0212] 51A, a wafer-shaped glass substrate 212 provided with a release layer 308 for temporary bonding is attached to the back surface on which the back surface terminals 278 are provided. Then, the glass substrate 211 is debonded.

[0213] Then, as illustrated in FIG. 1B, the wafer is turned upside down, a potting resin 290 is applied to the upper surface of the rewiring layer 240 , and the individual pieces of glass 210 are bonded to the upper surface of the potting resin 290 .

[0214] 52A, the glass substrate 212 is debonded, and any residue of the release layer 308 on the backside is washed away. Then, as shown in FIG. 52B, the wafer is placed on dicing tape 307 and separated into individual pieces. Then, as shown in FIG. 52C, the semiconductor packages 200 are picked up, completing the manufacturing process.

[0215] It should be noted that each of the second to fifth embodiments can be applied to the second modified example of the ninth embodiment.

[0216] As described above, according to the second modification of the ninth embodiment of the present technology, a non-open molding process is used, thereby preventing process damage to the image plane. [Third Modification] In the second modification of the ninth embodiment described above, the potting resin 290 is disposed between the glass 210 and the redistribution layer 240, but it is preferable to ensure sufficient strength. The semiconductor package 200 in this third modification of the ninth embodiment differs from the second modification of the ninth embodiment in that the side surfaces of the glass 210 and the potting resin 290 are covered with mold resin.

[0217] 53 is an example of a cross-sectional view of a semiconductor package 200 according to a third modified example of the ninth embodiment of the present technology. The semiconductor package 200 according to the third modified example of the ninth embodiment differs from the second modified example of the ninth embodiment in that it further includes a mold resin 235.

[0218] The mold resin 235 covers the side surfaces of the glass 210 and the potting resin 290. Since the side surfaces of the glass 210 and the potting resin 290 are covered with the mold resin 235, the glass 210 and the like can be protected from the external environment and strength can be improved.

[0219] Next, a description will be given of a method for manufacturing the semiconductor package 200 according to the third modification of the ninth embodiment. In the third modification of the ninth embodiment, the steps illustrated in FIGS. 24 to 26 are performed.

[0220] 54A, a wafer-shaped glass substrate 212 provided with a release layer 308 for temporary bonding is attached to the back surface on which the back surface terminals 278 are provided. Then, the glass substrate 211 is debonded.

[0221] Then, as illustrated in FIG. 1B, the wafer is turned upside down, a potting resin 290 is applied to the upper surface of the rewiring layer 240 , and the individual pieces of glass 210 are bonded to the upper surface of the potting resin 290 .

[0222] 55A, a mold resin 235 is formed by a transfer molding method or the like using a mold 305 so as to cover the side surfaces of the glass 210 and the potting resin 290. Then, as shown in FIG. 55B, the glass substrate 212 is debonded, and any residue of the release layer 308 on the back surface is washed away.

[0223] 56A, the wafer is placed on a dicing tape 307 and divided into individual pieces. Then, as shown in FIG. 56B, the semiconductor packages 200 are picked up, completing the manufacturing process.

[0224] It should be noted that each of the second to fifth embodiments can be applied to the third modified example of the ninth embodiment.

[0225] Thus, according to the third variant of the ninth embodiment of the present technology, the side surfaces of the glass 210 and the potting resin 290 are covered with the mold resin 235, thereby protecting the glass 210 and the like from the external environment and improving their strength.

[0226] 10. Application Examples to Mobile Bodies The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be realized as a device mounted on any type of mobile body, such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, personal mobility, an airplane, a drone, a ship, or a robot.

[0227] FIG. 57 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile object control system to which the technology of the present disclosure can be applied.

[0228] The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example shown in Fig. 57, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside-vehicle information detection unit 12030, an inside-vehicle information detection unit 12040, and an integrated control unit 12050. Also shown as functional components of the integrated control unit 12050 are a microcomputer 12051, an audio / video output unit 12052, and an in-vehicle network I / F (Interface) 12053.

[0229] The drivetrain control unit 12010 controls the operation of devices related to the drivetrain of the vehicle in accordance with various programs. For example, the drivetrain control unit 12010 functions as a control device for a drive force generating device for generating a drive force of the vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating a braking force of the vehicle.

[0230] The body system control unit 12020 controls the operation of various devices equipped in the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as headlamps, backup lamps, brake lamps, turn signals, and fog lamps. In this case, radio waves transmitted from a portable device that serves as a key or signals from various switches can be input to the body system control unit 12020. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door lock device, power window device, lamps, etc.

[0231] The outside-vehicle information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the outside-vehicle information detection unit 12030. The outside-vehicle information detection unit 12030 causes the imaging unit 12031 to capture images outside the vehicle and receives the captured images. The outside-vehicle information detection unit 12030 may perform object detection processing or distance detection processing for people, cars, obstacles, signs, characters on the road surface, etc. based on the received images.

[0232] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0233] The in-vehicle information detection unit 12040 detects information inside the vehicle. For example, a driver state detection unit 12041 that detects the state of the driver is connected to the in-vehicle information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 may calculate the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041, or may determine whether the driver is dozing off.

[0234] The microcomputer 12051 can calculate control target values ​​for the driving force generating device, steering mechanism, or braking device based on the information inside and outside the vehicle acquired by the outside-vehicle information detection unit 12030 or the inside-vehicle information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of an ADAS (Advanced Driver Assistance System), including vehicle collision avoidance or impact mitigation, following driving based on the distance between vehicles, maintaining vehicle speed, vehicle collision warning, vehicle lane departure warning, etc.

[0235] In addition, the microcomputer 12051 can perform cooperative control for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on driver operation, by controlling the driving force generating device, steering mechanism, braking device, etc. based on information about the surroundings of the vehicle obtained by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040.

[0236] Furthermore, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information outside the vehicle acquired by the outside information detection unit 12030. For example, the microcomputer 12051 can control the headlamps according to the position of a preceding vehicle or an oncoming vehicle detected by the outside information detection unit 12030, and perform cooperative control aimed at preventing glare, such as switching from high beams to low beams.

[0237] The audio / video output unit 12052 transmits at least one of audio and video output signals to an output device capable of visually or audibly notifying the passengers of the vehicle or the outside of the vehicle of information. In the example of Fig. 57, the output devices are exemplified by an audio speaker 12061, a display unit 12062, and an instrument panel 12063. The display unit 12062 may include, for example, at least one of an on-board display and a head-up display.

[0238] FIG. 48 is a diagram showing an example of the installation position of the imaging unit 12031.

[0239] In FIG. 48, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

[0240] The imaging units 12101, 12102, 12103, 12104, and 12105 are provided, for example, at positions such as the front nose, side mirrors, rear bumper, back door, and the top of the windshield inside the vehicle cabin of the vehicle 12100. The imaging unit 12101 provided on the front nose and the imaging unit 12105 provided on the top of the windshield inside the vehicle cabin mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 provided on the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 provided on the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The imaging unit 12105 provided on the top of the windshield inside the vehicle cabin is mainly used to detect preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, etc.

[0241] 58 shows an example of the imaging ranges of the imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of the imaging unit 12104 provided on the rear bumper or back door. For example, by overlaying the image data captured by the imaging units 12101 to 12104, an overhead image of the vehicle 12100 viewed from above can be obtained.

[0242] At least one of the image capturing units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the image capturing units 12101 to 12104 may be a stereo camera made up of multiple image capturing elements, or may be an image capturing element having pixels for phase difference detection.

[0243] For example, based on the distance information obtained from the imaging units 12101 to 12104, the microcomputer 12051 can calculate the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and the change in this distance over time (relative speed with respect to the vehicle 12100), thereby extracting as a preceding vehicle, in particular, the three-dimensional object that is the closest three-dimensional object on the path of the vehicle 12100 and traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (e.g., 0 km / h or higher). Furthermore, the microcomputer 12051 can set a vehicle-to-vehicle distance to be maintained in advance in front of the preceding vehicle, and perform automatic braking control (including follow-up stop control), automatic acceleration control (including follow-up start control), etc. In this way, cooperative control can be performed for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on driver operation.

[0244] For example, the microcomputer 12051 classifies and extracts three-dimensional object data regarding three-dimensional objects into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on distance information obtained from the imaging units 12101 to 12104, and can use the data for automatic obstacle avoidance. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. The microcomputer 12051 then determines a collision risk that indicates the risk of collision with each obstacle, and when the collision risk is equal to or greater than a set value and a collision is possible, the microcomputer 12051 can provide driving assistance for collision avoidance by outputting an alarm to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or avoidance steering via the drive system control unit 12010.

[0245] At least one of the image capturing units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether a pedestrian is present in the images captured by the image capturing units 12101 to 12104. Such pedestrian recognition is performed, for example, by extracting feature points from the images captured by the image capturing units 12101 to 12104 as infrared cameras and performing pattern matching on a series of feature points that indicate the outline of an object to determine whether the object is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the image capturing units 12101 to 12104 and recognizes the pedestrian, the audio / image output unit 12052 controls the display unit 12062 to superimpose a rectangular outline on the recognized pedestrian for emphasis. The audio / image output unit 12052 may also control the display unit 12062 to display an icon or the like indicating the pedestrian at a desired position.

[0246] The above describes an example of a vehicle control system to which the technology according to the present disclosure can be applied. The technology according to the present disclosure can be applied to, for example, the imaging unit 12031 and the in-vehicle information detection unit 12040 among the above-described configurations. Specifically, the imaging device 100 of FIG. 15 can be applied to the imaging unit 12031. Furthermore, the electronic device 400 of FIG. 16 can be applied to the in-vehicle information detection unit 12040. By applying the technology according to the present disclosure to the imaging unit 12031 and the in-vehicle information detection unit 12040, high-speed transmission can be achieved, thereby improving performance.

[0247] Note that the above-described embodiment shows an example for realizing the present technology, and the matters in the embodiment and the matters specifying the invention in the claims correspond to each other. Similarly, the matters specifying the invention in the claims and the matters in the embodiment of the present technology having the same name correspond to each other. However, the present technology is not limited to the embodiment, and can be realized by applying various modifications to the embodiment within the scope of the gist thereof.

[0248] The effects described in this specification are merely examples and are not limiting, and other effects may also be obtained.

[0249] The present technology can also be configured as follows: (1) A semiconductor package comprising: a semiconductor chip; a first molding resin covering a side surface of the semiconductor chip; a through via penetrating the first molding resin; and a rewiring layer in which a coplanar waveguide is wired as a rewiring, connecting a chip pad provided on the surface of the semiconductor chip to one end of the through via. (2) The semiconductor package according to (1), wherein the through via includes a pair of signal vias that transmit differential signals and a plurality of ground vias formed around or on one side of the pair of signal vias. (3) The semiconductor package according to (1) or (2), wherein the rewiring includes a ground layer, a pair of ground lines formed between the ground layer and the first molding resin, and differential equal-length wiring that transmits differential signals, the differential equal-length wiring being wired between the pair of ground lines. (4) The semiconductor package according to any one of (1) to (3), further comprising a land pad connected to the other end of the through via. (5) The semiconductor package according to (4), further comprising an external terminal connected to the land pad. (6) The semiconductor package according to any one of (1) to (3), further comprising a predetermined number of external terminals and an interposer connecting the external terminals to the other ends of the through vias. (7) The semiconductor package according to any one of (1) to (6), wherein the diameter of the through vias does not exceed 300 μm. (8) The semiconductor package according to any one of (1) to (7), wherein the resistivity of silicon of the semiconductor chip is not less than 5000 Ω / cm. (9) The semiconductor package according to any one of (1) to (8), wherein the thickness of the semiconductor chip is not less than 500 μm. (10) An imaging device comprising: a semiconductor package including a semiconductor chip, a first molding resin covering a side surface of the semiconductor chip, a through via penetrating the first molding resin, and a rewiring layer in which a coplanar waveguide is wired as a rewiring to connect a chip pad provided on the surface of the semiconductor chip to one end of the through via; and an optical unit that collects incident light and guides it to the semiconductor chip.(11) An electronic device comprising: a transmitting unit that transmits a transmission wave; a receiving unit that receives a reception wave in response to the transmission wave; and a semiconductor package comprising: a semiconductor chip; a first molding resin that covers a side surface of the semiconductor chip; a through via that penetrates the first molding resin; and a rewiring layer in which a coplanar waveguide that connects a chip pad provided on the surface of the semiconductor chip to one end of the through via is wired as a rewiring. (12) A method for manufacturing a semiconductor package, comprising: forming a through via around the periphery of the semiconductor chip; forming a molding resin through which the through via penetrates and that covers the side surface of the semiconductor chip; and forming a rewiring layer in which a coplanar waveguide that connects a chip pad provided on the surface of the semiconductor chip to one end of the through via is wired as a rewiring. (13) The semiconductor package according to (1), further comprising a resin frame arranged between the rewiring layer and glass. (14) The semiconductor package according to (13), further comprising a second molding resin that covers the side surface of the glass and the side surface of the resin frame. (15) The semiconductor package according to (1), further comprising a second molding resin disposed between the rewiring layer and the glass. (16) The semiconductor package according to (15), further comprising connection terminals connecting the rewiring layer and chip pads provided on the light-receiving surface of the semiconductor chip, and an underfill covering the periphery of the connection terminals. (17) The semiconductor package according to (16), further comprising a resin frame disposed between the rewiring layer and the glass. (18) The semiconductor package according to (17), further comprising a second molding resin covering side surfaces of the glass and the resin frame. (19) The semiconductor package according to (16), further comprising a second molding resin disposed between the rewiring layer and the glass. (20) The semiconductor package according to (19), wherein the second molding resin covers side surfaces of the rewiring layer in the cavity. (21) The semiconductor package according to any one of (16) to (20), further comprising a rib disposed between the pixel portion of the semiconductor chip and the connection terminal. (22) The semiconductor package according to any one of (16) to (21), wherein the underfill further covers the periphery of the through via.(23) The semiconductor package according to any one of (13) to (22), wherein the distance between the light-receiving surface of the semiconductor chip and one of the two surfaces of the glass facing the semiconductor chip is not less than 300 micrometers. (24) The semiconductor package according to (1), further comprising a potting resin disposed between the redistribution layer and the glass. (25) The semiconductor package according to (24), further comprising a second molding resin covering the side surfaces of the glass and the potting resin. (26) The semiconductor package according to (24) or (25), further comprising connection terminals connecting the redistribution layer and chip pads provided on the light-receiving surface of the semiconductor chip, and an underfill covering the periphery of the connection terminals.

[0250] 100 Imaging device 110 Optical unit 120 DSP circuit 130 Display unit 140 Operation unit 150 Bus 160 Frame memory 170 Storage unit 180 Power supply unit 200 Semiconductor package 201 CIS wafer 210 Glass 211, 212, 213 Glass substrate 220 CIS chip 221 Pixel unit 222 Chip pad 230, 235 Molding resin 240 Rewiring layer 241 Dielectric layer 250, 250-1, 250-2, 250-3 Rewiring 251 Ground layer 252, 253 Ground line 254 Differential equal length wiring 254-1, 254-2 Signal line 260 TMV 261 Ground via 262, 263 Signal via 270 Interposer 271 Land pad 272 Solder ball 275 Connection terminal 276 Underfill 277 Photosensitive insulating film 278 Back surface terminal 279 Rib 280 Black resin frame 290 Potting resin 301 Seed layer 302 Protective film 303 Support wafer 304 Dummy wafer 305 Mold 306 Photoresist 307 Dicing tape 308 Release layer 400 Electronic device 410 Lens barrel 420 Transmitter 430 Receiver 440 Interposer substrate 12031 Imaging unit 12040 In-vehicle information detection unit

Claims

1. A semiconductor package comprising: a semiconductor chip; a first molding resin covering a side surface of the semiconductor chip; a through via penetrating the first molding resin; and a rewiring layer in which a coplanar waveguide is wired as a rewiring, connecting a chip pad provided on the surface of the semiconductor chip to one end of the through via.

2. The semiconductor package according to claim 1, wherein the through vias include a pair of signal vias for transmitting differential signals and a plurality of ground vias formed around or on one side of the pair of signal vias.

3. The semiconductor package according to claim 1, wherein the rewiring includes a ground layer, a pair of ground lines formed between the ground layer and the first molding resin, and differential equal-length wiring for transmitting differential signals, the differential equal-length wiring being wired between the pair of ground lines.

4. The semiconductor package according to claim 1, further comprising a land pad connected to the other end of the through via.

5. The semiconductor package according to claim 4, further comprising an external terminal connected to said land pad.

6. The semiconductor package according to claim 1, further comprising: a predetermined number of external terminals; and an interposer connecting said external terminals to the other ends of said through vias.

7. The semiconductor package of claim 1, wherein the diameter of said through via does not exceed 300 μm.

8. The semiconductor package according to claim 1, wherein the resistivity of the silicon of said semiconductor chip is not less than 5000 Ω / cm.

9. The semiconductor package according to claim 1, wherein the thickness of the semiconductor chip is not less than 500 μm.

10. An imaging device comprising: a semiconductor package including a semiconductor chip, a first molding resin covering the side surfaces of the semiconductor chip, a through via penetrating the first molding resin, and a rewiring layer in which a coplanar waveguide is wired as a rewiring to connect a chip pad provided on the surface of the semiconductor chip to one end of the through via; and an optical unit that focuses incident light and guides it to the semiconductor chip.

11. An electronic device comprising: a transmitting unit that transmits a transmission wave; a receiving unit that receives a reception wave corresponding to the transmission wave; and a semiconductor package including a semiconductor chip; a first molding resin that covers the side surface of the semiconductor chip; a through via that penetrates the first molding resin; and a rewiring layer in which a coplanar waveguide that connects a chip pad provided on the surface of the semiconductor chip to one end of the through via is wired as a rewiring.

12. A method for manufacturing a semiconductor package, comprising the steps of: forming through vias around a semiconductor chip; forming a first molding resin through which the through vias pass and which covers the side surfaces of the semiconductor chip; and forming a rewiring layer in which coplanar waveguides are wired as rewirings to connect chip pads provided on the surface of the semiconductor chip to one end of the through vias.

13. The semiconductor package according to claim 1, further comprising a resin frame disposed between the rewiring layer and the glass.

14. The semiconductor package according to claim 13, further comprising a second molding resin covering the side surfaces of the glass and the resin frame.

15. The semiconductor package of claim 1, further comprising a second molding compound disposed between the redistribution layer and the glass.

16. The semiconductor package according to claim 15, further comprising: connection terminals that connect the rewiring layer to chip pads provided on the light-receiving surface of the semiconductor chip; and underfill that covers the periphery of the connection terminals.

17. The semiconductor package according to claim 16, further comprising a resin frame disposed between the rewiring layer and the glass.

18. The semiconductor package according to claim 17, further comprising a second molding resin covering the side surfaces of the glass and the resin frame.

19. The semiconductor package of claim 16, further comprising a second molding compound disposed between the redistribution layer and the glass.

20. The semiconductor package according to claim 19, wherein the second molding compound covers the side surfaces of the rewiring layer within the cavity.

21. The semiconductor package according to claim 16, further comprising a rib disposed between the pixel portion of the semiconductor chip and the connection terminal.

22. The semiconductor package of claim 16, wherein the underfill further covers the periphery of the through via.

23. The semiconductor package according to claim 13, wherein the distance between the light-receiving surface of the semiconductor chip and one of the two surfaces of the glass that faces the semiconductor chip is not less than 300 micrometers.

24. The semiconductor package of claim 1, further comprising a potting resin disposed between the redistribution layer and the glass.

25. The semiconductor package according to claim 24, further comprising a second molding resin covering the side surfaces of the glass and the potting resin.

26. The semiconductor package according to claim 24, further comprising: connection terminals that connect the rewiring layer to chip pads provided on the light-receiving surface of the semiconductor chip; and underfill that covers the periphery of the connection terminals.

Images