Electronic device

Abstract

This electronic device comprises: a base substrate including light-emitting areas and a non-light-emitting area disposed between the light-emitting areas; a pixel unit including pixels each including a light-emitting element and disposed on the base substrate; a power line crossing the pixel unit; and a partition wall surrounding each of the pixels and including a first partition wall pattern including different metals and a second partition wall pattern disposed on the first partition wall pattern, wherein the partition wall is divided into a contact area connected to the power line through a contact hole and a normal area other than the contact area, and an upper surface of the first partition wall pattern in the normal area and an upper surface of the first partition wall pattern in the contact area have different shapes.

Description

electronic devices

[0001] The present invention relates to electronic devices, and more particularly, to electronic devices with improved display quality.

[0002] Electronic devices that typically provide images to users, such as smartphones, digital cameras, laptops, navigation systems, and smart televisions, include electronic devices for displaying images. These devices generate images and display them to users via a display screen.

[0003] An electronic device includes a plurality of pixels for generating an image and a plurality of lines connected to the pixels. The pixels are driven by receiving driving signals through the lines.

[0004] Large-scale electronic devices such as tablets and smart televisions may experience differences in the driving voltages delivered to each pixel, and a design that compensates for this difference is required.

[0005] The present invention aims to provide an electronic device capable of providing a uniform driving voltage to pixels in an electronic device.

[0006] An electronic device according to one embodiment comprises: a base substrate including a display region including light-emitting regions and a non-light-emitting region disposed between the light-emitting regions; pixel units each including pixels including light-emitting elements and disposed on the base substrate; a power line disposed on the base substrate, the power line crossing the pixel units; and a partition wall having partition openings overlapping the light-emitting regions, the partition wall being disposed in the non-light-emitting region to surround each of the pixels, the partition wall including a first partition wall pattern and a second partition wall pattern disposed on the first partition wall pattern, wherein the partition wall is divided into a contact region connected to the power line through a contact hole and a normal region other than the contact region, and the shapes of an upper surface of the first partition wall pattern in the normal region and an upper surface of the first partition wall pattern in the contact region are different.

[0007] In the above contact area, the upper surface of the first partition wall pattern may have a concave shape in a direction from the upper surface of the first partition wall pattern toward the lower surface of the first partition wall pattern, and a portion of the second partition wall pattern may have a shape corresponding to the shape of the upper surface of the first partition wall pattern.

[0008] The upper surface of the first bulkhead pattern in the above normal region may be characterized as being flat.

[0009] In the above contact area, the upper surface of the first partition wall pattern may be characterized in that a trench is defined that is sunken in a direction from the upper surface of the first partition wall pattern toward the lower surface of the first partition wall pattern, the trench has an inverted trapezoidal shape in a cross-section, and a portion of the second partition wall pattern has a shape corresponding to the shape of the trench.

[0010] The first bulkhead pattern may be characterized in that it includes aluminum, and the second bulkhead pattern may be characterized in that it includes titanium.

[0011] The width of the first bulkhead pattern may be smaller than the width of the second bulkhead pattern, and the thickness of the first bulkhead pattern may be larger than the thickness of the second bulkhead pattern.

[0012] Each of the light-emitting elements may include a first electrode, a second electrode disposed on the first electrode, and a common layer disposed between the first electrode and the second electrode, wherein the second electrode may be characterized as a single pattern commonly disposed on the light-emitting elements.

[0013] The second electrode overlapping the above-mentioned partition wall may be characterized in that it contacts the side surface of the first partition wall pattern, the lower surface of the second partition wall pattern exposed from the first partition wall pattern, and the side surface of the second partition wall pattern.

[0014] The side surface of the first bulkhead pattern may be characterized as being oxidized and not having conductivity.

[0015] It may further include a dummy pattern disposed on the second barrier pattern and covered by the second electrode, wherein the dummy pattern may include the same material as the common layer.

[0016] It may further include a protective layer disposed between the second bulkhead pattern and the dummy pattern, and the protective layer may be characterized by including an inorganic material.

[0017] A portion of the second bulkhead pattern exposed from the first bulkhead pattern may be characterized by including a tip portion bent downward.

[0018] The thickness of the second electrode disposed on the common layer may be characterized as being greater than the thickness of the second electrode surrounding the partition wall.

[0019] The above-mentioned partition wall may include a first insulating pattern disposed below the first partition wall pattern and a second insulating pattern disposed between the first insulating pattern and the first partition wall pattern, and the first insulating pattern and the second insulating pattern may be characterized in that they include different materials.

[0020] The first insulating pattern may include at least one of indium zinc oxide, indium gallium zinc oxide, and indium tin oxide, and the second insulating pattern may include at least one of silicon oxide, silicon oxynitride, and silicon nitride.

[0021] The width of the first insulating pattern may be characterized as being smaller than the width of the second insulating pattern.

[0022] An electronic device further comprising a third partition pattern disposed between the first partition pattern and the second insulating pattern and including the same material as the second partition pattern.

[0023] It may further include an interlayer insulating layer on which the power line is arranged; an interlayer insulating layer arranged on the interlayer insulating layer and covering the power line; and a pixel defining film on which the first insulating pattern is arranged, openings corresponding to the light-emitting areas are defined, and arranged on the interlayer insulating layer.

[0024] The above contact hole may be defined by a first contact hole overlapping a portion of the power line and penetrating the insulating layer therebetween, and a second contact hole overlapping the first contact hole and penetrating the pixel defining film, and an opening overlapping the contact hole is defined in the first insulating pattern and the second insulating pattern in the contact area.

[0025] The above first bulkhead pattern may be characterized by being arranged in the opening and the contact hole and connected to the power line.

[0026] According to the present invention, since the second electrode is connected to the power line through the partition within the display area, a voltage drop phenomenon can be prevented and a constant voltage can be provided to the pixels. In addition, since the connection between the second electrode and the power line is made within the display area, unnecessary space for connecting the second electrode and the second power line in the non-display area can be reduced. In addition, pixel units with different resolutions can be driven individually.

[0027] FIG. 1A is a perspective view of an electronic device according to one embodiment of the present invention.

[0028] FIG. 1b is a block diagram of an electronic device according to one embodiment of the present invention.

[0029] Figure 2 is a cross-sectional view of an electronic device according to one embodiment of the present invention.

[0030] Figure 3 is a cross-sectional view of a display panel according to one embodiment of the present invention.

[0031] FIG. 4a is a block diagram of a display module according to one embodiment of the present invention.

[0032] Figure 4b is an equivalent circuit of one of the pixels illustrated in Figure 4a.

[0033] FIG. 5a is a plan view of a pixel unit according to one embodiment of the present invention.

[0034] Figure 5b is a plan view of a pixel according to one embodiment of the present invention.

[0035] Figure 6 is a cross-sectional view taken along line I-I' of Figure 5a.

[0036] Figure 7 is a cross-sectional view taken along line II-II' of Figure 5a.

[0037] Fig. 8 is a cross-sectional view taken along line II-II' of Fig. 5a.

[0038] FIG. 9 is a cross-sectional view of a partition wall overlapping a contact area according to one embodiment of the present invention.

[0039] FIG. 10 is a cross-sectional view of a partition wall overlapping a contact area according to one embodiment of the present invention.

[0040] FIG. 11 is a cross-sectional view of a partition wall overlapping a contact area according to one embodiment of the present invention.

[0041] FIG. 12 is a cross-sectional view of a partition wall overlapping a contact area according to one embodiment of the present invention.

[0042] FIGS. 13A to 13G are cross-sectional views illustrating a method for manufacturing a display panel according to one embodiment of the present invention.

[0043] FIG. 14 is a block diagram schematically illustrating a display system according to one embodiment of the present invention.

[0044] FIG. 15 is a schematic diagram illustrating a smartwatch including an electronic device according to one embodiment of the present invention.

[0045] In this specification, when it is said that a component (or region, layer, portion, etc.) is “on,” “connected to,” or “coupled to” another component, it means that it can be directly disposed / connected / coupled to the other component, or a third component may be disposed between them.

[0046] Identical drawing numbers indicate identical components. Furthermore, in the drawings, the thicknesses, proportions, and dimensions of components are exaggerated for the purpose of effectively illustrating the technical content. "And / or" encompasses any combination of one or more of the associated components.

[0047] While terms such as "first" and "second" may be used to describe various components, these components should not be limited by these terms. These terms are used solely to distinguish one component from another. For example, without departing from the scope of the present invention, a first component may be referred to as a "second component," and similarly, a second component may also be referred to as a "first component." Singular expressions include plural expressions unless the context clearly indicates otherwise.

[0048] Additionally, terms such as "below," "lower," "above," and "upper" are used to describe the relationships between components depicted in the drawings. These terms are relative concepts and are explained based on the directions indicated in the drawings.

[0049] It should be understood that terms such as "include" or "have" are intended to specify the presence of a feature, number, step, operation, component, part or combination thereof described in the specification, but do not preclude the possibility of the presence or addition of one or more other features, numbers, steps, operations, components, parts or combinations thereof.

[0050] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art to which this invention pertains. Furthermore, terms defined in commonly used dictionaries should be interpreted to have a meaning consistent with their meaning in the context of the relevant technology, and should not be interpreted in an overly idealistic or overly formal sense unless explicitly defined herein.

[0051] Hereinafter, embodiments of the present invention will be described with reference to the drawings.

[0052] FIG. 1A is a perspective view of an electronic device according to an embodiment of the present invention. FIG. 1B is a block diagram of an electronic device according to an embodiment of the present invention. FIG. 2 is a cross-sectional view of an electronic device according to an embodiment of the present invention. FIG. 3 is a cross-sectional view of a display panel according to an embodiment of the present invention. FIG. 4A is a block diagram of a display module according to an embodiment of the present invention. FIG. 4B is an equivalent circuit of one of the pixels illustrated in FIG. 4A.

[0053] Referring to FIG. 1A, an electronic device (DD) according to an embodiment of the present invention may have long sides extending parallel to a first direction (DR1) and short sides extending parallel to a second direction (DR2) intersecting the first direction (DR1). The corners of the electronic device (DD) connecting the long sides and the short sides may have a curved shape. The corners of the electronic device (DD) having a curved shape may be defined as rounded corners. The shape of the electronic device (DD) may be defined as a rounded corner rectangle. However, this is only one example of the shape of the electronic device (DD) and is not limited to a rounded corner rectangle.

[0054] Hereinafter, a direction substantially perpendicular to the plane defined by the first direction (DR1) and the second direction (DR2) is defined as a third direction (DR3). In addition, in this specification, the meaning of when viewed on a plane is defined as a state viewed from the third direction (DR3).

[0055] The front surface of the electronic device (DD) may be defined as a display surface (DS) and may have a plane defined by a first direction (DR1) and a second direction (DR2). Images (IM) generated by the electronic device (DD) may be provided to a user through the display surface (DS).

[0056] A display surface (DS) may include a display area (DA) and a non-display area (NDA) surrounding the display area (DA). The display area (DA) may display an image, and the non-display area (NDA) may not display an image. The non-display area (NDA) may define a border of the electronic device (DD) that surrounds the display area (DA) and is printed in a predetermined color.

[0057] The display area (DA) may have a rounded-corner rectangular shape, depending on the shape of the electronic device (DD). For example, the display area (DA) may include rectangular sides extending in a first direction (DR1) and a second direction (DR2) and rounded corners connecting the sides. Of the four sides, the sides extending in the first direction (DR1) may be defined as long sides, and of the four sides, the sides extending in the second direction (DR2) may be defined as short sides.

[0058] An electronic device (DD) can detect inputs applied from outside the electronic device (DD). For example, the electronic device (DD) can detect a first input by a touch pen (PEN) and a second input by a touch (TC). The touch pen (PEN) can be defined as an input device.

[0059] A touch pen (PEN) may be an active pen that outputs signals. The second input by touch (TC) may include various forms of external input, such as a part of the user's body, light, heat, or pressure.

[0060] The electronic device (DD) and the touch pen (PEN) can communicate bidirectionally. The electronic device (DD) can provide an uplink signal to the touch pen (PEN). For example, the uplink signal may include, but is not limited to, information such as panel information and protocol version.

[0061] The touch pen (PEN) can provide a downlink signal to the electronic device (DD). The downlink signal may include a synchronization signal or status information of the touch pen (PEN). For example, the downlink signal may include, but is not limited to, coordinate information of the touch pen (PEN), battery information of the touch pen (PEN), tilt information of the touch pen (PEN), and / or various information stored in the touch pen (PEN).

[0062] The electronic device (DD) can be used in large electronic devices such as televisions, monitors, or outdoor billboards. Furthermore, the electronic device (DD) can also be used in small and medium-sized electronic devices such as personal computers, laptops, personal digital assistants, car navigation systems, game consoles, smartphones, tablets, or cameras. However, these are presented as exemplary embodiments only, and the electronic device (DD) can be used in other electronic devices without departing from the scope of the present invention.

[0063] FIG. 1B illustrates a block diagram of an electronic device (DD) according to one embodiment. Referring to FIG. 1B, the electronic device (DD) outputs various information through a display module (DM) within an operating system. When the processor (110) executes an application stored in the memory (120), the display module (DM) provides application information to the user through a display panel (DP).

[0064] The processor (110) obtains external input through the input module (130) or the sensor module (161) and executes an application corresponding to the external input. For example, when a user selects a camera icon displayed on the display panel (DP), the processor (110) obtains the user input through the input sensor (161-2) and activates the camera module (171). The processor (110) transmits image data corresponding to the captured image obtained through the camera module (171) to the display module (DM). The display module (DM) can display an image corresponding to the captured image through the display panel (DP).

[0065] As another example, when personal information authentication is performed in the display module (DM), the fingerprint sensor (161-1) acquires the input fingerprint information as input data. The processor (110) compares the input data acquired through the fingerprint sensor (161-1) with the authentication data stored in the memory (120) and executes an application based on the comparison result. The display module (DM) can display the information executed according to the application's logic through the display panel (DP).

[0066] As another example, when a music streaming icon displayed on a display module (DM) is selected, the processor (110) acquires user input through an input sensor (161-2) and activates a music streaming application stored in a memory (120). When a music execution command is input from the music streaming application, the processor (110) activates an audio output module (163) to provide the user with audio information corresponding to the music execution command.

[0067] Above, the operation of the electronic device (DD) has been briefly described. Below, the configuration of the electronic device (DD) is described in detail. Some of the configurations of the electronic device (DD) described below may be integrated and provided as a single configuration, or one configuration may be provided as two or more separate configurations.

[0068] Referring to FIG. 1B, the electronic device (DD) may communicate with an external electronic device (102) via a network (e.g., a short-range wireless communication network or a long-range wireless communication network). According to one embodiment, the electronic device (DD) may include a processor (110), a memory (120), an input module (130), a display module (DM), a power module (150), a built-in module (160), and an external module (170). According to one embodiment, the electronic device (DD) may omit at least one of the above-described components, or may have one or more other components added. According to one embodiment, some of the above-described components (e.g., the sensor module (161), the antenna module (162), or the audio output module (163)) may be integrated into another component (e.g., the display module (DM)).

[0069] The processor (110) may execute software to control at least one other component (e.g., a hardware or software component) of an electronic device (DD) connected to the processor (110) and perform various data processing or operations. According to one embodiment, as at least a part of the data processing or operations, the processor (110) may store commands or data received from other components (e.g., an input module (130), a sensor module (161), or a communication module (173)) in a volatile memory (121), process the commands or data stored in the volatile memory (121), and store the resulting data in a non-volatile memory (122).

[0070] The processor (110) may include a main processor (111) and a secondary processor (112). The main processor (111) may include one or more of a central processing unit (CPU: central processing unit) (111-1) or an application processor (AP: application processor). The main processor (111) may further include one or more of a graphic processing unit (GPU: graphic processing unit) (111-2), a communication processor (CP: communication processor), and an image signal processor (ISP: image signal processor). The main processor (111) may further include a neural network processing unit (NPU: neural processing unit) (111-3). The neural network processing unit is a processor specialized in processing artificial intelligence models, and the artificial intelligence models can be generated through machine learning. The artificial intelligence models may include a plurality of artificial neural network layers. The artificial neural network may be one of a deep neural network (DNN), a convolutional neural network (CNN), a recurrent neural network (RNN), a restricted Boltzmann machine (RBM), a deep belief network (DBN), a bidirectional recurrent deep neural network (BRDNN), deep Q-networks, or a combination of two or more of the above, but is not limited to the examples described above. In addition to or as an alternative to the hardware structure, the artificial intelligence model may include a software structure. At least two of the processing units and processors described above may be implemented as a single integrated configuration (e.g., a single chip), or each may be implemented as an independent configuration (e.g., multiple chips).

[0071] The auxiliary processor (112) may include a controller (112-1). The controller (112-1) may include an interface conversion circuit and a timing control circuit. The controller (112-1) receives a video signal from the main processor (111), converts the data format of the video signal to conform to the interface specifications with the display module (DM), and outputs the video data. The controller (112-1) may output various control signals necessary for driving the display module (DM).

[0072] The auxiliary processor (112) may further include a data conversion circuit (112-2), a gamma correction circuit (112-3), a rendering circuit (112-4), etc. The data conversion circuit (112-2) may receive image data from the controller (112-1) and compensate for the image data so that the image is displayed at a desired luminance according to the characteristics of the electronic device (DD) or the user's settings, or may convert the image data to reduce power consumption or compensate for afterimages. The gamma correction circuit (112-3) may convert the image data or the gamma reference voltage so that the image displayed on the electronic device (DD) has a desired gamma characteristic. The rendering circuit (112-4) may receive image data from the controller (112-1) and render the image data in consideration of the pixel layout of the display panel (DP) applied to the electronic device (DD). At least one of the data conversion circuit (112-2), the gamma correction circuit (112-3), and the rendering circuit (112-4) may be integrated into another component (e.g., the main processor (111) or the controller (112-1)). At least one of the data conversion circuit (112-2), the gamma correction circuit (112-3), and the rendering circuit (112-4) may also be integrated into a data driving unit (DDV) described later.

[0073] The memory (120) can store various data used by at least one component of the electronic device (DD) (e.g., a processor (110) or a sensor module (161)) and input data or output data for commands related thereto. The memory (120) can include at least one of a volatile memory (121) and a non-volatile memory (122).

[0074] The input module (130) can receive commands or data to be used for components of the electronic device (DD) (e.g., a processor (110), a sensor module (161), or an audio output module (163)) from an external source of the electronic device (DD) (e.g., a user or an external electronic device (102)).

[0075] The input module (130) may include a first input module (131) for inputting a command or data from a user and a second input module (132) for inputting a command or data from an external electronic device (102). The first input module (131) may include a microphone, a mouse, a keyboard, a key (e.g., a button), or a pen (e.g., a passive pen or an active pen). The second input module (132) may support a designated protocol that can be connected to the external electronic device (102) wired or wirelessly. According to one embodiment, the second input module (132) may include a high definition multimedia interface (HDMI), a universal serial bus (USB) interface, an SD card interface, or an audio interface. The second input module (132) may include a connector that can be physically connected to the external electronic device (102), for example, an HDMI connector, a USB connector, an SD card connector, or an audio connector (e.g., a headphone connector).

[0076] A display module (DM) provides visual information to a user. The display module (DM) may include a display panel (DP), a scan driver (SDV), and a data driver (DDV). The display module (DM) may further include a window, a chassis, and a bracket to protect the display panel (DP).

[0077] The display panel (DP) may include a liquid crystal display panel, an organic light-emitting display panel, or an inorganic light-emitting display panel, and the type of the display panel (DP) is not particularly limited. The display panel (DP) may be of a rigid type or of a flexible type that can be rolled or folded. The display module (DM) may further include a supporter, a bracket, or a heat dissipation member that supports the display panel (DP).

[0078] The scan driver (SDV) can be mounted on the display panel (DP) as a driver chip. In addition, the scan driver (SDV) can be integrated into the display panel (DP). For example, the scan driver (SDV) can include an ASG (Amorphous Silicon TFT Gate driver circuit), an LTPS (Low Temperature Polycrystalline Silicon) TFT Gate driver circuit, or an OSG (Oxide Semiconductor TFT Gate driver circuit) built into the display panel (DP). The scan driver (SDV) receives a control signal from the controller (112-1) and outputs scan signals to the display panel (DP) in response to the control signal.

[0079] The display panel (DP) may further include a light-emitting driver. The light-emitting driver outputs a light-emitting control signal to the display panel (DP) in response to a control signal received from the controller (112-1). The light-emitting driver may be formed separately from the scan driver (SDV) or may be integrated into the scan driver (SDV).

[0080] The data drive unit (DDV) receives a control signal from the controller (112-1), converts image data into analog voltages (e.g., data voltages) in response to the control signal, and then outputs the data voltages to the display panel (DP).

[0081] The data driver (DDV) may be integrated into another component (e.g., the controller (112-1)). The functions of the interface conversion circuit and timing control circuit of the controller (112-1) described above may also be integrated into the data driver (DDV).

[0082] The display module (DM) may further include a light emitting driver and a voltage generation circuit. The voltage generation circuit may output various voltages required to drive the display panel (DP).

[0083] The power module (150) supplies power to components of the electronic device (DD). The power module (150) may include a battery that charges a power voltage. The battery may include a non-rechargeable primary battery, a rechargeable secondary battery, or a fuel cell. The power module (150) may include a power management integrated circuit (PMIC). The PMIC supplies optimized power to each of the modules described above and those described below. The power module (150) may include a wireless power transmitting / receiving member electrically connected to the battery. The wireless power transmitting / receiving member may include a plurality of coil-shaped antenna radiators.

[0084] The electronic device (DD) may further include a built-in module (160) and an external module (170). The built-in module (160) may include a sensor module (161), an antenna module (162), and an audio output module (163). The external module (170) may include a camera module (171), a light module (172), and a communication module (173).

[0085] The sensor module (161) can detect input by the user's body or input by a pen among the first input modules (131), and generate an electric signal or data value corresponding to the input. The sensor module (161) can include at least one of a fingerprint sensor (161-1), an input sensor (161-2), and a digitizer (161-3).

[0086] The fingerprint sensor (161-1) can generate a data value corresponding to the user's fingerprint. The fingerprint sensor (161-1) can include either an optical or capacitive fingerprint sensor.

[0087] The input sensor (161-2) can generate data values ​​corresponding to coordinate information of input by the user's body or input by a pen. The input sensor (161-2) generates a data value based on the amount of change in electrostatic capacity due to the input. The input sensor (161-2) can detect input by a passive pen or transmit and receive data with an active pen.

[0088] The input sensor (161-2) can also measure bio-signals such as blood pressure, moisture, or body fat. For example, when a user touches a part of his or her body to the sensor layer or sensing panel and remains motionless for a certain period of time, the input sensor (161-2) can detect the bio-signal based on the change in the electric field caused by the part of his or her body and output the information desired by the user to the display module (DM).

[0089] The digitizer (161-3) can generate data values ​​corresponding to coordinate information input by the pen. The digitizer (161-3) generates the electromagnetic change amount due to the input as a data value. The digitizer (161-3) can detect input by a passive pen or transmit and receive data with an active pen.

[0090] At least one of the fingerprint sensor (161-1), the input sensor (161-2), and the digitizer (161-3) may be implemented as a sensor layer formed on the display panel (DP) through a continuous process. The fingerprint sensor (161-1), the input sensor (161-2), and the digitizer (161-3) may be arranged on the upper side of the display panel (DP), and any one of the fingerprint sensor (161-1), the input sensor (161-2), and the digitizer (161-3), for example, the digitizer (161-3), may be arranged on the lower side of the display panel (DP).

[0091] At least two of the fingerprint sensor (161-1), the input sensor (161-2), and the digitizer (161-3) may be formed to be integrated into a single sensing panel through the same process. When integrated into a single sensing panel, the sensing panel may be arranged between the display panel (DP) and a window arranged on an upper side of the display panel (DP). According to one embodiment, the sensing panel may be arranged on the window, and the position of the sensing panel is not particularly limited.

[0092] At least one of the fingerprint sensor (161-1), the input sensor (161-2), and the digitizer (161-3) can be built into the display panel (DP). That is, at least one of the fingerprint sensor (161-1), the input sensor (161-2), and the digitizer (161-3) can be formed simultaneously through a process of forming elements (e.g., light-emitting elements, transistors, etc.) included in the display panel (DP).

[0093] In addition, the sensor module (161) can generate an electrical signal or data value corresponding to an internal or external state of the electronic device (DD). The sensor module (161) may further include, for example, a gesture sensor, a gyro sensor, a pressure sensor, a magnetic sensor, an acceleration sensor, a grip sensor, a proximity sensor, a color sensor, an IR (infrared) sensor, a biometric sensor, a temperature sensor, a humidity sensor, or an illuminance sensor.

[0094] The antenna module (162) may include one or more antennas for transmitting or receiving signals or power to or from the outside. According to one embodiment, the communication module (173) may transmit signals to or receive signals from an external electronic device through an antenna suitable for a communication method. The antenna pattern of the antenna module (162) may be integrated into one component of the display module (DM) (e.g., a display panel (DP)) or an input sensor (161-2).

[0095] The audio output module (163) is a device for outputting audio signals to the outside of the electronic device (DD), and may include, for example, a speaker used for general purposes such as multimedia playback or recording playback, and a receiver used exclusively for phone reception. According to one embodiment, the receiver may be formed integrally with or separately from the speaker. The audio output pattern of the audio output module (163) may also be integrated into the display module (DM).

[0096] The camera module (171) can capture still images and videos. According to one embodiment, the camera module (171) may include one or more lenses, image sensors, or image signal processors. The camera module (171) may further include an infrared camera capable of measuring the presence or absence of a user, the user's location, the user's line of sight, etc.

[0097] The light module (172) can provide light. The light module (172) can include a light-emitting diode or a xenon lamp. The light module (172) can operate in conjunction with the camera module (171) or can operate independently.

[0098] The communication module (173) can support the establishment of a wired or wireless communication channel between the electronic device (DD) and the external electronic device (102), and the performance of communication through the established communication channel. The communication module (173) can include any one or all of a wireless communication module such as a cellular communication module, a short-range wireless communication module, or a global navigation satellite system (GNSS) communication module, and a wired communication module such as a local area network (LAN) communication module or a power line communication module. The communication module (173) can communicate with the external electronic device (102) through a short-range communication network such as Bluetooth, WiFi direct, or IrDA (infrared data association), or a long-range communication network such as a cellular network, the Internet, or a computer network (e.g., a LAN or WAN). The various types of communication modules (173) described above can be implemented as one chip or can be implemented as separate chips.

[0099] The input module (130), sensor module (161), camera module (171), etc. can be used to control the operation of the display module (DM) in conjunction with the processor (110).

[0100] The processor (110) outputs a command or data to the display module (DM), the audio output module (163), the camera module (171), or the light module (172) based on the input data received from the input module (130). For example, the processor (110) may generate image data corresponding to input data applied through a mouse or an active pen, etc., and output the image data to the display module (DM), or generate command data corresponding to the input data, and output the command data to the camera module (171) or the light module (172). When no input data is received from the input module (130) for a certain period of time, the processor (110) may reduce the power consumed by the electronic device (DD) by switching the operation mode of the electronic device (DD) to a low-power mode or a sleep mode.

[0101] The processor (110) outputs a command or data to the display module (DM), the audio output module (163), the camera module (171), or the light module (172) based on the sensing data received from the sensor module (161). For example, the processor (110) may compare the authentication data authorized by the fingerprint sensor (161-1) with the authentication data stored in the memory (120), and then execute an application based on the comparison result. The processor (110) may execute a command or output corresponding image data to the display module (DM) based on the sensing data detected by the input sensor (161-2) or the digitizer (161-3). When the sensor module (161) includes a temperature sensor, the processor (110) may receive temperature data on the temperature measured from the sensor module (161) and further perform brightness correction, etc. on the image data based on the temperature data.

[0102] The processor (110) can receive measurement data regarding the presence or absence of a user, the user's location, the user's line of sight, etc. from the camera module (171). The processor (110) can further perform brightness correction, etc. on the image data based on the measurement data. For example, the processor (110) that determines the presence or absence of a user through input from the camera module (171) can output the brightness-corrected image data to the display module (DM) through the data conversion circuit (112-2) or the gamma correction circuit (112-3).

[0103] Some of the above components may be interconnected with each other through a communication method between peripheral devices, such as a bus, GPIO (general purpose input / output), SPI (serial peripheral interface), MIPI (mobile industry processor interface), or UPI (ultra path interconnect) link, to exchange signals (e.g., commands or data) with each other. The processor (110) may communicate with the display module (DM) through a mutually agreed upon interface, and may use, for example, any one of the above-described communication methods, and is not limited to the above-described communication methods.

[0104] The electronic device (DD) according to various embodiments disclosed in this document may be a device of various forms. The electronic device (DD) may include, for example, at least one of a portable communication device (e.g., a smartphone), a computer device, a portable multimedia device, a portable medical device, a camera, a wearable device, or a home appliance device. The electronic device (DD) according to the embodiments of this document is not limited to the aforementioned devices.

[0105] Fig. 2 is a drawing illustrating a cross-section of the electronic device illustrated in Fig. 1a. Fig. 2 illustrates a cross-section of the electronic device (DD) as viewed from a second direction (DR2). Some of the components of the electronic device (DD) described in Fig. 1b are omitted in Fig. 2.

[0106] Referring to FIG. 2, the electronic device (DD) may include a display panel (DP), an input sensor (ISP), an anti-reflection layer (RPL), a window (WIN), a panel protection film (PPF), and first and second adhesive layers (AL1, AL2). The input sensor (ISP) illustrated in FIG. 2 may have the same configuration as the input sensor (161-2) described in FIG. 1B.

[0107] The display panel (DP) according to one embodiment of the present invention may be an emissive display panel. For example, the display panel (DP) may be an organic light-emitting display panel or an inorganic light-emitting display panel. The light-emitting layer of the organic light-emitting display panel may include an organic light-emitting material. The light-emitting layer of the inorganic light-emitting display panel may include quantum dots, quantum rods, and the like. Hereinafter, the display panel (DP) is described as an organic light-emitting display panel.

[0108] An input sensor (ISP) may be disposed on a display panel (DP). The input sensor (ISP) may include a plurality of sensing units (not shown) for sensing an external input in a capacitive manner. The input sensor (ISP) may be manufactured directly on the display panel (DP) during the manufacturing of the electronic device (DD). Therefore, the input sensor (ISP) according to one embodiment may be directly disposed on the display panel (DP). However, the present invention is not limited thereto, and the input sensor (ISP) may be manufactured as a separate panel from the display panel (DP) and attached to the display panel (DP) by an adhesive layer.

[0109] An anti-reflection layer (RPL) may be disposed on the input sensor (ISP). The anti-reflection layer (RPL) may be manufactured directly on the input sensor (ISP) during the manufacturing of the electronic device (DD). However, this is not limited to the above, and the anti-reflection layer (RPL) may be manufactured as a separate panel and attached to the input sensor (ISP) using an adhesive layer.

[0110] An anti-reflection layer (RPL) can be defined as an external light anti-reflection film. The RPL can reduce the reflectance of external light incident from above the electronic device (DD) toward the display panel (DP). The RPL can prevent the external light from being perceived by the user.

[0111] When external light directed toward the display panel (DP) is reflected by the display panel (DP) and re-exposed to an external user, the user may perceive the external light as a mirror. To prevent this phenomenon, for example, the anti-reflection layer (RPL) may include a plurality of color filters that display the same color as the pixels of the display panel (DP).

[0112] Color filters can filter external light to the same color as the pixels. In this case, the external light may not be visible to the user. However, the present invention is not limited thereto, and the anti-reflection layer (RPL) may include a phase retarder and / or a polarizer to reduce the reflectance of external light.

[0113] The window (WIN) can be placed on an anti-reflection layer (RPL). The window (WIN) can protect the display panel (DP), the input sensor (ISP), and the anti-reflection layer (RPL) from external scratches and impacts.

[0114] A panel protection film (PPF) may be placed under the display panel (DP). The panel protection film (PPF) may protect the lower portion of the display panel (DP). The panel protection film (PPF) may include a flexible plastic material such as polyethylene terephthalate (PET).

[0115] A first adhesive layer (AL1) is disposed between a display panel (DP) and a panel protection film (PPF), and the display panel (DP) and the panel protection film (PPF) can be bonded to each other by the first adhesive layer (AL1). A second adhesive layer (AL2) is disposed between a window (WIN) and an anti-reflection layer (RPL), and the window (WIN) and the anti-reflection layer (RPL) can be bonded to each other by the second adhesive layer (AL2).

[0116] Fig. 3 is a drawing illustrating a cross-section of the display panel illustrated in Fig. 2. As an example, Fig. 3 illustrates a cross-section of the display panel (DP) as viewed from the second direction (DR2).

[0117] Referring to FIG. 3, the display panel (DP) may include a substrate (SUB), a circuit element layer (DP-CL) disposed on the substrate (SUB), a display element layer (DP-OLED) disposed on the circuit element layer (DP-CL), and a thin film encapsulation layer (TFE) disposed on the display element layer (DP-OLED).

[0118] The substrate (SUB) may include a display area (DA) and a non-display area (NDA) surrounding the display area (DA). The substrate (SUB) may include glass or a flexible plastic material such as polyimide. A display element layer (DP-OLED) may be disposed on the display area (DA).

[0119] A plurality of pixels may be arranged on the circuit element layer (DP-CL) and the display element layer (DP-OLED). Each pixel may include a transistor arranged on the circuit element layer (DP-CL) and a light-emitting element arranged on the display element layer (DP-OLED) and connected to the transistor.

[0120] A thin film encapsulation layer (TFE) may be disposed on a circuit element layer (DP-CL) to cover a display element layer (DP-OLED). The thin film encapsulation layer (TFE) may protect pixels from moisture, oxygen, and external foreign substances. The thin film encapsulation layer (TFE) may include inorganic layers and organic layers. The organic layer may be disposed between the inorganic layers to be sealed from the inorganic layers, thereby providing a flat surface. According to one embodiment, the organic layer may be disposed on the inorganic layers or may be omitted, and is not limited to any one embodiment.

[0121] FIG. 4a is a block diagram of the electronic device illustrated in FIG. 1a.

[0122] Referring to FIG. 4A, the electronic device (DD) may include a display panel (DP), a timing controller (TC), a scan driver (SDV), a data driver (DDV), a light emission driver (EDV), and a voltage generator (VG).

[0123] The display panel (DP) may include a plurality of scanning lines (GIL1 to GILm, GCL1 to GCLm, GWL1 to GWLm, GBL1 to GBLm), a plurality of emission control lines (EML1 to EMLm), a plurality of data lines (DL1 to DLn), and a plurality of pixels (PX). m and n are natural numbers.

[0124] The pixels (PX) can be electrically connected to scan lines (GIL1 to GILm, GCL1 to GCLm, GWL1 to GWLm, GBL1 to GBLm), emission control lines (EML1 to EMLm), and data lines (DL1 to DLn), respectively. Each of the pixels (PX) can be electrically connected to four corresponding scan lines, one corresponding data line, and one corresponding emission control line.

[0125] The scan lines (GIL1 to GILm, GCL1 to GCLm, GWL1 to GWLm, GBL1 to GBLm) may include a plurality of initialization scan lines (GIL1 to GILm), a plurality of compensation scan lines (GCL1 to GCLm), a plurality of write scan lines (GWL1 to GWLm), and a plurality of bias scan lines (GBL1 to GBLm).

[0126] Each of the pixels (PX) can be connected to a corresponding one of the initialization scan lines (GIL1 to GILm), a corresponding one of the compensation scan lines (GCL1 to GCLm), a corresponding one of the write scan lines (GWL1 to GWLm), and a corresponding one of the bias scan lines (GBL1 to GBLm).

[0127] The scan lines (GIL1 to GILm, GCL1 to GCLm, GWL1 to GWLm, GBL1 to GBLm) are connected to the scan driver (SDV), extend in a first direction (DR1), and can be arranged in a second direction (DR2). The emission control lines (EML1 to EMLm) are connected to the emission driver (EDV), extend in a first direction (DR1), and can be arranged in a second direction (DR2). The data lines (DL1 to DLn) are connected to the data driver (DDV), extend in a second direction (DR2), and can be arranged in the first direction (DR1).

[0128] The scanning driver (SDV), the emission driver (EDV), and the data driver (DDV) can be substantially arranged on the display panel (DP), and this configuration will be illustrated in FIG. 8 below.

[0129] The timing controller (TC) can receive a video signal (RGB) and a control signal (CTRL). The timing controller (TC) can generate a video data signal (DAS) by converting the data format of the video signal (RGB) to meet the interface specifications with the data driver (DDV). In response to the control signal (CTRL), the timing controller (TC) can output a scan control signal (SCS), a data control signal (DCS), and an emission control signal (ECS).

[0130] A voltage generator (VG) can generate voltages required for the operation of a display panel (DP). The voltage generator (VG) can generate a first driving voltage (ELVDD), a second driving voltage (ELVSS), a first initialization voltage (VINT), and a second initialization voltage (VAINT). The first driving voltage (ELVDD), the second driving voltage (ELVSS), the first initialization voltage (VINT), and the second initialization voltage (VAINT) can be applied to pixels (PX).

[0131] The scan driver (SDV) can receive a scan control signal (SCS) from a timing controller (TC). The scan driver (SDV) can output scan signals to scan lines (GIL1 to GILm, GCL1 to GCLm, GWL1 to GWLm, GBL1 to GBLm) in response to the scan control signal (SCS). The scan signals can be applied to pixels (PX) through the scan lines (GIL1 to GILm, GCL1 to GCLm, GWL1 to GWLm, GBL1 to GBLm).

[0132] The data driver (DDV) can receive a data control signal (DCS) and an image data signal (DAS) from a timing controller (TC). The data driver (DDV) can convert the image data signal (DAS) into data signals and output them. The data signals can be defined as analog voltages corresponding to the grayscale levels of the image data signal (DAS). The data signals can be applied to the pixels (PX) through data lines (DL1 to DLn).

[0133] The emission driver (EDV) can receive an emission control signal (ECS) from a timing controller (TC). The emission driver (EDV) can output emission signals to the emission control lines (EML1 to EMLm) in response to the emission control signal (ECS). The emission signals can be applied to the pixels (PX) through the emission control lines (EML1 to EMLm).

[0134] Pixels (PX) can receive data voltages in response to scanning signals. Pixels (PX) can display images by emitting light with a brightness corresponding to the data voltages in response to light emission signals.

[0135] FIG. 4b is a diagram showing an equivalent circuit of one of the pixels illustrated in FIG. 4a.

[0136] For example, Fig. 4b illustrates a pixel (PXij) connected to the jth data line (DLj), the ith scan lines (GWLi, GCLi, GILi, GBLi), and the ith emission control line (EMLi). i and j are natural numbers.

[0137] Referring to FIG. 4b, a pixel (PXij) may include a pixel circuit (PC) and a light-emitting element (OLED) connected to the pixel circuit (PC). The pixel circuit (PC) may drive the light-emitting element (OLED).

[0138] The pixel circuit (PC) may include a plurality of transistors (T1 to T8) and a capacitor (CST). The transistors (T1 to T8) and the capacitor (CST) may control the amount of current flowing to the light-emitting element (OLED). The light-emitting element (OLED) may generate light having a predetermined brightness depending on the amount of current supplied.

[0139] The ith write scan line (GWLi) can receive the ith write scan signal (GWi), the ith compensation scan line (GCLi) can receive the ith compensation scan signal (GCi), the ith initialization scan line (GILi) can receive the ith initialization scan signal (GIi), the ith bias scan line (GBLi) can receive the ith bias scan signal (GBi), and the ith emission control line (EMLi) can receive the ith emission signal (EMi).

[0140] A pixel (PXij) can be connected to a j-th data line (DLj), an i-th write scan line (GWLi), an i-th compensation scan line (GCLi), an i-th initialization scan line (GILi), an i-th bias scan line (GBLi), an i-th emission control line (EMLi), a first initialization line (VIL1), a second initialization line (VIL2), a bias line (VBL), and first and second power lines (PL1, PL2).

[0141] The first initialization line (VIL1) can receive the first initialization voltage (VINT), and the second initialization line (VIL2) can receive the second initialization voltage (VAINT). The bias line (VBL) can receive the bias voltage (VBIAS). The first power line (PL1) can receive the first driving voltage (ELVDD), and the second power line (PL2) can receive the second driving voltage (ELVSS).

[0142] Each of the transistors (T1 to T8) may include a source electrode, a drain electrode, and a gate electrode. Hereinafter, in FIG. 4b, for convenience, one of the source electrode and the drain electrode is defined as the first electrode, and the other is defined as the second electrode. In addition, the gate electrode is defined as the control electrode.

[0143] The transistors (T1 to T8) may include first to eighth transistors (T1 to T8). The first, second, and fifth to eighth transistors (T1, T2, T5 to T8) may be PMOS transistors. The third and fourth transistors (T3, T4) may be NMOS transistors.

[0144] The first transistor (T1) may be defined as a driving transistor, the second transistor (T2) may be defined as a switching transistor, the third transistor (T3) may be defined as a compensation transistor, the fourth transistor (T4) and the seventh transistor (T7) may be defined as initialization transistors, the fifth transistor (T5) and the sixth transistor (T6) may be defined as light-emitting control transistors, and the eighth transistor (T8) may be defined as a bias transistor.

[0145] The light-emitting element (OLED) may be defined as an organic light-emitting element. The light-emitting element (OLED) may include a first electrode (AE) and a second electrode (CE). The first electrode (AE) may receive a first driving voltage (ELVDD) through the sixth, first, and fifth transistors (T6, T1, T5). The first driving voltage (ELVDD) may be applied to the pixel circuit (PC) through the first power line (PL1).

[0146] The second electrode (CE) can receive a second driving voltage (ELVSS) having a lower level than the first driving voltage (ELVDD). The second driving voltage (ELVSS) can be applied to the pixel circuit (PC) through a second power line (PL2).

[0147] A first transistor (T1) is disposed between a fifth transistor (T5) and a sixth transistor (T6), and can be connected to the fifth transistor (T5) and the sixth transistor (T6). The first transistor (T1) can be connected to a first power line (PL1) through the fifth transistor (T5), and to a first electrode (AE) through the sixth transistor (T6).

[0148] The first transistor (T1) may include a first electrode connected to the first power line (PL1) via a fifth transistor (T5), a second electrode connected to the first electrode (AE) via a sixth transistor (T6), and a control electrode connected to the first node (N1).

[0149] A first electrode of a first transistor (T1) may be connected to a fifth transistor (T5), and a second electrode of the first transistor (T1) may be connected to a sixth transistor (T6). The first transistor (T1) may control the amount of current flowing to the light-emitting element (OLED) according to the voltage of the first node (N1) applied to the control electrode of the first transistor (T1).

[0150] A second transistor (T2) may be disposed between the first transistor (T1) and the j-th data line (DLj) and may be connected to the first transistor (T1) and the j-th data line (DLj). The second transistor (T2) may include a first electrode connected to the j-th data line (DLj), a second electrode connected to the first electrode of the first transistor (T1), and a control electrode connected to the i-th write scan line (GWLi).

[0151] The second transistor (T2) can be turned on by the i-th write scan signal (GWi) applied through the i-th write scan line (GWLi) to electrically connect the j-th data line (DLj) and the first electrode of the first transistor (T1). The second transistor (T2) can perform a switching operation of providing the data voltage (VD) (corresponding to the aforementioned data signal) applied through the j-th data line (DLj) to the first electrode of the first transistor (T1).

[0152] A third transistor (T3) may be connected to the second electrode of the first transistor (T1) and the first node (N1). The third transistor (T3) may include a first electrode connected to the second electrode of the first transistor (T1), a second electrode connected to the first node (N1), and a control electrode connected to the ith compensation scan line (GCLi).

[0153] The third transistor (T3) can be turned on by the i-th compensation scan signal (GCi) applied through the i-th compensation scan line (GCLi) to electrically connect the second electrode of the first transistor (T1) and the control electrode of the first transistor (T1). When the third transistor (T3) is turned on, the first transistor (T1) and the third transistor (T3) can be connected in a diode form.

[0154] A fourth transistor (T4) may be connected to a first node (N1). The fourth transistor (T4) may include a first electrode connected to the first node (N1), a second electrode connected to a first initialization line (VIL1), and a control electrode connected to an ith initialization scan line (GILi). The fourth transistor (T4) may be turned on by an ith initialization scan signal (GIi) applied through the ith initialization scan line (GILi) and may provide a first initialization voltage (VINT) applied through the first initialization line (VIL1) to the first node (N1).

[0155] The fifth transistor (T5) may include a first electrode connected to the first power line (PL1), a second electrode connected to the first electrode of the first transistor (T1), and a control electrode connected to the ith emission control line (EMLi).

[0156] The sixth transistor (T6) may include a first electrode connected to the second electrode of the first transistor (T1), a second electrode connected to the first electrode (AE), and a control electrode connected to the ith emission control line (EMLi).

[0157] The fifth transistor (T5) and the sixth transistor (T6) can be turned on by the ith light emission signal (EMi) applied through the ith light emission control line (EMLi). The first driving voltage (ELVDD) is provided to the light emitting element (OLED) by the turned-on fifth transistor (T5) and sixth transistor (T6), so that a driving current can flow to the light emitting element (OLED). Therefore, the light emitting element (OLED) can emit light.

[0158] The seventh transistor (T7) may include a first electrode connected to the first electrode (AE), a second electrode connected to the second initialization line (VIL2), and a control electrode connected to the ith bias scan line (GBLi). The seventh transistor (T7) may be turned on by the ith bias scan signal (GBi) applied through the ith bias scan line (GBLi), and may provide the second initialization voltage (VAINT) received through the second initialization line (VIL2) to the first electrode (AE) of the light-emitting element (OLED).

[0159] In an embodiment of the present invention, the second initialization voltage (VAINT) may have a different level from the first initialization voltage (VINT), but is not limited thereto and may have the same level as the first initialization voltage (VINT).

[0160] The seventh transistor (T7) can improve the black expression capability of the pixel (PXij). When the seventh transistor (T7) is turned on, the parasitic capacitor (not shown) of the light-emitting element (OLED) can be discharged. Therefore, when implementing black luminance, the light-emitting element (OLED) does not emit light due to the leakage current of the first transistor (T1), and thus the black expression capability can be improved.

[0161] The capacitor (CST) may include a first electrode connected to a first power line (PL1) and a second electrode connected to a first node (N1). When the fifth transistor (T5) and the sixth transistor (T6) are turned on, the amount of current flowing to the first transistor (T1) may be determined according to the voltage stored in the capacitor (CST).

[0162] The eighth transistor (T8) may include a first electrode connected to a bias line (VBL), a second electrode connected to the first electrode of the first transistor (T1), and a control electrode connected to an i-th bias scan line (GBLi).

[0163] The eighth transistor (T8) is turned on by the ith bias scan signal (GBi) and can provide a bias voltage (VBIAS) applied through the bias line (VBL) to the first electrode of the first transistor (T1). However, the transistors included in the pixel (PXij) are not limited thereto.

[0164] Fig. 5a is a plan view of a pixel unit according to one embodiment of the present invention. Fig. 5b is a plan view of a pixel according to one embodiment of the present invention.

[0165] Referring to FIG. 5a, in the present embodiment, one pixel unit (PXU) may include the pixels described in FIGS. 4a and 4b. The pixel units (PXU) may be provided in multiple numbers and arranged along the first and second diagonal directions (CDR1, CDR2) within the display area (DA) described in FIG. 1a.

[0166] A pixel unit (PXU) according to one embodiment may include first to third pixels (PX-G1, PX-G2, PX-R, PX-B). The first pixel (PX-G1) may provide green light. Light generated in the first pixel (PX-G1) may be provided to a display area (DA, see FIG. 1A) through the first emission area (PXA-G1). In the present embodiment, the first emission area (PXA-G1) may have a rhombus shape.

[0167] The first-second pixel (PX-G2) can provide the same green light as the first-first pixel (PX-G1). The light generated in the first-second pixel (PX-G2) can be provided to the display area (DA, see FIG. 1A) through the first-second emission area (PXA-G2). The first-second emission area (PXA-G2) can be spaced apart from the first-first emission area (PXA-G1) along the first direction (DR1). In the present embodiment, the first-second emission area (PXA-G2) can have a rhombus shape.

[0168] The second pixel (PX-R) can provide red light. The light generated in the second pixel (PX-R) can be provided to the display area (DA, see FIG. 1A) through the second light-emitting area (PXA-R). The second light-emitting area (PXA-R) can be spaced apart from the third light-emitting area (PXA-B) along the second direction (DR2). The second light-emitting area (PXA-R) can be spaced apart from the first-first light-emitting area (PXA-G1) along the first diagonal direction (CDR1) and can be spaced apart from the first-second light-emitting area (PXA-G2) along the second diagonal direction (CDR2). In the present embodiment, the second light-emitting area (PXA-R) can have a diamond shape.

[0169] The third pixel (PX-B) can provide blue light. The light generated from the third pixel (PX-B) can be provided to the display area (DA, see FIG. 1A) through the third light-emitting area (PXA-B). The third light-emitting area (PXA-B) can be spaced apart from the first-second light-emitting area (PXA-G2) along the first diagonal direction (CDR1) and can be spaced apart from the first-first light-emitting area (PXA-G1) along the first diagonal direction (CDR1). In the present embodiment, the third light-emitting area (PXA-B) can have a rhombus shape.

[0170] According to one embodiment, the area of ​​the second light-emitting region (PXA-R) may be larger than the areas of the first-first and second light-emitting regions (PXA-G1, PXA-G2) and smaller than the area of ​​the third light-emitting region (PXA-B).

[0171] The area between the first to third light-emitting areas (PXA-G1, PXA-G2, PXA-R, PXA-B) can be defined as a non-light-emitting area (NPXA).

[0172] An electronic device (DD) according to the present invention may include a partition wall (WL) included in a display panel (DP, see FIG. 3). The partition wall (WL) may be arranged in a non-emission area (NPXA) and may define partition wall openings (W-OP) overlapping the first to third emission areas (PXA-G1, PXA-G2, PXA-R, PXA-B). In the present embodiment, each of the partition wall openings (W-OP) may have a rhombus shape. The partition wall openings (W-OP) may be defined by side surfaces of partition wall patterns included in the partition wall (WL) and including metal. A description thereof will be given later. The partition wall (WL) may surround pixels (PX-G1, PX-G2, PX-R, PX-B).

[0173] FIG. 5A illustrates a portion of a second power line (PL2, power line of the claim) arranged within a display area (DA, see FIG. 1A). The second power line (PL2) may cross the pixel unit (PXU). Although FIG. 5A illustrates one second power line (PL2) extending in the second direction (DR2), the present invention is not limited thereto, and a plurality of second power lines (PL2) may be provided, and at least one of the second power lines (PL2) may extend along the first direction (DR1).

[0174] According to one embodiment, a partition wall (WL) may include a normal area (NA) and a contact area (CA) within one pixel unit (PXU). The contact area (CA) may be defined as a portion where a second power line (PL2) and a partition wall pattern included in the partition wall (WL) come into contact with each other through a contact hole (CNT). The normal area (NA) may correspond to the remaining area excluding the contact area (CA). Although one contact area (CA) is illustrated in FIG. 5A, the number of contact areas (CA) is not limited thereto, and when a plurality of second power lines (PL2) are provided, a plurality of contact areas (CA) may be provided within one pixel unit (PXU).

[0175] In Fig. 5a, a second electrode (CE) included in a light-emitting element included in each of the pixels (PX-G1, PX-G2, PX-R, PX-B) is illustrated with a dotted line. The second electrode (CE) may be commonly arranged in the pixels (PX-G1, PX-G2, PX-R, PX-B) to have a single pattern shape. The second electrode (CE) may be connected to a second power line (PL2) through a partition wall (WL) including metal, and a description thereof will be omitted.

[0176] Referring to FIG. 5b, in the present embodiment, one pixel unit (PXU-a) may include the pixels described in FIGS. 4a and 4b. The pixel units (PXU-a) may be provided in plurality and arranged along the first and second directions (DR1, DR2) within the display area (DA) described in FIG. 1a.

[0177] According to one embodiment, a pixel unit (PXU-a) may include first to third pixels (PX-R, PX-G, PX-B). The first pixel (PX-R) may provide red light. Light generated in the first pixel (PX-R) may be provided to a display area (DA, see FIG. 1A) through a first light-emitting area (PXA-R). In the present embodiment, the first light-emitting area (PXA-R) may have a rounded corner square shape.

[0178] The second pixel (PX-B) can provide blue light. The light generated in the second pixel (PX-B) can be provided to the display area (DA, see FIG. 1A) through the second light-emitting area (PXA-B). The second light-emitting area (PXA-B) can be spaced apart from the first light-emitting area (PXA-R) along the first direction (DR1). When viewed in the second direction (DR2), the second light-emitting area (PXA-B) can overlap the first and third light-emitting areas (PXA-R, PXA-G). The second light-emitting area (PXA-B) can have a rounded corner square shape extending along the second direction (DR2).

[0179] The third pixel (PX-G) can provide green light. The light generated from the third pixel (PX-G) can be provided to the display area (DA, see FIG. 1A) through the third emission area (PXA-G). The third emission area (PXA-G) can be spaced apart from the first emission area (PXA-R) along the second direction (DR2). The third emission area (PXA-G) can have a rounded corner square shape.

[0180] According to one embodiment, the area of ​​the first light-emitting region (PXA-R) may be larger than the area of ​​the third light-emitting region (PXA-G) and smaller than the area of ​​the second light-emitting region (PXA-B).

[0181] The area between the first to third light-emitting areas (PXA-R, PXA-G, PXA-B) can be defined as a non-light-emitting area (NPXA).

[0182] An electronic device (DD) according to the present invention may include a partition wall (WL) included in a display panel (DP, see FIG. 3). The partition wall (WL) may be arranged in a non-emission area (NPXA) and may define partition wall openings (W-OP) overlapping first to third emission areas (PXA-G, PXA-R, PXA-B). In the present embodiment, each of the partition wall openings (W-OP) may have a rectangular shape. The partition wall openings (W-OP) may be defined by side surfaces of partition wall patterns included in the partition wall (WL) and including metal. A description thereof will be given later. The partition wall (WL) may surround pixels (PX-G, PX-R, PX-B).

[0183] FIG. 5b illustrates a portion of a second power line (PL2, power line of the claim) arranged within a display area (DA, see FIG. 1a). The second power line (PL2) may cross the pixel unit (PXU-a). FIG. 5b illustrates one second power line (PL2) extending in the second direction (DR2), but is not limited thereto, and a plurality of second power lines (PL2) may be provided, and at least one of the second power lines (PL2) may extend along the first direction (DR1).

[0184] According to one embodiment, a partition wall (WL) may include a normal area (NA) and a contact area (CA) within one pixel unit (PXU-a). The contact area (CA) may be defined as a portion where a second power line (PL2) and a partition wall pattern included in the partition wall (WL) come into contact with each other through a contact hole (CNT). The normal area (NA) may correspond to the remaining area excluding the contact area (CA).

[0185] In Fig. 5b, a second electrode (CE) included in a light-emitting element included in each of the pixels (PX-G1, PX-G2, PX-R, PX-B) is illustrated with a dotted line. The second electrode (CE) may be commonly arranged in the pixels (PX-G, PX-R, PX-B) to have a single pattern shape. The second electrode (CE) may be connected to a second power line (PL2) through a partition wall (WL) including metal, and a description thereof will be omitted.

[0186] Fig. 6 is a cross-sectional view taken along line I-I' of Fig. 5a. Fig. 7 is a cross-sectional view taken along line II-II' of Fig. 5a. Fig. 8 is a cross-sectional view taken along line II-II' of Fig. 5a.

[0187] Fig. 6 illustrates a cross-sectional view of the first pixel (PX-R) in Fig. 5a. Referring to Fig. 6, a light-emitting element (OLED-R) according to one embodiment may include a first electrode (AE-R), a second electrode (CE), and a first common layer (CL-R). The first common layer (CL-R) may include a hole control layer, an electron control layer, and a light-emitting layer.

[0188] A second electrode (CE) may be disposed on a first electrode (AE-R), and a first common layer (CL-R) may be disposed between the first electrode (AE-R) and the second electrode (CE). The light-emitting device (OLED-R) according to one embodiment may further include a protective layer disposed on the second electrode (CE). The protective layer includes an organic material and may prevent damage to components disposed under the protective layer during a subsequent process. According to one embodiment, the protective layer may be omitted.

[0189] The first, fourth, and sixth transistors (T1, T4, T6) and the light-emitting element (OLED-R) may be arranged on the substrate (SUB). The display area (DA) may include a second light-emitting area (PXA-R) corresponding to a pixel (PXij, see FIG. 4b) and a non-light-emitting area (NPXA) adjacent to the second light-emitting area (PXA-R).

[0190] The substrate (SUB) may include glass or a flexible plastic material such as polyimide (PI). A circuit element layer (DP-CL), a display element layer (DP-OLED), and a thin film encapsulation layer (TFE) may be disposed on the substrate (SUB). The circuit element layer (DP-CL) may be disposed on the substrate (SUB). The circuit element layer (DP-CL) may include insulating layers and conductive patterns. The display element layer (DP-OLED) may include a light emitting element (OLED-R) and a pixel defining layer (PDL).

[0191] A barrier layer (BRL) may be disposed on a substrate (SUB). The barrier layer (BRL) may increase the bonding strength between the semiconductor pattern included in the transistors and the substrate (SUB). The barrier layer (BRL) may include an inorganic material.

[0192] A metal layer (BML) may be disposed on the barrier layer (BRL). The metal layer (BML) may overlap the first transistor (T1). According to one embodiment, a constant voltage may be applied to the metal layer (BML). When the constant voltage is applied to the metal layer (BML), the threshold voltage (Vth) value of the first transistor (T1) disposed on the metal layer (BML) may be maintained without change.

[0193] The metal layer (BML) can block light incident on the first transistor (T1) from beneath the metal layer (BML). The metal layer (BML) can include a reflective metal. In one embodiment, the metal layer (BML) can be omitted.

[0194] A buffer layer (BFL) may be disposed on a barrier layer (BRL) and cover a metal layer (BML). The buffer layer (BFL) may include an inorganic material.

[0195] The semiconductor layers (S1, A1, D1) of the first transistor (T1) and the semiconductor layers (S6, A6, D6) of the sixth transistor (T6) may be arranged on the buffer layer (BFL). The semiconductor layers (S1, A1, D1, S6, A6, D6) may include polysilicon. However, the present invention is not limited thereto, and the semiconductor layers (S1, A1, D1, S6, A6, D6) may include amorphous silicon.

[0196] The semiconductor layers (S1, A1, D1, S6, A6, D6) may be doped with an N-type dopant or a P-type dopant. The semiconductor layers (S1, A1, D1, S6, A6, D6) may include a high-doping region and a low-doping region. The conductivity of the high-doping region is greater than that of the low-doping region, and may substantially function as a source electrode and a drain electrode of the first and sixth transistors (T1, T6). The low-doping region may substantially correspond to an active (or channel) of the first and sixth transistors (T1, T6).

[0197] The first source region (S1), the first channel region (A1), and the first drain region (D1) of the first transistor (T1) may be formed from semiconductor layers (S1, A1, D1). The sixth source region (S6), the sixth channel region (A6), and the sixth drain region (D6) of the sixth transistor (T6) may be formed from semiconductor layers (S6, A6, D6). The first channel region (A1) may be disposed between the first source region (S1) and the first drain region (D1). The sixth channel region (A6) may be disposed between the sixth source region (S6) and the sixth drain region (D6).

[0198] A first insulating layer (INS1) may be disposed on a buffer layer (BFL) to cover the semiconductor layers (S1, A1, D1, S6, A6, D6). A first gate electrode (G1, or control electrode) of a first transistor (T1) and a sixth gate electrode (G6, or control electrode) of a sixth transistor (T6) may be disposed on the first insulating layer (INS1). When viewed in plan view, the first gate electrode (G1) may overlap the first channel region (A1), and the sixth gate electrode (G6) may overlap the sixth channel region (A6).

[0199] Although not shown, the structure of the source region, channel region, drain region, and gate electrode of each of the second, fifth, and seventh transistors (T2, T5, T7) may be substantially the same as that of the first and sixth transistors (T1, T6).

[0200] A second insulating layer (INS2) may be disposed on the first insulating layer (INS1) to cover the first and sixth gate electrodes (G1, G6). A dummy electrode (DME) may be disposed on the second insulating layer (INS2). The dummy electrode (DME) is disposed on the first gate electrode (G1) and may overlap the first gate electrode (G1) when viewed in a plan view. The dummy electrode (DME) may form the aforementioned capacitor together with the first gate electrode (G1).

[0201] A third insulating layer (INS3) may be disposed on the second insulating layer (INS2) to cover the dummy electrode (DME). A semiconductor layer (S4, A4, D4) of the fourth transistor (T4) may be disposed on the third insulating layer (INS3). The semiconductor layers (S4, A4, D4) may include an oxide semiconductor formed of a metal oxide. The oxide semiconductor may include a crystalline or amorphous oxide semiconductor.

[0202] The semiconductor layer (S4, A4, D4) may include a plurality of regions that are distinguished depending on whether the metal oxide is reduced. The region where the metal oxide is reduced (hereinafter, referred to as a reduced region) may have higher conductivity than the region where the metal oxide is not reduced (hereinafter, referred to as a non-reduced region). The reduced region may substantially function as a source electrode or a drain electrode of the fourth transistor (T4). The non-reduced region may substantially correspond to the active (or channel) of the fourth transistor (T4).

[0203] The fourth source region (S4), the fourth channel region (A4), and the fourth drain region (D4) of the fourth transistor (T4) may be formed from semiconductor layers (S4, A4, D4). The fourth channel region (A4) may be positioned between the fourth source region (S4) and the fourth drain region (D4).

[0204] A fourth insulating layer (INS4) may be disposed on the third insulating layer (INS3) to cover the semiconductor layers (S4, A4, D4). A fourth gate electrode (G4) of a fourth transistor (T4) may be disposed on the fourth insulating layer (INS4). When viewed in plan view, the fourth gate electrode (G4) may overlap the fourth channel region (A4).

[0205] A fifth insulating layer (INS5) may be disposed on the fourth insulating layer (INS4) to cover the fourth gate electrode (G4). Although not illustrated, the structure of the source region, channel region, drain region, and gate electrode of the third transistor (T3) may be substantially the same as that of the fourth transistor (T4).

[0206] The barrier layer (BRL), the buffer layer (BFL), and the first to fifth insulating layers (INS1 to INS5) may include an inorganic material. For example, the barrier layer (BRL), the buffer layer (BFL), and the first to fifth insulating layers (INS1 to INS5) may include either silicon oxide or silicon nitride, or one insulating layer may include multiple inorganic layers, without being limited to any embodiment. The multiple inorganic layers may have a structure in which layers including silicon nitride and silicon oxide are alternately laminated.

[0207] A connection electrode (CNE) may be disposed between the sixth transistor (T6) and the light-emitting element (OLED-R). The connection electrode (CNE) may electrically connect the sixth transistor (T6) and the light-emitting element (OLED-R). The connection electrode (CNE) may include a first connection electrode (CNE1) and a second connection electrode (CNE2) disposed on the first connection electrode (CNE1).

[0208] The first connection electrode (CNE1) may be disposed on the fifth insulating layer (INS5) and connected to the sixth drain region (D6) through the first contact hole (CH1) defined in the first to fifth insulating layers (INS1 to INS5). A sixth insulating layer (INS6) may be disposed on the fifth insulating layer (INS5) to cover the first connection electrode (CNE1).

[0209] The second connection electrode (CNE2) may be disposed on the sixth insulating layer (INS6). The second connection electrode (CNE2) may be connected to the first connection electrode (CNE1) through a second contact hole (CH2) defined in the sixth insulating layer (INS6).

[0210] According to the present embodiment, the second power line (PL2) may be disposed on the sixth insulating layer (INS6) and covered by the seventh insulating layer (INS7). According to one embodiment, a portion of the second power line (PL2) may be disposed in the second light-emitting region (PXA-R). The second power line (PL2) and the second connection electrode (CNE2) may be patterned by the same process and may include the same material.

[0211] A seventh insulating layer (INS7) may be disposed on the sixth insulating layer (INS6) to cover the second connecting electrode (CNE2) and the second power line (PL2). The sixth and seventh insulating layers (INS6, INS7) may include an organic material.

[0212] A pixel defining layer (PDL) may be disposed on the seventh insulating layer (INS7). An opening (PDL-OP) exposing at least a portion of the first electrode (AE-R) may be defined in the pixel defining layer (PDL). In the present embodiment, the pixel defining layer (PDL) may include an organic material. In addition, the pixel defining layer (PDL) may have a predetermined color, and is not limited to any one embodiment.

[0213] A first common layer (CL-R) and a second electrode (CE) included in a light-emitting element (OLED-R) may be arranged on a pixel defining layer (PDL).

[0214] A thin film encapsulation layer (TFE) may be disposed on the light-emitting element (OLED-R) to cover the light-emitting element (OLED-R). The thin film encapsulation layer (TFE) may be disposed over the entire area of ​​the display area (DA). The thin film encapsulation layer (TFE) may include inorganic films and an organic film disposed between the inorganic films, and is not limited to any one embodiment.

[0215] Fig. 7 illustrates a cross-sectional view of a normal area (NA) among the partition walls (WL) arranged in a non-luminous area (NPXA). Fig. 8 illustrates a cross-sectional view of a contact area (CA) among the partition walls (WL) arranged in a non-luminous area (NPXA).

[0216] Referring to FIGS. 7 and 8, a partition wall (WL) according to one embodiment may include a first insulating pattern (IN1), a second insulating pattern (IN2), a first partition wall pattern (W1), and a second partition wall pattern (W2). In the present specification, the first partition wall pattern (W1) and the second partition wall pattern (W2) arranged in the normal area (NA) are defined as a normal partition wall layer (WA-N), and the first partition wall pattern (W1) and the second partition wall pattern (W2) arranged in the contact area (CA) are defined as a contact partition wall layer (WA-C). The normal partition wall layer (WA-N) and the contact partition wall layer (WA-C) are substantially one connected pattern, and will be described separately for convenience of explanation. First, the commonly applied partition wall (WL) will be described.

[0217] A first insulating pattern (IN1) may be disposed on a pixel defining layer (PDL). The first insulating pattern (IN1) may include an inorganic material. A second insulating pattern (IN2) may be disposed on the first insulating pattern (IN1). The second insulating pattern (IN2) may include an inorganic material different from the first insulating pattern (IN1).

[0218] For example, the first insulating pattern (IN1) may include at least one of indium zinc oxide, indium gallium zinc oxide, and indium tin oxide, and the second insulating pattern (IN2) may include at least one of silicon oxide, silicon oxynitride, and silicon nitride.

[0219] In this embodiment, the first insulating pattern (IN1) may be configured to short-circuit the P-type hole injection layer among the layers included in the first common layer (CL-G1). Accordingly, the thickness of the first insulating pattern (IN1) may be thicker than the thickness of the P-type hole injection layer among the layers included in the first common layer (CL-G1).

[0220] According to one embodiment, the width of the second insulating pattern (IN2) in cross-section may be greater than the width of the first insulating pattern (IN1). The width difference may be formed due to a difference in etching rates of the etchants of the first insulating pattern (IN1) and the second insulating pattern (IN2).

[0221] A step may be formed in a portion of the second insulating pattern (IN2) that overlaps with the first partition wall pattern (W1) and in other portions. Accordingly, the thickness of the portion of the second insulating pattern (IN2) that overlaps with the first partition wall pattern (W1) may be greater than the thickness of the portion of the second insulating pattern (IN2) that is exposed from the first partition wall pattern (W1).

[0222] Common layers (CL-G1, CL-B) included in different pixels are disconnected from each other with a partition wall (WL) interposed therebetween by a first insulating pattern (IN1) and a second insulating pattern (IN2), and the disconnected common layers (CL-G1, CL-B) can contact side surfaces of the first insulating pattern (IN1) and the second insulating pattern (IN2). However, the present invention is not limited thereto, and the disconnected common layers (CL-G1, CL-B) can contact side surfaces (N1-S, C1-S) of the first partition wall pattern (W1), and are not limited to any one embodiment.

[0223] The first partition wall pattern (W1) is disposed on the second insulating pattern (IN2). The first partition wall pattern (W1) may include a metal. For example, the first partition wall pattern (W1) may include aluminum. Since the first partition wall pattern (W1) includes aluminum, the side surfaces (N1-S, C1-S) of the first partition wall pattern (W1) may be oxidized and not have conductivity. Accordingly, the side surfaces (N1-S, C1-S) of the first partition wall pattern (W1) may include non-conductive regions (N1-O, C1-O).

[0224] The second bulkhead pattern (W2) may be arranged on the first bulkhead pattern (W1). The second bulkhead pattern (W2) may include a different metal than the first bulkhead pattern (W1). For example, the second bulkhead pattern (W2) may include titanium.

[0225] According to the present embodiment, the thickness of the first partition wall pattern (W1) may be greater than the thickness of the second partition wall pattern (W2), and the width of the first partition wall pattern (W1) may be less than the width of the second partition wall pattern (W2). According to one embodiment, a portion of the second partition wall pattern (W2) may protrude from the first partition wall pattern (W1) and be exposed from the first partition wall pattern (W1). Therefore, the lower surface (N2-B, C2-B) of the second partition wall pattern (W2) may be exposed from the first partition wall pattern (W1). This may be formed due to a difference in etching rates of the etchants of the first partition wall pattern (W1) and the second partition wall pattern (W2). The first partition wall pattern (W1) and the second partition wall pattern (W2) may be defined as having a tip structure.

[0226] The second electrode (CE) may be disposed on the barrier rib (WL) extending from the second light-emitting region (PXA-R) illustrated in FIG. 6 to the non-light-emitting region (NPXA). The second electrode (CE) overlapping the barrier rib (WL) may be in contact with the side surfaces (N1-S, C1-S) of the first barrier rib pattern (W1), the lower surface (N2-B, C2-B) of the second barrier rib pattern (W2) exposed from the first barrier rib pattern (W1), and the side surfaces (N2-S, C2-S) of the second barrier rib pattern (W2).

[0227] As described above, since the side surfaces (N1-S, C1-S) of the first partition wall pattern (W1) include non-conductive regions (N1-O, C1-O) that are oxidized and do not have conductivity, a part of the second electrode (CE) covering the partition wall (WL) is connected to another part of the second electrode (CE) through the lower surface (N2-B, C2-B) of the second partition wall pattern (W2) exposed from the first partition wall pattern (W1) and the inner part of the first partition wall pattern (W1), and a part of the second electrode (CE) can receive a signal from the second power line (PL2) and be connected to each other.

[0228] According to one embodiment, the first thickness (TH1) of the second electrode (CE) disposed on the common layer (CL-G1, CL-B) may be greater than the second thickness (TH2) of the second electrode (CE) surrounding the partition wall (WL). The second thickness (TH2) may have a thickness of 20% to 25% of the first thickness (TH1).

[0229] A dummy pattern (CL-P) may be arranged on the second partition wall pattern (W2). The dummy pattern (CL-P) may be covered by the second electrode (CE). The dummy pattern (CL-P) may be formed by the same process as the common layers (CL-G1, CL-B) and may include the same material as the common layers (CL-G1, CL-B). The common layers (CL-G1, CL-B) may be disconnected on the second partition wall pattern (W2) due to the tip structure of the partition wall (WL), and the disconnected portion of the common layers (CL-G1, CL-B) may be defined as the common layers (CL-G1, CL-B).

[0230] Referring to FIGS. 7 and 8, the upper surface (N1-U) of the first partition pattern (W1) in the normal area (NA) and the upper surface (C1-U) of the first partition pattern (W1) in the contact area (CA) may have different shapes.

[0231] In the normal area (NA), the upper surface (N1-U) of the first partition wall pattern (W1) may be flat. Accordingly, the lower surface (N2-B) and the upper surface (N2-U) of the second partition wall pattern (W2) arranged on the first partition wall pattern (W1) may have a flat shape corresponding to the upper surface (N1-U) of the first partition wall pattern (W1).

[0232] In the contact area (CA), the upper surface (C1-U) of the first partition wall pattern (W1) may have a concave shape in a direction from the upper surface (C1-U) of the first partition wall pattern (W1) toward the lower surface of the first partition wall pattern (W1). This may be a shape formed as the first partition wall pattern (W1) fills the opening (OP) and the contact hole (CNT) in the contact area (CA). Accordingly, the lower surface (C2-B) and the upper surface (C2-U) of the second partition wall pattern (W2) disposed on the first partition wall pattern (W1) may have a shape corresponding to the upper surface (N1-U) of the first partition wall pattern (W1).

[0233] A contact hole (CNT) may be defined in the contact area (CA). The contact hole (CNT) may be defined by a first contact hole (IC) through which a seventh insulating layer (INS7, interlayer insulating layer) overlapping a second power line (PL2) is penetrated, and a second contact hole (PC) through which a pixel defining layer (PDL) overlapping the first contact hole (IC) is penetrated.

[0234] An opening (OP) may be defined in the first insulating pattern (IN1) and the second insulating pattern (IN2) in the contact area (CA). The opening (OP) may overlap with the contact hole (CNT) and expose the second power line (PL2) together with the contact hole (CNT). The opening (OP) may be defined by a first opening (I-OP1) penetrating the first insulating pattern (IN1) and a second opening (I-OP2) penetrating the second insulating pattern (IN2) and overlapping the first opening (I-OP1) to expose the second power line (PL2).

[0235] According to one embodiment, the second insulating pattern (IN2) can cover a side surface of the seventh insulating layer (INS7) defining the first contact hole (IC) and a side surface of the pixel defining layer (PDL) defining the second contact hole (PC). In addition, the second insulating pattern (IN2) can cover an upper surface of the pixel defining layer (PDL) exposed from the first insulating pattern (IN1) by the first opening (I-OP1). However, the shape of the second insulating pattern (IN2) is not limited thereto.

[0236] According to the present invention, the first partition pattern (W1) in the contact area (CA) can be connected to the second power line (PL2) through the opening (OP) and the contact hole (CNT). The second power line (PL2) can include three layers of laminated metal layers. The lower layer and the upper layer can include titanium, and the middle layer can include aluminum.

[0237] As illustrated in FIG. 5a, the second electrode (CE) is commonly arranged in one pixel unit (PXU) and can be connected to the second power line (PL2) through the lower surface (N2-B, C2-B), the side surface (N2-S, C2-S) of the second partition wall pattern (W2) and the inner portion of the first partition wall pattern (W1) in the contact area (CA).

[0238] According to the present invention, since the second electrode (CE) is connected to the second power line (PL2) through the partition wall (WL) within the display area (DA, see FIG. 1a), a voltage drop phenomenon can be prevented and a constant voltage can be provided to the pixels. In addition, since the connection between the second electrode (CE) and the second power line (PL2) is made within the display area (DA, see FIG. 1a), an unnecessary space for connecting the second electrode (CE) and the second power line (PL2) in the non-display area (NDA) can be reduced. In addition, pixel units (PXU) having different resolutions can be individually driven.

[0239] FIG. 9 is a cross-sectional view of a partition wall overlapping a contact area according to an embodiment of the present invention. FIG. 10 is a cross-sectional view of a partition wall overlapping a contact area according to an embodiment of the present invention. FIG. 11 is a cross-sectional view of a partition wall overlapping a contact area according to an embodiment of the present invention. FIG. 12 is a cross-sectional view of a partition wall overlapping a contact area according to an embodiment of the present invention. The same / similar reference numerals are used for the same / similar components as those described in FIGS. 1A to 8 , and duplicate descriptions are omitted. FIGS. 9 to 12 are examples showing cross-sectional views of contact partition walls arranged in a contact area (CA) corresponding to FIG. 8 . The following embodiments of the contact partition walls described can also be commonly applied to a normal partition wall layer (WA-N, see FIG. 7 ) arranged in a normal area (NA, see FIG. 7 ) described in FIG. 7 .

[0240] Referring to FIG. 9, a display device (DD-A) according to one embodiment may include a barrier rib (WL-A) disposed in a non-emitting area (NPXA). The barrier rib (WL-A) may include a normal barrier rib layer (WA-N), a contact barrier rib layer (WA-C), a first insulating pattern (IN1), a second insulating pattern (IN2), and a protective layer (PL). Each of the normal barrier rib layer (WA-N) and the contact barrier rib layer (WA-C) may include a first barrier rib pattern (W1) and a second barrier rib pattern (W2).

[0241] Fig. 9 illustrates a contact barrier layer (WA-C) disposed in a contact area (CA) corresponding to Fig. 8 among the barrier layers (WL-A). The description of the contact barrier layer (WA-C) can be commonly applied to the normal barrier layer (WA-N) disposed in the normal area (NA, see Fig. 7), and duplicate descriptions are omitted.

[0242] A first insulating pattern (IN1) may be disposed on a pixel defining layer (PDL). The first insulating pattern (IN1) may include an inorganic material. A second insulating pattern (IN2) may be disposed on the first insulating pattern (IN1). The second insulating pattern (IN2) may include an inorganic material different from the first insulating pattern (IN1).

[0243] The first partition wall pattern (W1) is arranged on the second insulating pattern (IN2). The first partition wall pattern (W1) may include aluminum. The side surfaces (N1-S, C1-S) of the first partition wall pattern (W1) may be oxidized and not have conductivity. Accordingly, the side surfaces (N1-S, C1-S) of the first partition wall pattern (W1) may include non-conductive regions (N1-O, C1-O).

[0244] The second bulkhead pattern (W2) may be arranged on the first bulkhead pattern (W1). The second bulkhead pattern (W2) may include titanium.

[0245] The barrier rib (WL-A) according to the present embodiment may further include a protective layer (PL). The protective layer (PL) may be disposed on the upper surface (C2-U) of the second barrier rib pattern (W2). The protective layer (PL) may be disposed on the second barrier rib pattern (W2) to prevent the second barrier rib pattern (W2) from being damaged in a subsequent process.

[0246] The protective layer (PL) may include an inorganic material. For example, the protective layer (PL) may include at least one of silicon nitride and silicon oxide.

[0247] The second electrode (CE) may be disposed on the barrier rib (WL-A) extending from the second light-emitting region (PXA-R) illustrated in FIG. 6 to the non-light-emitting region (NPXA). The second electrode (CE) overlapping the barrier rib (WL-A) may be in contact with the side surface (C1-S) of the first barrier rib pattern (W1), the lower surface (C2-B) of the second barrier rib pattern (W2) exposed from the first barrier rib pattern (W1), the side surface (C2-S) of the second barrier rib pattern (W2), and the side surface (PL) of the protective layer (PL).

[0248] According to the present embodiment, a barrier rib (WL-A) having a robust tip structure can be provided by placing a protective layer (PL) on the second barrier rib pattern (W2).

[0249] In the contact area (CA), the upper surface (C1-U) of the first partition wall pattern (W1) may have a concave shape in a direction from the upper surface (C1-U) of the first partition wall pattern (W1) toward the lower surface of the first partition wall pattern (W1). The second partition wall pattern (W2) and the protective layer (PL) arranged on the first partition wall pattern (W1) may have a concave shape corresponding to the upper surface (N1-U) of the first partition wall pattern (W1).

[0250] A contact hole (CNT) can be defined in the contact area (CA) including a first contact hole (IC) through which a seventh insulating layer (INS7, interlayer insulating layer) is penetrated and a second contact hole (PC) through which a pixel defining layer (PDL) overlapping the first contact hole (IC) is penetrated.

[0251] An opening (OP) can be defined that includes a first opening (I-OP1) overlapping a contact hole (CNT) in a contact area (CA) and through which a first insulating pattern (IN1) passes, and a second opening (I-OP2) overlapping the first opening (I-OP1) and exposing a second power line (PL2) and through which a second insulating pattern (IN2) passes.

[0252] According to the present invention, the first partition pattern (W1) in the contact area (CA) can contact the second power line (PL2) through the opening (OP) and the contact hole (CNT).

[0253] Referring to FIG. 10, a display device (DD-B) according to one embodiment may include a barrier rib (WL-B) disposed in a non-emitting area (NPXA). The barrier rib (WL-B) may include a normal barrier rib layer (WA-N), a contact barrier rib layer (WA-C), a first insulating pattern (IN1), and a second insulating pattern (IN2). Each of the normal barrier rib layer (WA-N) and the contact barrier rib layer (WA-C) may include a first barrier rib pattern (W1), a second barrier rib pattern (W2), and a third barrier rib pattern (W3).

[0254] Fig. 10 illustrates a contact barrier layer (WA-C) disposed in a contact area (CA) corresponding to Fig. 8 among the barrier layers (WL-B). The description of the contact barrier layer (WA-C) can be commonly applied to the normal barrier layer (WA-N) disposed in the normal area (NA, see Fig. 7), and duplicate descriptions are omitted.

[0255] A first insulating pattern (IN1) may be disposed on a pixel defining layer (PDL). A second insulating pattern (IN2) may be disposed on the first insulating pattern (IN1).

[0256] The first partition wall pattern (W1) is arranged on the second insulating pattern (IN2). The first partition wall pattern (W1) may include aluminum. The side surfaces (N1-S, C1-S) of the first partition wall pattern (W1) may be oxidized and not have conductivity. Accordingly, the side surfaces (N1-S, C1-S) of the first partition wall pattern (W1) may include non-conductive regions (N1-O, C1-O).

[0257] The second bulkhead pattern (W2) may be arranged on the first bulkhead pattern (W1). The second bulkhead pattern (W2) may include titanium.

[0258] The partition wall (WL-B) according to the present embodiment may further include a third partition wall pattern (W3). The third partition wall pattern (W3) may be positioned between the first partition wall pattern (W1) and the second insulating pattern (IN2). The third partition wall pattern (W3) may include the same material as the first partition wall pattern (W1). Accordingly, the third partition wall pattern (W3) may include titanium.

[0259] In this embodiment, the third partition pattern (W3) is arranged in the opening (OP) and the contact hole (CNT) so as to be in contact with the second power line (PL2). More specifically, the third partition pattern (W3) can be in contact with the upper surface of the second insulating pattern (IN2), the side surface of the second insulating pattern (IN2) defining the second opening (I-OP2), and the second power line (PL2). The third partition pattern (W3) can have a shape corresponding to the lower surface (C1-B) of the first partition pattern (W1).

[0260] The second electrode (CE) may be placed on the partition wall (WL-B). The second electrode (CE) overlapping the partition wall (WL-B) may be in contact with the side surface (C1-S) of the first partition wall pattern (W1), the lower surface (C2-B) of the second partition wall pattern (W2) exposed from the first partition wall pattern (W1), and the side surface (C2-S) of the second partition wall pattern (W2).

[0261] According to the present embodiment, the common layers (CL-G1, CL-G2) can be in contact with the first and second insulating patterns (IN1, IN2) and the third partition wall pattern (W3).

[0262] In the contact area (CA), the upper surface (C1-U) of the first partition wall pattern (W1) may have a concave shape in a direction from the upper surface (C1-U) of the first partition wall pattern (W1) toward the lower surface of the first partition wall pattern (W1). The second partition wall pattern (W2) arranged on the first partition wall pattern (W1) may have a concave shape corresponding to the upper surface (N1-U) of the first partition wall pattern (W1).

[0263] According to the present invention, the third partition pattern (W3) in the contact area (CA) can contact the second power line (PL2) through the opening (OP) and the contact hole (CNT).

[0264] Fig. 11 will focus on explaining differences from Fig. 10. Referring to Fig. 11, a display device (DD-C) according to one embodiment may include a barrier rib (WL-C) arranged in a non-emitting area (NPXA). The barrier rib (WL-C) may include a normal barrier rib layer (WA-N), a contact barrier rib layer (WA-C), a first insulating pattern (IN1), and a second insulating pattern (IN2). Each of the normal barrier rib layer (WA-N) and the contact barrier rib layer (WA-C) may include a first barrier rib pattern (W1), a second barrier rib pattern (W2), and a third barrier rib pattern (W3).

[0265] In this embodiment, a portion of the second partition pattern (W2) exposed from the first partition pattern (W1) may include a tip portion (TIP) bent downward.

[0266] According to the present embodiment, since the second bulkhead pattern (W2) includes a tip portion (TIP), the common layers (CL-G1, CL-G2) can be more easily disconnected from the bulkhead (WL-C).

[0267] Fig. 12 will focus on explaining differences from Fig. 10. Referring to Fig. 12, a display device (DD-D) according to one embodiment may include a barrier rib (WL-D) arranged in a non-emitting area (NPXA). The barrier rib (WL-D) may include a normal barrier rib layer (WA-N), a contact barrier rib layer (WA-C), a first insulating pattern (IN1), and a second insulating pattern (IN2). Each of the normal barrier rib layer (WA-N) and the contact barrier rib layer (WA-C) may include a first barrier rib pattern (W1), a second barrier rib pattern (W2), and a third barrier rib pattern (W3).

[0268] In this embodiment, a trench (TR) may be defined in the first partition wall pattern (W1). The trench (TR) may be defined by being sunken in a direction from the upper surface (C1-U) of the first partition wall pattern (W1) toward the lower surface (C1-B) of the first partition wall pattern (W1). The trench (TR) may be defined as an empty space, and in a cross-section, the trench (TR) may have an inverted trapezoidal shape.

[0269] The trench (TR) shape may be a shape formed by filling a first barrier pattern (W1) into a contact hole (CNT) in a contact area (CA). A second barrier pattern (W2) may be arranged on the first barrier pattern (W1) so as to correspond to the shape of the trench (TR).

[0270] Figures 13a to 13g are cross-sectional views illustrating a method for manufacturing a display panel according to an embodiment of the present invention. Figures 13a to 13g illustrate a method for forming a normal barrier layer (WA-N) disposed in the normal area (NA) described in Figure 7 and a contact barrier layer (WA-C) disposed in the contact area (CA) described in Figure 8. Among the configurations described in Figure 6, configurations below the sixth insulating layer (INS6) are omitted.

[0271] Referring to FIG. 13A, a method for manufacturing a display panel according to one embodiment may include a step of forming a second power line (PL2) in a contact area (CA). The second power line (PL2) may include three layers of laminated metal layers. The lower layer and the upper layer may include titanium, and the middle layer may include aluminum.

[0272] Thereafter, the method may include a step of forming a seventh insulating layer (INS7) on a sixth insulating layer (INS6), a step of forming a pixel defining layer (PDL) on the seventh insulating layer (INS7), and a step of forming a first insulating pattern (IN1) on the pixel defining layer (PDL).

[0273] The first insulating pattern (IN1) may include at least one of indium zinc oxide, indium gallium zinc oxide, and indium tin oxide.

[0274] A first contact hole (IC) exposing a second power line (PL2) can be formed in the seventh insulating layer (INS7). A second contact hole (PC) overlapping the first contact hole (IC) can be formed in the pixel defining layer (PDL). The first contact hole (IC) and the second contact hole (PC) can be defined as contact holes (CNT). The process of forming the first contact hole (IC) and the second contact hole (PC) can be performed using a photoresist process.

[0275] A first opening (I-OP1) overlapping with a contact hole (CNT) can be formed in the first insulating pattern (IN1). The process of forming the first opening (I-OP1) can be performed using a wet etching process.

[0276] Hereinafter, referring to FIG. 13b, a method for manufacturing a display panel according to one embodiment may include a step of forming a second insulating pattern (IN2), a step of forming a first partition wall pattern (W1), and a step of forming a second partition wall pattern (W2).

[0277] A second insulating pattern (IN2) may be formed on the first insulating pattern (IN1). The first insulating pattern (IN1) may include at least one of silicon oxide, silicon oxynitride, and silicon nitride.

[0278] A second opening (I-OP2) can be formed in the second insulating pattern (IN2) to overlap the contact hole (CNT) and the first opening (I-OP1) and expose the second power line (PL2). The second opening (I-OP2) can be formed by a dry etching process. The first opening (I-OP1) and the second opening (I-OP2) can be defined as an opening (OP).

[0279] The first partition wall pattern (W1) may be formed on the second insulating pattern (IN2). The first partition wall pattern (W1) may include aluminum. In the contact area (CA), the first partition wall pattern (W1) may be in contact with the second power line (PL2) through the opening (OP) and the contact hole (CNT).

[0280] The second bulkhead pattern (W2) may be formed on the first bulkhead pattern (W1). The second bulkhead pattern (W2) may include titanium. The thickness of the second bulkhead pattern (W2) may be smaller than the thickness of the first bulkhead pattern (W1).

[0281] According to the present invention, the upper surface (C1-U) of the first partition wall pattern (W1) in the contact area (CA) may have a concave shape in a direction from the upper surface (C1-U) of the first partition wall pattern (W1) toward the lower surface of the first partition wall pattern (W1). This may be a shape formed as the first partition wall pattern (W1) fills the opening (OP) and the contact hole (CNT) in the contact area (CA). Accordingly, the second partition wall pattern (W2) disposed on the first partition wall pattern (W1) may have a shape corresponding to the upper surface (N1-U) of the first partition wall pattern (W1).

[0282] Hereinafter, referring to FIG. 13c, a method for manufacturing a display panel according to one embodiment may include a step of first patterning the first and second partition patterns (W1, W2). The first patterning step may be performed using a photo process using a photoresist layer (PR) as a mask. Through the photo process, only the first and second partition patterns (W1, W2) overlapping the photoresist layer (PR) may remain.

[0283] At this time, a step (IC) may be formed in the portion of the first insulating pattern (IN1) that overlaps with the first and second partition patterns (W1, W2) and in other portions. This may be because a portion of the first insulating pattern (IN1) is removed together in the process of etching the first and second partition patterns (W1, W2) removed in the photo process.

[0284] Hereinafter, referring to FIG. 13d, a method for manufacturing a display panel according to one embodiment may include a step of second-patterning the second partition wall pattern (W2). The second-patterning step may be performed by a wet etching process. By the second-patterning step, the width of the first partition wall pattern (W1) may become smaller than the width of the second partition wall pattern (W2). A portion of the second partition wall pattern (W2) may protrude from the first partition wall pattern (W1) and be exposed from the first partition wall pattern (W1), thereby forming a tip structure.

[0285] Hereinafter, referring to FIG. 13e, a method for manufacturing a display panel according to one embodiment may include a step of patterning a second insulating pattern (IN2). The step of patterning the second insulating pattern (IN2) may be performed by a dry etching process. The second insulating pattern (IN2) may be patterned such that portions other than the portion overlapping the first partition wall pattern (W1) are removed.

[0286] Hereinafter, referring to FIG. 13F, a method for manufacturing a display panel according to one embodiment may include a step of patterning a first insulating pattern (IN1). The step of patterning the first insulating pattern (IN1) may be performed by a wet etching process. The first insulating pattern (IN1) may be patterned so that portions other than the portion overlapping the second insulating pattern (IN2) are removed.

[0287] According to the present embodiment, the width of the first insulating pattern (IN1) in one direction may be smaller than the width of the second insulating pattern (IN2).

[0288] Hereinafter, referring to FIG. 13g, a method for manufacturing a display panel according to one embodiment may include a step of forming a common layer (CL) and a step of forming a second electrode (CE). The common layer (CL) may include a hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer, and an electron injection layer.

[0289] According to the present embodiment, among the layers included in the common layer (CL), the P-type hole injection layer may be disconnected by the first insulating pattern (IN1). Therefore, the thickness of the first insulating pattern (IN1) may be greater than the thickness of the P-type hole injection layer.

[0290] The second electrode (CE) may be disposed on the barrier rib (WL) extending from the second light-emitting region (PXA-R) illustrated in FIG. 6 to the non-light-emitting region (NPXA). The second electrode (CE) overlapping the barrier rib (WL) may be in contact with the side surfaces (N1-S, C1-S) of the first barrier rib pattern (W1), the lower surface (N2-B, C2-B) of the second barrier rib pattern (W2) exposed from the first barrier rib pattern (W1), and the side surfaces (N2-S, C2-S) of the second barrier rib pattern (W2).

[0291] The side surfaces (N1-S, C1-S) of the first partition wall pattern (W1) may include non-conductive regions (N1-O, C1-O) that are oxidized and do not have conductivity. According to the present invention, the second electrode (CE) covering the partition wall (WL) may receive a signal from the second power line (PL2) and be connected to each other through the lower surface (N2-B, C2-B) of the second partition wall pattern (W2) exposed from the first partition wall pattern (W1) and the inner portion of the first partition wall pattern (W1).

[0292] Referring to FIG. 14, the display system (1000) may include a processor (1100) and a display device (1200).

[0293] The processor (1100) can perform various tasks and calculations. The processor (1100) may include an application processor, a graphics processor, a microprocessor, a central processing unit (CPU), etc. The processor (1100) may be electrically connected to other components of the display system (1000) via a bus system and control the other components.

[0294] The processor (1100) can transmit image data (IMG) and a control signal (CTRL) to the display device (1200). The display device (1200) can display an image based on the image data (IMG) and the control signal (CTRL). The display device (1200) can be configured similarly to the electronic device (DD) described with reference to FIG. 1A. 1.

[0295] The display system (1000) may include a computing system that provides an image display function, such as a smartwatch, a mobile phone, a smart phone, a portable computer, a tablet PC, a watch phone, a vehicle display, smart glasses, a portable multimedia player (PMP), a navigation system, an ultra mobile PC (UMPC), etc. The display system (1000) may include at least one of a head-mounted display (HMD) device, a virtual reality (VR) device, a mixed reality (MR) device, and an augmented reality (AR) device.

[0296] Referring to FIG. 15, the display system (1000) of FIG. 14 can be applied to a smart watch (2000) including a display unit (2100) and a strap unit (2200).

[0297] The smartwatch (2000) may be a wearable electronic device. For example, the smartwatch (2000) may have a structure in which a strap unit (2200) is attached to the user's wrist. In this case, a display system (1000) and / or a display device (1200) may be applied to the display unit (2100) to provide image data including time information to the user.

[0298] Although the present invention has been described above with reference to preferred embodiments thereof, it will be understood by those skilled in the art or having ordinary knowledge in the art that various modifications and changes to the present invention can be made without departing from the spirit and technical scope of the present invention as set forth in the claims to be described below.

[0299] Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the patent claims.

[0300] An electronic device comprises a base substrate including light-emitting areas and a non-light-emitting area disposed between the light-emitting areas, pixels each including a light-emitting element, pixel units disposed on the base substrate, a power line crossing the pixel units, a partition wall surrounding each of the pixels and including a first partition wall pattern including different metals and a second partition wall pattern disposed on the first partition wall pattern, wherein the partition wall is divided into a contact area connected to the power line through a contact hole and a normal area other than the contact area, and since the shapes of the upper surface of the first partition wall pattern in the normal area and the upper surface of the first partition wall pattern in the contact area are different, a voltage drop phenomenon can be prevented and a constant voltage can be provided to the pixels, and pixel units having different resolutions can be individually driven, so that the present invention has high industrial applicability.

Claims

A base substrate comprising a display region including light-emitting regions and a non-light-emitting region disposed between the light-emitting regions; A pixel unit, each of which includes pixels including a light-emitting element, and arranged on the base substrate; A power line crossing the pixel unit and arranged on the base substrate; and A barrier rib is defined that overlaps the above light-emitting areas, is arranged in the non-light-emitting area, surrounds each of the pixels, and includes a barrier rib that includes a first barrier rib pattern and a second barrier rib pattern arranged on the first barrier rib pattern, The above bulkhead is divided into a contact area connected to the power line through a contact hole and a normal area other than the contact area, An electronic device in which the shapes of the upper surface of the first partition pattern in the normal region and the upper surface of the first partition pattern in the contact region are different. In the first paragraph, In the above contact area, the upper surface of the first partition wall pattern has a concave shape in a direction from the upper surface of the first partition wall pattern toward the lower surface of the first partition wall pattern, An electronic device in which a portion of the second bulkhead pattern has a shape corresponding to the shape of the upper surface of the first bulkhead pattern. In the first paragraph, An electronic device in which the upper surface of the first bulkhead pattern in the above normal region is flat. In the first paragraph, In the above contact area, the upper surface of the first partition wall pattern is defined with a trench sunken in the direction from the upper surface of the first partition wall pattern toward the lower surface of the first partition wall pattern, In cross-section, the trench has an inverted trapezoidal shape, An electronic device wherein a portion of the second bulkhead pattern has a shape corresponding to the shape of the trench. In the first paragraph, The above first bulkhead pattern comprises aluminum, The above second bulkhead pattern is an electronic device comprising titanium. In paragraph 5, The width of the first bulkhead pattern is smaller than the width of the second bulkhead pattern, An electronic device wherein the thickness of the first bulkhead pattern is greater than the thickness of the second bulkhead pattern. In the first paragraph, Each of the light-emitting elements includes a first electrode, a second electrode disposed on the first electrode, and a common layer disposed between the first electrode and the second electrode, An electronic device in which the second electrode is a single pattern commonly arranged in the light-emitting elements. In paragraph 7, The second electrode overlapping the above bulkhead is An electronic device in contact with the side surface of the first partition wall pattern, the lower surface of the second partition wall pattern exposed from the first partition wall pattern, and the side surface of the second partition wall pattern. In paragraph 8, An electronic device in which the side surface of the first bulkhead pattern is oxidized and has no conductivity. In paragraph 8, Further comprising a dummy pattern disposed on the second bulkhead pattern and covered by the second electrode, An electronic device wherein the dummy pattern comprises the same material as the common layer. In paragraph 9, Further comprising a protective layer disposed between the second bulkhead pattern and the dummy pattern, The above protective layer is an electronic device containing an inorganic material. In paragraph 8, An electronic device comprising a tip portion that is bent downwards, wherein a portion of the second bulkhead pattern exposed from the first bulkhead pattern is formed. In paragraph 8, The thickness of the second electrode disposed on the common layer is An electronic device having a thickness greater than that of the second electrode surrounding the above bulkhead. In the first paragraph, The above bulkhead includes a first insulating pattern disposed below the first bulkhead pattern and a second insulating pattern disposed between the first insulating pattern and the first bulkhead pattern, An electronic device wherein the first insulating pattern and the second insulating pattern include different materials. In Article 14, The first insulating pattern includes at least one of indium zinc oxide, indium gallium zinc oxide, and indium tin oxide, An electronic device wherein the second insulating pattern comprises at least one of silicon oxide, silicon oxynitride, and silicon nitride. In Article 14, An electronic device wherein the width of the first insulating pattern is smaller than the width of the second insulating pattern. In Article 14, An electronic device further comprising a third partition pattern disposed between the first partition pattern and the second insulating pattern and including the same material as the second partition pattern. In Article 14, Interlayer insulation layer in which the above power lines are arranged; an insulating layer disposed on the interlayer insulating layer and covering the power line; and An electronic device further comprising a pixel defining film disposed on the insulating layer between the first insulating pattern and defining openings corresponding to the light-emitting areas. In Article 14, The above contact hole is defined by a first contact hole overlapping a portion of the power line and penetrating the insulating layer therebetween, and a second contact hole overlapping the first contact hole and penetrating the pixel defining film, An electronic device in which an opening overlapping the contact hole is defined in the first insulating pattern and the second insulating pattern in the contact area. In Article 19, The above first bulkhead pattern is arranged in the opening and the contact hole and is an electronic device connected to the power line.

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