Interposer for multi-chip integration and chip integration system

Abstract

An interposer for multi-chip integration and a chip integration system. The interposer comprises a rewiring layer, a substrate provided on one side of the rewiring layer, and through holes penetrating through the rewiring layer and the substrate; the rewiring layer comprises a bonding interface layer, an embedded passive device layer used for manufacturing a passive device, and a signal transmission layer; the signal transmission layer comprises a radio frequency signal layer used for transmitting a radio frequency signal, a clock signal layer used for transmitting a clock signal, a low frequency signal layer used for transmitting a low frequency signal, and a power supply layer for power supply wiring; the radio frequency signal layer is arranged between the bonding interface layer and the embedded passive device layer, the clock signal layer is arranged between the embedded passive device layer and the low frequency signal layer, and the power supply layer is arranged on one side of the low frequency signal layer.

Description

Interposer and chip integration system for multi-chip integration

[0001] Related Applications

[0002] This application claims priority to the Chinese patent application No. 2024111305384, filed on August 16, 2024, entitled “Interposer and chip integration system for multi-chip integration”, the contents of which are incorporated herein by reference in its entirety. TECHNICAL FIELD

[0003] The present application relates to the technical field of integrated circuits, and in particular, to an interposer and chip integration system for multi-chip integration. BACKGROUND

[0004] The chip integration system based on the interposer is a system integration method that uses microelectronic back-end manufacturing processes to integrate different chips of different processes and even different materials and / or different functions on the same packaging system through re-wiring on a substrate.

[0005] In the chip integration system based on the interposer, as the number and types of chips to be integrated increase, the area of the interposer becomes larger and larger, and the types of transmitted signals become more and more complex and diverse.

[0006] SUMMARY

[0007] Based on this, the present application provides an interposer and chip integration system for multi-chip integration.

[0008] In a first aspect, the present application provides an interposer for multi-chip integration, the interposer comprising a re-wiring layer, a substrate disposed on one side of the re-wiring layer, and a via penetrating through the re-wiring layer and the substrate.

[0009] The re-wiring layer comprises a bonding interface layer, an embedded passive device layer for passive device fabrication, and a plurality of signal transmission layers.

[0010] In some embodiments, the plurality of signal transmission layers comprises a power layer for power wiring, and one or more of a radio frequency signal layer for transmitting radio frequency signals, a clock signal layer for transmitting clock signals, and a low frequency signal layer for transmitting low frequency signals. In some embodiments, the plurality of signal transmission layers comprises a radio frequency signal layer for transmitting radio frequency signals, a clock signal layer for transmitting clock signals, a low frequency signal layer for transmitting low frequency signals, and a power layer for power wiring.

[0011] In some embodiments, the radio frequency signal layer is disposed between the bonding interface layer and the embedded passive device layer, the clock signal layer is disposed between the embedded passive device layer and the low frequency signal layer, and the power layer is disposed on one side of the low frequency signal layer.

[0012] In some embodiments, the power supply layer is disposed on a side of the low frequency signal layer distal from the clock signal layer.

[0013] In some embodiments, the bonding interface layer includes a first dielectric layer and a first metal conductor; the first dielectric layer is made of an insulating material with surface dangling bonds and a coefficient of thermal expansion within a preset coefficient of thermal expansion threshold; the first metal conductor is made of a metallic material with a ductility greater than a preset ductility threshold and a coefficient of thermal expansion greater than a coefficient of thermal expansion threshold.

[0014] In some embodiments, the bonding interface layer includes a first dielectric layer and a first metal conductor; the first dielectric layer is made of silicon dioxide SiO2, silicon carbon nitride SiCN, or a combination thereof; the first metal conductor is made of tin, aluminum, copper, gold, or a combination thereof.

[0015] In some embodiments, the radio frequency signal layer includes a second dielectric layer and a second metal conductor; the second dielectric layer is made of a material with a thermal conductivity greater than a preset thermal conductivity threshold and a dielectric constant less than a preset dielectric constant threshold; the second metal conductor is made of a metallic material with an electrical resistance less than a preset electrical resistance threshold and an electrical mobility less than a preset electrical mobility threshold.

[0016] In some embodiments, the radio frequency signal layer includes a second dielectric layer and a second metal conductor; the second dielectric layer is made of aluminum nitride AIN, boron nitride BN, or a combination thereof; the second metal conductor is made of copper, cobalt, ruthenium, nickel, iridium, rhodium, molybdenum, or a combination thereof.

[0017] In some embodiments, the embedded passive device layer includes a third dielectric layer, a third metal conductor, and a passive device; the third dielectric layer is made of at least one of silicon nitride, silicon dioxide, and silicon oxynitride; the third metal conductor is made of at least one of copper, aluminum, tantalum, tantalum nitride, and titanium nitride.

[0018] In some embodiments, the clock signal layer includes a fourth dielectric layer and a fourth metal conductor; the fourth dielectric layer is made of a material with a dielectric constant less than a preset dielectric constant threshold; the fourth metal conductor is made of a material with an electrical resistivity less than a preset electrical resistivity threshold and an electrical migration resistance greater than a preset electrical migration resistance threshold.

[0019] In some embodiments, the clock signal layer includes a fourth dielectric layer and a fourth metal conductor; the fourth dielectric layer is made of an organic silicon, a fluorinated silicon, an organic material polyimide, or a combination thereof; the fourth metal conductor is made of copper, aluminum, ruthenium, cobalt, or a combination thereof.

[0020] In some embodiments, the low-frequency signal layer comprises a fifth dielectric layer and a fifth metal conductor; the material of the fifth dielectric layer is an insulating material, and the material of the fifth metal conductor is a material with an electrical resistivity less than a preset electrical resistivity threshold and an electromigration resistance greater than a preset electromigration resistance threshold.

[0021] In some embodiments, the low-frequency signal layer comprises a fifth dielectric layer and a fifth metal conductor; the material of the fifth metal conductor is copper, aluminum, ruthenium, cobalt, or a combination thereof.

[0022] In some embodiments, the power supply layer comprises a sixth dielectric layer and a sixth metal conductor; the material of the sixth dielectric layer is at least one of an organic dielectric material or an organic dielectric material, and the material of the sixth metal conductor is a material with an electrical resistivity less than a preset electrical resistivity threshold and an electromigration resistance greater than a preset electromigration resistance threshold.

[0023] In some embodiments, the power supply layer comprises a sixth dielectric layer and a sixth metal conductor; the material of the sixth dielectric layer is polyimide, silicon dioxide, or a combination thereof, and the material of the sixth metal conductor is copper, aluminum, ruthenium, cobalt, or a combination thereof.

[0024] In some embodiments, the material of the substrate is at least one of silicon, glass, an organic material, and a ceramic, and the substrate is provided with a second soldering point for soldering with a packaging substrate.

[0025] In some embodiments, the interposer further comprises a test point for monitoring the communication state of the through hole and a first soldering point for soldering with a chip, both of which are arranged on the bonding interface layer, and the material of the first soldering point is at least one of palladium, gold, copper, tin, and aluminum.

[0026] In a second aspect, the present application further provides a chip integration system, which comprises the interposer for multi-chip integration according to any one of the embodiments of the first aspect. BRIEF DESCRIPTION OF DRAWINGS

[0027] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the technical solutions in the related art, the drawings needed to be used in the description of the embodiments of the present application or the related art will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other related drawings can be obtained by those skilled in the art without any creative effort on the basis of these drawings.

[0028] FIG. 1 is a structural schematic diagram of an interposer according to an embodiment of the present application.

[0029] FIG. 2 is a structural schematic diagram of an interposer according to another embodiment of the present application. DETAILED DESCRIPTION

[0030] In order to make the above objectives, features and advantages of the present application more clear and comprehensible, the detailed description of the specific embodiments of the present application is made below with reference to the accompanying drawings. In the following description, a lot of specific details are set forth in order to provide a thorough understanding of the present application. However, the present application can be implemented in many different ways other than those described herein, and one of ordinary skill in the art can make similar improvements without departing from the spirit of the present application, and therefore the present application is not limited to the specific embodiments disclosed below.

[0031] In addition, if there are terms such as "first", "second", these terms are only for the purpose of description, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first", "second" can be explicitly or implicitly included at least one of the features. In the description of the present application, if the term "a plurality of" appears, the meaning of "a plurality of" is at least two, such as two, three, etc., unless otherwise specifically limited.

[0032] It should be noted that if an element is referred to as "fixed to" or "disposed on" another element, it can be directly on the other element or there can be a middle element. If an element is considered to be "connected" to another element, it can be directly connected to the other element or there can be a middle element. If present, the terms "vertical", "horizontal", "upper", "lower", "left", "right", and similar expressions used in the present application are for illustrative purposes only and do not indicate the only implementation.

[0033] In the present application, unless otherwise specified, the term "integration degree" refers to the number of chips integrated in a unit area of the interposer. The higher the number of chips integrated in a unit area of the interposer, the higher the integration degree.

[0034] In the present application, unless otherwise specified, the term "low frequency signal" refers to an electromagnetic frequency signal having a frequency of about less than 10 KHz, for example, including but not limited to an electromagnetic frequency signal having a frequency of 9 KHz, 8 KHz, 7 KHz, 6 KHz, 5 KHz, 4 KHz, 3 KHz, 2 KHz, 1 KHz, or a frequency between any two of the above values. Accordingly, the term "low frequency signal layer" refers to a signal layer capable of receiving or emitting an electromagnetic frequency signal having a frequency of about less than 10 KHz, for example, including but not limited to a signal layer capable of receiving or emitting an electromagnetic frequency signal having a frequency of 9 KHz, 8 KHz, 7 KHz, 6 KHz, 5 KHz, 4 KHz, 3 KHz, 2 KHz, 1 KHz, or a frequency between any two of the above values.

[0035] In the present application, the term "radio frequency signal" refers to an electromagnetic frequency signal having a frequency range between about 300 kHz and about 300 GHz, for example, including but not limited to an electromagnetic frequency signal having a frequency of 300 KHz, 400 KHz, 500 kHz, 100 MHz, 300 MHz, 500 MHz, 700 MHz, 900 MHz, 10 GHz, 100 GHz, 200 GHz, 300 GHz, or a frequency between any two of the aforementioned values. Accordingly, the term "radio frequency signal layer" refers to a signal layer capable of receiving or emitting an electromagnetic frequency signal having a frequency range between about 300 kHz and about 300 GHz, for example, including but not limited to a signal layer capable of receiving or emitting an electromagnetic frequency signal having a frequency of 300 KHz, 400 KHz, 500 kHz, 100 MHz, 300 MHz, 500 MHz, 700 MHz, 900 MHz, 10 GHz, 100 GHz, 200 GHz, 300 GHz, or a frequency between any two of the aforementioned values.

[0036] With the driving of large computing power artificial intelligence, the application requirements of "everything intelligent", "everything interconnected" and multi-modal perception computing have been put on the agenda and become increasingly urgent. Efficient and rapid system integration of chips with different information processing functions to meet the needs of various application scenarios is an important direction of the development of integrated circuits.

[0037] In the field of integrated circuits, traditional system integration is usually implemented by interconnecting different components on a printed circuit board through copper wiring. With the development of technology, the microminiaturization of system integration using printed circuit boards and signal crosstalk and loss caused by long wiring have gradually become the main problems limiting the development of the industry. Single-chip system integration (SoC) is only suitable for preparing all modules using the same silicon-based manufacturing process, and further development of yield, design cost and manufacturing cost and other problems are currently technical bottlenecks that cannot be broken through.

[0038] The chip integration system based on the interposer is a system integration method that uses microelectronic back-end manufacturing processes to integrate chips prepared by different processes and / or different materials and / or different functions on the same packaging system through re-wiring on the substrate.

[0039] In the chip integration system based on the interposer, as the number of integrated chips increases and the types of chips become more complex, the types of signals transmitted within a single integrated body are complex and the signal wiring density is high, resulting in large signal crosstalk and poor signal transmission quality. Therefore, there is an urgent need for an interposer and a chip integration system including the interposer that not only has a high degree of integration of chips, but also can effectively avoid the problem of signal crosstalk and improve signal transmission quality.

[0040] Based on this, referring to FIG. 1, the embodiment of the present application provides an interposer 100, which comprises a rewiring layer 101, a substrate 102 arranged on one side of the rewiring layer 101, and a via 103 penetrating through the rewiring layer 101 and the substrate 102.

[0041] The rewiring layer 101 comprises a bonding interface layer 1011, an embedded passive device layer 1012 for passive device preparation, and a plurality of signal transmission layers 1013.

[0042] The signal transmission layers 1013 can comprise various types of layers suitable for transmitting signals in chip integration related technologies.

[0043] The interposer 100 provided by the present application comprises the embedded passive device layer 1012, so that the passive devices originally arranged on the interposer 100 are arranged in the embedded passive device layer 1012, which not only reduces the number of chips integrated by bonding on the interposer 100, but also reduces the number of input / output ports of the interposer 100, thereby reducing the area of the interposer 100 and effectively improving the integration of the interposer 100.

[0044] In some embodiments, the plurality of signal transmission layers 1013 can be a plurality of layers suitable for transmitting signals in chip integration related technologies. The embedded passive device layer 1012 for passive device preparation can be located above the signal transmission layers 1013, or below the signal transmission layers 1013, or arranged between the plurality of signal transmission layers 1013, i.e. the embedded passive device layer 1012 for passive device preparation can be located between the bonding interface layer 1011 and the signal transmission layers 1013, or on the side of the signal transmission layers 1013 away from the bonding interface layer 1011, or between a plurality of signal transmission layers 1013 of different types.

[0045] In the above embodiment of the plurality of signal transmission layers 1013, the plurality of signal transmission layers 1013 are used to transmit different types of signals respectively, which effectively avoids the problem of mutual crosstalk between different types of signals and improves the quality of signal transmission.

[0046] In some embodiments, the plurality of signal transmission layers 1013 includes a power layer for power wiring, and one or more of a radio frequency signal layer 301 for transmitting radio frequency signals, a clock signal layer 302 for transmitting clock signals, and a low frequency signal layer 303 for transmitting low frequency signals, for example, any one, two or three of the above-mentioned layers. When the signal transmission layer 1013 includes a power layer, and one of the radio frequency signal layer 301, the clock signal layer 302 and the low frequency signal layer 303, the embedded passive device layer 1012 for passive device preparation can be located between the bonding interface layer 1011 and the signal transmission layer 1013, or on the side of the signal transmission layer 1013 away from the bonding interface layer 1011. When the signal transmission layer 1013 includes any two or three of the radio frequency signal layer 301, the clock signal layer 302 and the low frequency signal layer 303, the embedded passive device layer 1012 for passive device preparation can be located between the bonding interface layer 1011 and the signal transmission layer 1013, or on the side of the signal transmission layer 1013 away from the bonding interface layer 1011, or between the signal transmission layers 1013. In some embodiments, the plurality of signal transmission layers 1013 includes the radio frequency signal layer 301 for transmitting radio frequency signals, the clock signal layer 302 for transmitting clock signals, the low frequency signal layer 303 for transmitting low frequency signals, and the power layer 304 for power wiring.

[0047] The radio frequency signal layer 301 is arranged between the bonding interface layer 1011 and the embedded passive device layer 1012, the clock signal layer 302 is arranged between the embedded passive device layer 1012 and the low frequency signal layer 303, and the power layer 304 is arranged on one side of the low frequency signal layer 303, and optionally, on the side of the low frequency signal layer 303 away from the clock signal layer 302.

[0048] The interposer 100 refers to an intermediate layer structure that can be used to assist in realizing communication between chips. The substrate 102 is used to play a supporting role.

[0049] The via 103 is used to communicate between the various layers in the interposer 100 to transmit signals. Optionally, the via 103 can be a through-silicon via. The via 103 is provided in a plurality. The specific number of vias 103 can be set according to actual use requirements.

[0050] The redistribution layer 101 is used to connect and redistribute the input / output interfaces of the chip. The bonding interface layer 1011 is used to bond the chip. The embedded passive device layer 1012 is provided with passive devices prepared by microelectronic process technology.

[0051] Microelectronic process technology includes, but is not limited to, for example, deposition, photolithography, etching. Passive devices refer to electronic components in the circuit that can work when there is a signal without an external power supply. Passive devices include, but are not limited to, for example, resistors, capacitors, inductors.

[0052] The signal transmission layer 1013 is used for transmitting signals. Further, in the signal transmission layer 1013, according to the different transmission signals, the radio frequency signal layer 301, the clock signal layer 302, the low frequency signal layer 303 and the power supply layer 304 are correspondingly provided.

[0053] In some embodiments, in the interposer 100, the bonding interface layer 1011 is located at the uppermost layer, i.e., the first layer; the radio frequency signal layer 301 is located below the bonding interface layer 1011, i.e., the second layer; the embedded passive device layer 1012 is located below the radio frequency signal layer 301, i.e., the third layer; the clock signal layer 302 is located below the radio frequency signal layer 301, and optionally, is located below the embedded passive device layer 1012, i.e., the fourth layer; the low frequency signal layer 303 is located below the clock signal layer 302, i.e., the fifth layer; the power supply layer 304 is located below the low frequency signal layer 303, i.e., the sixth layer; and the substrate 102 is located at the lowermost layer, and the via 103 penetrates through the bonding interface layer 1011, the radio frequency signal layer 301, the embedded passive device layer 1012, the clock signal layer 302, the low frequency signal layer 303, the power supply layer 304, and the substrate 102. The above-mentioned interposer 100 includes a redistribution layer 101, a substrate 102 disposed on one side of the redistribution layer 101, and a via 103 penetrating through the redistribution layer 101 and the substrate 102; the redistribution layer 101 includes a bonding interface layer 1011, an embedded passive device layer 1012 for passive device preparation, and a signal transmission layer 1013; wherein the signal transmission layer 1013 includes a radio frequency signal layer 301 for transmitting radio frequency signals, a clock signal layer 302 for transmitting clock signals, a low frequency signal layer 303 for transmitting low frequency signals, and a power supply layer for power supply wiring, the radio frequency signal layer 301 is disposed between the bonding interface layer 1011 and the embedded passive device layer 1012, the clock signal layer 302 is disposed between the embedded passive device layer 1012 and the low frequency signal layer 303, and the power supply layer is disposed on one side of the low frequency signal layer 303, and optionally, the power supply layer is disposed on the side of the low frequency signal layer 303 away from the clock signal layer 302. The interposer 100 provided by the present application is provided with the embedded passive device layer 1012, which not only can reduce the number of chips integrated by bonding on the interposer 100, but also can reduce the number of input / output ports of the interposer 100, thereby reducing the area of the interposer 100 and effectively improving the integration of the interposer 100; and different signal transmission layers 1013 are provided according to the types of signal transmission, which effectively avoids the mutual crosstalk problem between different types of signals and improves the signal transmission quality. Therefore, the interposer 100 provided by the present application can effectively improve the working efficiency of the interposer 100.

[0054] In some embodiments, as shown in FIG. 2, the bonding interface layer 1011 includes a first dielectric layer and a first metal conductor. The first metal conductor is disposed in the first dielectric layer, and at least part of the first metal conductor is electrically connected to the chip integrated by bonding on the interposer 100, for example, is electrically connected to the chip through the via 103.

[0055] The material of the first dielectric layer is an insulating material that is easy to form surface dangling bonds and has a thermal expansion coefficient within a preset thermal expansion threshold range. The material of the first metal conductor is a metal material that has a ductility greater than a preset ductility threshold and a thermal expansion coefficient greater than a thermal expansion coefficient threshold.

[0056] The thermal expansion coefficient refers to the rate of change of the volume or length of a material when the temperature changes. It is used to reflect the stability of a material in a thermodynamic process. The thermal expansion coefficient mainly includes the linear thermal expansion coefficient and the volume thermal expansion coefficient. The linear thermal expansion coefficient refers to the ratio of the length change to the temperature change when the temperature of a material changes. The volume thermal expansion coefficient is the rate of change of the volume of a material when the temperature changes. The insulating material within the preset thermal expansion threshold range refers to an insulating material whose thermal expansion coefficient differs from that of copper by more than a preset threshold.

[0057] In some embodiments, the material of the first dielectric layer can be silicon dioxide SiO2, silicon carbon nitride SiCN, or a combination thereof. The material of the first metal conductor can be tin, aluminum, copper, gold, or a combination of two or more of the foregoing metals, such as, but not limited to, tin-aluminum alloy, tin-copper alloy, etc.

[0058] In some embodiments, as shown in FIG. 2, the radio frequency signal layer 301 includes a second dielectric layer and a second metal conductor 402. The second metal conductor 402 is disposed in the second dielectric layer, and at least part of the second metal conductor is electrically connected to the bonded integrated chip on the interposer 100, such as the radio frequency signal input / output terminal of the chip.

[0059] The material of the second dielectric layer is a material that has a thermal conductivity higher than a preset thermal conductivity threshold and a dielectric constant less than a preset dielectric constant threshold, and the material of the second metal conductor 402 is a metal material that has a resistance less than a preset resistance threshold and an electromigration rate less than a preset electromigration rate.

[0060] The thermal conductivity, i.e., the heat conductivity or the heat conduction coefficient, is used to characterize the ability of a material to conduct heat. The dielectric constant, i.e., the permittivity or the dielectric coefficient, is used to characterize the reaction of a material to an electric field. The preset thermal conductivity threshold and the preset dielectric constant threshold can be preset by a technician according to actual needs.

[0061] In some embodiments, the material of the second dielectric layer can be aluminum nitride (AIN), boron nitride (BN), or a combination thereof. The material of the second metal conductor 402 can be copper, cobalt, ruthenium, nickel, iridium, rhodium, molybdenum, or a combination of two or more of the foregoing metals. In some embodiments, as shown in FIG. 2, the embedded passive device layer 1012 includes a third dielectric layer, a third metal conductor, and a passive device prepared by microelectronic technology. The third metal conductor and the passive device are disposed in the third dielectric layer, and at least part of the third metal conductor is electrically connected to the bonded integrated chip on the interposer 100 and / or the passive device in the third dielectric layer.

[0062] wherein the material of the third dielectric layer is at least one of silicon nitride, silicon dioxide, and silicon oxynitride, and the material of the third metal conductor is at least one of copper, aluminum, tantalum, tantalum nitride, and titanium nitride.

[0063] R in FIG. 2 is a resistance in a passive device, C is a capacitance in a passive device, and L is an inductance in a passive device.

[0064] The passive devices such as resistors, capacitors, and inductors are disposed in the embedded passive device layer 1012, for example, the embedded passive device layer 1012 containing resistors, capacitors, and inductors is disposed between two redistribution layers 101, which improves the integration level, reduces the number of input / output (I / O) ports of the interposer 100, and reduces the area of the interposer 100.

[0065] In some embodiments, as shown in FIG. 2, the clock signal layer 302 includes a fourth dielectric layer and a fourth metal conductor 403. The fourth metal conductor 403 is disposed in the fourth dielectric layer, and at least part of the fourth metal conductor 403 is electrically connected to the bonded integrated chip on the interposer 100, for example, to the clock signal input / output terminal of the chip.

[0066] wherein the material of the fourth dielectric layer is a material with a dielectric constant less than a preset dielectric constant threshold. The material of the fourth metal conductor 403 is a material with a resistivity less than a preset resistivity threshold and an electromigration resistance greater than a preset electromigration resistance threshold.

[0067] The electromigration resistance refers to the ability of a material to resist the migration of metal ions and the destruction of the material structure under the action of long-term current.

[0068] The preset dielectric constant threshold, the preset resistivity threshold, and the preset electromigration resistance threshold can be preset by the skilled person according to actual needs.

[0069] Optionally, in some embodiments, the material of the fourth dielectric layer can be silicone, fluorinated silicon, organic material polyimide, or a combination thereof. The material of the fourth metal conductor 403 can be copper, aluminum, ruthenium, cobalt, or a combination of two or more of the foregoing metals. In some embodiments, as shown in FIG. 2, the low-frequency signal layer 303 includes a fifth dielectric layer and a fifth metal conductor 404. The fifth metal conductor 404 is disposed in the fifth dielectric layer, and at least a portion of the fifth metal conductor 404 is electrically connected to the bonded integrated chip on the interposer 100, for example, to the low-frequency signal input / output terminal of the chip.

[0070] The material of the fifth dielectric layer is an insulating material. The material of the fifth metal conductor 404 is a material with an electrical resistivity less than a preset electrical resistivity threshold and an electromigration resistance greater than a preset electromigration resistance threshold.

[0071] Optionally, in some embodiments, the material of the fifth metal conductor 404 can be copper, aluminum, ruthenium, cobalt, or a combination of two or more of the foregoing metals.

[0072] In some embodiments, as shown in FIG. 2, the power supply layer 304 includes a sixth dielectric layer and a sixth metal conductor 405. The sixth metal conductor 405 is disposed in the sixth dielectric layer, and at least a portion of the sixth metal conductor 405 is electrically connected to the bonded integrated chip on the interposer 100, for example, to the power input terminal of the chip.

[0073] The material of the sixth dielectric layer is at least one of an organic dielectric material or an inorganic dielectric material. The material of the sixth metal conductor 405 is a material with an electrical resistivity less than a preset electrical resistivity threshold and an electromigration resistance greater than a preset electromigration resistance threshold.

[0074] Optionally, in some embodiments, the material of the sixth dielectric layer can be polyimide, silicon dioxide, or a combination thereof. The material of the sixth metal conductor 405 can be copper, aluminum, ruthenium, cobalt, or a combination of two or more of the foregoing metals.

[0075] In some embodiments, as shown in FIG. 2, the substrate 102 is provided with a second soldering point A1 for soldering with a packaging substrate.

[0076] The material of the substrate 102 is at least one of silicon, glass, an organic material, and a ceramic.

[0077] For example, the material of the substrate 102 can be determined according to the use scenario and specific requirements.

[0078] In some embodiments, as shown in FIG. 2, the interposer 100 further includes a test point A2 for monitoring the communication state of the via 103 and a first soldering point A3 for soldering connection with the chip.

[0079] The test point A2 and the first solder point A3 are arranged on the bonding interface layer 1011, and the material of the first solder point A3 is at least one of palladium, gold, copper, tin and aluminum. For example, the material of the A3 solder point can be copper, and can also be a copper-tin alloy.

[0080] In some optional embodiments of the present application, a shielding layer (not shown in the figure) can be arranged between each signal transmission layer 1013 to further resist the interference between different signals. The shielding layer can be a grounded metal conductor.

[0081] In some optional embodiments of the present application, a shielding layer (not shown in the figure) is arranged between at least two adjacent layers of the radio frequency signal layer 301 for transmitting radio frequency signals, the clock signal layer 302 for transmitting clock signals, the low frequency signal layer 303 for transmitting low frequency signals 303 and the power layer 304 for power wiring to further resist the interference between different signals of adjacent layers. The arrangement position and the number of the shielding layer are not particularly required, and can be determined according to the actual application requirements.

[0082] In some optional embodiments of the present application, for the first signal transmission layer with high interference resistance requirement in the signal transmission layer 1013, a shielding unit is arranged in the first signal transmission layer; and for the second signal transmission layer with high heat generation, a heat dissipation unit is arranged in the second signal transmission layer.

[0083] In some embodiments, the present application also provides a chip integration system, which comprises the interposer 100 described in any of the above embodiments. The chip integration system refers to a system that can integrate multiple electronic systems into a single chip.

[0084] In some embodiments, the interposer 100 includes a redistribution layer 101, a substrate 102 disposed on one side of the redistribution layer 101, and a via 103 penetrating through the redistribution layer 101 and the substrate 102; the redistribution layer 101 includes a bonding interface layer 1011, an embedded passive device layer 1012 for passive device preparation, and a signal transmission layer 1013; wherein the signal transmission layer 1013 includes a radio frequency signal layer 301 for transmitting radio frequency signals, a clock signal layer 302 for transmitting clock signals, a low frequency signal layer 303 for transmitting low frequency signals, and a power layer 304 for power wiring, the radio frequency signal layer 301 is disposed between the bonding interface layer 1011 and the embedded passive device layer 1012, the clock signal layer 302 is disposed between the embedded passive device layer 1012 and the low frequency signal layer 303, and the power layer 304 is disposed on the side of the low frequency signal layer 303 away from the clock signal layer 302. The bonding interface layer 1011 includes a first dielectric layer; the material of the first dielectric layer is an insulating material that is easy to form surface dangling bonds and has a coefficient of thermal expansion within a preset thermal expansion threshold range. The radio frequency signal layer 301 includes a second dielectric layer and a second metal conductor 402; the material of the second dielectric layer is a material with a thermal conductivity higher than a preset thermal conductivity threshold and a dielectric constant less than a preset dielectric constant threshold, and the material of the second metal conductor 402 is copper. The embedded passive device layer 1012 includes a third dielectric layer, a third metal conductor, and a passive device prepared by microelectronic technology; the material of the third dielectric layer is at least one of silicon nitride, silicon dioxide, and silicon oxynitride, and the material of the third metal conductor is at least one of copper, aluminum, tantalum, tantalum, tantalum nitride, and titanium nitride. The clock signal layer 302 includes a fourth dielectric layer and a fourth metal conductor 403; the material of the fourth dielectric layer is a material with a dielectric constant less than a preset dielectric constant threshold, and the material of the fourth metal conductor 403 is a material with a resistivity less than a preset resistivity threshold and an electromigration resistance greater than a preset electromigration resistance threshold. The low frequency signal layer 303 includes a fifth dielectric layer and a fifth metal conductor 404; the material of the fifth dielectric layer is an insulating material, and the material of the fifth metal conductor 404 is a material with a resistivity less than a preset resistivity threshold and an electromigration resistance greater than a preset electromigration resistance threshold. The power layer 304 includes a sixth dielectric layer and a sixth metal conductor 405; the material of the sixth dielectric layer is at least one of an organic dielectric material or an inorganic dielectric material, and the material of the sixth metal conductor 405 is a material with a resistivity less than a preset resistivity threshold and an electromigration resistance greater than a preset electromigration resistance threshold. The material of the substrate 102 is determined according to the application scenario of the interposer 100, and the substrate 102 is provided with a second solder joint for welding with a packaging substrate.The interposer 100 further comprises a test point for monitoring the communication state of the through hole 103 and a first soldering point for soldering connection with a chip, both of which are arranged on the bonding interface layer 1011, and the material of the first soldering point is at least one of copper, tin and aluminum.

[0085] The technical features of the above embodiments can be combined in any manner, and for the sake of brevity, not all possible combinations of the technical features in the above embodiments are described, however, as long as the combinations of the technical features do not contradict each other, they should be considered within the scope of the present application.

[0086] The above embodiments only express several implementation manners of the present application, and the description is relatively specific and detailed, but it should not be understood as a limitation on the patent scope of the present application. It should be pointed out that for ordinary skilled persons in the art, several modifications and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the appended claims.

Claims

1. An interposer for multi-chip integration, the interposer comprising: The interposer comprises a redistribution layer, a substrate arranged on one side of the redistribution layer, and a via hole penetrating through the redistribution layer and the substrate, The redistribution layer comprises a bonding interface layer, an embedded passive device layer for passive device preparation, and a plurality of signal transmission layers.

2. The interposer of claim 1, wherein, The plurality of signal transmission layers comprises a power supply layer for power supply wiring, and one or more of a radio frequency signal layer for transmitting radio frequency signals, a clock signal layer for transmitting clock signals, and a low frequency signal layer for transmitting low frequency signals.

3. The interposer according to claim 1 or 2, characterized in that, The plurality of signal transmission layers comprises a radio frequency signal layer for transmitting radio frequency signals, a clock signal layer for transmitting clock signals, a low frequency signal layer for transmitting low frequency signals, and a power supply layer for power supply wiring.

4. The interposer of claim 3, wherein, The radio frequency signal layer is arranged between the bonding interface layer and the embedded passive device layer, the clock signal layer is arranged between the embedded passive device layer and the low frequency signal layer, and the power supply layer is arranged on one side of the low frequency signal layer.

5. The interposer according to claim 3 or 4, characterized in that, The power supply layer is arranged on the side of the low frequency signal layer away from the clock signal layer.

6. The interposer of any one of claims 1 to 5, wherein, The bonding interface layer comprises a first dielectric layer and a first metal conductor; The material of the first dielectric layer is an insulating material that is easy to form a surface dangling bond and has a thermal expansion coefficient within a preset thermal expansion threshold range, and the material of the first metal conductor is a metal material with a ductility greater than a preset ductility threshold and a thermal expansion coefficient greater than a thermal expansion coefficient threshold.

7. The interposer of any one of claims 1 to 5, wherein, The bonding interface layer comprises a first dielectric layer and a first metal conductor; The material of the first dielectric layer is silicon dioxide SiO2, silicon carbon nitride SiCN, or a combination thereof, and the material of the first metal conductor is tin, aluminum, copper, gold, or a combination thereof.

8. The interposer of any one of claims 2-7, wherein, The radio frequency signal layer comprises a second dielectric layer and a second metal conductor; The material of the second dielectric layer is a material with a thermal conductivity higher than a preset thermal conductivity threshold and a dielectric constant less than a preset dielectric constant threshold, and the material of the second metal conductor is a metal material with a resistance less than a preset resistance threshold and an electrical mobility less than a preset electrical mobility.

9. The interposer of any one of claims 2-7, wherein, The radio frequency signal layer comprises a second dielectric layer and a second metal conductor; The material of the second dielectric layer is aluminum nitride AIN, boron nitride BN, or a combination thereof, and the material of the second metal conductor is copper, cobalt, ruthenium, nickel, iridium, rhodium, molybdenum, or a combination thereof.

10. The interposer of any one of claims 1 to 9, wherein, The embedded passive device layer comprises a third dielectric layer, a third metal conductor, and a passive device; The material of the third dielectric layer is at least one of silicon nitride, silicon dioxide, and silicon oxynitride, and the material of the third metal conductor is at least one of copper, aluminum, tantalum, tantalum nitride, and titanium nitride.

11. The interposer of any one of claims 2-10, wherein, The clock signal layer comprises a fourth dielectric layer and a fourth metal conductor; The material of the fourth dielectric layer is a material with a dielectric constant less than a preset dielectric constant threshold, and the material of the fourth metal conductor is a material with a resistivity less than a preset resistivity threshold and an anti-electromigration property greater than a preset anti-electromigration threshold.

12. The interposer of any one of claims 2-10, wherein, The clock signal layer comprises a fourth dielectric layer and a fourth metal conductor; The material of the fourth dielectric layer can be silicone, fluorinated silicon, organic material polyimide, or a combination thereof, and the material of the fourth metal conductor is copper, aluminum, ruthenium, cobalt, or a combination thereof.

13. The interposer of any one of claims 2-12, wherein, The low-frequency signal layer comprises a fifth dielectric layer and a fifth metal conductor. The material of the fifth dielectric layer is an insulating material, and the material of the fifth metal conductor is a material with a resistivity less than a preset resistivity threshold and an electromigration resistance greater than a preset electromigration resistance threshold.

14. The interposer of any one of claims 2-12, wherein, The low-frequency signal layer comprises a fifth dielectric layer and a fifth metal conductor; and the material of the fifth metal conductor is copper, aluminum, ruthenium, cobalt, or a combination thereof.

15. The interposer of any one of claims 1 to 14, wherein, The power supply layer comprises a sixth dielectric layer and a sixth metal conductor. The material of the sixth dielectric layer is at least one of an organic dielectric material or an inorganic dielectric material, and the material of the sixth metal conductor is a material with a resistivity less than a preset resistivity threshold and an electromigration resistance greater than a preset electromigration resistance threshold.

16. The interposer of any one of claims 1 to 14, wherein, The power supply layer comprises a sixth dielectric layer and a sixth metal conductor. The material of the sixth dielectric layer is polyimide, silicon dioxide, or a combination thereof, and the material of the sixth metal conductor is copper, aluminum, ruthenium, cobalt, or a combination thereof.

17. The interposer of any one of claims 1 to 16, wherein, The material of the substrate is at least one of silicon, glass, an organic material, and a ceramic, and the substrate is provided with a second soldering point for soldering with a packaging substrate.

18. The interposer of any one of claims 1-17, wherein, The interposer further comprises: a test point for monitoring the communication state of the through hole and a first soldering point for soldering connection with a chip, both of which are arranged on the bonding interface layer, and the material of the first soldering point is at least one of palladium, gold, copper, tin, and aluminum.

19. A chip integration system, characterized by The chip integrated system comprises the interposer for multi-chip integration according to any one of claims 1 to 18.

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