Semiconductor device, manufacturing method, power module, conversion circuit, and vehicle

Abstract

A semiconductor device, a manufacturing method, a power module, a conversion circuit, and a vehicle. The semiconductor device comprises: a substrate (10), comprising a first region (Q1) extending in a first direction and second regions (Q2) located on two opposite sides of the first region (Q1); a semiconductor epitaxial layer (20), wherein the semiconductor epitaxial layer (20) located in the second regions (Q2) comprises a drift region (21), body regions (22), and first doping type contact regions (23) that are sequentially away from the substrate (10), and the semiconductor epitaxial layer (20) located in the first region (Q1) comprises a drift region (21) and second doping type contact regions (24) that are sequentially away from the substrate (10); gate trenches (01), located on the surface of the side of the semiconductor epitaxial layer (20) distant from the substrate (10) and extending in a second direction, trench gate structures (50) being located in the gate trenches (01); shielding layers (30), located at the bottoms of the trench gate structures (50); connecting pillars (40), located on at least one side of the trench gate structures (50) and configured to connect the shielding layers (30) and the second doping type contact regions (24); and a first electrode (70), being in contact with the first doping type contact regions (23) and the second doping type contact regions (24).

Description

Semiconductor device, manufacturing method, power module, conversion circuit and vehicle

[0001] The present application claims priority to the Chinese patent application No. 202411122088.4, filed on August 15, 2024, to the Chinese Patent Office, the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] Embodiments of the present application relate to the field of semiconductor technology, for example, to a semiconductor device, a manufacturing method, a power module, a conversion circuit and a vehicle. BACKGROUND

[0003] SiC Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) has undergone a process from planar to trench, by improving the gate structure, the current flow on the gate changes from planar to vertical direction, compared with the planar semiconductor device, the trench semiconductor device has the advantages of small cell size and large current density.

[0004] FIG. 1 is a structural schematic diagram of a trench-type semiconductor device provided in the related art, referring to FIG. 1, the current trench-type semiconductor device includes a substrate 1 and a semiconductor epitaxial layer 2 with SiC material located on one side of the substrate 1, the semiconductor epitaxial layer 2 includes N-drift region, P-body and contact region in sequence away from the substrate 1; wherein the P+ contact region is implanted in the interval of the N+ contact region, and the N+ contact region and the P+ contact region are connected to the source at the same time; however, due to the layout of the N+ contact region, the P+ contact region, and the N+ contact region interval adjacent to each other, the gate G spacing is large, which causes the size of the unit cell to be still large, and the area use efficiency is low, resulting in high cost and on-resistance of the semiconductor device; in addition, in the trench-type semiconductor device, the high electric field at the bottom of the gate trench and the slot angle can increase the electric field on the gate insulating layer, thereby causing the gate insulating layer to be easily broken down; in the related art, a P+ region can be formed at the bottom of the gate trench as an electric field shielding structure by ion implantation, but the gate bottom P+ region can easily cause the shielding effect to decrease and fail due to accumulated charge. SUMMARY

[0005] Embodiments of the present application provide a semiconductor device, a manufacturing method, a power module, a conversion circuit and a vehicle to reduce the on-resistance and volume of the semiconductor device while improving the breakdown voltage of the device.

[0006] According to an aspect of the present application, a semiconductor device is provided, comprising:

[0007] a substrate;

[0008] a semiconductor epitaxial layer on one side of the substrate; wherein the substrate comprises a first region extending along a first direction and second regions on opposite sides of the first region; the semiconductor epitaxial layer on the second regions comprises, in order away from the substrate, a drift region, a body region, and a first-doped-type contact region; the semiconductor epitaxial layer on the first region comprises, in order away from the substrate, a drift region and a second-doped-type contact region;

[0009] a gate trench on a surface of the semiconductor epitaxial layer away from the substrate and extending along a second direction; and a trench gate structure in the gate trench; the second direction intersects the first direction;

[0010] a shielding layer in the semiconductor epitaxial layer and at a bottom of the trench gate structure;

[0011] a connecting column in the semiconductor epitaxial layer and on at least one side of the trench gate structure, the connecting column configured to connect the shielding layer and the second-doped-type contact region;

[0012] a first electrode on a surface of the semiconductor epitaxial layer away from the substrate and in contact with the first-doped-type contact region and the second-doped-type contact region;

[0013] a second electrode on a side of the substrate away from the semiconductor epitaxial layer.

[0014] Optionally, the shielding layer extends along the second direction; in a plane perpendicular to the second direction, the shielding layer has a concave shape.

[0015] wherein the shielding layer comprises a first sidewall, a second sidewall, and a bottom layer between the first sidewall and the second sidewall; the bottom layer is between the bottom of the trench gate structure and the substrate; the first sidewall and the second sidewall are on opposite sides of the bottom of the trench gate structure, respectively.

[0016] According to another aspect of the present application, a method for manufacturing a semiconductor device is provided, which is used to manufacture the semiconductor device of any of the embodiments of the present application, comprising:

[0017] providing a substrate; the substrate comprises a first region extending along a first direction and second regions on opposite sides of the first region;

[0018] forming a semiconductor epitaxial layer on one side of the substrate;

[0019] forming a drift region, a body region and a first doped type contact region in the semiconductor epitaxial layer in the second region in sequence away from the substrate, forming a drift region and a second doped type contact region in the semiconductor epitaxial layer in the first region in sequence away from the substrate, and forming a connecting column extending along a second direction in the drift region;

[0020] forming a gate trench extending along the second direction on a side surface of the semiconductor epitaxial layer away from the substrate;

[0021] forming a shielding layer by ion implantation at the bottom of the gate trench;

[0022] forming a trench gate structure in the gate trench; wherein the connecting column is located at at least one side of the trench gate structure, and the connecting column is configured to connect the shielding layer and the second doped type contact region;

[0023] forming a first electrode on a side of the semiconductor epitaxial layer away from the substrate, and forming a second electrode on a side of the substrate away from the semiconductor epitaxial layer; wherein the first electrode is in contact with the first doped type contact region and the second doped type contact region.

[0024] According to another aspect of the present application, there is provided a power module comprising a substrate and at least one semiconductor device as described in any of the embodiments of the present application, the substrate being configured to carry the double-gate semiconductor device.

[0025] According to another aspect of the present application, there is provided a power conversion circuit for one or more of current conversion, voltage conversion, and power factor correction.

[0026] The power conversion circuit comprises a circuit board and at least one semiconductor device as described in any of the embodiments of the present application, the semiconductor device being electrically connected to the circuit board.

[0027] According to another aspect of the present application, there is provided a vehicle comprising a load and a power conversion circuit as described in any of the embodiments of the present application, the power conversion circuit being configured to convert alternating current into direct current, convert alternating current into alternating current, convert direct current into direct current, or convert direct current into alternating current before inputting to the load. BRIEF DESCRIPTION OF DRAWINGS

[0028] FIG. 1 is a structural schematic diagram of a trench-type semiconductor device provided in the related art;

[0029] FIG. 2 is a perspective view of a semiconductor device provided in an embodiment of the present application;

[0030] FIG. 3 is a cross-sectional structural schematic diagram of FIG. 2 along the cross-sectional line AA1.

[0031] Fig. 4 is a schematic view of a cross-sectional structure of Fig. 2 along section line BB1 ;

[0032] Fig. 5 is a top view of a substrate according to an embodiment of the present application;

[0033] Fig. 6 is a schematic view of another cross-sectional structure of Fig. 2 along section line BB1 ;

[0034] Fig. 7 is a perspective view of another semiconductor device according to an embodiment of the present application;

[0035] Fig. 8 is a schematic view of a cross-sectional structure of Fig. 7 along section line CC1 ;

[0036] Fig. 9 is a schematic view of another cross-sectional structure of Fig. 7 along section line CC1 ;

[0037] Fig. 10 is a schematic view of another cross-sectional structure of a semiconductor device in a second region according to an embodiment of the present application;

[0038] Fig. 11 is a schematic view of another cross-sectional structure of a semiconductor device in a second region according to an embodiment of the present application;

[0039] Fig. 12 is a schematic view of a structure corresponding to step S110 in a method for manufacturing a semiconductor device according to an embodiment of the present application;

[0040] Fig. 13 is a schematic view of a structure corresponding to step S120 in a method for manufacturing a semiconductor device according to an embodiment of the present application;

[0041] Figs. 14-15 are schematic views of a structure corresponding to step S130 in a method for manufacturing a semiconductor device according to an embodiment of the present application;

[0042] Figs. 16-17 are schematic views of a structure corresponding to step S140 in a method for manufacturing a semiconductor device according to an embodiment of the present application;

[0043] Figs. 18-19 are schematic views of a structure corresponding to step S150 in a method for manufacturing a semiconductor device according to an embodiment of the present application;

[0044] Fig. 20 is a top view of a semiconductor epitaxial layer according to an embodiment of the present application;

[0045] Fig. 21 is a top view of another semiconductor epitaxial layer according to an embodiment of the present application.

[0046] In the figure, 1, substrate; 2, semiconductor epitaxial layer; 01, gate trench; 10, substrate; 20, semiconductor epitaxial layer; 21, drift region; 22, body region; 23, first doped type contact region; 24, second doped type contact region; 30, shielding layer; 31, bottom layer; 32, first sidewall; 33, second sidewall; 40, connecting column; 50, trench gate structure; 51, polysilicon gate; 52, gate insulating layer; 70, first electrode; 90, passivation layer; Q1, first region; Q2, second region. DETAILED DESCRIPTION

[0047] The scheme in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. The described embodiments are partial or complete embodiments of the present application. All other embodiments obtained by those skilled in the art without creative labor based on the embodiments in the present application shall fall within the scope of protection of the present application.

[0048] The terms "first", "second", and the like in the specification and claims of the present application and the above-described drawings are used to distinguish similar objects, and do not necessarily have to be used to describe a specific order or sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product, or device including a series of steps or units can include other steps or units not clearly listed or inherent to the process, method, product, or device.

[0049] The embodiments of the present application provide a semiconductor device, Fig. 2 is a perspective view of a semiconductor device provided by the embodiments of the present application, Fig. 3 is a cross-sectional structure schematic diagram of Fig. 2 along the cross-sectional line AA1 (the first electrode 70 and the passivation layer 90 are not drawn in Fig. 3), Fig. 4 is a cross-sectional structure schematic diagram of Fig. 2 along the cross-sectional line BB1, wherein the left area in Fig. 2 exemplarily shows the external structure of the semiconductor device, and the right area in Fig. 2 exemplarily shows the internal structure of the semiconductor device; referring to Figs. 2-4, the semiconductor device comprises:

[0050] a substrate 10;

[0051] a semiconductor epitaxial layer 20 located on one side of the substrate 10; wherein the substrate 10 comprises a first region Q1 extending along a first direction X and a second region Q2 located on opposite sides of the first region Q1; the semiconductor epitaxial layer 20 located in the second region Q2 comprises a drift region 21, a body region 22, and a first doped type contact region 23 in turn away from the substrate 10; the semiconductor epitaxial layer 20 located in the first region Q1 comprises a drift region 21 and a second doped type contact region 24 in turn away from the substrate 10;

[0052] gate trenches and trench gate structures 50; the gate trenches are located on a surface of the semiconductor epitaxial layer 20 away from the substrate 10 and extend along a second direction Y; the trench gate structures 50 are located in the gate trenches; the second direction Y is perpendicular to the first direction X;

[0053] a shielding layer 30 located in the semiconductor epitaxial layer 20 and at the bottom of the trench gate structure 50;

[0054] a connecting column 40 located in the semiconductor epitaxial layer 20 and at least one side of the trench gate structure 50, the connecting column 40 being configured to communicate the shielding layer 30 and the second-doped-type contact region 24;

[0055] a first electrode 70 located on a surface of the semiconductor epitaxial layer 20 away from the substrate 10 and in contact with the first-doped-type contact region 23 and the second-doped-type contact region 24;

[0056] a second electrode located on a surface of the substrate 10 away from the semiconductor epitaxial layer 20.

[0057] Optionally, the material of the substrate 10 can be the same as or different from the material of the semiconductor epitaxial layer 20. In the embodiments of the present application, the material of the substrate 10 is the same as the material of the semiconductor epitaxial layer 20, and both can be SiC. That is, the trench-type power device in the embodiments of the present application can be a trench-type SiC power device. SiC has excellent physical and electrical properties. Compared with silicon material, SiC material has a large band gap, high breakdown field, high thermal conductivity, high electron saturation velocity, strong radiation resistance, and other advantages, so the semiconductor device prepared by using SiC material can not only operate stably at a higher temperature, but also is suitable for high-voltage and high-frequency scenarios. In some embodiments of the present application, the substrate 10 and the semiconductor epitaxial layer 20 can be integrally arranged. The substrate 10 and the semiconductor epitaxial layer 20 integrally arranged can be understood as that the substrate 10 and the semiconductor epitaxial layer 20 are a whole piece of SiC film layer structure formed in the same preparation process. After the front process is performed on the whole piece of SiC film layer structure, the back of the SiC film layer structure is thinned, and the back of the SiC film layer structure is heavily doped with ions to form the substrate 10.

[0058] The surface of the semiconductor epitaxial layer 20 away from the substrate 10 includes at least one gate trench. The gate trench extends along a second direction Y, which is perpendicular to the first direction X. A third direction Z is perpendicular to both the second direction Y and the first direction X. The gate trench can be etched from the surface of the semiconductor epitaxial layer 20 away from the substrate 10 to the contact region, the body region 22, and part of the thickness of the drift region 21 in sequence. FIG. 5 is a top view of a substrate according to an embodiment of the present application. Referring to FIG. 5, the substrate 10 includes a first region Q1 extending along the first direction X and a second region Q2 located on opposite sides of the first region Q1 in the second direction Y. The thickness of the drift region 21 located in the second region Q2 can be the same as the thickness of the drift region 21 located in the first region Q1. The sum of the thicknesses of the body region 22 and the first-doped-type contact region 23 located in the second region Q2 can be the same as the thickness of the second-doped-type contact region 24 located in the second region Q2, so as to ensure that the second-doped-type contact region 24 is in contact with at least part of the thickness of the body region 22. A trench gate structure 50 is arranged in the gate trench. The trench gate structure 50 includes a polysilicon gate 51 and a gate insulating layer 52 between the polysilicon gate 51 and the gate trench. The material of the gate insulating layer 52 can include at least one of aluminum oxide and silicon oxide.

[0059] The semiconductor epitaxial layer 20 further includes a shielding layer 30 and a connecting column 40, which can be formed by implanting doped ions of the second doping type into the semiconductor epitaxial layer 20. The connecting column 40 is located on at least one side of the trench gate structure 50 and extends along the direction in which the trench gate structure 50 extends. During the extension, the top of the connecting column 40 is in contact with the second-doped-type contact region 24, so as to realize electrical connection with the second-doped-type contact region 24. The shielding layer 30 is located at the bottom of the trench gate structure 50 and is in contact with the adjacent connecting column 40, so as to realize electrical connection between the shielding layer 30 and the second-doped-type contact region 24 through the connecting column 40. The second-doped-type contact region 24 is in contact with a first electrode 70, so as to realize electrical connection between the shielding layer 30 and the first electrode 70. This prevents the shielding layer 30 at the bottom of the gate from having a decline in shielding effect and failure due to accumulated charges, and ensures the breakdown voltage of the device. Moreover, the connecting column 40 can generate a lateral electric field similar to a super-junction when the device is turned off, which protects the vulnerable points on both sides of the gate bottom of the device and also improves the breakdown voltage of the device. The materials of the first electrode 70 and the second electrode can both include metal materials. The first electrode 70 can be a drain electrode, and the second electrode can be a source electrode. Alternatively, the first electrode 70 can be a source electrode, and the second electrode can be a drain electrode. In the embodiment of the present application, the first electrode 70 is a source electrode, and the second electrode is a drain electrode.

[0060] In addition, compared with FIG. 3, FIG. 4 and FIG. 1, the embodiment of the present application arranges the first-doped-type contact region 23 and the second-doped-type contact region 24 in sequence in the direction (the second direction Y) in which the trench gate structure 50 extends, so that the contact region between two adjacent trench gate structures 50 is only the first-doped-type contact region 23 or only the second-doped-type contact region 24; instead of arranging the first-doped-type contact region (N+ contact region) and the second-doped-type contact region (P+ contact region) in sequence in the direction (the first direction X) in which the trench gate structure (gate G) is arranged in the related art. Compared with the way of arranging the first-doped-type contact region and the second-doped-type contact region in sequence between two adjacent trench gate structures in the related art, the embodiment of the present application can reduce the gate pitch between two adjacent trench gate structures, so as to reduce the volume of the unit cell, improve the device area utilization efficiency and reduce the on-resistance.

[0061] The semiconductor device is described as follows in combination with the accompanying drawings.

[0062] Referring to FIG. 2-5, optionally, the shielding layer 30, the connecting column 40 and the body region 22 are all doped with ions of the second-doped-type, and the doping concentration of the shielding layer 30 and the doping concentration of the connecting column 40 are both greater than the doping concentration of the body region 22; the drift region 21 is doped with ions of the first-doped-type.

[0063] Optionally, the doping type of the shielding layer 30, the doping type of the connecting column 40 and the doping type of the body region 22 are all the same as the doping type of the second-doped-type contact region 24. The doping type of the substrate 10 and the doping type of the drift region 21 are all the same as the doping type of the first-doped-type contact region 23. The doping type of the first-doped-type contact region 23 can be N type, and the doping type of the second-doped-type contact region 24 can be P type. Alternatively, the doping type of the first-doped-type contact region 23 can be P type, and the doping type of the second-doped-type contact region 24 can be N type. In FIG. 4, the first-doped-type contact region 23 and the drift region 21 are doped with N type doping ions by way of example; the second-doped-type contact region 24, the body region 22, the shielding layer 30 and the connecting column 40 are doped with P type doping ions. P+ and N+ in the drawings represent that the ion doping concentration of the region is high, and P- and N- represent that the ion doping concentration of the region is low. The N type doping ions can be phosphorus (P) ions or nitrogen (N) ions, and the P type doping ions can be aluminum (Al) ions or boron (B) ions.

[0064] Please continue to refer to FIG. 2-5, optionally, the shielding layer 30 extends along the second direction Y; in the plane perpendicular to the second direction Y, the shielding layer 30 is in the shape of a concave character.

[0065] Optionally, the shielding layer 30 extends along the extending direction of the trench gate structure 50, so that the entire bottom of the trench gate structure 50 is protected by the shielding layer 30. The shielding layer 30 includes a first sidewall 32, a second sidewall 33, and a bottom layer 31 between the first sidewall 32 and the second sidewall 33; the bottom layer 31 is located between the bottom of the trench gate structure 50 and the substrate 10; the first sidewall 32 and the second sidewall 33 are located on opposite sides of the bottom of the trench gate structure 50, respectively. In a plane perpendicular to the second direction Y, the shielding layer 30 is in a concave shape, forming a hat-shaped shielding layer, which can effectively improve the protection of the shielding layer 30 on the bottom surface and the bottom corner of the trench gate structure 50, reduce the risk of breakdown of the bottom surface and the bottom corner of the trench gate structure 50 by the electric field, and thus improve the breakdown voltage of the semiconductor device.

[0066] Please continue to refer to FIGS. 2 and 3. Optionally, in the second region Q2, the distance between the top of the first sidewall 32 and the body region 22 is greater than zero, and the distance between the top of the second sidewall 33 and the body region 22 is greater than zero; that is, there is a gap between the shielding layer 30 in the second region Q2 and the body region 22, so as to ensure that the electrons flowing from the second electrode can flow into the body region 22 from the drift region 21 at the gap.

[0067] Please refer to FIGS. 4 and 6, and in combination with FIG. 2. In the first region Q1, the distance between the top of the first sidewall 32 and the second-doped-type contact region 24 is greater than or equal to zero; and the distance between the top of the second sidewall 33 and the second-doped-type contact region 24 is greater than or equal to zero. That is, the shielding layer 30 in the first region Q1 can be in contact with the second-doped-type contact region 24 (as shown in FIG. 4) or not in contact with the second-doped-type contact region 24 (as shown in FIG. 6). When the shielding layer 30 is in contact with the second-doped-type contact region 24, the shielding layer 30 can be directly in communication with the second-doped-type contact region 24, thereby realizing conduction with the first electrode 70.

[0068] Please continue to refer to FIGS. 2-6. Optionally, the connecting column 40 extends along the second direction Y;

[0069] The connecting column 40 in the second region Q2 is in a columnar shape in a plane perpendicular to the second direction Y, the top of which is in contact with the body region 22, and the bottom of which is spaced apart from the shielding layer 30 in the first direction X (please refer to FIGS. 2 and 3);

[0070] The connecting column 40 in the first region Q1 is in an inverted T shape in a plane perpendicular to the second direction Y, the top of which is in contact with the second-doped-type contact region 24, and the bottom of which includes an extension part connected with the adjacent shielding layer 30 (please refer to FIGS. 2, 4 and 6).

[0071] Optionally, the connecting column 40 extends along the second direction Y, i.e. the direction in which the connecting column 40 extends along the trench gate structure 50. In the process of extension, the connecting column 40 contacts the second-doped-type contact region 24 located in the first region Q1 and the first-doped-type contact region 23 located in the second region Q2. The connecting column 40 is formed by injecting doped ions of the second doping type in the semiconductor epitaxial layer 20, so that the connecting column 40 in the second region Q2 can be regarded as a second-doped-type contact region in the second region Q2 and contacts the body region 22, so that the body region 22 in the second region Q2 can also be conducted with the second-doped-type contact region 24 located in the first region Q1 through the connecting column 40 in the second region Q2, and in turn with the first electrode 70, so as to reduce the on-resistance of the semiconductor device.

[0072] Optionally, the connecting column 40 located in the second region Q2 is columnar in a plane perpendicular to the second direction Y and is spaced apart from the shielding layer 30 in the first direction X, so as to ensure that the electrons flowing from the second electrode can flow from the drift region 21 between the shielding layer 30 and the connecting column 40 to the body region 22. The connecting column 40 located in the first region Q1 is inverted T-shaped in a plane perpendicular to the second direction Y, and the bottom includes an extension portion in contact with the adjacent shielding layer 30, so as to realize the electrical connection between the connecting column 40 and the shielding layer 30.

[0073] Optionally, the surface of the semiconductor epitaxial layer 20 away from the substrate 10 side includes a plurality of gate trenches extending along the second direction Y and spaced apart along the first direction X, and each gate trench is correspondingly provided with a trench gate structure 50; the connecting column 40 is located between two adjacent trench gate structures 50.

[0074] Please continue to refer to FIGS. 2-6. Optionally, in the first region Q1, the second-doped-type contact region 24 is continuously arranged between adjacent trench gate structures 50 in the first direction X; each adjacent trench gate structure 50 has a second-doped-type contact region 24, and each adjacent two trench gate structures 50 can be provided with a connecting column 40.

[0075] Alternatively, FIG. 7 is a perspective view of another semiconductor device according to an embodiment of the present application, FIG. 8 is a sectional view of the semiconductor device of FIG. 7 along the section line CC1, and FIG. 9 is another sectional view of the semiconductor device of FIG. 7 along the section line CC1. Referring to FIGS. 7-9, in the first region Q1, the second-doping-type contact regions 24 are arranged between the adjacent trench gate structures 50 in the first direction X. The connecting pillars 40 are located between the two adjacent trench gate structures 50 that contain the second-doping-type contact regions 24. Referring to FIG. 9, the two adjacent second-doping-type contact regions 24 contain the body regions 22 and the first-doping-type contact regions 23 in sequence and away from the substrate 10. In the embodiment, the P+ ions are selectively and spacedly doped between the continuous gate structures, so that the space occupied by the P+ regions can be reduced.

[0076] The semiconductor device of FIG. 7 is located in the second region Q1, and the structure can refer to that shown in FIG. 3. The structures shown in FIGS. 8 and 9 are located in the first region Q2 (the first electrode 70 and the passivation layer 90 are not shown). The structures shown in FIGS. 8 and 9 are different in that the shielding layer 30 contacts the second-doping-type contact regions 24 in FIG. 8, and the shielding layer 30 does not contact the second-doping-type contact regions 24 in FIG. 9.

[0077] FIG. 10 is a sectional view of another semiconductor device located in the second region according to an embodiment of the present application, and FIG. 11 is a sectional view of another semiconductor device located in the second region according to an embodiment of the present application. Referring to FIGS. 10 and 11, optionally, in the direction perpendicular to the substrate 10, the thickness of the shielding layer 30 is greater than a first preset value, and / or the height of the connecting pillar 40 is greater than a second preset value.

[0078] In the structure shown in FIG. 10, in the direction perpendicular to the substrate 10, the height of the connecting pillar 40 is greater than the second preset value. In the structure shown in FIG. 11, in the direction perpendicular to the substrate 10, the thickness of the shielding layer 30 is greater than the first preset value, and the height of the connecting pillar 40 is greater than the second preset value.

[0079] Optionally, the first preset value and the second preset value can be set according to actual needs. The P+ connecting pillar 40 not only serves as a communication between the p-body and the source terminal ground, but also generates a lateral electric field similar to the super-junction when the device is off, thereby protecting the easy breakdown points on both sides of the device gate bottom and improving the breakdown voltage. The thickness of the shielding layer 30 is greater than the first preset value, and the height of the connecting pillar 40 is greater than the second preset value, which can be understood as deepening the P+ connecting pillar 40 and the P+ shielding layer 30, thereby improving the electric field shielding effect on the bottom of the trench gate structure 50.

[0080] The application further provides a semiconductor device manufacturing method for manufacturing the semiconductor device of any of the embodiments of the application, and the semiconductor device manufacturing method comprises the following steps:

[0081] S110, providing a substrate; the substrate comprises a first region extending along a first direction and a second region located on opposite sides of the first region.

[0082] Optionally, referring to FIG. 12, the material of the substrate 10 can be SiC. Referring to FIG. 5, the substrate 10 comprises a first region Q1 extending along a first direction X and a second region Q2 located on opposite sides of the first region Q1.

[0083] S120, forming a semiconductor epitaxial layer on one side of the substrate.

[0084] Optionally, referring to FIG. 13, the material of the semiconductor epitaxial layer 20 can be the same as or different from the material of the substrate 10. In the embodiments of the application, the material of the substrate 10 is the same as the material of the semiconductor epitaxial layer 20, and both can be SiC. That is, the trench-type power device in the embodiments of the application can be a trench-type SiC power device. In some embodiments of the application, the substrate 10 and the semiconductor epitaxial layer 20 can be integrally arranged. The integrally arranged substrate 10 and semiconductor epitaxial layer 20 can be understood as a whole SiC film layer structure formed in the same preparation process.

[0085] S130, performing ion implantation on the semiconductor epitaxial layer to form, in the semiconductor epitaxial layer located in the second region, a drift region, a body region and a first-doping-type contact region in sequence away from the substrate, and to form, in the semiconductor epitaxial layer located in the first region, a drift region and a second-doping-type contact region in sequence away from the substrate, and to form a connecting column extending along a second direction in the drift region.

[0086] Optionally, the pattern of the mask can be transferred to the SiO2 mask layer by using plasma enhanced chemical vapor deposition (PECVD) and photolithography technology, and then based on the patterned mask layer, the semiconductor epitaxial layer 20 is subjected to front-side ion implantation to form, in the semiconductor epitaxial layer 20 located in the second region Q2, a drift region 21, a body region 22 and a first-doping-type contact region 23 in sequence away from the substrate 10 (see FIG. 14), to form, in the semiconductor epitaxial layer 20 located in the first region Q1, a drift region 21 and a second-doping-type contact region 24 in sequence away from the substrate 10 (see FIG. 15), and to form a connecting column 40 extending along a second direction Y in the drift region 21 (see FIGS. 14 and 15). Then the mask layer is removed. Different patterned mask layers can be used when ion implantation is performed on different regions.

[0087] In FIG. 14 and FIG. 15, the first-doped-type contact region 23 and the drift region 21 are doped with N-type doping ions; the second-doped-type contact region 24, the body region 22 and the connecting column 40 are doped with P-type doping ions. The P-type doping ion implantation can be batch implantation, which can first form the P+ connecting column 40 (a little deeper with high-energy); then implant P-type doping ions in the second region Q2 upwards to form the P-type doping ion concentration lower P-body region 22; then implant N-type doping ions to form the N+ contact region (the first-doped-type contact region 23) above the P-body region 22. Implant P-type doping ions in the first region Q1 to form the P+ contact region (the second-doped-type contact region 24).

[0088] S140, forming a gate trench extending along the second direction on the side surface of the semiconductor epitaxial layer away from the substrate.

[0089] FIG. 16 is a schematic diagram of forming a gate trench in the second region Q2 corresponding to step S140, and FIG. 17 is a schematic diagram of forming a gate trench in the first region Q1 corresponding to step S140. Referring to FIG. 16 and FIG. 17, the gate trench 01 extending along the second direction Y can be formed on the side of the semiconductor epitaxial layer 20 away from the substrate 10 by a photolithography process, which can include: depositing SiO2 as a mask layer on the surface of the semiconductor epitaxial layer 20 away from the substrate 10 by a deposition process such as chemical vapor deposition (CVD), spin-coating photoresist (PR) on the surface of the mask layer, forming a photoresist PR with a desired pattern by exposure and development, and then patterning the mask layer based on the patterned photoresist PR. The patterned mask layer exposes the preset position of the gate trench. Based on the patterned mask layer, the semiconductor epitaxial layer 20 is etched to form the gate trench 01. The etching process can use a plasma dry etching process, such as reactive ion etching (RIE) or inductively coupled plasma (ICP) etching process. The gate trench 01 extends along the second direction Y, and the number of gate trenches 01 can be set according to actual needs. In an embodiment of the present application, a plurality of gate trenches 01 extending along the second direction Y and spaced apart along the first direction X are formed on the surface of the semiconductor.

[0090] In some optional embodiments, before forming the shielding layer 30 by ion implantation at the bottom of the gate trench 01, the method further includes: forming a first sacrificial oxide layer on the surface of the semiconductor epitaxial layer 20 away from the substrate 10, the sidewall and the bottom of the gate trench 01, and removing the first sacrificial oxide layer located at the bottom of the gate trench.

[0091] Optionally, a first sacrificial oxide layer is formed on the sidewall and bottom of the gate trench 01 to repair the damage caused by etching. The first sacrificial oxide layer on the bottom of the gate trench is removed, and the first sacrificial oxide layer on the sidewall of the gate trench is retained, which can use the patterned first sacrificial oxide layer as a mask during ion implantation to form the shielding layer 30, thereby simplifying the preparation process of the semiconductor device. The first sacrificial oxide layer on the bottom of the gate trench 01 can be removed by buffered oxide etch (BOE) cleaning.

[0092] S150, ion implantation is performed on the bottom of the gate trench to form a shielding layer.

[0093] FIG. 18 is a schematic diagram of forming the shielding layer 30 in the second region Q2 corresponding to step S150, and FIG. 19 is a schematic diagram of forming the shielding layer 30 in the first region Q1 corresponding to step S150. Referring to FIGS. 18 and 19, based on the patterned first sacrificial oxide layer, ion implantation is performed on the bottom of the gate trench 01 to form the shielding layer 30 extending along the second direction Y. The shielding layer 30 can include a first sidewall 32, a second sidewall 33, and a bottom layer 31 located between the first sidewall 32 and the second sidewall 33; the bottom layer 31 is located at the bottom of the gate trench; and the first sidewall 32 and the second sidewall 33 are located at opposite sides of the gate trench, respectively. In a plane perpendicular to the second direction Y, the shielding layer 30 has a concave shape, forming a hat-shaped shielding layer, which can effectively improve the protection of the shielding layer 30 on the bottom surface and the bottom corner of the trench gate structure 50.

[0094] In some optional embodiments, after ion implantation is performed on the bottom of the gate trench to form the shielding layer, the method further includes:

[0095] A carbon film is formed on the surface of the semiconductor epitaxial layer 20 away from the substrate 10, the sidewall and bottom of the gate trench 01, and the sidewall of the gate trench 01 is passivated by argon and subjected to high-temperature annealing treatment, and then the carbon film is removed.

[0096] Optionally, in order to activate the implanted doping ions and eliminate the lattice damage defects caused by the doping ion implantation, activation annealing at a high temperature is needed for the semiconductor epitaxial layer 20, and the temperature is generally as high as 1600-1800℃. However, at such a high activation annealing temperature, since the material of the semiconductor epitaxial layer 20 is silicon carbide, the silicon on the surface of the silicon carbide is easy to sublimate from the surface of the silicon carbide and re-deposited on the wafer surface in the form of Si, Si2C, SiC2, etc., forming step clusters, increasing the surface roughness of the SiC wafer and the interface state density, and seriously affecting the performance of the device. The commonly used method during high-temperature annealing is carbon film protection method, and the manufacturing method is generally to sputter a carbon film protection layer or to form a carbon film protection layer by baking and curing a photoresist. After the high-temperature annealing is completed, the carbon film for protecting the surface of the silicon carbide needs to be removed, and if the carbon film is not removed completely, it will affect the ohmic contact and seriously affect the performance of the device such as switching characteristics, conduction characteristics, voltage withstand characteristics, etc. The carbon film can be removed by chemical solution immersion, and the chemical solution is generally a certain concentration of hydrochloric acid plus a certain amount of nitric acid as a catalyst.

[0097] In some optional embodiments, after the carbon film is removed, further comprising: forming a second sacrificial oxide layer on the surface of the semiconductor epitaxial layer 20 away from the substrate 10, the sidewall and the bottom of the gate trench 01, and sequentially removing the second sacrificial oxide layer and the first sacrificial oxide layer. Optionally, after the carbon film on the surface of the semiconductor epitaxial layer 20 is removed, a second sacrificial oxide layer is formed on the surface of the semiconductor epitaxial layer 20 by a thermal oxidation process to repair the lattice on the surface of the semiconductor epitaxial layer 20; and then the second sacrificial oxide layer and the first sacrificial oxide layer are removed. The surface sacrificial oxide layer can be removed by BOE cleaning.

[0098] S160, forming a trench gate structure in the gate trench; wherein the connecting column is located at least one side of the trench gate structure, and the connecting column is arranged to communicate the shielding layer and the second doping type contact region.

[0099] Referring to FIGS. 3 and 4, a first gate insulating layer 52 is formed on the sidewall of the gate trench; and a polysilicon material is filled in the gate trench to form a polysilicon gate 51. The trench gate structure 50 includes the polysilicon gate 51 and the gate insulating layer 52 wrapping the polysilicon gate 51. The material of the gate insulating layer 52 can include at least one of SiO2 and Al2O3, and the preparation method of the gate insulating layer 52 can be at least one of atomic layer deposition (ALD), thermal oxidation, and wet method.

[0100] S170, forming a first electrode on the side of the semiconductor epitaxial layer away from the substrate, and forming a second electrode on the side of the substrate away from the semiconductor epitaxial layer; wherein the first electrode is in contact with the first doping type contact region and the second doping type contact region.

[0101] Optionally, the second electrode can be formed on the side of the substrate 10 distal to the semiconductor epitaxial layer 20 after the first electrode 70 is formed on the side of the semiconductor epitaxial layer 20 distal to the substrate 10. Before the second electrode is formed on the surface of the substrate 10 distal to the semiconductor epitaxial layer 20, the substrate 10 can be thinned from the side of the substrate 10 distal to the semiconductor epitaxial layer 20, and the substrate 10 can be heavily doped with the first doping ions so that the doping concentration of the first doping ions in the substrate 10 is greater than the doping concentration of the first doping ions in the drift region 21.

[0102] Before the first electrode 70 is formed on the side of the semiconductor epitaxial layer 20 distal to the substrate 10, a passivation layer 90 can be formed on the side of the semiconductor epitaxial layer 20 distal to the substrate 10, and then an opening is formed in the passivation layer 90, and then the first electrode 70 is formed, so that the first electrode 70 and the trench gate structure 50 can be isolated by the passivation layer 90.

[0103] Referring to FIG. 20, optionally, the second-doping-type contact region 24 in the semiconductor epitaxial layer 20 in the first region Q1 is formed by forming the second-doping-type contact region 24 in the semiconductor epitaxial layer 20 in the first region Q1 in the first direction X. Then, the connecting column 40 extending in the second direction Y in the drift region 21 is formed by forming the connecting column 40 extending in the second direction Y between every two adjacent trench gate structures 50, so that the arrangement of the second-doping-type contact region 24 and the connecting column 40 in FIG. 2 can be formed.

[0104] Referring to FIG. 21, optionally, the second-doping-type contact region 24 in the semiconductor epitaxial layer 20 in the first region Q1 is formed by forming a plurality of second-doping-type contact regions 24 in the semiconductor epitaxial layer 20 in the first region Q1 in the first direction X. Then, the connecting column 40 extending in the second direction Y in the drift region 21 is formed by forming the connecting column 40 between the two adjacent trench gate structures 50 in which the second-doping-type contact region 24 is contained, so that the arrangement of the second-doping-type contact region 24 and the connecting column 40 in FIG. 7 can be formed.

[0105] The embodiments of the present application also provide a power module, which comprises a substrate and at least one semiconductor device as described in any of the embodiments of the present application, and the substrate is used to carry the semiconductor device. The power module and the semiconductor device as described in any of the embodiments of the present application have the same technical effects, which will not be described here.

[0106] The embodiment of the present application further provides a power conversion circuit, which is used for one or more of current conversion, voltage conversion and power factor correction; the power conversion circuit comprises a circuit board and at least one semiconductor device as described in any embodiment of the present application, and the semiconductor device is electrically connected with the circuit board. The power conversion circuit and the semiconductor device as described in any embodiment of the present application have the same technical effects, which will not be repeated here.

[0107] The embodiment of the present application further provides a vehicle, which comprises a load and a power conversion circuit as described in any embodiment of the present application, and the power conversion circuit is arranged to convert alternating current into direct current, convert alternating current into alternating current, convert direct current into direct current or convert direct current into alternating current, and then input to the load. The vehicle and the semiconductor device as described in any embodiment of the present application have the same technical effects, which will not be repeated here.

Claims

1. A semiconductor device, comprising: a substrate; a semiconductor epitaxial layer on one side of the substrate; wherein the substrate comprises a first region extending along a first direction and second regions on opposite sides of the first region; the semiconductor epitaxial layer on the second regions comprises, in order from the substrate, a drift region, a body region, and a first-doped-type contact region; and the semiconductor epitaxial layer on the first region comprises, in order from the substrate, a drift region and a second-doped-type contact region; a gate trench and a trench gate structure; the gate trench is on a surface of the semiconductor epitaxial layer away from the substrate and extends along a second direction; the trench gate structure is in the gate trench; the second direction intersects the first direction; a shielding layer in the semiconductor epitaxial layer and at the bottom of the trench gate structure; a connecting column in the semiconductor epitaxial layer and on at least one side of the trench gate structure, the connecting column being configured to connect the shielding layer and the second-doped-type contact region; a first electrode on a surface of the semiconductor epitaxial layer away from the substrate and in contact with the first-doped-type contact region and the second-doped-type contact region; and a second electrode on a side of the substrate away from the semiconductor epitaxial layer. The shielding layer extends along the second direction; in a plane perpendicular to the second direction, the shielding layer is in a concave shape; wherein the shielding layer comprises a first sidewall, a second sidewall, and a bottom layer between the first sidewall and the second sidewall; the bottom layer is between the bottom of the trench gate structure and the substrate; the first sidewall and the second sidewall are on opposite sides of the bottom of the trench gate structure, respectively. The connecting column extends along the second direction; the connecting column in the second region is in a column shape in a plane perpendicular to the second direction, the top of the column is in contact with the body region, and the bottom of the column is spaced apart from the shielding layer in the first direction; the connecting column in the first region is in an inverted T shape in a plane perpendicular to the second direction, the top of the column is in contact with the second-doped-type contact region, and the bottom of the column comprises an extension connected to the adjacent shielding layer. The surface of the semiconductor epitaxial layer away from the substrate comprises a plurality of gate trenches extending along the second direction and spaced apart along the first direction, and each of the gate trenches is provided with a corresponding trench gate structure; the connecting column is between two adjacent trench gate structures. 5.The semiconductor device of claim 4, wherein, in the first region, the second-doped-type contact regions are continuously arranged between two adjacent trench gate structures in the first direction; and the connecting column is between the two adjacent trench gate structures; or, in the first region, the second-doped-type contact regions are spaced apart between two adjacent trench gate structures in the first direction; the connecting column is between the two adjacent trench gate structures containing the second-doped-type contact regions; and the second-doped-type contact regions comprise, in order from the substrate, the body region and the first-doped-type contact region. ​ ​ ​ ​ ​ ​ 2. The semiconductor device of claim 1, wherein, ​ ​ 3. The semiconductor device of claim 1, wherein, ​ ​ ​ 4. The semiconductor device of claim 1, wherein, ​ ​ ​ ​ ​ 6. The semiconductor device of claim 2, wherein, in the second region, a distance between a top of the first sidewall and the body region is greater than zero, and a distance between a top of the second sidewall and the body region is greater than zero; in the first region, a distance between a top of the first sidewall and the second doping type contact region is greater than or equal to zero, and a distance between a top of the second sidewall and the second doping type contact region is greater than or equal to zero.

7. The semiconductor device of claim 1, wherein, in a direction perpendicular to the substrate, a thickness of the shielding layer is greater than a first preset value, and a height of the connecting column is greater than a second preset value.

8. The semiconductor device of any one of claims 1-7, wherein, ions of the second doping type are doped in the shielding layer, the connecting column and the body region, and a doping concentration of the shielding layer and a doping concentration of the connecting column are greater than a doping concentration of the body region; ions of the first doping type are doped in the drift region.

9. A method for manufacturing a semiconductor device, the method comprising: providing a substrate; the substrate comprising a first region extending along a first direction and second regions located on opposite sides of the first region; forming a semiconductor epitaxial layer on one side of the substrate; performing ion implantation on the semiconductor epitaxial layer to form, in the semiconductor epitaxial layer located in the second regions, a drift region, a body region and a first doping type contact region in sequence away from the substrate, to form, in the semiconductor epitaxial layer located in the first region, a drift region and a second doping type contact region in sequence away from the substrate, and to form a connecting column extending along a second direction in the drift region; forming a gate trench extending along the second direction on a side surface of the semiconductor epitaxial layer away from the substrate; performing ion implantation on a bottom of the gate trench to form a shielding layer; forming a trench gate structure in the gate trench; wherein the connecting column is located on at least one side of the trench gate structure, and the connecting column is configured to connect the shielding layer and the second doping type contact region; forming a first electrode on the semiconductor epitaxial layer away from the substrate, and forming a second electrode on the substrate away from the semiconductor epitaxial layer; wherein the first electrode is in contact with the first doping type contact region and the second doping type contact region.

10. The method for manufacturing a semiconductor device of claim 9, before performing ion implantation on a bottom of the gate trench to form a shielding layer, the method further comprising: forming a first sacrificial oxide layer on a side surface of the semiconductor epitaxial layer away from the substrate, a sidewall and a bottom of the gate trench; removing the first sacrificial oxide layer located on the bottom of the gate trench.

11. The method for manufacturing a semiconductor device of claim 10, after performing ion implantation on a bottom of the gate trench to form a shielding layer, the method further comprising: forming a carbon film on a side surface of the semiconductor epitaxial layer away from the substrate, a sidewall and a bottom of the gate trench, and removing the carbon film after passivating the sidewall of the gate trench with argon and high-temperature annealing treatment.

12. The method of claim 11, after removing the carbon film, further comprising: forming a second sacrificial oxide layer on a surface of the semiconductor epitaxial layer away from the substrate side, sidewalls and bottom of the gate trench, and sequentially removing the second sacrificial oxide layer and the first sacrificial oxide layer.

13. The method of producing a semiconductor device according to Claim 9, wherein forming a second doped type contact region in the semiconductor epitaxial layer in the first region, comprising: forming a second doped type contact region in the semiconductor epitaxial layer in the first region, comprising: forming a second doped type contact region in the semiconductor epitaxial layer in the first region, comprising: forming a connecting pillar in the drift region extending in the second direction, comprising: forming a connecting pillar in the drift region extending in the second direction, comprising: forming a connecting pillar in the drift region extending in the second direction, comprising: forming a connecting pillar in the drift region extending in the second direction, comprising: forming a connecting pillar in the drift region extending in the second direction, comprising: forming a connecting pillar in the drift region extending in the second direction, comprising: forming a connecting pillar in the drift region extending in the second direction, comprising:

14. A power module comprising a substrate and at least one semiconductor device according to any one of claims 1-8, the substrate being arranged to carry the semiconductor device.

15. A power conversion circuit, the power conversion circuit comprising a circuit board and at least one semiconductor device according to any one of claims 1-8, the semiconductor device being electrically connected to the circuit board.

16. A vehicle comprising a load and a power conversion circuit according to claim 15, the power conversion circuit being arranged to convert alternating current to direct current, convert alternating current to alternating current, convert direct current to direct current or convert direct current to alternating current before input to the load.

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