Semiconductor device and manufacturing method therefor

Abstract

A semiconductor device and a manufacturing method therefor. The semiconductor device comprises: a substrate (10); a semiconductor epitaxial layer (20) located on one side of the substrate (10), wherein the semiconductor epitaxial layer (20) comprises a first nitride semiconductor layer (21) and a second nitride semiconductor layer (22), and the band gap of the first nitride semiconductor layer (21) is different from that of the second nitride semiconductor layer (22); and a gate structure (30) located on the side of the semiconductor epitaxial layer (20) away from the substrate (10), wherein the gate structure (30) comprises a cap layer (31), a compensation-doped protective layer (32), and a gate electrode (33) that are successively stacked. The cap layer (31) is doped with doping ions of a first conductivity type, and the compensation-doped protective layer (32) is doped with doping ions of the first conductivity type and doping ions of a second conductivity type, so that the electrical properties of the first conductivity type of the cap layer (31) are stronger than those of the first conductivity type of the compensation-doped protective layer (32).

Description

Semiconductor device and method of manufacturing the same

[0001] This application claims priority to the Chinese patent application No. 202411127556.7, filed on August 16, 2024, to the Chinese Patent Office, the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] Embodiments of the present application relate to the field of semiconductor technology, for example, to a semiconductor device and a method of manufacturing the same. BACKGROUND

[0003] Nitride-based semiconductor devices utilize heterojunction interfaces between two materials with different bandgaps to form quantum well-like structures that accommodate two-dimensional electron gas regions, thereby meeting the needs of high-power / frequency devices.

[0004] However, there are still some reliability issues that are worth attention. FIG. 1 is a schematic diagram of the structure of a semiconductor device provided in the related art. Referring to FIG. 1, in the related art, the semiconductor device includes a semiconductor epitaxial layer 2 and a gate structure disposed on a side of the semiconductor epitaxial layer 2 away from a substrate 1. The operation of the semiconductor device is controlled by a gate voltage applied to the gate structure, which controls the on-off of the channel, and the voltage applied between the source and the drain can drive the flow of 2DEG. When the semiconductor device is an enhancement-mode HEMT device (i.e., an E-mode enhancement-mode HEMT), the gate structure includes a pGaN layer 3 and a gate electrode 4, which depletes the 2DEG in the underlying channel by using the holes in the pGaN layer 3 to achieve normally-off. The structure of the device has the following problems when in operation: when a higher positive voltage is applied to the gate electrode 4, the top region of the pGaN layer 3 has a higher electric field, and as the gate voltage is further increased, most of the increased voltage falls on the Schottky junction, and there is a very high electric field at the Schottky interface. After long-term high-gate-voltage stress, the Schottky junction will degrade, resulting in a series of reliability problems.

[0005] To solve the above problems, US patent US9478632B2 sets the gate structure as a composite structure containing a P-type doped layer (172), an N-type doped layer (174), and a gate electrode, that is, an N-type doped layer is introduced between the pGaN layer 3 and the gate electrode 4 of the HEMT structure described in FIG. 1, and at this time the N-type doped layer and the gate electrode are in direct contact to eliminate the Schottky junction. This patent technology solution will bring some new problems, such as the P-type doped layer (172) and the N-type doped layer (174) have a clear doping boundary, and the leakage current of the gate structure is large due to the direct contact between the N-type doped layer and the gate electrode. SUMMARY

[0006] Embodiments of the present application provide a semiconductor device and a preparation method thereof to improve gate electric field distribution and improve reliability of a gate structure.

[0007] According to an aspect of the present application, a semiconductor device is provided, comprising:

[0008] a substrate;

[0009] a semiconductor epitaxial layer located on one side of the substrate; the semiconductor epitaxial layer comprises a first nitride semiconductor layer and a second nitride semiconductor layer; the band gap of the first nitride semiconductor layer is different from the band gap of the second nitride semiconductor layer;

[0010] a gate structure located on the side of the semiconductor epitaxial layer away from the substrate; the gate structure comprises a cap layer, a compensating doped protection layer and a gate electrode which are sequentially stacked; the compensating doped protection layer and the gate electrode are in Schottky contact;

[0011] wherein the cap layer is doped with first-conductivity-type dopant ions, and the cap layer as a whole exhibits first conductivity type; the compensating doped protection layer is doped with first-conductivity-type dopant ions and second-conductivity-type dopant ions, and the compensating doped protection layer as a whole exhibits first conductivity type or electrical neutrality, and the first conductivity type of the cap layer is stronger than the first conductivity type of the compensating doped protection layer.

[0012] Optionally, in the compensating doped protection layer, at least the part adjacent to the gate electrode has weak first conductivity type or electrical neutrality.

[0013] Optionally, the cap layer and the compensating doped protection layer have the same first-conductivity-type dopant ions, and the concentration of the first-conductivity-type dopant ions at the top of the cap layer and the bottom of the compensating doped protection layer is equal.

[0014] Optionally, the thickness of the compensating doped protection layer is less than the thickness of the cap layer.

[0015] Optionally, the thickness of the compensating doped protection layer is less than the thickness of the cap layer.

[0016] Optionally, the doping concentration of the first-conductivity-type dopant ions in the cap layer is greater than or equal to the doping concentration of the first-conductivity-type dopant ions in the compensating doped protection layer.

[0017] Optionally, along the direction of the cap layer pointing to the gate electrode, the doping concentration of the first-conductivity-type dopant ions in the compensating doped protection layer gradually decreases.

[0018] The doping concentration of the second conductive type doping ions in the compensating doped protection layer is gradually increased or uniformly set.

[0019] Optionally, the doping concentration of the first conductive type doping ions in the compensating doped protection layer is uniformly set along a direction pointing from the cap layer to the gate electrode.

[0020] The doping concentration of the second conductive type doping ions in the compensating doped protection layer is gradually increased or uniformly set.

[0021] Optionally, the first conductive type doping ions are P-type doping ions, and the second conductive type doping ions are N-type doping ions.

[0022] Optionally, the P-type doping ions include but are not limited to Mg ions, C ions, Fe ions and Zn ions, and the N-type doping ions include but are not limited to Si ions and O ions.

[0023] Optionally, the material of the cap layer is GaN, and the material of the compensating doped protection layer is at least one of GaN and AlGaN.

[0024] According to another aspect of the present application, a preparation method of a semiconductor device is provided, comprising:

[0025] providing a substrate;

[0026] forming a semiconductor epitaxial layer on one side of the substrate; the semiconductor epitaxial layer comprises a first nitride semiconductor layer and a second nitride semiconductor layer; the band gap of the first nitride semiconductor layer is different from the band gap of the second nitride semiconductor layer;

[0027] forming a gate structure on the side of the semiconductor epitaxial layer away from the substrate; wherein the gate structure comprises a cap layer, a compensating doped protection layer and a gate electrode which are sequentially stacked, and the compensating doped protection layer and the gate electrode are in Schottky contact; the cap layer is doped with first conductive type doping ions, and the cap layer as a whole presents the first conductive type; the compensating doped protection layer is doped with first conductive type doping ions and second conductive type doping ions, and the compensating doped protection layer as a whole presents the first conductive type or electrical neutrality, and the electrical property of the first conductive type of the cap layer is stronger than the electrical property of the first conductive type of the compensating doped protection layer.

[0028] Optionally, forming a gate structure on the side of the semiconductor epitaxial layer away from the substrate comprises:

[0029] In the first stage, depositing a cap layer material on the side of the semiconductor epitaxial layer away from the substrate, and introducing first conductive type doping ions in the growth environment to form the cap layer.

[0030] In a second stage after the first stage, a compensating doped protection layer material is deposited on a side of the semiconductor epitaxial layer away from the substrate, and a first conductive type doping ion and a second conductive type doping ion are introduced into a growth environment to form the compensating doped protection layer.

[0031] A gate electrode is formed on a side of the compensating doped protection layer away from the substrate.

[0032] Optionally, the compensating doped protection layer is formed by depositing a compensating doped protection layer material on a side of the semiconductor epitaxial layer away from the substrate, and introducing a first conductive type doping ion and a second conductive type doping ion into a growth environment, and the method comprises:

[0033] In the second stage, the amount of the first conductive type doping ion introduced is gradually reduced, and the amount of the second conductive type doping ion introduced is gradually increased, or the second conductive type doping ion is uniformly introduced, or the amount of the second conductive type doping ion introduced is gradually reduced.

[0034] Alternatively, in the second stage, the amount of the first conductive type doping ion introduced is uniformly introduced, and the amount of the second conductive type doping ion introduced is gradually increased or the second conductive type doping ion is uniformly introduced.

[0035] The embodiments of the present application provide a semiconductor device and a preparation method thereof. The semiconductor device comprises a substrate, a semiconductor epitaxial layer located on a side of the substrate, wherein the semiconductor epitaxial layer has a two-dimensional electron gas heterojunction, and a gate structure located on a side of the semiconductor epitaxial layer away from the substrate. The gate structure comprises a cap layer, a compensating doped protection layer and a gate electrode which are sequentially stacked. The cap layer is doped with a first conductive type doping ion. The compensating doped protection layer is doped with the first conductive type doping ion and a second conductive type doping ion, so that the first conductive type electrical property of the cap layer is stronger than the first conductive type electrical property of the compensating doped protection layer. The technical solution provided by the embodiments of the present application can weaken the first conductive type electrical property of the compensating doped protection layer by doping the compensating doped protection layer above the cap layer with the first conductive type doping ion and the second conductive type doping ion, so that the compensating doped protection layer is configured to provide a relatively low electric field than the cap layer, thereby improving the gate electric field distribution, increasing the gate breakdown voltage, and improving the reliability of the gate structure.

[0036] It should be understood that the content described in this part is not intended to identify key or important features of the embodiments of the present application, nor is it used to limit the scope of the present application. BRIEF DESCRIPTION OF DRAWINGS

[0037] FIG. 1 is a structural schematic diagram of a semiconductor device provided in the related art;

[0038] FIG. 2 is a structural schematic diagram of a semiconductor device provided in an embodiment of the present application;

[0039] FIG. 3 is a comparison diagram of CV test curves of a semiconductor device without a compensating doped protection layer and a semiconductor device with a compensating doped protection layer provided in an embodiment of the present application;

[0040] FIG. 4 is a comparison diagram of probability distribution of gate breakdown voltage of a semiconductor device without a compensating doped protection layer and a semiconductor device with a compensating doped protection layer provided in an embodiment of the present application;

[0041] FIG. 5 is a structural schematic diagram of another semiconductor device provided in an embodiment of the present application;

[0042] FIG. 6 is a flow chart of a preparation method of a semiconductor device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0043] It should be noted that the terms "first", "second", and the like in the description and claims of the present application and the above-mentioned accompanying drawings are used to distinguish similar objects, and do not necessarily indicate a specific order or a chronological sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances, so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device including a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but can include other steps or units not clearly listed or inherent to the process, method, product or device.

[0044] An embodiment of the present application provides a semiconductor device, and FIG. 2 is a structural schematic diagram of a semiconductor device provided in an embodiment of the present application, referring to FIG. 2, the semiconductor device comprises:

[0045] a substrate 10;

[0046] a semiconductor epitaxial layer 20 located on one side of the substrate 10; wherein the semiconductor epitaxial layer 20 comprises a first nitride semiconductor layer 21 and a second nitride semiconductor layer 22; the band gap of the first nitride semiconductor layer 21 is different from the band gap of the second nitride semiconductor layer 22;

[0047] a gate structure 30 located on the side of the semiconductor epitaxial layer 20 away from the substrate 10; the gate structure 30 comprises a cap layer 31, a compensating doped protection layer 32 and a gate electrode 33 which are sequentially stacked, and the compensating doped protection layer 32 and the gate electrode 33 are in Schottky contact;

[0048] The cap layer 31 is doped with a first conductivity type dopant ion, and the cap layer 31 as a whole exhibits the first conductivity type. The compensating doped protection layer 32 is doped with a first conductivity type dopant ion and a second conductivity type dopant ion, and the compensating doped protection layer 32 as a whole exhibits the first conductivity type or is electrically neutral, and the first conductivity type of the cap layer 31 is stronger than the first conductivity type of the compensating doped protection layer 32.

[0049] The substrate 10 can be a semiconductor substrate. The material of the substrate 10 can include, but is not limited to, Si, SiGe, SiC, gallium arsenide, P-doped Si, N-doped Si, sapphire, semiconductor-on-insulator (such as silicon-on-insulator (SOI) or other suitable substrate 10 material. In some embodiments, the substrate 10 can include, for example, but not limited to, a group III element, a group IV element, a group V element, or a combination thereof (e.g., a III-V compound). In other embodiments, the material of the substrate 10 can include a silicon substrate having a <111> orientation.

[0050] In some embodiments, a buffer layer 11 can be disposed between the substrate 10 and the semiconductor epitaxial layer 20, the buffer layer 11 can be in contact with the semiconductor epitaxial layer 20, and the buffer layer 11 is used to reduce the lattice and thermal mismatch between the substrate 10 and the semiconductor epitaxial layer 20, thereby solving defects due to the mismatch / difference. The buffer layer 11 can include a III-V compound. The III-V compound can include, but is not limited to, aluminum, gallium, indium, nitrogen, or a combination thereof. Thus, exemplary materials of the buffer layer 11 can include, for example, but not limited to, GaN, AlN, AlGaN, InAlGaN, or a combination thereof. In some embodiments, a nucleation layer can be included between the substrate 10 and the semiconductor epitaxial layer 20. The nucleation layer can be formed below the buffer layer 11. The nucleation layer is used to provide a transition to accommodate the mismatch / difference between the substrate 10 and the III-nitride layer of the buffer layer 11. Exemplary materials of the nucleation layer can include, but are not limited to, AlN.

[0051] The semiconductor epitaxial layer 20 includes a first nitride semiconductor layer 21 and a second nitride semiconductor layer 22. The first nitride semiconductor layer 21 is located on one side of the substrate 10, and the second nitride semiconductor layer 22 is located on a side of the first nitride semiconductor layer 21 away from the substrate 10 and has a different band gap than the first nitride semiconductor layer 21. There can be a heterojunction with a two-dimensional electron gas between the first nitride semiconductor layer 21 and the second nitride semiconductor layer 22. The material of the first nitride semiconductor layer 21 can include, but is not limited to, a nitride or a III-V compound, such as GaN, AlN, InN, In x Al y Ga (1-x-y) N (wherein x+y≤1), Al y Ga (1-y)N (where y < 1). The material of the second nitride semiconductor layer 2222 can include, but is not limited to, a III-V nitride semiconductor material such as GaN, AlGaN, InN, AlInN, InGaN, AlInGaN, or a combination thereof. The band gap (i.e., the forbidden band width) of the material of the first nitride semiconductor layer 21 and the band gap of the material of the second nitride semiconductor layer 22 are selected to be different such that the electron affinities of the two are different from each other and a heterojunction is formed therebetween.

[0052] The band gap of the material of the first nitride semiconductor layer 21 is set to be smaller than the band gap of the material of the second nitride semiconductor layer 22. For example, the first nitride semiconductor layer 21 can be selected to be a GaN layer having a band gap of about 3.4 eV, and the second nitride semiconductor layer 22 can be selected to be an AlGaN layer having a band gap of about 4.0 eV, whereby the first nitride semiconductor layer 21 and the second nitride semiconductor layer 22 can function as a channel layer and a barrier layer, respectively. A triangular well potential is generated at the junction interface between the channel layer and the barrier layer, such that electrons accumulate in the triangular well, thereby generating a two-dimensional electron gas (2DEG) region adjacent to the heterojunction. Thus, the semiconductor device can include at least one GaN-based high electron mobility transistor (HEMT). It should be noted that the formation of the 2DEG region is positively correlated with the degree of polarization effect between the channel and the barrier layer.

[0053] The gate structure 30 is disposed on the side of the semiconductor epitaxial layer 20 away from the substrate 10. The operation of the semiconductor device is controlled by a gate voltage applied on the gate structure 30, which controls the on-off of the channel. The semiconductor device in the present application is an enhancement-mode HEMT device (i.e., an E-mode enhancement-mode HEMT). The gate structure 30 includes a cap layer 31, a compensating doped protection layer 32, and a gate electrode 33 which are sequentially stacked. The cap layer 31 is located on the surface of the semiconductor epitaxial layer 20 away from the substrate 10, the compensating doped protection layer 32 is located on the surface of the cap layer 31 away from the substrate 10, and the gate electrode 33 is located on the surface of the compensating doped protection layer 32 away from the substrate 10. Among them, the cap layer 31 is doped with first-conductivity-type dopant ions, and the conductivity type of the cap layer 31 is the first conductivity type; the compensating doped protection layer 32 is doped with first-conductivity-type dopant ions and second-conductivity-type dopant ions, and the conductivity type of the compensating doped protection layer 32 is weaker than the first conductivity type of the cap layer 31, or can be neutral.

[0054] If the first conductivity type is P-type, the second conductivity type is N-type; if the first conductivity type is N-type, the second conductivity type is P-type. In the embodiments of the present application, the first conductivity type is P-type, and the second conductivity type is N-type. The first conductivity type doping ions are P-type doping ions, and the second conductivity type doping ions are N-type doping ions; wherein the P-type doping ions include but are not limited to Mg ions, C ions, Fe ions and Zn ions; the N-type doping ions include but are not limited to Si ions and O ions. The cap layer 31 is a P-type cap layer, which depletes the 2DEG in the underlying channel by holes in the P-type cap layer, to realize normally-off. The compensating doped protection layer 32 can be a weak P-type compensating doped protection layer 32, or a neutral compensating doped protection layer 32, which is configured to provide a relatively low electric field than the cap layer 31, so as to improve the gate electric field distribution, increase the gate breakdown voltage, and improve the reliability of the gate structure 30. The compensating doped protection layer 32 can be a film layer epitaxially grown between the P-type cap layer 31 and the gate electrode 33 shown in Fig. 1, or the thickness of the portion of the P-type cap layer 31 adjacent to the gate electrode 33 shown in Fig. 1 can be replaced by a weak P-type or neutral, so as to form the compensating doped protection layer 32.

[0055] Fig. 3 is a CV test curve comparison diagram of a semiconductor device without a compensating doped protection layer (the structure shown in Fig. 1) and a semiconductor device with a compensating doped protection layer (the structure shown in Fig. 2) according to the embodiments of the present application. Referring to Fig. 3, each CV test curve in the left graph of Fig. 3 corresponds to a semiconductor device without a compensating doped protection layer, and these semiconductor devices belong to the same wafer; that is, the left graph of Fig. 3 is a test graph obtained by testing semiconductor devices at different positions of a wafer in the related art, wherein different CV test curves correspond to semiconductor devices at different positions of the wafer. Each CV test curve in the right graph of Fig. 3 corresponds to a semiconductor device with a compensating doped protection layer, and these semiconductor devices belong to the same wafer; that is, the right graph of Fig. 3 is a test graph obtained by testing semiconductor devices at different positions of a wafer in the improved embodiments of the present application, wherein different CV test curves correspond to semiconductor devices at different positions of the wafer. As can be seen from Fig. 3, the CV curve of the semiconductor device with the compensating doped protection layer 32 only has one step, and the size of the capacitance is 3.230×10 -11 F, which does not change significantly compared with the capacitance value 3.259×10 -11 F of the conventional structure shown in Fig. 1. Therefore, the semiconductor device shown in Fig. 2 is still a Schottky junction controlled enhancement mode HEMT device.

[0056] The gate breakdown voltage of the semiconductor device provided by the embodiment of the present application is significantly improved, which indicates that the device has higher gate reliability. And since the compensation doped protection layer and the gate electrode in the semiconductor device still maintain the Schottky contact, the leakage current will not be increased.

[0057] FIG. 4 is a probability distribution comparison diagram of the gate breakdown voltage of a semiconductor device without a compensation doped protection layer and a semiconductor device with a compensation doped protection layer provided by the embodiment of the present application. Referring to FIG. 4, the gate breakdown voltage of a plurality of semiconductor devices without a compensation doped protection layer 32 is tested, wherein curve 1 shows the proportion of the semiconductor devices without a compensation doped protection layer 32 at different gate breakdown voltages. The breakdown voltage of a plurality of first semiconductor devices with a compensation doped protection layer 32 and the breakdown voltage of a plurality of second semiconductor devices with a compensation doped protection layer 32 are tested, wherein curve 2 shows the proportion of the first semiconductor devices with a compensation doped protection layer 32 at different gate breakdown voltages, and curve 3 shows the proportion of the second semiconductor devices with a compensation doped protection layer 32 at different gate breakdown voltages. As shown in FIG. 4, the gate breakdown voltage of the semiconductor device with a compensation doped protection layer 32 is significantly improved, which indicates that the device has higher gate reliability.

[0058] The semiconductor device provided by the embodiment of the present application comprises a substrate 10; a semiconductor epitaxial layer 20 located on one side of the substrate 10; and a gate structure 30 located on the side of the semiconductor epitaxial layer 20 away from the substrate 10. The gate structure 30 comprises a cap layer 31, a compensation doped protection layer 32 and a gate electrode 33 which are sequentially stacked. The cap layer 31 is doped with first-conductivity-type doping ions. The compensation doped protection layer 32 is doped with first-conductivity-type doping ions and second-conductivity-type doping ions, so that the first-conductivity-type electrical property of the cap layer 31 is stronger than the first-conductivity-type electrical property of the compensation doped protection layer 32. The technical solution provided by the embodiment of the present application is that the compensation doped protection layer 32 is arranged above the cap layer 31, and the compensation doped protection layer 32 is doped with first-conductivity-type doping ions and second-conductivity-type doping ions at the same time, so as to weaken the first-conductivity-type electrical property of the compensation doped protection layer 32. The compensation doped protection layer 32 is configured to provide a relatively low electric field than the cap layer 31, so as to improve the gate electric field distribution, increase the gate breakdown voltage, and improve the reliability of the gate structure 30.

[0059] On the basis of the above embodiments, optionally, the cap layer 31 can be a P-type doped III-V semiconductor layer. Exemplary materials of the cap layer 31 can include P-doped III-V nitride semiconductor materials, such as P-type gallium nitride, P-type aluminum gallium nitride, P-type indium nitride, P-type aluminum indium nitride, P-type indium gallium nitride, P-type aluminum indium gallium nitride, or a combination thereof. In some embodiments, the P-type doped material is achieved by using P-type impurities, such as beryllium (Be), zinc (Zn), cadmium (Cd), and magnesium (Mg). Exemplary materials of the gate electrode 33 can include metals or metal compounds. The gate electrode 33 can be formed as a single layer or multiple layers with the same or different compositions. Exemplary materials of the metals or metal compounds can include, for example, but are not limited to, tungsten (W), gold (Au), palladium (Pd), titanium (Ti), tantalum (Ta), cobalt (Co), nickel (Ni), platinum (Pt), molybdenum (Mo), titanium nitride (TiN), tantalum nitride (TaN), metal alloys, or compounds thereof, or other metal compounds.

[0060] Optionally, the material of the cap layer 31 is the same as the material of the compensating doped protection layer 32.

[0061] Optionally, the material of the cap layer is GaN, and the material of the compensating doped protection layer is at least one of GaN and AlGaN.

[0062] On the basis of the above embodiments, optionally, in the compensating doped protection layer 32, at least the part adjacent to the gate electrode 33 has a weak first conductivity type or is electrically neutral.

[0063] It can be understood that the entire compensating doped protection layer 32 can be set to have a weak first conductivity type or be electrically neutral; or the top of the compensating doped protection layer 32 is set to have a weak first conductivity type or be electrically neutral, and the rest is the same as or slightly weaker than the cap layer 31. The top of the compensating doped protection layer 32 is in contact with the gate electrode 33, and only the top of the compensating doped protection layer 32 is set to have a weak first conductivity type or be electrically neutral, which can meet the needs of improving the gate field distribution, increasing the gate breakdown voltage, and improving the reliability of the gate structure 30, while also utilizing the holes in the bottom of the compensating doped protection layer 32 to deplete the 2DEG in the lower channel, thereby improving the reliability of the device when it is turned off.

[0064] On the basis of the above embodiments, optionally, the cap layer 31 and the compensation doped protective layer 32 have the same first-conductivity-type doped ions, and the concentration of the first-conductivity-type doped ions at the top of the cap layer 31 and at the bottom of the compensation doped protective layer 32 is equal. The concentration of the first-conductivity-type doped ions at the top of the cap layer 31 and at the bottom of the compensation doped protective layer 32 being equal can be understood as follows: the concentration of the first-conductivity-type doped ions at the top of the cap layer 31 and at the bottom of the compensation doped protective layer 32 fluctuates within ±5% of the same concentration value, and both are considered equal, that is, the concentration of the first-conductivity-type doped ions at the top of the cap layer 31 and at the bottom of the compensation doped protective layer 32 is within the same preset concentration interval, so that the cap layer 31 and the compensation doped protective layer 32 can be prepared by a continuous deposition process.

[0065] On the basis of the above embodiments, optionally, the thickness of the compensation doped protective layer 32 is less than the thickness of the cap layer 31. The ratio of the thickness of the compensation doped protective layer 32 to the thickness of the cap layer 31 is 1:3 to 1:19; for example, when the total thickness of the gate structure is 80 nm, the thickness of the compensation doped protective layer 32 ranges from 4 nm to 20 nm, and the thickness of the cap layer 31 ranges from 60 nm to 76 nm. By setting the thickness of the compensation doped protective layer 32 to be less than the thickness of the cap layer 31, the need to improve the gate electric field distribution, increase the gate breakdown voltage, and improve the reliability of the gate structure 30 can be met, while the effect of the cap layer 31 depleting the 2DEG in the underlying channel can be ensured, and the reliability of the device when turned off can be improved.

[0066] On the basis of the above embodiments, optionally, the doping concentration of the first-conductivity-type doped ions in the cap layer 31 is greater than or equal to the doping concentration of the first-conductivity-type doped ions in the compensation doped protective layer 32.

[0067] The doping concentration of the first-conductivity-type doped ions in the cap layer 31 can be greater than the doping concentration of the first-conductivity-type doped ions in the compensation doped protective layer 32, or the doping concentration of the first-conductivity-type doped ions in the cap layer 31 can be equal to the doping concentration of the first-conductivity-type doped ions in the compensation doped protective layer 32. By mixing the second-conductivity-type doped ions in the compensation doped protective layer 32, the application embodiments weaken the electrical properties of the first conductivity type of the compensation doped protective layer 32, so that the first conductivity type of the compensation doped protective layer 32 is weaker than that of the cap layer 31. The compensation doped protective layer 32 is configured to provide a relatively low electric field than the cap layer 31, thereby improving the gate electric field distribution, increasing the gate breakdown voltage, and improving the reliability of the gate structure 30.

[0068] Optionally, the doping concentration of the first conductive type doping ions in the cap layer 31 is greater than the doping concentration of the first conductive type doping ions in the compensation doped protective layer 32, which can reduce the P-type ions in the compensation doped protective layer 32, thereby reducing the cost and facilitating the realization of a weak P-type compensation doped protective layer 32 or a neutral compensation doped protective layer 32. In addition, reducing the doping content of P-type ions in the compensation doped protective layer 32 can also reduce the roughness of the surface of the compensation doped protective layer 32, thereby improving the crystal quality of the surface of the compensation doped protective layer 32.

[0069] On the basis of the above embodiments, in an embodiment of the present application, the doping concentration of the first conductive type doping ions in the compensation doped protective layer 32 is uniformly set along the direction X of the cap layer 31 pointing to the gate electrode 33.

[0070] The doping concentration of the second conductive type doping ions in the compensation doped protective layer 32 is gradually increased or uniformly set.

[0071] The doping concentration of the first conductive type doping ions in the cap layer 31 is greater than or equal to the doping concentration of the first conductive type doping ions in the compensation doped protective layer 32, and the doping concentration of the first conductive type doping ions in the compensation doped protective layer 32 is uniformly set along the direction X of the cap layer 31 pointing to the gate electrode 33. The doping concentration of the second conductive type doping ions in the compensation doped protective layer 32 is gradually reduced or uniformly set. The technical solution provided in the embodiment of the present application can set the doping concentration of the first conductive type doping ions in the compensation doped protective layer 32 uniformly, so that the amount of the first conductive type doping ions introduced does not need to be adjusted when doping the first conductive type doping ions in the compensation doped protective layer 32, thereby reducing the difficulty of preparing the device.

[0072] If the second conductive type doping ions in the compensation doped protective layer 32 are uniformly set, the amount of the second conductive type doping ions introduced does not need to be adjusted, thereby further reducing the difficulty of preparing the device. If the doping concentration of the second conductive type doping ions in the compensation doped protective layer 32 gradually increases along the direction X of the cap layer 31 pointing to the gate electrode 33, the electrical property of the first conductive type of the compensation doped protective layer 32 gradually weakens along the direction X of the cap layer 31 pointing to the gate electrode 33, thereby further improving the gate breakdown voltage and the reliability of the gate structure 30.

[0073] On the basis of the above embodiments, in another embodiment of the present application, the doping concentration of the first conductive type doping ions in the compensation doped protective layer 32 gradually decreases along the direction X of the cap layer 31 pointing to the gate electrode 33; the doping concentration of the second conductive type doping ions in the compensation doped protective layer 32 gradually decreases, or is uniformly set, or gradually increases.

[0074] The doping concentration of the first conductivity type doped ions in the capping layer 31 is greater than that in the compensation doping protection layer 32. Furthermore, along the direction X from the capping layer 31 towards the gate electrode 33, the doping concentration of the first conductivity type doped ions in the compensation doping protection layer 32 gradually decreases, as does the doping concentration of the second conductivity type doped ions. By setting both the doping concentrations of the first and second conductivity type doped ions in the compensation doping protection layer 32 to gradually decrease, the cost of the device can be further reduced. Additionally, the doping content of the ions in the compensation doping protection layer 32 can be reduced, further decreasing the surface roughness of the compensation doping protection layer 32 and improving the crystal quality of the surface of the compensation doping protection layer 32. In addition, to achieve the characteristic that the electrical properties of the first conductivity type of the compensation doping protection layer 32 gradually decrease in the direction X from the capping layer 31 to the gate electrode 33, while ensuring that the concentration of the first conductivity type doped ions at the same position in the compensation doping protection layer 32 is greater than the concentration of the second conductivity type doped ions, it is possible to set the decreasing gradient of the doping concentration of the first conductivity type doped ions in the direction X from the capping layer 31 to the gate electrode 33 to be greater than the decreasing gradient of the doping concentration of the second conductivity type doped ions.

[0075] Alternatively, the doping concentration of the first conductivity type dopant ions in the capping layer 31 is greater than the doping concentration of the first conductivity type dopant ions in the compensation doping protection layer 32, and the doping concentration of the first conductivity type dopant ions in the compensation doping protection layer 32 gradually decreases along the direction X from the capping layer 31 to the gate electrode 33, while the doping concentration of the second conductivity type dopant ions in the compensation doping protection layer 32 is uniformly set. The technical solution provided in this application, by setting the doping concentration of the first conductivity type dopant ions in the compensation doping protection layer 32 to gradually decrease, can satisfy the requirement that the electrical properties of the first conductivity type in the compensation doping protection layer 32 gradually weaken in the direction X from the capping layer 31 to the gate electrode 33, while ensuring the doping concentration of the second conductivity type dopant ions in the compensation doping protection layer 32 is uniformly set, thereby improving the reliability of the gate structure 30. Simultaneously, as the doping concentration of the first conductivity type doped ions gradually decreases while the doping concentration of the second conductivity type doped ions is uniformly set, the difference between the doping concentrations of the first conductivity type doped ions and the second conductivity type doped ions becomes smaller and smaller in the direction X from the capping layer 31 to the gate electrode 33. This means the compensation effect of the second conductivity type doped ions becomes stronger, which is beneficial for achieving neutrality at the top of the compensation doping protective layer 32. It is important to emphasize that the compensation doping protective layer 32 after compensation doping will not exhibit an N-type structure.

[0076] Alternatively, the doping concentration of the first-conductivity-type dopant ions in the cap layer 31 is greater than the doping concentration of the first-conductivity-type dopant ions in the compensating doped protection layer 32, and the doping concentration of the first-conductivity-type dopant ions in the compensating doped protection layer 32 gradually decreases in the direction X of the cap layer 31 pointing to the gate electrode 33, and the doping concentration of the second-conductivity-type dopant ions in the compensating doped protection layer 32 gradually increases. The technical solution provided by the embodiment of the present application gradually increases the doping concentration of the first-conductivity-type dopant ions in the compensating doped protection layer 32, which facilitates the characteristic that the electrical property of the first-conductivity-type of the compensating doped protection layer 32 gradually weakens in the direction X of the cap layer 31 pointing to the gate electrode 33, and can accelerate the speed of weakening the electrical property of the first-conductivity-type of the compensating doped protection layer 32 in the direction X of the cap layer 31 pointing to the gate electrode 33, so that the first-conductivity-type of the part of the compensating doped protection layer 32 in contact with the gate electrode 33 is weaker, which is conducive to achieving the neutrality of the top of the compensating doped protection layer 32 and improving the reliability of the gate structure 30.

[0077] On the basis of the above-mentioned embodiments, FIG. 5 is a structural schematic diagram of another semiconductor device provided by the embodiment of the present application, referring to FIG. 5, optionally, the semiconductor device further comprises:

[0078] The source electrode S and the drain electrode D are located on the side of the semiconductor epitaxial layer 20 away from the substrate 10, and are located on the opposite sides of the gate structure 30.

[0079] The source electrode S is located on the side of the second nitride semiconductor layer 22 away from the substrate 10 and is in contact with the second nitride semiconductor layer 22. The drain electrode D is located on the side of the second nitride semiconductor layer 22 away from the substrate 10 and is in contact with the second nitride semiconductor layer 22. The source electrode S and the drain electrode D are located on the opposite sides of the gate structure 30. The source electrode S and the drain electrode D can include but are not limited to metal, alloy, doped semiconductor material (such as doped crystalline silicon), compound such as silicide and nitride, other conductor material or combination thereof. The source electrode S and the drain electrode D can be a single layer or multiple layers with the same or different compositions. In some embodiments, the source electrode S and the drain electrode D form an ohmic contact with the second nitride semiconductor layer 22. The ohmic contact can be achieved by applying Ti, Al or other suitable materials to the source electrode S and the drain electrode D.

[0080] On the basis of the above-mentioned embodiments, referring to FIG. 5, optionally, the semiconductor device further comprises: a strain layer 40 located on the sidewall of the gate structure 30, between the gate structure 30 and the source electrode S, and between the gate structure and the drain electrode D.

[0081] To further increase the 2DEG concentration, a strain layer 40 can be added on top of the semiconductor epitaxial layer 20. The strain layer 40 modulates the stress state of the AlGaN / GaN heterojunction, which achieves the effect of reducing the on-resistance and increasing the 2DEG concentration, thereby improving the saturation current density and the device FOM (Factor of Merit) of the HEMT device. In addition, the strain layer 40 can also repair the damage to the surface of the semiconductor epitaxial layer 20 (the surface of the barrier layer) caused by the patterning process of the gate structure 30, thereby achieving the effect of reducing the defect state density on the surface of the semiconductor epitaxial layer 20, reducing the dynamic on-resistance, and improving the conversion efficiency of the device.

[0082] The semiconductor device further includes a passivation layer on the side of the strain layer 40 away from the substrate 10 and covering the surfaces of the strain layer 40, the gate electrode 33, and the drain electrode D. The material of the passivation layer includes a dielectric material such as an oxide, which can be SiO2. The passivation layer is used for protection and electrical insulation of the semiconductor device.

[0083] The embodiment of the present application also provides a preparation method of a semiconductor device for preparing the semiconductor device described in any embodiment of the present application. FIG. 6 is a flowchart of a preparation method of a semiconductor device provided by the embodiment of the present application. Referring to FIG. 6, the preparation method of the semiconductor device includes the following steps.

[0084] S110, providing a substrate.

[0085] The substrate 10 can be a semiconductor substrate 10. The material of the substrate 10 can include but is not limited to Si, SiGe, SiC, gallium arsenide, P-doped Si, n-doped Si, sapphire, semiconductor-on-insulator (such as silicon-on-insulator (SOI) or other suitable substrate 10 materials. In some embodiments, the substrate 10 can include, for example but not limited to, group III elements, group IV elements, group V elements or combinations thereof (for example, III-V compounds). In other embodiments, the material of the substrate 10 can include a silicon substrate with <111> orientation.

[0086] S120, forming a semiconductor epitaxial layer on one side of the substrate; the semiconductor epitaxial layer includes a first nitride semiconductor layer and a second nitride semiconductor layer, and the band gap of the first nitride semiconductor layer is different from the band gap of the second nitride semiconductor layer.

[0087] Forming the semiconductor epitaxial layer 20 on one side of the substrate 10 includes sequentially forming a first nitride semiconductor layer 21 and a second nitride semiconductor layer 22 on one side of the substrate 10. The second nitride semiconductor layer 22 has a different bandgap than the first nitride semiconductor layer 21, such that a two-dimensional electron gas heterojunction can be formed between the first nitride semiconductor layer 21 and the second nitride semiconductor layer 22. The material of the first nitride semiconductor layer 21 can include, but is not limited to, a nitride or a III-V compound, such as GaN, AlN, InN, In x Al y Ga (1-x-y) N (where x + y < 1), Al y Ga (1-y) N (where y < 1). The material of the second nitride semiconductor layer 2222 can include, but is not limited to, a III-V nitride semiconductor material, such as GaN, AlGaN, InN, AlInN, InGaN, AlInGaN, or combinations thereof.

[0088] Optionally, before forming the semiconductor epitaxial layer 20 on one side of the substrate 10, further includes forming a buffer layer 11 on one side of the substrate 10. The buffer layer 11 is located between the substrate 10 and the semiconductor epitaxial layer 20, and the buffer layer 11 can be in contact with the semiconductor epitaxial layer 20. The buffer layer 11 is used to reduce the lattice and thermal mismatch between the substrate 10 and the semiconductor epitaxial layer 20, thereby addressing defects due to the mismatch / differences. The buffer layer 11 can include a III-V compound. The III-V compound can include, but is not limited to, aluminum, gallium, indium, nitrogen, or combinations thereof. Thus, exemplary materials of the buffer layer 11 can include, for example, but are not limited to, GaN, AlN, AlGaN, InAlGaN, or combinations thereof. In some embodiments, before forming the buffer layer 11 on one side of the substrate 10, further includes forming a nucleation layer on one side of the substrate 10. The nucleation layer is used to provide a transition to accommodate the mismatch / differences between the substrate 10 and the III-nitride layer of the buffer layer 11. Exemplary materials of the nucleation layer can include, but are not limited to, AlN or any of its alloys.

[0089] S130, forming a gate structure on a side of the semiconductor epitaxial layer away from the substrate; wherein the gate structure includes a cap layer, a compensating doped protection layer and a gate electrode which are sequentially stacked, the compensating doped protection layer and the gate electrode are Schottky contact; the cap layer is doped with first-conductivity-type dopant ions, and the cap layer as a whole exhibits the first conductivity type; the compensating doped protection layer is doped with first-conductivity-type dopant ions and second-conductivity-type dopant ions, and the compensating doped protection layer as a whole exhibits the first conductivity type or electrical neutrality, and the electrical property of the first conductivity type of the cap layer is stronger than that of the first conductivity type of the compensating doped protection layer.

[0090] A cap layer 31, a compensating doped protection layer 32 and a gate electrode 33 are sequentially formed in the gate region of the semiconductor epitaxial layer 20. The cap layer 31 is doped with first-conductivity-type dopant ions, and the cap layer 31 is of the first conductivity type. The compensating doped protection layer 32 is doped with first-conductivity-type dopant ions and second-conductivity-type dopant ions, and the compensating doped protection layer 32 can be of a first conductivity type weaker than the cap layer 31 or neutral. If the first conductivity type is P-type, the second conductivity type is N-type; if the first conductivity type is N-type, the second conductivity type is P-type. In the embodiments of the present application, the first conductivity type is P-type, and the second conductivity type is N-type.

[0091] Exemplary materials of the cap layer 31 can include III-V nitride semiconductor materials, such as gallium nitride, aluminum gallium nitride, indium nitride, aluminum indium nitride, indium gallium nitride, aluminum indium gallium nitride, or a combination thereof. The cap layer 31 and the compensating doped protection layer 32 can be of the same material or different materials. In the embodiments of the present application, the cap layer 31 and the compensating doped protection layer 32 are of the same material to simplify the preparation process of the device.

[0092] Exemplary materials of the gate electrode 33 can include metals or metal compounds. The gate electrode 33 can be formed as a single layer or multiple layers with the same or different compositions. Exemplary materials of the metals or metal compounds can include, for example but not limited to, tungsten (W), gold (Au), palladium (Pd), titanium (Ti), tantalum (Ta), cobalt (Co), nickel (Ni), platinum (Pt), molybdenum (Mo), titanium nitride (TiN), tantalum nitride (TaN), metal alloys, or compounds or other metal compounds thereof.

[0093] The preparation method of the semiconductor device provided by the embodiments of the present application can weaken the electrical property of the first conductivity type of the compensating doped protection layer 32 by forming the compensating doped protection layer 32 between the cap layer 31 and the gate electrode 33 and doping the compensating doped protection layer 32 with first-conductivity-type dopant ions and second-conductivity-type dopant ions at the same time, so that the compensating doped protection layer 32 is configured to provide a relatively low electric field than the cap layer 31, thereby improving the gate electric field distribution, increasing the gate breakdown voltage, and improving the reliability of the gate structure 30.

[0094] Optionally, the step S130 forms the gate structure on the side of the semiconductor epitaxial layer away from the substrate, including:

[0095] In the first stage, a cap layer material is deposited on the side of the semiconductor epitaxial layer away from the substrate, and first-conductivity-type dopant ions are introduced into the growth environment to form the cap layer.

[0096] S1320, in the second stage after the first stage, depositing a compensating doped protective layer material on the side of the semiconductor epitaxial layer away from the substrate, and introducing the first conductive type doping ions and the second conductive type doping ions in the growth environment to form the compensating doped protective layer.

[0097] S1330, forming a gate electrode on the side of the compensating doped protective layer away from the substrate.

[0098] The cap layer material can exemplarily include III-V nitride semiconductor materials, such as gallium nitride, aluminum gallium nitride, indium nitride, aluminum indium nitride, indium gallium nitride, aluminum indium gallium nitride, or a combination thereof. The compensating doped protective layer material can exemplarily include III-V nitride semiconductor materials, such as gallium nitride, aluminum gallium nitride, indium nitride, aluminum indium nitride, indium gallium nitride, aluminum indium gallium nitride, or a combination thereof. Optionally, in the embodiments of the present application, the materials of the cap layer 31 and the compensating doped protective layer 32 are the same, and the preparation of the cap layer 31 and the compensating doped protective layer 32 is realized by controlling the type and amount of the ions introduced in the first stage and the type and amount of the ions introduced in the second stage.

[0099] The first conductive type doping ions are P-type doping ions, and the second conductive type doping ions are N-type doping ions. The P-type doping ions introduced in the first stage include but are not limited to Mg ions, C ions, Fe ions, and Zn ions. In the second stage after the first stage, the P-type doping ions and the N-type doping ions are introduced to form the compensating doped protective layer 32, wherein the P-type doping ions introduced in the second stage include but are not limited to Mg ions, C ions, Fe ions, and Zn ions, and the N-type doping ions introduced include but are not limited to Si ions and O ions.

[0100] In the second stage, the first conductive type doping ions and the second conductive type doping ions are introduced in the growth environment, including: in the second stage, gradually reducing the amount of the first conductive type doping ions introduced, and gradually reducing the amount of the second conductive type doping ions introduced, or uniformly introducing the second conductive type doping ions, or gradually increasing the amount of the second conductive type doping ions introduced.

[0101] Alternatively, in the second stage, the amount of the first conductive type doping ions introduced is uniformly introduced, and the amount of the second conductive type doping ions introduced is gradually increased or the second conductive type doping ions are uniformly introduced.

[0102] Exemplarily, a compensation doped protective layer 32 with gradually reduced P-type ion doping concentration is formed above the P-type cap layer 31. Due to the strong memory effect of Mg, a gradually reduced P-type ion doping concentration is achieved, and the regulation effect can be achieved in steps. The Mg source is gradually reduced until the Mg source is turned off, p-doped is achieved, but these methods are still difficult to achieve p--doped, so some N-type impurities such as Si need to be doped to compensate for Mg, so as to achieve p--doped; in addition, the crystal quality of the surface of the epitaxial layer (the compensation doped protective layer 32) can be improved and the surface roughness can be reduced.

Claims

1. A semiconductor device, comprising: a substrate; a semiconductor epitaxial layer on one side of the substrate; the semiconductor epitaxial layer comprising a first nitride semiconductor layer and a second nitride semiconductor layer; the first nitride semiconductor layer having a different band gap from the second nitride semiconductor layer; a gate structure on a side of the semiconductor epitaxial layer away from the substrate; the gate structure comprising a cap layer, a compensating doped protection layer and a gate electrode arranged in sequence; the compensating doped protection layer and the gate electrode being a Schottky contact; wherein the cap layer is doped with first-conductivity-type dopant ions, and the cap layer as a whole is of the first conductivity type; the compensating doped protection layer is doped with first-conductivity-type dopant ions and second-conductivity-type dopant ions, and the compensating doped protection layer as a whole is of the first conductivity type or electrically neutral, and the first conductivity type of the cap layer is stronger than the first conductivity type of the compensating doped protection layer. At least a portion of the compensating doped protection layer adjacent to the gate electrode is of a weak first conductivity type or electrically neutral. The cap layer and the compensating doped protection layer have the same first-conductivity-type dopant ions, and the first-conductivity-type dopant ion concentration at the top of the cap layer is equal to the first-conductivity-type dopant ion concentration at the bottom of the compensating doped protection layer. The thickness of the compensating doped protection layer is less than the thickness of the cap layer. The thickness ratio of the compensating doped protection layer to the cap layer is between 1:3 and 1:

19.

2. The semiconductor device of claim 1, wherein, The first-conductivity-type dopant ion concentration in the cap layer is greater than or equal to the first-conductivity-type dopant ion concentration in the compensating doped protection layer.

3. The semiconductor device of claim 1, wherein, The first-conductivity-type dopant ion concentration in the compensating doped protection layer gradually decreases along a direction from the cap layer to the gate electrode.

4. The semiconductor device of claim 1, wherein, The second-conductivity-type dopant ion concentration in the compensating doped protection layer gradually increases, is uniformly arranged, or gradually decreases.

5. The semiconductor device of claim 4, wherein, The first-conductivity-type dopant ion concentration in the compensating doped protection layer is uniformly arranged along a direction from the cap layer to the gate electrode.

6. The semiconductor device of claim 1, wherein, The second-conductivity-type dopant ion concentration in the compensating doped protection layer gradually increases or is uniformly arranged.

7. The semiconductor device of claim 6, wherein, The first-conductivity-type dopant ions are P-type dopant ions, and the second-conductivity-type dopant ions are N-type dopant ions. The P-type dopant ions include, but are not limited to, Mg ions, C ions, Fe ions and Zn ions, and the N-type dopant ions include, but are not limited to, Si ions and O ions.

8. The semiconductor device of claim 6, wherein, The material of the cap layer is GaN, and the material of the compensating doped protection layer is at least one of GaN and AlGaN. 12.A method for manufacturing a semiconductor device, comprising: providing a substrate; forming a semiconductor epitaxial layer on one side of the substrate; the semiconductor epitaxial layer comprising a first nitride semiconductor layer and a second nitride semiconductor layer; the first nitride semiconductor layer having a different band gap from the second nitride semiconductor layer.

9. The semiconductor device of claim 1, wherein, ​ 10. The semiconductor device of claim 9, wherein, ​ 11. The semiconductor device of claim 1, wherein, ​ ​ ​ ​ ​ ​ A gate structure is formed on a side of the semiconductor epitaxial layer away from the substrate; wherein the gate structure comprises a cap layer, a compensating doped protection layer and a gate electrode which are sequentially stacked, the compensating doped protection layer and the gate electrode are Schottky contact; the cap layer is doped with first-conductivity-type doping ions, and the cap layer as a whole presents the first conductivity type; the compensating doped protection layer is doped with first-conductivity-type doping ions and second-conductivity-type doping ions, and the compensating doped protection layer as a whole presents the first conductivity type or electrical neutrality, and the first-conductivity-type electrical property of the cap layer is stronger than the first-conductivity-type electrical property of the compensating doped protection layer.

13. The method of producing a semiconductor device according to Claim 12, wherein A gate structure is formed on a side of the semiconductor epitaxial layer away from the substrate, comprising: In the first stage, a cap layer material is deposited on a side of the semiconductor epitaxial layer away from the substrate, and first-conductivity-type doping ions are introduced into a growth environment to form the cap layer; In the second stage after the first stage, a compensating doped protection layer material is deposited on a side of the semiconductor epitaxial layer away from the substrate, and first-conductivity-type doping ions and second-conductivity-type doping ions are introduced into a growth environment to form the compensating doped protection layer; A gate electrode is formed on a side of the compensating doped protection layer away from the substrate.

14. The method of producing a semiconductor device according to Claim 13, wherein A compensating doped protection layer material is deposited on a side of the semiconductor epitaxial layer away from the substrate, and first-conductivity-type doping ions and second-conductivity-type doping ions are introduced into a growth environment to form the compensating doped protection layer, comprising: In the second stage, the introduction amount of the first-conductivity-type doping ions is gradually reduced, and the introduction amount of the second-conductivity-type doping ions is gradually reduced, or the second-conductivity-type doping ions are uniformly introduced, or the introduction of the second-conductivity-type doping ions is gradually increased; Or, in the second stage, the introduction amount of the first-conductivity-type doping ions is uniformly introduced, and the introduction amount of the second-conductivity-type doping ions is gradually increased or the second-conductivity-type doping ions are uniformly introduced.

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