Semiconductor device and method for manufacturing same

Abstract

A method for manufacturing a semiconductor device may comprise the steps of: forming a source electrode and a drain electrode at respective set positions on an epitaxial layer formed on a substrate; forming a first insulating layer on the epitaxial layer; forming a gate electrode between the source electrode and the drain electrode on the upper surface of the epitaxial layer; forming a second insulating layer on the first insulating layer, the source electrode, the drain electrode, and the gate electrode, and etching and planarizing an upper portion of the second insulating layer by an etch-back process; forming a third insulating layer on the second insulating layer and the gate electrode; forming a field plate by etching the second insulating layer and the third insulating layer at a set position between the drain electrode and the gate electrode; and forming a fourth insulating layer for insulating and protecting the field plate.

Description

Semiconductor devices and their manufacturing methods

[0001] The disclosed invention relates to a semiconductor device to which a field plate using an etchback process is applied and a method for manufacturing the same.

[0002] As 5G communications services expand, the need for high-power, high-frequency, wideband, and high-efficiency transistors operating in high-speed switching and high-voltage environments is increasing. Gallium nitride (GaN) transistors, which have emerged to meet these demanding performance requirements, are attracting significant attention due to their high-speed switching performance compared to conventional silicon (Si) transistors, making them suitable for ultra-high-speed signal processing. Furthermore, the material's inherent high-voltage characteristics make them suitable for stable application in high-voltage environments.

[0003] High electron mobility transistors (HEMTs) using gallium nitride (GaN) materials can increase electron mobility by utilizing the two-dimensional electron gas (2DEG) generated at the interface between heterogeneous materials such as AlxGaN / GaN, making them suitable for high-speed signal transmission. In addition, they have a bandgap voltage approximately three times higher and a breakdown field 10 times higher than silicon (Si), ensuring stable operation in high-temperature environments and high operating voltages.

[0004] These high-electron-mobility transistors are undergoing significant efforts to reduce the current collapse phenomenon in order to achieve high output power and power density. Among these efforts, field plates are used to disperse the electric field between the gate and drain. However, in high-frequency devices, the application of field plates generates parasitic capacitance, which degrades frequency characteristics. Therefore, it is necessary to find an appropriate balance between the operating frequency and output power characteristics and optimize them.

[0005] In general, the field plate is formed after the gate electrode and dielectric are formed. At this time, depending on the thickness of the dielectric and the area that the field plate covers the gate electrode, an unnecessary parasitic capacitance component increases, which lowers the maximum operating frequency (cutoff frequency) characteristics of the high electron mobility transistor.

[0006] To reduce these parasitic capacitance components, low-dielectric polyimide or benzocyclobutene (BCB) can be additionally formed after the gate process, but this creates a problem in that the curvature of the substructure for forming the field plate becomes severe, making it difficult to form a precise pattern.

[0007] One aspect of the disclosed invention is to provide a semiconductor device and a method for manufacturing the same, which can freely form a distance between a gate electrode and a field plate greater than the thickness of a dielectric by applying a field plate using an etchback process, thereby reducing unnecessary parasitic capacitance and improving maximum operating frequency characteristics.

[0008] In addition, the present invention aims to provide a semiconductor device and a manufacturing method thereof that can improve the defect rate during production by reducing the failure of microelectrode formation and position alignment that occurs during the manufacturing of a field plate, and can improve high-frequency characteristics by applying multiple layers of materials having different dielectric constants between the upper layer of a gate electrode and the field plate.

[0009] A method for manufacturing a semiconductor device according to one aspect of the disclosed invention may include the steps of: forming a source electrode and a drain electrode at set positions on an epi layer formed on a substrate; forming a first insulating layer on the epi layer to protect a surface and insulate the source electrode and the drain electrode; forming a gate electrode between the source electrode and the drain electrode on an upper surface of the epi layer; forming a second insulating layer on the first insulating layer, the source electrode, the drain electrode, and the gate electrode, and etching an upper portion of the second insulating layer to planarize it using an etch-back process; forming a third insulating layer on the second insulating layer and the gate electrode, wherein the third insulating layer is formed thicker than an electrode length of the gate electrode; etching the second insulating layer and the third insulating layer at a set position between the drain electrode and the gate electrode to form a field plate; and forming a fourth insulating layer to insulate and protect the field plate.

[0010] In the step of forming the above field plate, the field plate can be formed in a partially folded shape on the third insulating layer corresponding to the gate electrode so as to be spaced apart from the gate electrode by a set interval.

[0011] In the step of forming the above field plate, the field plate can be formed by filling the inside of a trench prepared by etching the second insulating layer and the third insulating layer.

[0012] The above field plate can be formed by the second insulating layer and the third insulating layer at a set distance from the gate electrode.

[0013] The separation distance between the field plate and the gate electrode can be set as a separation adjustment value whose range is set according to the length of the gate electrode.

[0014] The first insulating layer may include a capping film material that caps traps on the inside and surface of the epi layer, and may include a material having a higher dielectric constant than the second insulating layer and the third insulating layer.

[0015] The second insulating layer and the third insulating layer may include a material having a dielectric constant of 7.5 or less.

[0016] In the step of forming the above field plate, the inside of a trench prepared by etching the first insulating layer, the second insulating layer, and the third insulating layer can be filled to form the field plate whose lower part is positioned on a position line corresponding to the position of the lower surface of the gate electrode.

[0017] An ohmic recess in the shape of a trench is formed in the above epi layer and an ion implantation region provided at a set position of the above epi layer, and the source electrode and the drain electrode are formed in the ohmic recess as ohmic contacts, so that the lower surfaces of each of the source electrode and the drain electrode can be arranged on a position line corresponding to a channel region through which a two-dimensional electron gas moves in the above epi layer.

[0018] According to another aspect of the disclosed invention, a semiconductor device may include: a substrate; an epi layer provided on the substrate; a source electrode provided on the epi layer; a drain electrode provided on the epi layer and spaced apart from the source electrode; a first insulating layer provided on the epi layer; a gate electrode provided between the source electrode and the drain electrode on an upper surface of the first insulating layer provided on the epi layer; a second insulating layer provided on the first insulating layer, the source electrode, the drain electrode, and the gate electrode; a third insulating layer provided on the second insulating layer and the gate electrode, but thicker than an electrode length of the gate electrode; a field plate disposed on an upper side of the gate electrode at a position set between the drain electrode and the gate electrode; and a fourth insulating layer provided on the third insulating layer and the field plate.

[0019] The above field plate may be provided in a partially folded form on the third insulating layer corresponding to the gate electrode so as to be spaced apart from the gate electrode by a set interval.

[0020] The above field plate can be prepared by filling the inside of a trench prepared by etching the second insulating layer and the third insulating layer.

[0021] The field plate is spaced apart from the gate electrode by a set distance by the second insulating layer and the third insulating layer, and the distance between the field plate and the gate electrode can be set as a distance adjustment value whose range is set according to the length of the gate electrode.

[0022] The above field plate can be placed on a position line where the lower portion thereof corresponds to the position of the lower surface of the gate electrode by filling the inside of a trench prepared by etching the first insulating layer, the second insulating layer, and the third insulating layer.

[0023] The first insulating layer may include a capping film material that caps traps on the inside and surface of the epi layer, and may include a material having a higher dielectric constant than the second insulating layer and the third insulating layer.

[0024] The second insulating layer and the third insulating layer may include a material having a dielectric constant of 7.5 or less.

[0025] According to one aspect of the disclosed invention, a field plate can be formed using an etchback process.

[0026] In addition, according to one aspect of the disclosed invention, the distance between the gate electrode and the field plate can be freely formed to be greater than the thickness of the dielectric without being limited by the separation distance determined by the thickness of the dielectric formed between the gate electrode and the field plate, thereby reducing unnecessary parasitic capacitance and improving the maximum operating frequency characteristics.

[0027] In addition, according to one aspect of the disclosed invention, by using a dielectric and a planarization etch-back process on the upper layer of the gate electrode, the failure of microelectrode formation and position alignment that occurs during the manufacturing of the field plate can be reduced, thereby improving the defect rate during production.

[0028] Additionally, according to one aspect of the disclosed invention, high-frequency characteristics can be improved by applying a material having a low dielectric constant between the upper layer of the gate electrode and the field plate.

[0029] FIG. 1 is a drawing showing a cross-sectional structure of a semiconductor device according to one embodiment of the present invention.

[0030] FIG. 2 is a drawing showing a part of a planar structure of a semiconductor device according to one embodiment of the present invention.

[0031] FIG. 3 is a drawing showing a cross-sectional structure of a semiconductor device according to another embodiment of the present invention.

[0032] FIGS. 4A to 4S are drawings showing a method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0033] FIGS. 5A to 5I are drawings showing a method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0034] Throughout the specification, the same reference numerals denote the same components. This specification does not describe all elements of the embodiments, and any content that is general in the technical field to which the disclosed invention belongs or that overlaps between the embodiments is omitted. The terms 'part, module, element, block' used in the specification may be implemented in software or hardware, and depending on the embodiments, multiple 'parts, modules, elements, blocks' may be implemented as a single component, or a single 'part, module, element, block' may include multiple components.

[0035] Throughout the specification, when a part is said to be 'connected' to another part, this includes not only direct connection but also indirect connection, and indirect connection includes connection via a wireless communication network.

[0036] Additionally, when a part is said to 'include' a component, this does not mean that it excludes other components, but rather that it may include other components, unless otherwise specifically stated.

[0037] Throughout the specification, when we say that an element is located 'on' another element, this includes not only cases where the element is in contact with the other element, but also cases where another element exists between the two elements.

[0038] The terms first, second, etc. are used to distinguish one component from another, and the components are not limited by the aforementioned terms.

[0039] Singular expressions include plural expressions unless the context clearly indicates otherwise.

[0040] The identification codes for each step are used for convenience of explanation and do not describe the order of each step. Each step may be performed in a different order than specified unless the context clearly indicates a specific order.

[0041] Hereinafter, the operating principle and embodiments of the disclosed invention will be described with reference to the attached drawings.

[0042] Fig. 1 is a drawing showing a cross-sectional structure of a semiconductor device according to one embodiment of the present invention. Fig. 2 is a drawing showing a portion of a planar structure of a semiconductor device according to one embodiment of the present invention.

[0043] Referring to FIGS. 1 and 2, a semiconductor device according to one embodiment of the present invention may include a substrate (110), an epi layer (120), a plurality of ion implantation regions (130), a source electrode (160), a drain electrode (170), a gate electrode (180), a plurality of isolation regions (200), an insulating layer (210), a field plate (190), and a lower conductive layer (320).

[0044] The substrate (110) may be a silicon carbide (SiC) substrate, a silicon (Si) substrate, or a sapphire (Al2O3) substrate.

[0045] The epi layer (120) is a nitride semiconductor layer and may include a first compound semiconductor layer (121) and a second compound semiconductor layer (122) sequentially arranged on top of the substrate (110).

[0046] The first compound semiconductor layer (121) is a buffer layer and may be formed of a layer including gallium nitride (GaN), aluminum gallium nitride (AlGaN), or aluminum nitride (AlN).

[0047] The second compound semiconductor layer (122) is a barrier layer and may be formed of one or more layers including one or more selected from gallium nitride (GaN) and aluminum gallium nitride (AlGaN). For example, the second compound semiconductor layer (122) may be a gallium nitride (GaN) layer, Al x Ga y N(x+y=1) layers, Al x In y N(x+y=1) layer and Al x In y Ga z It can be formed by two or more multilayers among N(x+y+z=1) layers.

[0048] The first compound semiconductor layer (121) can have a channel region (125) formed by a two-dimensional electron gas (2DEG) generated at the top of the first compound semiconductor layer (121) through heterojunction with the second compound semiconductor layer (122).

[0049] The epilayer (120) can be grown on the substrate (110) using various known methods such as MOCVD (Metal-Organic Chemical Vapor Deposition), MBE (Molecular Beam Epitaxy), and HVPE (Hydride Vapor Phase Epitaxy). At this time, the growth height of the epilayer (120) can be set to about 0.1 μm to about 5 μm. More preferably, the epilayer (120) can be set to a total thickness of about 2 μm.

[0050] A plurality of ion implantation regions (130) may be provided at a plurality of set positions of the epi layer (120). Specifically, the plurality of ion implantation regions (130) may be arranged at positions corresponding to the source electrode (160) and the drain electrode (170), respectively. For example, the plurality of ion implantation regions (130) may be provided in the epi layer (120) located below each of the source electrode (160) and the drain electrode (170), respectively. At this time, each of the plurality of ion implantation regions (130) may be provided to have a size corresponding to or larger than the area in which each of the source electrode (160) and the drain electrode (170) is in contact with the first compound semiconductor layer (121).

[0051] Additionally, a plurality of ion implantation regions (130) can be prepared by implanting an n-type dopant into at least a portion of the epi layer (120). Here, high-temperature annealing at about 1000°C or higher can be performed to activate the n-type dopant implanted into the epi layer (120).

[0052] The source electrode (160) may include a conductive material and be provided at a set position on the first compound semiconductor layer (121). Here, a portion of the source electrode (160) may be provided inside a first trench (140) formed through the second compound semiconductor layer (122) to the first compound semiconductor layer (121). In addition, the source electrode (160) may be disposed on the upper portion of the ion implantation region (130) exposed by the first trench (140). In addition, a portion of the area of ​​the source electrode (160) may be in contact with the second compound semiconductor layer (122). The source electrode (160) may be electrically connected to the lower conductive layer (320) through a via hole (310) formed on the back surface of the substrate (110). A conductive material may be formed inside the via hole (310) so that the source electrode (160) and the lower conductive layer (320) may be electrically connected. The lower conductive layer (320) is a metal layer that connects the upper source electrode (160) and the lower ground electrode, and can be prepared by depositing or plating at least one of titanium (Ti) and gold (Au) or an alloy thereof.

[0053] The drain electrode (170) includes a conductive material and may be provided at a set position on the first compound semiconductor layer (121) spaced apart from the source electrode (160). Here, the drain electrode (170) may be provided inside a first trench (140) formed so that a portion thereof passes through the second compound semiconductor layer (122) to the first compound semiconductor layer (121). In addition, the drain electrode (170) may be disposed on an upper portion of an ion implantation region (130) exposed by the first trench (140). In addition, a portion of the area of ​​the drain electrode (170) may be in contact with the second compound semiconductor layer (122). Here, the areas where the source electrode (160) and the drain electrode (170) are in contact with the second compound semiconductor layer (122) may be the same or different depending on the transistor design.

[0054] Here, the drain electrode (170) may be formed in multiple layers to withstand high current and RF power while lowering contact resistance. As an example, the drain electrode (170) may include a first drain electrode layer (171) and a second drain electrode layer (172). At this time, each of the first drain electrode layer (171) and the second drain electrode layer (172) may include at least one of titanium (Ti), silicon (Si), nickel (Ni), platinum (Pt), and gold (Au), or an alloy thereof.

[0055] The first trench (140) can be prepared by etching the epi layer (120) and the ion implantation region (130) until a portion of the ion implantation region (130) remains. At this time, the first trench (140) can be prepared corresponding to the positions of the source electrode (160) and the drain electrode (170), respectively.

[0056] Meanwhile, in the case of a non-recessed ohmic contact, the source electrode (160) and the drain electrode (170) are formed at a location far from the channel region (125) through which the two-dimensional electron gas (2DEG) moves, so that the contact resistance becomes relatively large.

[0057] On the other hand, as in the present invention, if an ohmic recess is selectively formed in the epi layer (120) and the ion implantation region (130), and a source electrode (160) and a drain electrode (170) are formed in the formed ohmic recess as ohmic contacts, the source electrode (160) and the drain electrode (170) are formed relatively close to the channel region (125) through which the two-dimensional electron gas (2DEG) moves, so that the contact resistance becomes relatively small. Accordingly, the contact ability with the metal forming the source electrode (160) and the drain electrode (170) can be improved.

[0058] The gate electrode (180) includes a conductive material and can be provided on the upper surface of the second compound semiconductor layer (122) between the source electrode (160) and the drain electrode (170).

[0059] An isolation region (200) can be provided at a set location of the epi layer (120) for isolation between adjacent semiconductor elements.

[0060] The isolation region (200) can prevent the formation of an unwanted channel region in the epi layer (120). The isolation region (200) can serve as an electrical barrier to block leakage current generation in a semiconductor device. For example, the isolation region (200) can be expanded by a set volume in a portion of the epi layer (120), so that a two-dimensional electron gas (2DEG) can be formed only in the channel region (125) through which the two-dimensional electron gas (2DEG) moves. In addition, the isolation region (200) can also be provided through etching of the epi layer (120).

[0061] The insulating layer (210) insulates the epi layer (120), minimizes traps that may act as defects on the surface of the epi layer (120), weakens current collapse, and protects against external force. In addition, the insulating layer (210) may include silicon nitride (SiN), silicon oxide (SiO2), silicon oxynitride (SiON), hafnium oxide (HfO2), aluminum nitride (AlN), and a nitride or oxide combined therewith.

[0062] Specifically, the insulating layer (210) may include a first insulating layer (220), a second insulating layer (230), a third insulating layer (240), and a fourth insulating layer (250) for insulation and protection of the epi layer (120).

[0063] The first insulating layer (220) is provided on the second compound semiconductor layer (122) and can insulate and protect the source electrode (160), the drain electrode (170), and the gate electrode (180). The first insulating layer (220) can be provided so that a portion of each of the source electrode (160), the drain electrode (170), and the gate electrode (180) is exposed.

[0064] Here, as an example of the insulating layer (210), the first insulating layer (220) can be formed of a capping film material that can cap traps that can act as defects on the interior and surface of the epi layer (120) and weaken current collapse.

[0065] The capping film material may include silicon nitride (SiN), silicon oxide (SiO2), silicon oxynitride (SiON), hafnium oxide (HfO2), aluminum nitride (AlN), and nitrides or oxides thereof. In particular, a material having a higher dielectric constant than the materials of the second insulating layer (230) and the third insulating layer (240), such as an oxide including hafnium oxide (HfO2) or a nitride including hafnium oxide (HfO2), is suitable as the capping film material.

[0066] Next, the second insulating layer (230) may be provided so that at least a portion of each of the source electrode (160), the drain electrode (170), and the gate electrode (180) is exposed on the first insulating layer (220). The second insulating layer (230) may be provided to have a thickness equal to or relatively thicker than the electrode height of the gate electrode (180) in consideration of a planarization etching process (e.g., an etch-back process) performed in a subsequent process of the first insulating layer (220) and the gate electrode (180). The second insulating layer (230) may be made of a nitride or an oxide for insulation between the source electrode (160), the drain electrode (170), and the gate electrode (180).

[0067] The third insulating layer (240) may be provided on the second insulating layer (230) and the gate electrode (180), the upper portion (surface) of which is etched and planarized by an etch-back process. The third insulating layer (240) may be provided so that at least a portion of each of the source electrode (160) and the drain electrode (170) is exposed. The third insulating layer (240) may be made of a nitride or an oxide for insulation between the gate electrode (180) and the field plate (190).

[0068] The fourth insulating layer (250) may be provided on the third insulating layer (240) and the field plate (190). The fourth insulating layer (250) may be provided so that at least a portion of each of the source electrode (160) and the drain electrode (170) is exposed. The fourth insulating layer (250) may be made of a nitride or oxide for insulation and protection of the field plate (190).

[0069] Here, each of the second insulating layer (230) and the third insulating layer (240) may be formed of a material having a relatively lower dielectric constant than the first insulating layer (220) and the fourth insulating layer (250). However, it is preferable that each of the second insulating layer (230) and the third insulating layer (240) have a lower dielectric constant than the first insulating layer (220) and the fourth insulating layer (250), but this is not limited thereto.

[0070] In another embodiment of the insulating layer (210), each of the second insulating layer (230) and the third insulating layer (240) may include a material having a dielectric constant of about 7.5 or less, such as fluorine-doped silicon dioxide, carbon-doped silicon dioxide, porous carbon-doped silicon dioxide, spin-on organic polymeric dielectrics, spin-on silicon based polymeric dielectric, polyimide, benzocyclobutene (BCB), and a nitride or oxide combined therewith.

[0071] The field plate (190) may be positioned above the gate electrode (180) and spaced apart from the gate electrode (180) by a set distance to increase the breakdown voltage of the transistor element. In addition, the field plate (190) may be connected to the source electrode (160) as illustrated in FIG. 2.

[0072] Specifically, the field plate (190) can be spaced apart from the gate electrode (180) by a set distance by the second insulating layer (230) and the third insulating layer (240) that are planarized using an etch-back process. Here, the separation distance between the field plate (190) and the gate electrode (180) can be set by a separation adjustment value (Y). As the field plate (190) moves away from the gate electrode (180), the breakdown voltage by the field plate (190) gradually increases and then becomes saturated, and when it exceeds the set range, the breakdown voltage characteristics of the semiconductor device are no longer improved. Furthermore, if the field plate (190) is spaced too far from the gate electrode (180), the maximum breakdown voltage may actually decrease.

[0073] Accordingly, the separation adjustment value (Y) may vary depending on the gate length (Lg) and the structure of the semiconductor device. If the operating frequency of the semiconductor device is the S-band (about 2 GHz to about 4 GHz), the separation distance between the gate electrode (180) and the field plate (190) may be set to about 0.5 times or more of the gate length (Lg), and if the operating frequency of the semiconductor device is the X-band (about 8 GHz to about 12 GHz), the separation distance between the gate electrode (180) and the field plate (190) may be set to about 1 times or more of the gate length (Lg). Additionally, the separation adjustment value (Y) should be at least equal to or greater than the thickness of the second insulating layer (230), but may be set to less than three times the gate length (Lg).

[0074] The field plate (190) applied to a conventional semiconductor device is formed according to the curvature of the gate electrode (180) and the first insulating layer (220). At this time, there was a problem in that the parasitic capacitance increased depending on the thickness of the first insulating layer (220) and the area that the field plate (190) covers the gate electrode (180), thereby lowering the maximum operating frequency (cutoff frequency) characteristics of the semiconductor device.

[0075] In order to solve these problems, in the present invention, the separation distance between the gate electrode (180) and the field plate (190) can be adjusted to a desired condition according to the operating frequency band of the semiconductor device, thereby reducing unnecessary parasitic capacitance and improving the maximum operating frequency characteristics. If the separation adjustment value (Y) increases to more than three times the gate length (Lg), the field plate (190) may no longer be able to increase the breakdown voltage.

[0076] The field plate (190) can be formed by filling the inside of a trench prepared by etching the second insulating layer (230) and the third insulating layer (240) at a position corresponding to the gate electrode (180) and patterning it in a preset pattern. For example, the field plate (190) can be formed in a partially bent shape on the third insulating layer (240) corresponding to the gate electrode (180) so as to be spaced apart from the gate electrode (180) by a preset interval. In addition, the field plate (190) can include at least one material selected from the group consisting of nickel (Ni), tungsten (W), titanium (Ti), copper (Cu), and gold (Au), or an alloy thereof.

[0077] The field plate (190) can be freely adjusted in distance from the gate electrode (180) without being affected by the thickness of the third insulating layer (240), thereby reducing the parasitic capacitance occurring between the field plate (190) and itself, thereby improving the maximum operating frequency.

[0078] Meanwhile, referring to FIG. 3, a semiconductor device according to another embodiment of the present invention may be formed in a form in which a field plate (190) fills the inside of a trench prepared by etching the first insulating layer (220), the second insulating layer (230), and the third insulating layer (240) at a position corresponding to the gate electrode (180). At this time, the lower part of the field plate (190) filling the inside of the trench may be positioned on a position line substantially corresponding to the position of the lower surface of the gate electrode (180). In addition, the field plate (190) may include at least one material selected from the group consisting of nickel (Ni), tungsten (W), titanium (Ti), copper (Cu), and gold (Au), or an alloy thereof. Through this, the field plate (190) may have the effect of dispersing an electric field concentrated at the edge of the gate electrode (180).

[0079] In addition, the source electrode (160) may be formed in multiple layers to withstand high current and RF power while lowering the contact resistance, like the drain electrode (170). Here, the source electrode (160) may include a first source electrode layer (161) and a second source electrode layer (162). At this time, each of the first source electrode layer (161) and the second source electrode layer (162) may include at least one of titanium (Ti), silicon (Si), nickel (Ni), platinum (Pt), and gold (Au), or an alloy thereof.

[0080] Hereinafter, a method for manufacturing a semiconductor device according to an embodiment of the present invention will be described step by step. The method includes: a step of forming an epi layer on a substrate; a step of forming an ion implantation region at a set position of the epi layer; a high-temperature heat treatment step for activating an n-type dopant implanted in the epi layer; a step of etching a portion of the epi layer and a portion of the ion implantation region to form a plurality of trenches; a step of forming a selected one of a source electrode and a drain electrode in each of a plurality of preset trenches; a step of forming an isolation region at a set position of the epi layer; a step of forming a gate electrode at a set position of the epi layer; a step of forming a first insulating layer that insulates the source electrode, the drain electrode, and the gate electrode on the epi layer; a step of forming a second insulating layer on the first insulating layer, the source electrode, the drain electrode, and the gate electrode, and etching and planarizing the upper portion of the second insulating layer by an etch-back process; a step of forming a third insulating layer on the second insulating layer and the gate electrode; and a process of etching and filling at least a portion of each of the second insulating layer and the third insulating layer at a set position between the drain electrode and the gate electrode. The method may include a step of forming a field plate, a step of forming a fourth insulating layer that insulates and protects the field plate, a step of etching a portion of the second insulating layer, the third insulating layer, and the fourth insulating layer so that an upper portion of the drain electrode is exposed, and a step of depositing or plating a conductive material on the drain electrode to form a multi-layered drain electrode, a step of etching a back surface of a substrate to form a via hole, and a step of forming a lower conductive layer connected to the via hole on the back surface of the substrate.

[0081] Hereinafter, a method for manufacturing a semiconductor device according to an embodiment of the present invention will be described in detail with reference to FIGS. 4a to 4s.

[0082] FIGS. 4A to 4S are drawings showing a method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0083] First, referring to FIG. 4a, an epi layer (120) can be formed on the upper portion of the substrate (110). Specifically, a first compound semiconductor layer (121) including gallium nitride (GaN) and a second compound semiconductor layer (122) including at least one selected from gallium nitride (GaN) and aluminum gallium nitride (AlGaN) can be sequentially formed on the upper portion of the substrate (110). For example, the second compound semiconductor layer (122) can be formed of a gallium nitride (GaN) layer, an Al x Ga y N(x+y=1) layers, Al x In y N(x+y=1) layer and Al x In y Ga z It can be formed by two or more multilayers among N(x+y+z=1) layers.

[0084] Here, the epi layer (120) can be formed on the upper portion of the substrate (110) at a growth height of about 0.1 μm to about 5 μm using various known methods such as MOCVD (Metal-Organic Chemical Vapor Deposition), MBE (Molecular Beam Epitaxy), and HVPE (Hydride Vapor Phase Epitaxy).

[0085] Next, referring to FIG. 4b, a plurality of ion implantation regions (130) can be formed by implanting an n-type dopant at a set location of the epi layer (120). For example, an ion implantation mask pattern can be formed on the upper portion of the epi layer (120) to expose a portion of the epi layer (120), and then Si+ ions can be implanted to form a plurality of ion implantation regions (130). Through this process, a plurality of ion implantation regions (130) can be formed in a set volume in the first compound semiconductor layer (121) and the second compound semiconductor layer (122).

[0086] In addition, after forming a plurality of ion implantation regions (130), an insulating material made of a nitride or oxide such as silicon nitride (SiN), silicon oxide (SiO2), or aluminum nitride (AlN) may be deposited over the entire surface of the substrate (110) to form an insulating layer (not shown) on the upper portion of each of the epi layer (120) and the plurality of ion implantation regions (130). In addition, the insulating layer (not shown) may include various materials such as hafnium oxide (HfO2), which can reduce surface traps of the epi layer (120) and the plurality of ion implantation regions (130) and reduce thermal shock due to temperature change without exposing the upper portion of the plurality of ion implantation regions (130) and the epi layer (120).

[0087] Here, the insulating layer (not shown) can be formed of a capping film material capable of capping internal and surface traps. The capping film material can include silicon nitride (SiN), silicon oxide (SiO2), silicon oxynitride (SiON), hafnium oxide (HfO2), aluminum nitride (AlN), and nitrides or oxides combined therewith. In particular, a material having a preset dielectric constant as a capping film material, such as an oxide including hafnium oxide (HfO2) or a nitride including hafnium oxide (HfO2), is suitable.

[0088] Meanwhile, depending on the process settings, an insulating layer (not shown) may be formed before the formation of multiple ion implantation regions (130), or may be formed after the formation of multiple ion implantation regions (130). Here, high-temperature annealing at about 1000°C or higher may be performed to activate the n-type dopant implanted into the epi layer (120).

[0089] Next, referring to FIG. 4c, a portion of the insulating layer (not shown) may be removed to expose a portion of the epi layer (120). Specifically, in the area where the source electrode (160) and the drain electrode (170) are to be formed among the insulating layer (not shown) deposited on the upper surface of the epi layer (120) and the upper surface of the plurality of ion implantation regions (130), a portion of the epi layer (120) and an upper portion of each of the plurality of ion implantation regions (130) may be exposed.

[0090] In addition, a portion of the exposed epi layer (120) and an upper portion of each of the plurality of ion implantation regions (130) may be removed to form a plurality of first trenches (140). Meanwhile, when removing the insulating layer (not shown), a portion of the second compound semiconductor layer (122) may also be removed, thereby further reducing the ohmic contact resistance.

[0091] In the case where an ohmic contact is formed without being recessed, i.e., without forming a first trench (140), the source electrode (160) and the drain electrode (170) are formed at a position far from the channel region (125) through which the two-dimensional electron gas (2DEG) moves, so that the contact resistance may be relatively high. On the other hand, as in the present invention, when an ohmic recess in the shape of a first trench (140) is formed in the epi layer (120) and the ion implantation region (130) and the source electrode (160) and the drain electrode (170) are formed as an ohmic contact, the source electrode (160) and the drain electrode (170) may be formed at a position relatively close to the channel region (125) through which the two-dimensional electron gas (2DEG) moves.

[0092] Next, referring to FIG. 4d, a source electrode (160) and a drain electrode (170) can be formed at set positions among a plurality of first trenches (140). For example, at least one of titanium (Ti), silicon (Si), nickel (Ni), platinum (Pt), and gold (Au) or an alloy thereof can be deposited or plated on the upper portion of the epi layer (120) on which a plurality of first trenches (140) are formed, and then patterned in a preset pattern to form a first drain electrode layer (171) of the source electrode (160) and the drain electrode (170). At this time, each of the source electrode (160) and the drain electrode (170) can be formed by filling the interior of the first trench (140).

[0093] Additionally, before or after patterning, a heat treatment such as a rapid thermal annealing process may be performed to reduce the electrical contact resistance of the source electrode (160), the drain electrode (170), and the ion implantation region (130).

[0094] In addition, an isolation region (200) may be formed through an ion implantation process or etching of an epi layer (120) for an electrical isolation process to prevent leakage current from occurring outside the semiconductor device. At this time, the isolation region (200) may be formed with a volume set in the outer portion of a plurality of repeatedly arranged source electrodes (160) and drain electrodes (170). The electrical isolation process may be performed before forming a trench after ion implantation and high-temperature heat treatment to reduce ohmic contact resistance.

[0095] Next, referring to FIG. 4e, a first insulating layer (220) may be formed to reduce surface traps that may act as defects on the epi layer (120), minimize current collapse, and protect and insulate the source electrode (160) and the drain electrode (170). For example, a first insulating layer (220) made of a nitride or oxide may be deposited on the epi layer (120), the source electrode (160), and the drain electrode (170), and a portion of the first insulating layer (220) may be etched so that an upper portion of the source electrode (160) and the drain electrode (170) is exposed.

[0096] Here, the first insulating layer (220) can be formed of a capping film material capable of capping surface traps. The capping film material can include silicon nitride (SiN), silicon oxide (SiO2), silicon oxynitride (SiON), hafnium oxide (HfO2), aluminum nitride (AlN), and nitrides or oxides combined therewith. In particular, a material having a higher dielectric constant than the material of the second insulating layer (230 in FIG. 4g) and the third insulating layer (240 in FIG. 4j) to be formed through a subsequent process as the capping film material, for example, an oxide including hafnium oxide (HfO2) is suitable.

[0097] Next, referring to FIG. 4f, after etching the first insulating layer (220) at a position between the source electrode (160) and the drain electrode (170), the gate electrode (180) can be formed. For example, the gate electrode (180) can be formed by depositing or plating at least one of nickel (Ni), tungsten (W), titanium (Ti), tantalum (Ta), tantalum nitride (TaN), molybdenum (Mo), iridium (Ir), platinum (Pt), and gold (Au) or an alloy thereof over the entire surface of the substrate (110) and then patterning the deposited layer in a preset pattern. At this time, the gate electrode (180) can be formed on the epi layer (120) between the source electrode (160) and the drain electrode (170).

[0098] Next, referring to FIG. 4g, a second insulating layer (230) can be formed on the first insulating layer (220), the source electrode (160), the drain electrode (170), and the gate electrode (180). For example, a second insulating layer (230) made of a nitride or oxide can be deposited on the first insulating layer (220), the source electrode (160), the drain electrode (170), and the gate electrode (180).

[0099] Next, referring to FIG. 4h, the upper portion of the second insulating layer (230) may be etched using an etch-back process to planarize the second insulating layer (230) as shown in FIG. 4i. For example, the upper portion of the second insulating layer (230) may be etched using an etch-back process to a thickness or depth set to expose the upper portion of the gate electrode (180) to planarize it.

[0100] Next, referring to FIG. 4j, a third insulating layer (240) may be formed on the second insulating layer (230) and the gate electrode (180). For example, a third insulating layer (240) made of a nitride or oxide may be deposited on the second insulating layer (230) and the gate electrode (180). Here, the third insulating layer (240) may be formed with a set thickness on the second insulating layer (230) and the gate electrode (180) to provide insulation between the gate electrode (180) and a field plate (190 of FIG. 4o) to be formed in a subsequent process.

[0101] Next, referring to FIG. 4k, a second trench (142) or a third trench (144) may be formed through a patterning process of etching the second insulating layer (230) and the third insulating layer (240) at a set first position (①) or a set second position (②) between the drain electrode (170) and the gate electrode (180). At this time, each of the first position (①) and the second position (②) may be set to a position spaced apart from the gate electrode (180) by a set distance in order to form a field plate (190 of FIG. 4o).

[0102] Here, for convenience of explanation, the subsequent process is described based on the third trench (144) formed at the second position (②).

[0103] Next, referring to FIG. 4l, a photoresist layer (410) can be formed using photoresist (PR) on the third trench (144) and the third insulating layer (240).

[0104] Next, referring to FIG. 4m, a photomask (420) may be placed on a photoresist layer (410) in a set pattern, and an exposure process may be performed using the photomask (420).

[0105] Next, referring to FIG. 4n, the photomask (420) may be removed, and the exposed area may be developed to form a photoresist layer (410) having a patterning area (146) formed therein to form a third trench (144) and a field plate (190 of FIG. 4o). Here, the patterning area (146) may be formed by removing the exposed area of ​​the photoresist layer (410).

[0106] Next, referring to FIG. 4o, a field plate (190) may be formed by filling the third trench (144) and the patterning region (146) with at least one material selected from the group consisting of nickel (Ni), tungsten (W), titanium (Ti), copper (Cu), and gold (Au) or an alloy thereof by deposition or plating. As a method for forming the field plate (190), the field plate (190) may be deposited or plated in the third trench (144) and the patterning region (146) through electron beam evaporation, a sputtering process, plating, or the like.

[0107] The field plate (190) can be formed in a partially folded shape on the third insulating layer (240) corresponding to the gate electrode (180) so as to be spaced apart from the gate electrode (180) by a set interval.

[0108] The field plate (190) can be formed by separating a set distance from the gate electrode (180) by a second insulating layer (230) and a third insulating layer (240) that are flattened using an etch-back process. Here, the separation distance between the field plate (190) and the gate electrode (180) can be set by a separation adjustment value (Y).

[0109] In addition, the separation adjustment value (Y) may vary depending on the gate length (Lg) and the structure of the semiconductor device. If the operating frequency of the semiconductor device is the S-band (about 2 GHz to about 4 GHz), the separation distance between the gate electrode (180) and the field plate (190) may be set to about 0.5 times or more of the gate length (Lg), and if the operating frequency of the semiconductor device is the X-band (about 8 GHz to about 12 GHz), the separation distance between the gate electrode (180) and the field plate (190) may be set to about 1 times or more of the gate length (Lg). Additionally, the separation adjustment value (Y) should be at least equal to or greater than the thickness of the second insulating layer (230), and may be set to less than three times the gate length (Lg). If the spacing adjustment value (Y) increases to more than three times the gate length (Lg), the field plate (190) may no longer be able to increase the breakdown voltage.

[0110] Next, referring to FIG. 4p, the photoresist layer (410) on the third insulating layer (240) can be removed, and the field plate (190) can be completed.

[0111] Here, the distance between the gate electrode (180) and the field plate (190) can be freely adjusted without being affected by the thickness of the third insulating layer (240), thereby reducing the parasitic capacitance occurring between the gate electrode (180) and the field plate (190) and improving the maximum operating frequency.

[0112] Next, referring to FIG. 4q, a fourth insulating layer (250) can be formed on the third insulating layer (240) and the field plate (190). Specifically, a fourth insulating layer (250) made of a nitride or oxide can be deposited on the third insulating layer (240) and the field plate (190). Through this, a protective film that protects the field plate (190) can be formed.

[0113] Next, referring to FIG. 4r, at least a portion of each of the second insulating layer (230), the third insulating layer (240), and the fourth insulating layer (250) is etched so that the upper portion of the first drain electrode layer (171) of the drain electrode (170) is exposed, and a predetermined conductive material is deposited by plating or electron beam evaporation to form the second drain electrode layer (172). Through this, a drain electrode (170) composed of multiple layers can be formed.

[0114] Next, referring to FIG. 4s, a via hole (310) is formed by etching the back surface of the substrate (110) to expose the lower surface of the source electrode (160), and at least one of nickel (Ni), tungsten (W), titanium (Ti), tantalum (Ta), tantalum nitride (TaN), and gold (Au) or an alloy thereof is deposited or plated on the via hole (310) and the back surface of the substrate (110) to form a lower conductive layer (320).

[0115] However, before forming the via hole (310), the lower surface of the substrate (110) may be processed to reduce the thickness of the substrate (110). For example, the lower surface of the substrate (110) may be polished to have a thickness of about 50 μm to about 120 μm, and the polishing method may use a mechanical or chemical treatment method.

[0116] Additionally, the lower conductive layer (320) may be patterned in a pattern set according to the circuit design. For example, the lower conductive layer (320) may be patterned in a pattern that commonly connects the source electrode (160) through a via hole (310) to perform a set function.

[0117] Hereinafter, a method for manufacturing a semiconductor device according to another embodiment of the present invention will be described in detail with reference to FIGS. 5A to 5D. For convenience, a redundant description will be omitted based on the method for manufacturing a semiconductor device according to one embodiment of the present invention described with reference to FIGS. 4A to 4S.

[0118] Referring to FIG. 5A, a second trench (142) or a third trench (144) can be formed through a patterning process of etching at least a portion of each of the first insulating layer (220), the second insulating layer (230), and the third insulating layer (240). Here, for convenience of explanation, the subsequent process is described based on the third trench (144) formed at the second location (②).

[0119] Next, referring to FIG. 5b, a photoresist layer (410) can be formed using photoresist (PR) on the third trench (144) and the third insulating layer (240).

[0120] Next, referring to FIG. 5c, a photomask (420) may be placed on a photoresist layer (410) in a set pattern, and an exposure process may be performed using the photomask (420).

[0121] Next, referring to FIG. 5d, the photomask (420) may be removed, and the exposed area may be developed to form a photoresist layer (410) having a patterning area (146) formed therein to form a third trench (144) and a field plate (190 of FIG. 5e). Here, the patterning area (146) may be formed by removing the exposed area of ​​the photoresist layer (410).

[0122] Next, referring to FIG. 5e, a field plate (190) may be formed by filling the third trench (144) and the patterning region (146) with at least one material selected from the group consisting of nickel (Ni), tungsten (W), titanium (Ti), copper (Cu), and gold (Au) or an alloy thereof by deposition or plating. The field plate (190) may be formed in a partially folded shape on the third insulating layer (240) corresponding to the gate electrode (180) so as to be spaced apart from the gate electrode (180) by a set interval.

[0123] Next, referring to FIG. 5f, the photoresist layer (410) on the third insulating layer (240) can be removed, and the field plate (190) can be completed. Here, the distance between the gate electrode (180) and the field plate (190) can be freely adjusted without being affected by the thickness of the third insulating layer (240), thereby reducing the parasitic capacitance occurring between the gate electrode (180) and the field plate (190), thereby improving the maximum operating frequency.

[0124] The lower portion of the field plate (190) filling the interior of the third trench (144) can be positioned on a position line that substantially corresponds to the position of the lower surface of the gate electrode (180). Through this, the field plate (190) can exert an effect of dispersing an electric field concentrated at the edge of the gate electrode (180).

[0125] Next, referring to FIG. 5g, a fourth insulating layer (250) can be formed on the third insulating layer (240) and the field plate (190). Specifically, a fourth insulating layer (250) made of a nitride or oxide can be deposited on the third insulating layer (240) and the field plate (190). Through this, a protective film that protects the field plate (190) can be formed.

[0126] Next, referring to FIG. 5h, at least a portion of each of the second insulating layer (230), the third insulating layer (240), and the fourth insulating layer (250) is etched so that the upper portion of the first drain electrode layer (171) of the drain electrode (170) is exposed, and a predetermined conductive material is deposited by plating or electron beam evaporation to form a second drain electrode layer (172). Through this, a drain electrode (170) composed of multiple layers can be formed.

[0127] Next, referring to FIG. 5i, a via hole (310) is formed by etching the back surface of the substrate (110) to expose the lower surface of the source electrode (160), and at least one of nickel (Ni), tungsten (W), titanium (Ti), tantalum (Ta), tantalum nitride (TaN), and gold (Au) or an alloy thereof is deposited or plated on the via hole (310) and the back surface of the substrate (110) to form a lower conductive layer (320).

[0128] However, before forming the via hole (310), the lower surface of the substrate (110) may be processed to reduce the thickness of the substrate (110). For example, the lower surface of the substrate (110) may be polished to have a thickness of about 50 μm to about 120 μm, and the polishing method may use a mechanical or chemical treatment method.

[0129] Additionally, the lower conductive layer (320) may be patterned in a pattern set according to the circuit design. For example, the lower conductive layer (320) may be patterned in a pattern that commonly connects the source electrode (160) through a via hole (310) to perform a set function.

[0130] According to the present invention, a field plate can be formed using an etchback process.

[0131] Specifically, the distance between the gate electrode and the field plate can be freely adjusted regardless of the thickness of the dielectric formed between the gate electrode and the field plate, thereby reducing the parasitic capacitance occurring between the gate electrode and the field plate and improving the maximum operating frequency. In addition, by using a dielectric and a planarization etch-back process on the upper layer of the gate electrode, the failure of micro-electrode formation and position alignment that occurs during the manufacturing of the field plate can be reduced, thereby improving the defect rate during production. In addition, high-frequency characteristics can be improved by applying a material with a low dielectric constant between the upper layer of the gate electrode and the field plate.

[0132] The disclosed embodiments have been described with reference to the attached drawings. Those skilled in the art will understand that the present invention can be implemented in forms other than the disclosed embodiments without altering the technical spirit or essential features of the present invention. The disclosed embodiments are illustrative and should not be construed as limiting.

Claims

1. A step of forming a source electrode and a drain electrode at a set position on an epi layer formed on a substrate; A step of forming a first insulating layer on the epi layer to protect the surface and insulate the source electrode and the drain electrode; A step of forming a gate electrode between the source electrode and the drain electrode on the upper surface of the epi layer; A step of forming a second insulating layer on the first insulating layer, the source electrode, the drain electrode, and the gate electrode, and etching the upper portion of the second insulating layer using an etch-back process to planarize it; A step of forming a third insulating layer on the second insulating layer and the gate electrode, wherein the third insulating layer is formed to be thicker than the electrode length of the gate electrode; A step of forming a field plate by etching the second insulating layer and the third insulating layer at a set position between the drain electrode and the gate electrode; and A step of forming a fourth insulating layer that insulates and protects the above field plate; A method for manufacturing a semiconductor device, comprising:

2. In paragraph 1, In the step of forming the above field plate, A method for manufacturing a semiconductor device, wherein the inside of a trench prepared by etching the second insulating layer and the third insulating layer is filled, and the field plate is formed in a partially bent shape on the third insulating layer corresponding to the gate electrode so as to be spaced apart from the gate electrode by a set interval.

3. In paragraph 1, The above field plate, A method for manufacturing a semiconductor device, wherein the field plate is spaced apart from the gate electrode by a set distance by the second insulating layer and the third insulating layer, and the distance between the field plate and the gate electrode is set as a distance adjustment value whose range is set according to the length of the gate electrode.

4. In paragraph 1, A method for manufacturing a semiconductor device, wherein the first insulating layer includes a capping film material that caps traps on the inside and surface of the epi layer, and includes a material having a higher dielectric constant than the second insulating layer and the third insulating layer.

5. In paragraph 1, A method for manufacturing a semiconductor device, wherein the second insulating layer and the third insulating layer include a material having a dielectric constant of 7.5 or less.

6. In paragraph 1, In the step of forming the above field plate, A method for manufacturing a semiconductor device, wherein the field plate is formed by filling the inside of a trench prepared by etching the first insulating layer, the second insulating layer, and the third insulating layer, and the lower portion is positioned on a position line corresponding to the position of the lower surface of the gate electrode.

7. In paragraph 1, A method for manufacturing a semiconductor device, wherein a trench-shaped ohmic recess is formed in the epi layer and an ion implantation region provided at a set position of the epi layer, and the source electrode and the drain electrode are formed in the ohmic recess as ohmic contacts, such that the lower surfaces of each of the source electrode and the drain electrode are arranged on a position line corresponding to a channel region through which a two-dimensional electron gas moves in the epi layer.

8. Substrate; An epi layer provided on the above substrate; A source electrode provided on the above epi layer; A drain electrode provided on the epi layer and spaced apart from the source electrode; A first insulating layer provided on the above epi layer; A gate electrode provided between the source electrode and the drain electrode on the upper surface of the epi layer; A second insulating layer provided on the first insulating layer, the source electrode, the drain electrode, and the gate electrode; A third insulating layer provided on the second insulating layer and the gate electrode, but thicker than the electrode length of the gate electrode; a field plate disposed on the upper side of the gate electrode at a position set between the drain electrode and the gate electrode; and A fourth insulating layer provided on the third insulating layer and the field plate; A semiconductor device comprising:

9. In paragraph 8, The above field plate, A semiconductor device that fills the inside of a trench prepared by etching the second insulating layer and the third insulating layer, and is formed in a partially bent shape on the third insulating layer corresponding to the gate electrode so as to be spaced apart from the gate electrode by a set interval.

10. In paragraph 8, The above field plate, It is spaced apart from the gate electrode by a set distance by the second insulating layer and the third insulating layer, A semiconductor device, wherein the distance between the field plate and the gate electrode is set as a distance adjustment value whose range is set according to the length of the gate electrode.

11. In paragraph 8, The above field plate, A semiconductor device, wherein the inside of a trench prepared by etching the first insulating layer, the second insulating layer, and the third insulating layer is filled so that the lower portion is positioned on a position line corresponding to the position of the lower surface of the gate electrode.

12. In paragraph 8, A semiconductor device, wherein the first insulating layer includes a capping film material that caps traps on the inside and surface of the epi layer, and includes a material having a higher dielectric constant than the second insulating layer and the third insulating layer.

13. In paragraph 8, A semiconductor device, wherein the second insulating layer and the third insulating layer include a material having a dielectric constant of 7.5 or less.

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