Method and system for determining integrated circuit parameters using machine learning

Abstract

A method includes determining, by a computer processor, a set of optimal active device parameters for an active device of an integrated circuit using an optimization engine, a first machine-learning model, and a set of target circuit performance metrics; determining, by the computer processor, a set of optimal passive network parameters for a passive network of the integrated circuit using the optimization engine, a second machine-learning model, and the set of target circuit performance metrics; and generating, by the computer processor, a circuit design for the integrated circuit based on the set of optimal active device parameters and the set of optimal passive network parameters.

Description

PROVISIONAL PATENT APPLICATIONATTORNEY DOCKET NO. 17500 / 276W01CLIENT REF. NO. 2025-004-PCTMETHOD AND SYSTEM FOR DETERMINING INTEGRATED CIRCUIT PARAMETERS USING MACHINE LEARNINGCROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority to and the benefit of the filing date of U.S. Provisional Patent Application 63 / 684,150, filed on August 16, 2024, and U.S. Provisional Patent Application 63 / 827,603, filed on June 20, 2025, which are hereby incorporated by reference herein in their entirety.BACKGROUND

[0002] Radio-frequency integrated circuits (RFIC) are foundational to wireless communication and sensing systems, enabling applications such as Wi-Fi connectivity, cellular communications, automotive radars, and many more. Traditionally, RFICs are designed manually, requiring (1) deep domain knowledge, (2) iterative manual tuning of the passive networks (i.e., including, resistors, capacitors, and / or inductors) involving computationally intensive electromagnetic (EM) simulations, and (3) iterative co-optimizations between active components (i.e., including transistors) and the passive networks. As a result, RFIC design time is often long (on the order of months to years), and the manual flow often cannot yield a globally optimal design. The conventional manual design flow poses significant challenges in meeting the target product-to-market time and performance specifications. Reliability issues, such as process variations, further complicate RFIC design and verification.SUMMARY

[0003] In general, in one aspect, one or more embodiments relate to a method, comprising: determining, by a computer processor, a plurality of optimal active device parameters for an active device of an integrated circuit using an optimization engine, a first machine-learning model, and a plurality of target circuit performance metrics; determining, by the computer processor, a plurality of optimal passive network parameters for a passive network of the integrated circuit using the optimization engine, a second machine-learning model, and the plurality of target circuitPROVISIONAL PATENT APPLICATIONATTORNEY DOCKET NO. 17500 / 276W01CLIENT REF. NO. 2025-004-PCT performance metrics; and generating, by the computer processor, a circuit design for the integrated circuit based on the plurality of optimal active device parameters and the plurality of optimal passive network parameters.

[0004] In general, in one aspect, one or more embodiments relate to a method, comprising: jointly determining, by a computer processor, a plurality of optimal active device parameters for an active device of an integrated circuit and a plurality of optimal passive network parameters for a passive network of the integrated circuit using an optimization engine, a machine-learning model, and a plurality of target circuit performance metrics; and generating, by the computer processor, a circuit design for the integrated circuit based on the plurality of optimal active device parameters and the plurality of optimal passive network parameters.

[0005] In general, in one aspect, one or more embodiments relate to a system, comprising: a computer system comprising a computer processor and a memory, wherein the memory comprises instructions configured to: determine a plurality of optimal active device parameters for an active device of an integrated circuit using an optimization engine, a first machine-learning model, and a plurality of target circuit performance metrics; determine a plurality of optimal passive network parameters for a passive network of the integrated circuit using the optimization engine, a second machine-learning model, and the plurality of target circuit performance metrics; and generate a circuit design for the integrated circuit based on the plurality of optimal active device parameters and the plurality of optimal passive network parameters.

[0006] In general, in one aspect, one or more embodiments relate to a system, comprising: a computer system comprising a computer processor and a memory, wherein the memory comprises instructions configured to: jointly determine, by a computer processor, a plurality of optimal active device parameters for an active device of an integrated circuit and a plurality of optimal passive network parameters for a passive network of the integrated circuit using an optimization engine, a machine-learning model, and a plurality of target circuit performance metrics; and generate, by the computer processor, a circuit design for the integrated circuit based on the plurality of optimal active device parameters and the plurality of optimal passive network parameters.PROVISIONAL PATENT APPLICATION ATTORNEY DOCKET NO. 17500 / 276W01 CLIENT REF. NO. 2025-004-PCT

[0007] Other aspects of the invention will be apparent from the following description and the appended claims.BRIEF DESCRIPTION OF DRAWINGS

[0008] Specific embodiments of the disclosed technology will now be described in detail with reference to the accompanying figures. Like elements in the various figures are denoted by like reference numerals for consistency.

[0009] FIG. 1 shows a system for determining integrated circuit parameters according to some embodiments.

[0010] FIG. 2 shows a flowchart of a method for determining integrated circuit parameters according to some embodiments.

[0011] FIG. 3A shows examples of passive components according to some embodiments.

[0012] FIG. 3B shows examples of passive networks according to some embodiments.

[0013] FIG. 3C shows an example of the generation of a training dataset for a passive network according to some embodiments.

[0014] FIG. 3D shows an example of the prediction of the performance of a passive network based on specified target passive network performance metrics according to some embodiments.

[0015] FIG. 3E shows an example of an inverse optimization performed for a power amplifier output matching network according to some embodiments.

[0016] FIG. 3F shows examples of active devices according to some embodiments.

[0017] FIG. 3G shows the obtaining of a training dataset for a specific example of an active device according to some embodiments.

[0018] FIG. 3H shows an example of an active device combined with a passive network modeled using an end-to-end modeling approach according to some embodiments.

[0019] FIG. 31 shows an example of an end-to-end synthesis using a combination of domain-specific knowledge and transfer learning to reduce the cost of data collection, according to some embodiments.PROVISIONAL PATENT APPLICATION ATTORNEY DOCKET NO. 17500 / 276W01 CLIENT REF. NO. 2025-004-PCT

[0020] FIG. 4 shows a computing system according to some embodiments.DETAILED DESCRIPTION

[0021] In the following detailed description of embodiments of the disclosure, numerous specific details are set forth in order to provide a more thorough understanding of the disclosure. However, it will be apparent to one of ordinary skill in the art that the disclosure may be practiced without these specific details. In other instances, well-known features have not been described in detail to avoid unnecessarily complicating the description.

[0022] Throughout the application, ordinal numbers (e.g., first, second, third, etc.) may be used as an adjective for an element (i.e., any noun in the application). The use of ordinal numbers is not to imply or create any particular ordering of the elements nor to limit any element to being only a single element unless expressly disclosed, such as by the use of the terms "before", "after", "single", and other such terminology. Rather, the use of ordinal numbers is to distinguish between the elements. By way of an example, a first element is distinct from a second element, and the first element may encompass more than one element and succeed (or precede) the second element in an ordering of elements.

[0023] Radio-frequency integrated circuits (RFICs), including wireless transceivers and wireline transceivers, consist of both active components (i.e., components that include transistors) and passive networks (including, e.g., resistors, capacitors, and / or inductors). The design of active components, similar to analog IC design, involves determining three key elements: (1) circuit topology, i.e., the wiring between transistors, (2) size of each transistor, and (3) DC bias. Passive networks, on the other hand, are responsible for providing the desired impedances, at both fundamental and harmonic frequencies, to interface with actives. Passive networks typically consist of two types of components. One includes process design kit (PDK) components, such as capacitors and resistors, whose layouts are readily available in the PDK provided by the foundry. The other includes “customized” EM structures, such as inductors, transformers, transmission lines, and coupled lines, whose layouts are conventionally determined by manual, iterative, and time-consuming EM simulations. Compared toPROVISIONAL PATENT APPLICATIONATTORNEY DOCKET NO. 17500 / 276W01CLIENT REF. NO. 2025-004-PCTPDK components, customized EM structures are often considered performance and productivity bottlenecks in passive and the whole RFIC design.

[0024] Embodiments of the disclosure include methods and systems for an automated synthesis of such RFICs. Embodiments of the disclosure enable the inverse design of both active devices and passive networks, either separately or in combination. For example, embodiments of the disclosure may determine the optimum biasing and size of transistors and optimum geometric parameters of passive networks, given specified target circuit performance metrics.

[0025] Embodiments of the disclosure are configured to build training datasets for both active components and passive networks of RFICs. Such training datasets may include characteristics or parameters of these components and networks and corresponding performance of these components and networks. Based on these training datasets, embodiments of the disclosure are configured to train machinelearning models. Once trained, these machine-learning models have the capability to predict the performance of active components and passive networks based on their characteristics or parameters provided as inputs to the machine learning models. In some embodiments, the trained machine-learning models are then used to solve the inverse problem, i.e., the prediction of optimal parameters of components and networks (i.e., optimal circuit parameters), given performance metrics specified as inputs. A detailed description is subsequently provided in reference to FIGs. 1 and 2. System components are described in reference to FIG. 1, whereas the operations performed by these system components are described in reference to FIG. 2.

[0026] The conventional design flow of RFICs is both time-consuming and labor- intensive. It begins with selecting a suitable RFIC topology based on target specifications, a process that often requires deep design expertise. Next, designers build the RFIC schematic and perform schematic-level simulations. In this step, lumped element models are usually constructed to model the passive components in the circuit (e.g., inductors and transformers (XFMRs)). Despite their limited accuracy compared with scattering parameters (S-parameters) derived from 3-D EM simulations, these lumped-element models are crucial in manual designs, as they provide valuable intuitions for human designers and can guide subsequentPROVISIONAL PATENT APPLICATIONATTORNEY DOCKET NO. 17500 / 276W01CLIENT REF. NO. 2025-004-PCT optimizations. Next, the transistor design parameters and lumped-element models are iteratively tuned to meet target RFIC specifications.

[0027] After the schematic-level design, 3-D EM models of the passive components are created. Designers manually adjust the geometric parameters of the EM models, run EM simulations, and extract circuit parameters from the simulation results. This step is repeated until the extracted circuit parameters match those of the lumped- element model.

[0028] Following this step, the EM-simulated S-parameters of the passive components are imported into the circuit design environment for co-simulation with the active components.

[0029] Given that RFIC performance is highly sensitive to device parasitics and nonlinearity, designers typically need to finetune the geometry of the 3-D EM models again and jointly optimize them with the active part until the overall RFIC achieves the target performance.

[0030] This iterative and heuristic process is not only time-consuming but also prone to sub-optimal results, as the large design space increases the risk of being trapped in local optima. Moreover, discrepancies often arise between the lumped element model and EM-simulated S-parameters of the passive components, especially for wide-band designs. Consequently, design productivity and overall performance are often limited by this manual design process.

[0031] An automated design flow according to embodiments of the disclosure may be used to address these issues. This may thus help address the ever-growing demand for high-throughput wireless communication that uses CMOS-based circuits and beamformers. Advanced CMOS technologies pose significant challenges for manual RF / mmWave design. As such, automated design automation using machine learning may emerge as a promising solution to overcome these challenges. Development cycles may be accelerated while also minimizing dependence on manual iterations and specialized domain knowledge.

[0032] Specific benefits associated with the automated design flow of passive networks include but are not limited to (i) a significant reduction of the design time fromPROVISIONAL PATENT APPLICATIONATTORNEY DOCKET NO. 17500 / 276W01CLIENT REF. NO. 2025-004-PCT possibly several weeks to ~80 seconds (based on a sample circuit), (ii) globally optimal designs, (iii) frequency agility, and (iv) generation of new, unseen passive networks to achieve functions beyond expert designs. The automated design flow can be readily extended to other frequencies, processes, and building blocks, offering a promising solution to enhance RFIC design productivity.

[0033] While the described tools can greatly reduce the design time for passive networks, it is important to note that the design of active circuits (i.e., building block topology, transistor sizing, and biasing) is equally crucial as the design of passive networks for RFICs. Even after the initial passive network is ready, its integration with active components still requires extensive nonlinear circuit simulations and further optimizations to account for transistor nonidealities (such as parasitics and nonlinearity). This makes the availability of an “end-to-end” design automation flow that can jointly optimize active and passive components to streamline the overall RF IC design process particularly beneficial.

[0034] The Al-assisted circuit design automation according to embodiments of the disclosure was demonstrated using two examples, taped out using the GlobalFoundries 22-nm CMOS SOI process. Compared with prior works, both designs achieve state-of-the-art performance. Importantly, such high performance is achieved in a compact, single-inductor footprint and without using any custom capacitors as in other manually designed circuits. These results clearly demonstrate the effectiveness of the design automation flow according to embodiments of the disclosure and its capability to achieve state-of-the-art circuit performance that outperforms existing human expert designs.

[0035] Turning to FIG. 1, a system for determining integrated circuit parameters 100 is shown. The system may be executing on a computing system, e.g., as shown in FIG. 4. The system 120 includes a model training engine 120 and an inverse optimization engine 150.

[0036] In some embodiments, the model training engine 120 is configured to generate a trained model 130 based on training datasets 110. The training dataset(s) 110 and the trained model(s) 130 may be stored in any types of databases. The operationsPROVISIONAL PATENT APPLICATIONATTORNEY DOCKET NO. 17500 / 276W01CLIENT REF. NO. 2025-004-PCT performed to obtain trained models based on training datasets are described in reference to the flowchart of FIG. 2.

[0037] RFIC building blocks can generally be divided into two primary components: active devices and passive networks, and high-quality training datasets are prerequisites for an effective Al-driven RFIC design flow.

[0038] The design of active devices may involve determining key elements such as circuit topology, i.e., the wiring between transistors, the size of each transistor, DC bias, and the impedance interfaces provided by the interfacing passive networks. For example, in the optimization of a power amplifier (PA), there may be three key parameters: the optimum gate biasing voltage (PGS, opt), the optimum load impedance (Ropt \ \ Lopt), and the optimum transistor size (Wopt). These parameters are crucial for maximizing the performance of the active device. In the example of a PA, the power- added efficiency (PAE) may be optimized while satisfying output power (Ptm et and linearity requirements. Accordingly, for active devices, the training datasets 110 may include one or more of these device parameters (e.g., transistor size, biasing, impedance presented to the transistor, etc.) as input features, and resulting performance characteristics of the active devices (e.g., gains at certain frequencies, noise characteristics, linearity, etc.) as labels. Different training datasets may be generated for different topologies. In the interest of focusing the description on the primary elements of system 100, a more detailed description of active devices and associated training data is provided separately below in reference to the examples shown in FIGs. 3F and 3G. The design of active devices according to embodiments of the disclosure may be used on any active device, including but not limited to, a power amplifier (PA) circuit, a radio frequency (RF) switch circuit, low-noise amplifier (LNA) circuit, an RF mixer circuit, an oscillator circuit, a duplexer circuit, including different topologies of these circuits (e.g., common-source PAs, cascode PAs, inductive degeneration LNAs, common-gate LNAs, cross-coupled oscillators), etc.

[0039] In most cases, an active device needs to be paired with a passive network. For example, a transformer-based matching network is a commonly used passive network element in RFIC applications. Such a transformer can simultaneously realize multiple functions (such as impedance transformation, DC feeding, and / or differential toPROVISIONAL PATENT APPLICATIONATTORNEY DOCKET NO. 17500 / 276W01CLIENT REF. NO. 2025-004-PCT single-ended conversion, etc.) in a compact, single-inductor footprint. Passive networks typically consist of two types of components. The first type includes components such as capacitors and resistors, whose layouts are readily available from the PDK. The second type includes customized EM structures, such as inductors, transformers, transmission lines, and coupled lines, whose layouts are typically determined by manual, iterative, and time-consuming EM simulations. Compared to components of the first type, customized EM structures are often considered performance and productivity bottlenecks in passive design. Accordingly, for passive networks that are considered custom EM structures, the training datasets 110 may include passive network parameters such as geometric parameters of the passive networks and capacitances as input parameters (e.g., geometric parameters) as input features, and the associated performance characteristics (e.g., in the form of impedance (real and imaginary parts, loss, S-parameters, coupling, and other circuit performance metrics over a frequency range) as labels. In the interest of focusing the description on the primary elements of system 100, a more detailed description of passive networks and associated training data is provided separately below in reference to the examples shown in FIGs. 3 A-3E.

[0040] Training datasets 110 may further be determined for the combination of one or more active devices and one or more passive networks. Such “end-to-end” datasets, comprise input parameters of the active device parameters (e.g., transistor size, biasing, impedance presented to the transistor) and the passive network parameters (e.g., geometric parameters) as input features. The labels are the corresponding circuit performance metrics of the end-to-end circuit (including both active device(s) and passive network(s)). Such performance metrics may include, but are not limited to, power, efficiency, gain, frequency, noise, linearity, etc. These performance metrics may be obtained, for example, from simulations. In the interest of focusing the description on the primary elements of system 100, a more detailed description of end- to-end approaches for the combination of active devices and passive networks and associated training data is provided separately below in reference to the examples shown in FIGs. 3H and 31.

[0041] With the system 100 being configured to determine integrated circuit parameters of circuits that include both at least one active device and at least onePROVISIONAL PATENT APPLICATIONATTORNEY DOCKET NO. 17500 / 276W01CLIENT REF. NO. 2025-004-PCT passive network, the training datasets 110 include training data for at least one active device and at least one passive network. The training of a model of an active device, a passive network, or a combination of active device(s) and passive network(s) may require a considerable number of training samples. Accordingly, to enable the training of a model 130 of active devices and / or passive networks by the model training engine 120, the training datasets 110 may include numerous training samples for the active device(s), for the passive network(s), or for the combination of the active device(s) and passive network(s) to be represented by the trained model 130. These training samples may be obtained or generated to cover the parameter space of the (input parameters) to at least some degree. Various methods, described below, may be used to obtain the training samples.

[0042] A training dataset 110 to be used to train one model 130 may include up to hundreds, thousands, or even more training samples. A training dataset 110 to be used to train a model 130 that includes both at least one active device and at least one passive network may need to be considerably larger than a training dataset to be used to train a model that is for an active device only or a passive network only. Assume, for example, that m training samples are used to train a first machine-learning model for the active device, and n training samples are used to train a second machinelearning model for the passive network. Accordingly, a total of m+n training samples are required to obtain the first and second machine-learning models. Training a single end-to-end machine learning model for both the active device and the passive network would, instead, require m n training samples, because a new dataset must be generated each time either the active or passive is changed. On the other hand, the end-to-end approach can generally lead to more accurate and efficient models, as it allows the model to learn and extract the most relevant features from both active devices and passive networks simultaneously.

[0043] Turning to the model training engine 120 and the trained model(s) 130, the model training engine may be any kind of algorithm with the capability to establish a trained model 130 of one of an active device, a passive network, and a combination of both. The trained model 130 may be any representation suitable to establish a relationship between the input features and the corresponding labels in the training dataset 110.PROVISIONAL PATENT APPLICATIONATTORNEY DOCKET NO. 17500 / 276W01CLIENT REF. NO. 2025-004-PCT

[0044] In some embodiments, a trained model 130 is a machine-learning model. Examples of machine-learning models may include linear regression models and artificial neural networks, such as feedforward neural networks, convolutional neural networks, deep neural networks, recurrent neural networks, and transformers. For example, a linear regression model may perform a model fit of a relationship between a scalar response and one or more explanatory variables. The linear regression model may perform a simple linear regression or a multivariate linear regression based on multiple correlated dependent variables are predicted. Machine-learning models may also include support vector machines, decision trees, inductive learning models, deductive learning models, supervised learning models, unsupervised learning models, reinforcement learning models, etc. In a deep neural network, for example, a layer of neurons may be trained on a predetermined list of features based on the previous network layer’s output. Thus, as data progresses through the deep neural network, more complex features may be identified within the data by neurons in later layers. In some embodiments, two or more different types of machine-learning models are integrated into a single machine-learning architecture, e.g., a machinelearning model may include support vector machines and neural networks.

[0045] In some embodiments, a system for determining integrated circuit parameters 100 may generate augmented data or synthetic data to produce a large volume of training samples for training a particular model. Data augmentation may include performing various processes on existing or acquired circuit data, such as simulatively sampling the parameter space of the circuit or network for which the training samples are to be generated. A description of the generation of augmented / synthetic data is provided below for the examples of FIGs. 3A-3I.

[0046] In some embodiments, the model training engine 120 may use various types of machine learning algorithms to train the model 130, such as a backpropagation algorithm. In a backpropagation algorithm, gradients are computed for each hidden layer of a neural network in reverse from the layer closest to the output layer proceeding to the layer closest to the input layer. As such, a gradient may be calculated using the transpose of the weights of a respective hidden layer based on an error function (also called a “loss function”). The error function may be based on various criteria, such as mean squared error function, a similarity function, etc., wherePROVISIONAL PATENT APPLICATIONATTORNEY DOCKET NO. 17500 / 276W01CLIENT REF. NO. 2025-004-PCT the error function may be used as a feedback mechanism for tuning weights in the machine-learning model.

[0047] With respect to artificial neural networks (ANN), for example, an ANN may include one or more hidden layers, where a hidden layer includes one or more neurons. Through machine learning, the model training engine 120 may determine which data inputs to the ANN should receive greater priority in determining one or more specified outputs of the ANN. Based on this determination gains and other parameters of the ANN may be set by the model training engine 120.

[0048] Turning to recurrent neural networks, a recurrent neural network (RNN) may perform a particular task repeatedly for multiple data elements in an input sequence, with the output of the recurrent neural network being dependent on past computations. As such, a recurrent neural network may operate with a memory or hidden cell state, which provides information for use by the current cell computation with respect to the current data input. To train a recurrent neural network, a supervised learning algorithm such as a backpropagation algorithm may also be used. In some embodiments, a recurrent neural network is trained using a reinforcement learning algorithm such as a deep reinforcement learning algorithm. For more information on reinforcement learning algorithms, see the discussion below.

[0049] Embodiments disclosed herein are contemplated with different types of RNNs. For example, classic RNNs, long short-term memory (LSTM) networks, a gated recurrent unit (GRU), a stacked LSTM that includes multiple hidden LSTM layers (i.e., each LSTM layer includes multiple RNN cells), recurrent neural networks with attention (i.e., the machine-learning model may focus attention on specific elements in an input sequence), bidirectional recurrent neural networks (e.g., a machinelearning model that may be trained in both time directions simultaneously, with separate hidden layers, such as forward layers and backward layers), as well as multidimensional LSTM networks, graph recurrent neural networks, grid recurrent neural networks, etc.

[0050] In some embodiments, an ensemble learning method is used to predict circuit data. For example, an ensemble learning method may use multiple types of machinelearning models to obtain better predictive performance than available with a singlePROVISIONAL PATENT APPLICATIONATTORNEY DOCKET NO. 17500 / 276W01CLIENT REF. NO. 2025-004-PCT machine-learning model. In some embodiments, for example, an ensemble architecture may combine multiple base models to produce a single machine-learning model. One example of an ensemble learning method is a BAGGing model (i.e., BAGGing refers to a model that performs Bootstrapping and Aggregation operations) that combines predictions from multiple neural networks. Another ensemble learning method includes a stacking method, which may involve fitting many different model types on the same data and using another machine-learning model to combine various predictions.

[0051] In some embodiments, a machine-learning model is trained using multiple epochs. For example, an epoch may be an iteration of a model through a portion or all of a training dataset. As such, a single machine-learning epoch may correspond to a specific batch of training data, where the training data is divided into multiple batches for multiple epochs. Thus, a machine-learning model may be trained iteratively using epochs until the model achieves a predetermined level of prediction accuracy. Thus, better training of a model may lead to better predictions by a trained model.

[0052] In some embodiments, the machine-learning model is pre-trained to predict circuit parameters based on input circuit data. For example, some training operations may benefit from “transfer learning” between models trained using similar problems with different training datasets. Accordingly, different types of pre-training processes may be performed to prepare for an actual training operation. In some embodiments, a pre-training operation may train only a portion of the hidden layers in a machinelearning model without changing the remaining hidden layers. In particular, lower hidden layers may refer to general features, while higher layers may refer to specific features. In some embodiments, a machine-learning architecture is reused from a previous model in order to retrain a new model.

[0053] In some embodiments, a transformer neural network (hereinafter “transformer model”) is used to determine predicted circuit data. A transformer model may be based on a sequence-to-sequence (Seq2Seq) architecture that transforms a given sequence of elements (e.g., a sequence of words in a sentence) into another sequence. For example, a Seq2Seq model may include an encoder and a decoder, where the encoder obtains the input sequence and maps the input sequence into a higherPROVISIONAL PATENT APPLICATIONATTORNEY DOCKET NO. 17500 / 276W01CLIENT REF. NO. 2025-004-PCT dimensional space. An abstract vector in the higher dimensional space may be provided to the decoder to produce a predicted output sequence. In particular, a transformer may include an attention-mechanism that analyzes a portion of an input sequence and determines at a particular step which other parts of the input sequence are relevant. As such, an attention-mechanism may determine a predicted output based on several other relevant inputs at the same time and attribute different weights to the other relevant inputs.

[0054] Turning to the optimization engine 150, once trained models 130 are available, the optimization engine may output optimal circuit parameters of a circuit based on specified target circuit performance metrics, using the trained model 130. In other words, in response to a user providing target circuit performance metrics (to make the desired circuit satisfactorily perform a certain task), the system for determining integrated circuit parameters 100 outputs the optimal circuit parameters that would result in the circuit to be built meeting the task requirements. The optimization performed by the optimization engine 150 may be considered an inverse design because, even though a trained model 130 predicts circuit performance based on circuit parameters, the optimization engine 150, operating on the trained model, performs the inverse design by outputting circuit parameters based on a specified circuit performance. Any type of suitable algorithm may be used for the optimization. For example, an evolutionary algorithm, genetic algorithms, Bayesian optimization or any other algorithms such as iterative cost function-based algorithms may be used. The optimization may be performed iteratively in a loop, e.g., starting from an initial “guess” of the circuit parameters to be determined, followed by algorithm-driven adjustment of these parameters until a design target is reached (e.g., a certain circuit performance)

[0055] In some embodiments, the optimization engine 150 is configured to generate optimal circuit parameters 160 separately for active devices and passive networks, given specified target circuit performance metrics 140. In this case, the output of the optimization engine may include a set of optimal circuit parameters for the active device(s) and a set of optimal circuit parameters for the passive network(s). In some embodiments, the optimization engine 150 is configured to generate optimal circuit parameters 160 jointly for active devices and passive networks, given specified targetPROVISIONAL PATENT APPLICATIONATTORNEY DOCKET NO. 17500 / 276W01CLIENT REF. NO. 2025-004-PCT circuit performance metrics 140. In this case, the output of the optimization engine may include a set of optimal circuit parameters for both the active device(s) and the passive network(s). The optimal circuit parameters 160 may be sufficient to establish a complete RFIC design or to enable a circuit designer to complete the RFIC design to subsequently have the circuit manufactured.

[0056] Turning to FIG. 2, FIG. 2 shows a flowchart in accordance with one or more embodiments. Specifically, FIG. 2 describes a general method for determining a circuit design of an integrated circuit using machine learning. One or more blocks in FIG. 2 may be performed by one or more components as described in FIG. 1. While the various blocks in FIG. 2 are presented and described sequentially, one of ordinary skill in the art will appreciate that some or all of the blocks may be executed in different orders, may be combined or omitted, and some or all of the blocks may be executed in parallel. Furthermore, the blocks may be performed actively or passively.

[0057] The flowchart of FIG. 2 includes a training phase (blocks 202-204) and an operating or use phase (blocks 206-210).

[0058] In Block 202, in some embodiments, a training dataset is obtained. The training dataset may include the training samples necessary to train the machine-learning model(s). For example, a training dataset may be obtained to train a machine-learning model of an active device, a passive network, or a combination of an active device and a passive network if the machine-learning model is an end-to-end model. The training dataset may be generated, e.g., by varying the circuit parameters and observing, e.g., simulatively, the resulting performance. A single training sample, thus, consists of a set of circuit parameter values and the resulting circuit performance value. All or at least some of the circuit parameters to be included in the machinelearning model may be varied to provide good coverage of the parameter space. In case of a training dataset for an active device, the active device parameters are varied. In case of a training dataset for a passive network, the passive network parameters are varied. In case of an end-to-end training dataset for a combination of an active device and a passive network, both the active device parameters and the passive network parameters are varied. Examples are provided below in reference to FIGs. 3 A-3I.PROVISIONAL PATENT APPLICATIONATTORNEY DOCKET NO. 17500 / 276W01CLIENT REF. NO. 2025-004-PCT

[0059] In Block 204, in some embodiments, the machine-learning model is trained using the obtained training dataset in accordance with one or more embodiments. The machine-learning model may be trained to predict circuit performance based on circuit parameters. Depending on the training dataset, the resulting trained machinelearning model may be for an active device, a passive network, or a combination of both. The machine-learning model may be any type of machine-learning model, including a machine learning model as previously provided in the description of the model training engine 120 and the trained model 130. Similarly, any suitable training operation may be used for the training, including a training method as previously provided in the description of the model training engine 120 and the trained model 130. The machine-learning model and the corresponding training are not limited to the examples as previously provided.

[0060] In Block 206, in some embodiments, the optimal circuit parameters are determined using an optimization engine, the machine learning model obtained in block 204, and target circuit performance which may be governed by the intended application of the circuit to be designed, maybe specified based on user preferences, etc.

[0061] The operations of block 206 may be separately performed for one or more active devices and for one or more passive networks using the corresponding trained models, resulting in separate optimal active device parameters and optimal passive network parameters.

[0062] Alternatively, the operations of block 206 may be jointly performed for a combination of one or more active devices and one or more passive networks using the corresponding end-to-end model, resulting in optimal circuit parameters that include both optimal active device parameters and optimal passive network parameters.

[0063] As previously noted, the execution of block 206 may involve an optimization which may be performed using any suitable algorithm, including, for example, an evolutionary algorithm.

[0064] In Block 208, a circuit design that includes a schematic and layout is determined based on various predicted active component parameters and / or various predictedPROVISIONAL PATENT APPLICATIONATTORNEY DOCKET NO. 17500 / 276W01CLIENT REF. NO. 2025-004-PCT passive network parameters in accordance with one or more embodiments. For passive networks, once the geometric parameters are determined, the corresponding layouts may be readily generated. For active devices, once their size, topology, and biasing are determined, their schematics may be ready, and their layout may be subsequently generated. The circuit design may include one or more logical and / or physical implementations in a circuit layout file. As such, various active component parameters and predicted passive network parameters may be converted into a software file that can be used to manufacture the respective integrated circuit. In some embodiments, a circuit design includes a list of terminal identifiers that map the connections of various cells within an integrated circuit. A cell may be a discrete logical and / or physical unit that represents at least a portion of a circuit. In a physical implementation, a cell may correspond to various transistors and interconnect structures that form a portion of an integrated circuit. Additionally, the circuit design may include a floorplan that describes the layout on an actual chip. The floorplan may be a two-dimensional schematic representation of the circuit presented using the graphical user interface as well as a three-dimensional schematic.

[0065] In some embodiments, multiple circuit designs of an integrated circuit may be generated using the above steps. The method may include presenting, within a graphical user interface, the circuit designs, where the circuit designs correspond to, for example, different form factors of integrated circuits. The user may then provide feedback to selected a circuit design among the circuit designs.

[0066] In Block 210, in some embodiments, one or more integrated circuits are manufactured based on the circuit design. The circuit design may be transmitted, over a computer network, to a server coupled to a foundry. An integrated circuit may then be manufactured, by the foundry, based on the circuit design.

[0067] Many aspects of the system shown in FIG. 1 and the method shown in FIG. 2 are subsequently discussed in reference to numerous specific examples that provide additional details.

[0068] Turning to FIG. 3 A, examples of customized passive components according to some embodiments are shown. These examples include “lumped” passive elements such as a multi -turn inductor, a 1 : 1 transformer and a 2: 1 transformer, along withPROVISIONAL PATENT APPLICATIONATTORNEY DOCKET NO. 17500 / 276W01CLIENT REF. NO. 2025-004-PCT“distributed” passive elements such as a transmission line, and coupled lines. For each of these examples, parameters and corresponding performance characteristics may be available. The parameters may be provided as, for example, tabular geometric parameters (providing, for example line width, gap, number of turns, etc.) or layout images. The performance characteristics may be provided in the form of, for example, s-parameters and / or key passive specs.

[0069] Turning to FIG. 3B, examples of passive networks according to some embodiments are shown. These passive networks may include one or more passive components (e.g., the customized EM structures as shown in FIG. 3 A, and additional PDK components). Several representative examples of single-stage passive networks are shown in FIG. 3B. These passive networks may be categorized based on their functionalities (e.g., impedance matching, power combining / dividing, and I / Q generation) and if their customized EM structures are based on lumped circuit elements (e.g., inductors and transformers) or distributed circuit elements (e.g., transmission lines and coupled lines). Typically, SiGe and CMOS RFICs favor lumped circuit element-based passive networks for area saving, while GaN RFICs employ distributed circuit element-based passive networks due to the limited number of metal layers.

[0070] Turning to FIG. 3C, an example of the generation of a training dataset for a passive network according to some embodiments is shown. Training datasets may be generated for passive networks, e.g., for common single-stage passive networks used in SiGe and GaN RFICs as shown in FIG. 3B. FIG. 3C is based on a single-stage passive network with both customized EM structures (a 1 : 1 transformer) and PDK components (shunt capacitors CPand Cs). The input features (i.e., the circuit parameters) of the corresponding training dataset include the capacitance values and the geometric parameters of the transformers (e.g., ro, W, gi, g2, gs). In the example of FIG. 3C, a key output label (i.e., a performance characteristic) is the impedance of the network at 28 GHz, which is presented on a Smith Chart for different input features. A total of 3,700 datapoints are included in the dataset used to generate the Smith Chart. Some or all of these 3,700 datapoints may be used to form training samples of a training dataset. Additionally, other labels such as S-parameters over frequency, input impedance, and loss, may also be included in the dataset.PROVISIONAL PATENT APPLICATIONATTORNEY DOCKET NO. 17500 / 276W01CLIENT REF. NO. 2025-004-PCT

[0071] Turning to FIG. 3D, an example of the prediction of the performance of a passive network based on specified target passive network performance metrics according to some embodiments is shown. A trained model based on ResNet is shown. This model may be applied to various passive components, including multiturn inductors and transformers, as illustrated in the example. During the ResNet training process, hyperparameters (e.g., numbers of layers, neurons per layer, learning rate, and loss functions) may be tuned to optimize the balance between training efficiency and model accuracy. For example, the example shows a two-turn inductor implemented in the GF22FDX process. By using a 7-layer ResNet with 1024 neurons per layer, its inductance (L) and quality factor (Q) can be predicted with <1% error compared to results from 3-D EM simulations over a frequency range of 1 to 12 GHz.

[0072] Turning to FIG. 3E, an example of an inverse design performed for a power amplifier output matching network according to some embodiments is shown. In the example, a multilayer perceptron that may have been trained, e.g., based on the data shown in FIG. 3C is used. The multilayer perceptron, in the example, predicts circuit performance based on circuit parameters. To obtain the optimal circuit parameters to achieve a specified circuit performance (inverse design), an optimization algorithm (evolutionary algorithm in this example) is used. In the example, the optimal transformer geometric parameters and optimal capacitances around the transformer are provided to achieve the desired impedance matching task with a minimal loss.

[0073] Turning to FIG. 3F, examples of active devices according to some embodiments are shown. These examples illustrate embodiments of the disclosure generating active datasets that incorporate, for example, (1) various RFIC active circuit topologies, (2) different transistor sizes and biases, and (3) different impedance interfaces provided by passive components. These datasets may be derived based on, for example, harmonic-balance simulations, conducted, e.g., in Cadence Virtuoso. To minimize the data collection overhead while ensuring the quality and accuracy of the data, two strategies may be adopted. First, the transistors used in the data collection may be based on custom, scalable transistor models that include layout parasitics up to the top metal layer. Accordingly, a scaling process may later be used to predict active component parameters based on the previously predicted active device parameters and predetermined circuit criteria. These models may be derived from, for example,PROVISIONAL PATENT APPLICATIONATTORNEY DOCKET NO. 17500 / 276W01CLIENT REF. NO. 2025-004-PCT previously manually laid out transistors, which may have been experimentally verified through multiple tapeouts. Second, the passives in these datasets may be abstracted as “lossy impedance tuners”, which provide tunable impedance and loss at the fundamental frequency and harmonics. This abstraction means that the specific implementation, topology, and geometric parameters of the passives do not need to be included in the active dataset generation, thereby reducing data collection overhead. For certain RF active topologies, such as capacitive neutralization and resistive feedback, the capacitance and resistance around the transistors may be considered as part of the active components, even though they are technically passive PDK components. This is because these PDK passives are essential components of these active topologies, and including their component values as part of the input features of the active datasets is more straightforward than lumping them into passive datasets. The resulting parameters may become part of training datasets for these active devices with input parameters being the previously recited parameters (such as transistor size, supply voltage, bias voltage, and impedance presented to the transistors). The output labels may be the corresponding circuit performance, derived based on, for example, circuit simulators.

[0074] Turning to FIG. 3G, the obtaining of a training dataset for a specific example of an active device according to some embodiments is illustrated. The active device in the example is a 28-GHz differential cascode power amplifier (PA). The left panel shows the circuit schematic and input features. Arrows identify the parameters that were swept during data collection. The right panel visualizes the Collected labels of output power at IdB compression point OPidB and drain efficiency DE. The PA topology as shown is based on the differential cascode amplifier with capacitive neutralization, a well-established topology for mmWave amplifiers. The input features of this active dataset include: (1) the gate biasing of the bottom transistor, (2) the gate biasing of the cascode transistor, (3) the supply voltage, (4) the size of the bottom transistor, (5) the size of the cascode transistor, (6) the load impedance (Rioad | | Lioad) at the fundamental frequency and harmonics, (7) the loss of the load tuner at the fundamental frequency and harmonics, (8) the value of the neutralization capacitor, and (9) the operating frequency.PROVISIONAL PATENT APPLICATIONATTORNEY DOCKET NO. 17500 / 276W01CLIENT REF. NO. 2025-004-PCT

[0075] Because the input feature space is large, RFIC domain knowledge was applied to reduce the number of simulations needed for data collection. For example, the supply voltage is typically set to be the highest level allowed by reliability constraints, as a higher supply directly increases the PA output power and efficiency. Another key insight is that the optimal biasing voltage is almost independent of the output power level and the operating frequency, while the optimal load impedance scales almost linearly with the output power. Therefore, a unit PA power cell with a transistor size of Wunit was first constructed, followed by harmonic-balance simulations under different biasing and load conditions. Corresponding metrics, such as gain, stability, output power, linearity, and efficiency, were recorded as labels. Next, Wunit was scaled into a few sparse values to collect data in a similar way without the need for a fine sweep of the transistor size. This process may be fully automated, e.g., using a combination of Cadence Virtuoso and Python scripts, which automatically sweep design parameters, perform harmonic-balance simulations, and record simulation results.

[0076] Turning to FIG. 3H, an example of an active device combined with a passive network modeled using an end-to-end modeling approach according to some embodiments is shown.

[0077] In this approach, the input features directly combine the transistor parameters and the passive geometric parameters in one dataset. End-to-end datasets of different circuit topologies may be generated, capturing both actives and passives at the same time. The input features for the end-to-end datasets generated for the illustrated example include, for example, transistor size, biasing, capacitance value, and geometrical parameters of the Class-F'1harmonic tank. Labels representing key VCO performance metrics, such as oscillation frequency, phase noise at 10 kHz offset, DC power, and figure-of-metric (FoM) may be collected, for example, by combining HFSS and Cadance co-simulations.

[0078] Turning to FIG. 31, an example of an end-to-end synthesis using a combination of domain-specific knowledge and transfer learning to reduce the cost of data collection, according to embodiments of the disclosure, is shown.PROVISIONAL PATENT APPLICATIONATTORNEY DOCKET NO. 17500 / 276W01CLIENT REF. NO. 2025-004-PCT

[0079] To reduce the data collection overhead associated with training high-fidelity models, domain-specific knowledge and transfer learning (TL) were leveraged in the example. For example, inductors with an even number of turns (2 -turn and 4-turn inductors) were used to cover 1 to 20 GHz, as they naturally offer a smaller LCM compared with inductors with an odd number of turns, making it easier to satisfy a desired LDM / LCM ~ 4 relationship for the Class-F'1harmonic tank. Additionally, datasets were first collected using a simplified stack-up to train an initial model, which was then fine-tuned with a smaller number of samples collected using the complete PDK-specific stack-up, as shown in Fig. 31. This TL approach significantly reduces the dataset collection time by ~ 3x. Once the S-parameters of the inductors were obtained from EM simulations, an end-to-end dataset was generated by co-simulating the S-parameters and the active core in Cadence Virtuoso. The overall data collection took ~26.5 hours on a 128-core workstation, generating ~91k data points.

[0080] Embodiments may be implemented on a computing system. Any combination of mobile, desktop, server, router, switch, embedded device, or other types of hardware may be used. For example, as shown in FIG. 3 A, the computing system 300 may include one or more computer processors 302, non-persistent storage 304 (e.g., volatile memory, such as random access memory (RAM), cache memory), persistent storage 306 (e.g., a hard disk, an optical drive such as a compact disk (CD) drive or digital versatile disk (DVD) drive, a flash memory, etc.), a communication interface 312 to a network (e.g., Bluetooth interface, infrared interface, network interface, optical interface, etc.), and numerous other elements and functionalities.

[0081] The computer processor(s) 302 may be an integrated circuit for processing instructions. For example, the computer processor(s) may be one or more cores or micro-cores of a processor. The computing system 300 may also include one or more input devices 310, such as a touchscreen, keyboard, mouse, microphone, touchpad, electronic pen, or any other type of input device.

[0082] The communication interface 312 may include an integrated circuit for connecting the computing system 300 to a network (not shown) (e.g., a local area network (LAN), a wide area network (WAN) such as the Internet, mobile network, or 1PROVISIONAL PATENT APPLICATIONATTORNEY DOCKET NO. 17500 / 276W01CLIENT REF. NO. 2025-004-PCT any other type of network) and / or to another device, such as another computing device.

[0083] Further, the computing system 300 may include one or more output devices 308, such as a screen (e.g., a liquid crystal display (LCD), a plasma display, touchscreen, cathode ray tube (CRT) monitor, projector, or other display device), a printer, external storage, or any other output device. One or more of the output devices may be the same or different from the input device(s). The input and output device(s) may be locally or remotely connected to the computer processor(s) 302, non-persistent storage 304, and persistent storage 306. Many different types of computing systems exist, and the aforementioned input and output device(s) may take other forms.

[0084] Software instructions in the form of computer readable program code to perform embodiments of the disclosure may be stored, in whole or in part, temporarily or permanently, on a non-transitory computer readable medium such as a CD, DVD, storage device, a diskette, a tape, flash memory, physical memory, or any other computer readable storage medium. Specifically, the software instructions may correspond to computer readable program code that, when executed by a processor(s), is configured to perform one or more embodiments of the disclosure.

[0085] The computing system 300 in FIG. 3 may be connected to or be a part of a network. By way of another example, embodiments of the disclosure may be implemented on a distributed computing system having multiple nodes, where each portion of the disclosure may be located on a different node within the distributed computing system. Further, one or more elements of the aforementioned computing system 300 may be located at a remote location and connected to the other elements over a network.

[0086] In some embodiments, the computing system 300 is implemented as part of a cloud computing system. For example, a cloud computing system may include one or more remote servers along with various other cloud components, such as cloud storage units and edge servers.

[0087] Although only a few example embodiments have been described in detail above, those skilled in the art will readily appreciate that many modifications are possible in the example embodiments without materially departing from this invention.PROVISIONAL PATENT APPLICATION ATTORNEY DOCKET NO. 17500 / 276W01 CLIENT REF. NO. 2025-004-PCTAccordingly, all such modifications are intended to be included within the scope of this disclosure as defined in the following claims.

Claims

PROVISIONAL PATENT APPLICATIONATTORNEY DOCKET NO. 17500 / 276W01CLIENT REF. NO. 2025-004-PCTCLAIMSWhat is claimed is:

1. A method, comprising: determining, by a computer processor, a plurality of optimal active device parameters for an active device of an integrated circuit using an optimization engine, a first machine-learning model, and a plurality of target circuit performance metrics; determining, by the computer processor, a plurality of optimal passive network parameters for a passive network of the integrated circuit using the optimization engine, a second machine-learning model, and the plurality of target circuit performance metrics; and generating, by the computer processor, a circuit design for the integrated circuit based on the plurality of optimal active device parameters and the plurality of optimal passive network parameters.

2. The method of claim 1, further comprising: transmitting, over a computer network, the circuit design to a server coupled to a foundry; and manufacturing, by the foundry, the integrated circuit based on the circuit design.

3. The method of claim 1, further comprising: obtaining a first training dataset that comprises at least one selected from a group consisting of first acquired circuit data, first synthetic circuit data, and first augmented circuit data for the active device; obtaining a second training dataset that comprises at least one selected from a group consisting of second acquired circuit data, second synthetic circuit data, and second augmented circuit data for the passive network; training the first machine-learning model using the first training dataset; and training the second machine-learning model using the second training dataset.

4. The method of claim 3, wherein: the first training dataset is selected from a plurality of training datasets, and the first training dataset is specific to a first type of active device.PROVISIONAL PATENT APPLICATION ATTORNEY DOCKET NO. 17500 / 276W01 CLIENT REF. NO. 2025-004-PCT5. The method of claim 3, wherein: the second training dataset is selected from a plurality of training datasets, and the second training dataset is specific to a first type of passive network.

6. The method of claim 1, wherein: the first machine-learning model is configured to predict an active device performance based on active device parameter inputs; and the determining the plurality of optimal active device parameters using the first machine-learning model comprises operating the first machine-learning model in an inverse design configuration.

7. The method of claim 1, further comprising: generating a plurality of circuit designs for a second integrated circuit; presenting, within a graphical user interface, the plurality of circuit designs, wherein the plurality of circuit designs correspond to different form factors of integrated circuits; and obtaining, from a user and using the graphical user interface, a selected circuit design among the plurality of circuit designs.

8. The method of claim 1, further comprising: determining a second plurality of optimal active device parameters using the first machine-learning model and a second plurality of target circuit performance metrics for a second integrated circuit; and determining, using a scaling process, a third plurality of optimal active device parameters based on the second plurality of optimal active device parameters and predetermined circuit criteria.

9. The method of claim 1, wherein the plurality of target circuit performance metrics comprises at least one circuit parameter selected from a group consisting of: an optimum gate biasing voltage for a first transistor, an optimum load impedance for the integrated circuit, and an optimum transistor size for the first transistor.PROVISIONAL PATENT APPLICATION ATTORNEY DOCKET NO. 17500 / 276W01 CLIENT REF. NO. 2025-004-PCT10. The method of claim 1, wherein the plurality of optimal passive network parameters for at least one selected from a group consisting of lumped circuit elements and distributed circuit elements comprises geometric parameters.

11. The method of claim 1, wherein the integrated circuit is selected from a group consisting of a wireless transceiver and a wireline transceiver.

12. A method, comprising: jointly determining, by a computer processor, a plurality of optimal active device parameters for an active device of an integrated circuit and a plurality of optimal passive network parameters for a passive network of the integrated circuit using an optimization engine, a machine-learning model, and a plurality of target circuit performance metrics; and generating, by the computer processor, a circuit design for the integrated circuit based on the plurality of optimal active device parameters and the plurality of optimal passive network parameters.

13. The method of claim 12, further comprising: transmitting, over a computer network, the circuit design to a server coupled to a foundry; and manufacturing, by the foundry, the integrated circuit based on the circuit design.

14. The method of claim 12, further comprising: obtaining a training dataset that comprises at least one selected from a group consisting of acquired circuit data, synthetic circuit data, and augmented circuit data for the active device and at least one selected from a group consisting of acquired circuit data, synthetic circuit data, and augmented circuit data for the passive network; training the machine-learning model using the training dataset.

15. The method of claim 14, wherein: the training dataset is selected from a plurality of training datasets, andPROVISIONAL PATENT APPLICATION ATTORNEY DOCKET NO. 17500 / 276W01 CLIENT REF. NO. 2025-004-PCT the training dataset is specific to a type of active device in combination with a passive network.

16. The method of claim 12, wherein: the machine-learning model is configured to predict a performance of the active device in combination with the passive network, based on active device parameter inputs and passive network parameter inputs; and the determining the plurality of optimal active device parameters and the plurality of optimal passive network parameters using the machine-learning model comprises operating the machine-learning model in an inverse design configuration.

17. The method of claim 12, further comprising: generating a plurality of circuit designs for a second integrated circuit; presenting, within a graphical user interface, the plurality of circuit designs, wherein the plurality of circuit designs correspond to different form factors of integrated circuits; and obtaining, from a user and using the graphical user interface, a selected circuit design among the plurality of circuit designs.

18. The method of claim 12, further comprising: jointly determining a second plurality of optimal active device parameters and a second plurality of optimal passive network parameters for a second integrated circuit using the machine-learning model; and determining, using a scaling process, a third plurality of optimal active device parameters based on the second plurality of optimal active device parameters and predetermined circuit criteria.

19. The method of claim 12, wherein the plurality of target circuit performance metrics comprises at least one circuit parameter selected from a group consisting of: an optimum gate biasing voltage for a first transistor, an optimum load impedance for the integrated circuit, and an optimum transistor size for the first transistor.PROVISIONAL PATENT APPLICATION ATTORNEY DOCKET NO. 17500 / 276W01 CLIENT REF. NO. 2025-004-PCT20. The method of claim 12, wherein the plurality of optimal passive network parameters for at least one selected from a group consisting of lumped circuit elements and distributed circuit elements comprises geometric parameters.

21. The method of claim 12, wherein the integrated circuit is selected from a group consisting of a wireless transceiver and a wireline transceiver.

22. A non-transitory computer readable medium comprising instructions that, when executed by a computer processor, are configured to perform a method comprising: determining, by a computer processor, a plurality of optimal active device parameters for an active device of an integrated circuit using an optimization engine, a first machine-learning model, and a plurality of target circuit performance metrics; determining, by the computer processor, a plurality of optimal passive network parameters for a passive network of the integrated circuit using the optimization engine, a second machine-learning model, and the plurality of target circuit performance metrics; and generating, by the computer processor, a circuit design for the integrated circuit based on the plurality of optimal active device parameters and the plurality of optimal passive network parameters.

23. A system, comprising: a computer system comprising a computer processor and a memory, wherein the memory comprises instructions configured to: determine a plurality of optimal active device parameters for an active device of an integrated circuit using an optimization engine, a first machinelearning model, and a plurality of target circuit performance metrics; determine a plurality of optimal passive network parameters for a passive network of the integrated circuit using the optimization engine, a second machine-learning model, and the plurality of target circuit performance metrics; andPROVISIONAL PATENT APPLICATION ATTORNEY DOCKET NO. 17500 / 276W01 CLIENT REF. NO. 2025-004-PCT generate a circuit design for the integrated circuit based on the plurality of optimal active device parameters and the plurality of optimal passive network parameters.

24. The system of claim 23, wherein the instructions are further configured to: transmit, over a computer network, the circuit design to a server coupled to a foundry to enable manufacturing, by the foundry, the integrated circuit based on the circuit design.

25. The system of claim 23, wherein the instructions are further configured to: obtain a first training dataset that comprises at least one selected from a group consisting of first acquired circuit data, first synthetic circuit data, and first augmented circuit data for the active device; obtain a second training dataset that comprises at least one selected from a group consisting of second acquired circuit data, second synthetic circuit data, and second augmented circuit data for the passive network; train the first machine-learning model using the first training dataset; and train the second machine-learning model using the second training dataset.

26. The system of claim 25, wherein: the first training dataset is selected from a plurality of training datasets, and the first training dataset is specific to a first type of active device.

27. The system of claim 25, wherein: the second training dataset is selected from a plurality of training datasets, and the second training dataset is specific to a first type of passive network.

28. The system of claim 23, wherein: the first machine-learning model is configured to predict an active device performance based on active device parameter inputs; and the determining the plurality of optimal active device parameters using the first machine-learning model comprises operating the first machine-learning model in an inverse design configuration.PROVISIONAL PATENT APPLICATIONATTORNEY DOCKET NO. 17500 / 276W01CLIENT REF. NO. 2025-004-PCT29. The system of claim 23, wherein the instructions are further configured to: generate a plurality of circuit designs for a second integrated circuit; present, within a graphical user interface, the plurality of circuit designs, wherein the plurality of circuit designs correspond to different form factors of integrated circuits; and obtain, from a user and using the graphical user interface, a selected circuit design among the plurality of circuit designs.

30. The system of claim 23, wherein the instructions are further configured to: determine a second plurality of optimal active device parameters using the first machine-learning model and a second plurality of target circuit performance metrics for a second integrated circuit; and determine, using a scaling process, a third plurality of optimal active device parameters based on the second plurality of optimal active device parameters and predetermined circuit criteria.

31. The system of claim 23, wherein the plurality of target circuit performance metrics comprises at least one circuit parameter selected from a group consisting of: an optimum gate biasing voltage for a first transistor, an optimum load impedance for the integrated circuit, and an optimum transistor size for the first transistor.

32. The system of claim 23, wherein the plurality of optimal passive network parameters for at least one selected from a group consisting of lumped circuit elements and distributed circuit elements comprises geometric parameters.

33. The system of claim 23, wherein the integrated circuit is selected from a group consisting of a wireless transceiver and a wireline transceiver.

34. A system, comprising: a computer system comprising a computer processor and a memory, wherein the memory comprises instructions configured to:PROVISIONAL PATENT APPLICATION ATTORNEY DOCKET NO. 17500 / 276W01 CLIENT REF. NO. 2025-004-PCT jointly determine, by a computer processor, a plurality of optimal active device parameters for an active device of an integrated circuit and a plurality of optimal passive network parameters for a passive network of the integrated circuit using an optimization engine, a machine-learning model, and a plurality of target circuit performance metrics; and generate, by the computer processor, a circuit design for the integrated circuit based on the plurality of optimal active device parameters and the plurality of optimal passive network parameters.

35. The system of claim 34, wherein the instructions are further configured to: transmit, over a computer network, the circuit design to a server coupled to a foundry to enable manufacturing, by the foundry, the integrated circuit based on the circuit design.

36. The system of claim 34, wherein the instructions are further configured to: obtain a training dataset that comprises at least one selected from a group consisting of acquired circuit data, synthetic circuit data, and augmented circuit data for the active device and at least one selected from a group consisting of acquired circuit data, synthetic circuit data, and augmented circuit data for the passive network; train the machine-learning model using the training dataset.

37. The system of claim 36, wherein: the training dataset is selected from a plurality of training datasets, and the training dataset is specific to a type of active device in combination with a passive network.

38. The system of claim 34, wherein: the machine-learning model is configured to predict a performance of the active device in combination with the passive network, based on active device parameter inputs and passive network parameter inputs; and the determining the plurality of optimal active device parameters and the plurality of optimal passive network parameters using the machine-learning modelPROVISIONAL PATENT APPLICATION ATTORNEY DOCKET NO. 17500 / 276W01 CLIENT REF. NO. 2025-004-PCT comprises operating the machine-learning model in an inverse design configuration.

39. The system of claim 34, wherein the instructions are further configured to: generate a plurality of circuit designs for a second integrated circuit; present, within a graphical user interface, the plurality of circuit designs, wherein the plurality of circuit designs correspond to different form factors of integrated circuits; and obtain, from a user and using the graphical user interface, a selected circuit design among the plurality of circuit designs.

40. The system of claim 34, wherein the instructions are further configured to: jointly determine a second plurality of optimal active device parameters and a second plurality of optimal passive network parameters for a second integrated circuit using the machine-learning model; and determine, using a scaling process, a third plurality of optimal active device parameters based on the second plurality of optimal active device parameters and predetermined circuit criteria.

41. The system of claim 34, wherein the plurality of target circuit performance metrics comprises at least one circuit parameter selected from a group consisting of: an optimum gate biasing voltage for a first transistor, an optimum load impedance for the integrated circuit, and an optimum transistor size for the first transistor.

42. The system of claim 34, wherein the plurality of optimal passive network parameters for at least one selected from a group consisting of lumped circuit elements and distributed circuit elements comprises geometric parameters.

43. The system of claim 34, wherein the integrated circuit is selected from a group consisting of a wireless transceiver and a wireline transceiver.PROVISIONAL PATENT APPLICATION ATTORNEY DOCKET NO. 17500 / 276W01 CLIENT REF. NO. 2025-004-PCT44. A non-transitory computer readable medium comprising instructions that, when executed by a computer processor, are configured to perform a method comprising: jointly determining, by a computer processor, a plurality of optimal active device parameters for an active device of an integrated circuit and a plurality of optimal passive network parameters for a passive network of the integrated circuit using an optimization engine, a machine-learning model, and a plurality of target circuit performance metrics; and generating, by the computer processor, a circuit design for the integrated circuit based on the plurality of optimal active device parameters and the plurality of optimal passive network parameters.

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