Communication method, communication apparatus, computer-readable storage medium, chip, and computer program product

Abstract

The present application provides a communication method, a communication apparatus, a computer-readable storage medium, a chip, and a computer program product. The communication method comprises: determining a log-likelihood ratio (LLR) vector associated with a received vector; taking absolute values of at least some elements in the LLR vector and then sorting same; dividing elements in a systematic bit vector into a plurality of groups according to an ascending order of sorting results, wherein the systematic bit vector comprises first to k-th elements in the received vector, and k is an integer greater than or equal to 1; determining a flipping order of bits in each group among the plurality of groups as being non-increasing; based on the flipping order, flipping the bits in each group to obtain a plurality of flipped systematic bit vectors; determining a plurality of codeword vectors on the basis of the plurality of flipped systematic bit vectors and a generator matrix; and from among the plurality of codeword vectors, selecting, as a decoding result of the received vector, a first codeword vector having the smallest Euclidean distance from the LLR vector. The method of the present application can be regarded as a decoding method combining the advantages of OSD and GRAND, is an efficient GRAND method that reduces the flip range by means of LLR sorting, and can also be regarded as a Gaussian-elimination-free OSD.

Description

Communication method, communication apparatus, computer readable storage medium, chip and computer program product

[0001] This application claims priority to the Chinese patent application No. 202411149550.X, filed on August 20, 2024, entitled “Communication method, communication apparatus, computer readable storage medium, chip and computer program product”, the entire content of which is incorporated herein by reference. TECHNICAL FIELD

[0002] The present application relates to the field of communication, and more particularly, to a communication method, a communication apparatus, a computer readable storage medium, a chip and a computer program product. BACKGROUND

[0003] In a communication system, in order to enhance the ability of data to resist various interference when transmitted in a channel and improve the reliability of the system, the transmitting end device needs to perform channel coding on the digital signal to be transmitted. The receiving end device needs to decode and recover the signal after channel coding and transmission to recover the original digital information.

[0004] Random noise guessing decoding (GRAND) and ordered statistics decoding (OSD) are two commonly used decoding methods. The advantage of GRAND decoding is that it only needs a check matrix to decode. For a code with very high code rate or very short code length, GRAND can quickly obtain the decoding result. However, when the code rate decreases or the code length increases, the average complexity and maximum complexity of GRAND decoding both increase by a combination number. Therefore, the application range of GRAND decoding is limited, and it is not suitable for current mainstream communication systems.

[0005] The biggest defect of OSD decoding is that it needs to do Gaussian elimination to replace the row of the column-permuted G' matrix with a new generator matrix. The process of Gaussian elimination is complex, and after the linear correlation row appears in the selected K columns, the matrix will not be full rank, at this time, a new G' generator matrix cannot be generated, and one column in the K column needs to be replaced and a new column needs to be put in to do Gaussian elimination again. Therefore, a decoding method with lower complexity is needed. SUMMARY

[0006] The present application provides a scheme for communication.

[0007] In a first aspect, a communication method is provided. The method comprises: determining a log likelihood ratio (LLR) vector associated with a received vector; sorting at least part of elements in the LLR vector after taking absolute values of the at least part of elements; dividing elements in a systematic bit vector into a plurality of groups in ascending order of the sorting result, wherein the systematic bit vector comprises first to k-th elements in the received vector, and k is an integer greater than or equal to 1; determining a flipping order of bits in each group of the plurality of groups as non-decreasing; flipping the bits in each group based on the flipping order to obtain a plurality of flipped systematic bit vectors; determining a plurality of coded vectors based on the plurality of flipped systematic bit vectors and a coding matrix; and selecting a first coded vector with a minimum Euclidean distance from the LLR vector from the plurality of coded vectors as a decoding result of the received vector.

[0008] The method of the present application can be regarded as a decoding method combining the advantages of OSD and GRAND, which is a high-efficiency GRAND for narrowing the flipping range through LLR sorting, and can also be regarded as a OSD without Gaussian elimination.

[0009] In a possible implementation, the sorting at least part of elements in the LLR vector after taking absolute values of the at least part of elements comprises: sorting elements in the LLR vector corresponding to the systematic bit vector after taking absolute values of the elements.

[0010] In a possible implementation, the sorting at least part of elements in the LLR vector after taking absolute values of the at least part of elements comprises: sorting all elements in the LLR vector after taking absolute values of the elements.

[0011] In a possible implementation, the dividing elements in the systematic bit vector into a plurality of groups in ascending order of the sorting result comprises: determining n-k smallest elements in the LLR vector, wherein n represents a number of all elements in the LLR vector; determining m1 elements from the n-k smallest elements, the m1 elements corresponding to m1 elements in the systematic bit vector, wherein m1 is an integer greater than or equal to 1; dividing the m1 elements in the systematic bit vector into a starting group of the plurality of groups; and dividing other k-m1 elements in the systematic bit vector into subsequent groups of the starting group.

[0012] In a possible implementation, the dividing elements in the systematic bit vector into a plurality of groups in ascending order of the sorting result comprises: determining n-k smallest elements in the LLR vector, wherein n represents a number of all elements in the LLR vector; determining x elements from the n-k smallest elements, the x elements corresponding to x elements in the systematic bit vector, wherein x is an integer greater than or equal to 1; dividing the x elements in the systematic bit vector into y groups; and dividing other k-x elements in the systematic bit vector into subsequent m-y groups of the y groups.

[0013] In a possible implementation, the method further includes: determining a Hamming distance between a second encoding vector in the plurality of encoding vectors and the LLR vector, wherein the second encoding vector is the same as or different from the first encoding vector; and stopping decoding the received vector if the Hamming distance is less than or equal to one half of a minimum distance of a code word space formed or corresponding to the encoding matrix.

[0014] In a second aspect of the present application, a communication apparatus is provided. The communication apparatus includes a processing unit.

[0015] The processing unit is configured to determine a log-likelihood ratio (LLR) vector associated with the received vector; sort at least part of elements in the LLR vector after taking absolute values of the at least part of elements; divide elements in a systematic bit vector into a plurality of groups in ascending order of the sorting result, wherein the systematic bit vector includes 1st to kth elements in the received vector, and k is an integer greater than or equal to 1; determine a flipping order of bits in each group in the plurality of groups as non-decreasing; flip the bits in each group based on the flipping order to obtain a plurality of flipped systematic bit vectors; determine a plurality of encoding vectors based on the plurality of flipped systematic bit vectors and an encoding matrix; and select a first encoding vector with a minimum Euclidean distance to the LLR vector from the plurality of encoding vectors as a decoding result of the received vector.

[0016] In a possible implementation, the sorting at least part of elements in the LLR vector after taking absolute values of the at least part of elements includes: sorting elements in the LLR vector corresponding to the systematic bit vector after taking absolute values of the elements.

[0017] In a possible implementation, the sorting at least part of elements in the LLR vector after taking absolute values of the at least part of elements includes: sorting all elements in the LLR vector after taking absolute values of the elements.

[0018] In a possible implementation, the dividing elements in the systematic bit vector into the plurality of groups in ascending order of the sorting result includes: determining n-k smallest elements in the LLR vector, wherein n represents a number of all elements in the LLR vector; determining m1 elements from the n-k smallest elements, the m1 elements corresponding to m1 elements in the systematic bit vector, wherein m1 is an integer greater than or equal to 1; dividing the m1 elements in the systematic bit vector into a starting group in the plurality of groups; and dividing other k-m1 elements in the systematic bit vector into subsequent groups after the starting group.

[0019] In a possible implementation, the dividing the elements in the systematic bit vector into groups in ascending order of the sorting result comprises: determining n-k smallest elements in the LLR vector, where n represents the number of all elements in the LLR vector; determining x elements from the n-k elements, the x elements corresponding to x elements in the systematic bit vector, where x is an integer greater than or equal to 1; dividing the x elements in the systematic bit vector into y groups; and dividing the other k-x elements in the systematic bit vector into the next m-y groups of the y groups.

[0020] In a possible implementation, the processing unit is further configured to: determine a Hamming distance between a second encoding vector in the plurality of encoding vectors and the LLR vector, where the second encoding vector is the same as or different from the first encoding vector; and stop decoding the received vector if the Hamming distance is less than or equal to one half of a minimum distance of a code word space formed or corresponding to the encoding matrix.

[0021] In a third aspect of the present application, a computer readable storage medium is provided. The computer readable storage medium has stored thereon a computer program which, when executed by a processor, implements the method according to the first aspect.

[0022] In a fourth aspect of the present application, a computer program product is provided. The computer program product is tangibly stored on a computer readable medium and includes computer executable instructions that, when executed, cause a device to implement the method according to the first aspect.

[0023] In a fifth aspect of the present application, a chip is provided. The chip is configured to execute the method according to the first aspect. BRIEF DESCRIPTION OF DRAWINGS

[0024] The features, advantages, and other aspects of the present application will become more apparent from the following detailed description in conjunction with the accompanying drawings. Several implementations of the present application are illustrated in the drawings, in which:

[0025] FIG. 1 shows a schematic block diagram of a communication system in which a possible implementation of the present application can be implemented;

[0026] FIG. 2 shows a basic flow diagram of wireless communication according to a possible implementation of the present application;

[0027] FIGS. 3, 4, 5 and 6 respectively show flow diagrams of a communication method according to a possible implementation of the present application;

[0028] FIG. 7 shows simulation results of decoding according to a possible implementation of the present application;

[0029] Fig. 8 shows a schematic block diagram of a communication apparatus according to a possible implementation manner of the present application; and

[0030] Fig. 9 is a simplified block diagram of an example device suitable for implementing possible implementation manners of the present application.

[0031] In the various figures, same or similar reference numerals indicate same or similar elements. DETAILED DESCRIPTION

[0032] Possible implementation manners of the present application will be described in more detail below with reference to the accompanying drawings.

[0033] In the description of possible implementation manners of the present application, the term "comprising" and its conjugations should be open-ended to the extent that the term "comprising" and its conjugations should not exclude other elements or steps. The term "based on" should not be construed that the described feature is required by all examples or examples. The term "one possible implementation" or "the possible implementation" should be construed as "at least one possible implementation". The terms "first", "second" and the like can refer to different or similar elements. Other explicit or implicit definitions can also be included below. Expressions such as "at least one of A, B, and C" or "at least one of A, B, or C" should be understood as any of the following: at least one A; at least one B; at least one C; at least one A and at least one B; at least one A and at least one C; at least one B and at least one C; at least one A, at least one B, and at least one C, the above is exemplified by A, B and C with three elements, when there are more elements in the expression, the meaning of the expression can be obtained according to the foregoing rules.

[0034] Fig. 1 shows a schematic block diagram of a communication system 100 in which a possible implementation of the present application can be implemented. As shown, the communication system 100 includes terminal devices 110-1, 110-2, …, 110-M and a network device 120. In the following, the terminal devices 110-1, 110-2, …, 110-M are also referred to as UE#1, UE#2, …, UE#M (M is a positive integer). In addition, in the following, the terminal devices 110-1, 110-2, …, 110-M are collectively referred to as terminal devices 110 or individually referred to as terminal device 110.

[0035] The terminal device 110 is a device with wireless transceiving function. The terminal device 110 can be deployed on land, including indoors or outdoors, handheld or vehicle-mounted; can also be deployed on water surface (such as ships, etc.); and can also be deployed in the air (such as airplanes, balloons and satellites, etc.). The terminal device 110 can be a mobile phone, a tablet computer, a vehicle-mounted mobile device, a personal digital assistant (PDA), a computer with wireless transceiving function, a virtual reality (VR) terminal device, an augmented reality (AR) terminal device, a wearable device, an Internet of Things device, a wireless terminal device in industrial control, a wireless terminal device in self driving, a wireless terminal device in remote medical treatment, a wireless terminal device in smart grid, a wireless terminal in transportation safety, a wireless terminal device in smart city, a wireless terminal device in smart home, a user equipment (UE), or the like.

[0036] The network device 120 is a Radio Access Network (RAN) device that accesses the terminal device 110 to a wireless network. A coverage area of the network device 120 is referred to as a cell 122. Examples of the RAN device can include, but are not limited to, a Next generation NodeB (gNB), a Transmission Reception Point (TRP), an Evolved Node B (eNB), a Radio Network Controller (RNC), a Node B (NB), a Base Station Controller (BSC), a Base Transceiver Station (BTS), a Home Base Station (for example, a Home eNodeB, or a Home NodeB), a Base Band Unit (BBU), or a Wireless Fidelity (WiFi) Access Point (AP), an Integrated Access and Backhaul (IAB) node, and the like. In a possible implementation, the network device 120 can include a Centralized Unit (CU), or a Distributed Unit (DU), or both the CU and the DU.

[0037] Examples of the communication system 100 can include, but are not limited to, a Narrow Band-Internet of Things (NB-IoT) system, a Global System for Mobile Communications (GSM) system, an Enhanced Data rate for GSM Evolution (EDGE) system, a Wideband Code Division Multiple Access (WCDMA) system, a Code Division Multiple Access 2000 (CDMA2000) system, a Time Division-Synchronization Code Division Multiple Access (TD-SCDMA) system, a Long Term Evolution (LTE) system, and three big application scenarios of a next-generation 5G mobile communication system, i.e., Enhanced Mobile Broadband (eMBB), Ultra-reliable and Low Latency Communications (URLLC), and enhanced Machine-Type Communication (eMTC).

[0038] It can be understood that the number of terminal devices and network devices shown in FIG. 1 is merely an example and is not intended to suggest any limitation. According to actual needs, the communication system 100 can include any appropriate number of terminal devices and network devices.

[0039] FIG. 2 shows a basic flow diagram of wireless communication according to a possible implementation of the present application. As shown in FIG. 2, after source encoding, channel encoding and modulation of a bit stream generated by a source, a transmitting terminal device transmits the bit stream to a receiving terminal device through a noisy channel. The receiving terminal device demodulates, channel decodes and source decodes the received signal, thereby recovering the bit stream generated by the source. In uplink transmission, the transmitting terminal device can be the terminal device 110 in FIG. 1, and the receiving terminal device can be the network device 120 in FIG. 1. In downlink transmission, the transmitting terminal device can be the network device 120 in FIG. 1, and the receiving terminal device can be the terminal device 110 in FIG. 1.

[0040] The transmitting device can perform channel coding on the digital signal to be transmitted based on a coding matrix (also referred to as a generator matrix). In coding theory, a coding matrix is a matrix whose rows form a basis of a linear code. All codewords are linear combinations of the rows of the matrix, that is, the linear code is the row space of its coding matrix.

[0041] If G denotes the coding matrix, it generates the codewords of the linear code C in the way w = s*G, where w is a codeword of the linear code C, s is the information to be encoded and can be an arbitrary vector. The format of the coding matrix of a linear (n, k, d, q) code is k*n, where n is the length of the codewords, k is the number of information bits (dimension of C as a vector space), d is the minimum distance of the code, and q is the size of the finite field, i.e. the number of symbols in the alphabet (so q = 2 denotes a binary code, etc.). The number of redundancy bits is denoted by r = n - k.

[0042] The standard form of a coding matrix is G = [I k |P], where I k is a k*k identity matrix and P is a k*r matrix. When the coding matrix is in standard form, the code C is a systematic code in its first k coordinate positions.

[0043] The receiving device can check whether the received symbols conform to the codeword characteristics based on a check matrix. For example, the receiving device can check whether the received symbols conform to the codeword characteristics based on , where H denotes a (n - k)*n parity check matrix, is the received symbol vector (also referred to as the "received vector"), and E denotes the check result. When E is all zeros, it means that the check is passed. In this case is a codeword of the linear space C. However, it does not mean that is necessarily a correct codeword. When errors happen in a sufficiently coincidental way, the received vector can happen to be equal to another codeword of the C space, in which case the error cannot be discovered based on the check matrix.

[0044] The receiving device can use the coding matrix to construct a parity check matrix of a code and vice versa. If the coding matrix is in the standard form G = [I k |P], then the C parity check matrix is H = [-P T |I n-k ]. Where P T is the transpose of the P matrix.

[0045] As mentioned before, GRAND decoding and OSD decoding are two commonly used decoding methods. GRAND decoding requires a check matrix H and the received vector The general process of GRAND decoding is as follows. First, the receiving end device checks , if the result is all 0, , the decoding ends. If the check fails, the receiving end device flips a certain position of the received vector , for example, flips 0 to 1 or flips 1 to 0, checks

[0046] , if the check passes, the decoding ends. Otherwise, flip another position of the received vector , and check until a flipped vector that passes the check is found, or any position of the received vector is flipped once. In the case that any position of the received vector is flipped once and the check fails, the receiving end device flips any two positions of the received vector

[0047] , and judges whether the check passes. After trying all two-position flipping combinations of the received vector , enter the combination of flipping 3, 4, 5, … positions, and keep flipping until the correct check result is found.

[0048] Therefore, GRAND decoding is a decoding method that finds the code word closest to the received vector by constantly trying to flip 1, 2, 3, … symbols and takes it as the decoding result.

[0049] The advantage of GRAND decoding is that it only needs a check matrix to decode, and can be used for any code and can always find the code word closest to the received symbol in Hamming distance as the decoding result. For example, tail-biting convolutional code (TBCC) and turbo code (TURBO) in 4G, polar code and low density parity check code (LDPC) in 5G, for very high code rate or very short code length, GRAND can quickly get the decoding result. However, when the code rate decreases or the code length increases, the average / maximum complexity of decoding increases by the number of combinations. Therefore, its application range is limited and is not suitable for current mainstream communication systems.

[0050] The advantage of GRAND decoding is that it only needs a check matrix to decode, and can be used for any code and can always find the code word closest to the received symbol in Hamming distance as the decoding result. For example, tail-biting convolutional code (TBCC) and turbo code (TURBO) in 4G, polar code and low density parity check code (LDPC) in 5G, for very high code rate or very short code length, GRAND can quickly get the decoding result. However, when the code rate decreases or the code length increases, the average / maximum complexity of decoding increases by the number of combinations. Therefore, its application range is limited and is not suitable for current mainstream communication systems.

[0051] OSD decoding is a sub-optimal maximum likelihood decoding, which performance approaches maximum likelihood decoding, and can improve performance by increasing the decoding order at lower signal-to-noise ratio. The disadvantage of OSD decoding is that the computational complexity increases exponentially with the order o.

[0052] The approximate process of OSD decoding is as follows. The receiving end device sorts the log likelihood ratio (LLR) values of the received symbols of the (N, K) encoding, where N represents the length of the encoding transmission code, and K represents the number of information bits contained. After sorting the absolute values of the LLRs, the K largest positions are marked and their signs are recorded, the encoding matrix G is reordered, and the marked K positions are placed in the first K positions by column permutation to obtain matrix G'. Gaussian elimination (row permutation and addition and subtraction operations) is performed on matrix G' to obtain a new encoding matrix G" (the first K columns form a unit matrix).

[0053] Then, the receiving end device multiplies the signs of the K largest positions by the encoding matrix G' to obtain the 0-order recovered code word. The Euclidean distance between the 0-order code word and the LLR of the received symbol is calculated, and the code word and the distance value are recorded.

[0054] Subsequently, the receiving end device flips the signs of the K largest positions by 1 position and multiplies them by the encoding matrix G' to obtain the 1-order recovered code word. The receiving end device calculates the Euclidean distance of the 1-order recovered code word, compares it with the recorded code word Euclidean distance, retains the smaller value, and retains the corresponding code word. The total number of first-order code words is K.

[0055] Further, the receiving end device flips the signs of the K largest positions by 2, 3, 4, … positions and multiplies them by the encoding matrix G' to obtain the 2, 3, 4, …-order recovered code words. The receiving end device calculates the Euclidean distance between the 2, 3, 4, …-order recovered code words and the LLR of the received symbol, compares it with the recorded code word Euclidean distance, retains the smaller value, and retains the corresponding code word. The total number of 2, 3, 4, …-order code words is (where C represents the number of combinations).

[0056] The OSD decoding of order o has 0, 1, 2, 3, … o flips, and after all are completed, the code word with the smallest Euclidean distance is selected as the output.

[0057] The biggest defect of OSD decoding is that it needs to do Gaussian elimination to transform the column-permuted G' matrix into a new generator matrix by row permutation. The process of Gaussian elimination is complex, and when linearly dependent rows appear in the selected K columns, the matrix will not be full rank, at which time a new column needs to be selected to replace one of the K columns and Gaussian elimination needs to be done again. Therefore, a decoding method with lower complexity is needed.

[0058] FIG. 3 shows a flowchart of a communication method 300 according to a possible implementation of the present application. In one possible implementation, the method 300 can be implemented by the terminal device 110 in the example communication system 100, for example, by a processor or processing unit of the terminal device 110 in cooperation with other components (e.g., a transceiver). In another possible implementation, the method 300 can be implemented by the network device 120 in the example communication system 100, for example, by a processor or processing unit of the network device 120 in cooperation with other components (e.g., a transceiver). In the following, possible implementations of the present application will be described by taking the terminal device 110 as an example. In other possible implementations, the method 300 can also be implemented by other communication apparatuses independent of the example communication system 100.

[0059] At step 310, the terminal device 110 determines a log-likelihood ratio (LLR) vector associated with the received vector.

[0060] At step 320, the terminal device 110 takes absolute values of at least part of elements in the LLR vector and sorts the absolute values in ascending order.

[0061] At step 330, the terminal device 110 divides elements in the systematic bit vector into a plurality of groups according to the sorted result in ascending order. The systematic bit vector includes the first to k-th elements in the received vector, where k is an integer greater than or equal to 1.

[0062] At step 340, the terminal device 110 determines a flipping order of bits in each group in the plurality of groups as non-decreasing.

[0063] At step 350, the terminal device 110 flips the bits in each group based on the flipping order to obtain a plurality of flipped systematic bit vectors.

[0064] At step 360, the terminal device 110 determines a plurality of encoded vectors based on the plurality of flipped systematic bit vectors and the encoding matrix. And

[0065] At step 370, the terminal device 110 selects a first encoded vector with a minimum Euclidean distance from the LLR vector from the plurality of encoded vectors as a decoding result of the received vector.

[0066] The scheme of the present application can be regarded as a decoding method combining the advantages of OSD and GRAND, a high-efficiency GRAND for narrowing the flipping range through LLR sorting, or a high-efficiency OSD without Gaussian elimination. In the scheme of the present application, the LLR vector is sorted, and then the k systematic bits are divided into multiple groups according to the sorting result, and different flipping orders are used for different groups, thereby reducing the total number of flips. After the systematic bits are flipped, the flipped systematic bits are obtained, and then the n-length encoding result is obtained through the generator matrix G. Because the encoding result is obtained according to the encoding matrix, the encoding result must be a codeword. By flipping a sufficient number of systematic bits, a codeword within a certain flipping range is obtained. The codeword is compared with the received symbol, and the flipped encoding result with the smallest Euclidean distance from the received symbol is selected as the decoding result and output.

[0067] In a possible implementation, sorting the elements in the LLR vector after taking the absolute values of the elements can include sorting the elements in the LLR vector corresponding to the systematic bit vector after taking the absolute values of the elements. This will be described with reference to FIG. 4.

[0068] FIG. 4 shows a flowchart of a communication method 400 according to a possible implementation of the present application. The method 400 can be regarded as an example implementation of the method 300. In a possible implementation, the method 400 can be implemented by the terminal device 110 in the example communication system 100, for example, by the processor or processing unit of the terminal device 110 in cooperation with other components (for example, the transceiver). In another possible implementation, the method 400 can be implemented by the network device 120 in the example communication system 100, for example, by the processor or processing unit of the network device 120 in cooperation with other components (for example, the transceiver). In the following, the possible implementation of the present application will be described by taking the terminal device 110 as an example. In other possible implementations, the method 400 can also be implemented by other communication apparatuses independent of the example communication system 100.

[0069] In the method 400, the received vector received by the terminal device 110 from the network device 120 is represented by The received vector may be a modulation symbol sequence (for example, a {-1, +1} sequence). The received vector The number of elements in the received vector The first k elements in the received vector are systematic bits (also referred to as information bits), and the k systematic bits constitute a systematic bit vector where k is an integer greater than or equal to 1, for example, k = 10.

[0070] In addition, in the method 400, the encoding matrix is denoted by G, where G is a k*n matrix.

[0071] As shown in FIG. 4, at step 410, the terminal device 110 can determine a log-likelihood ratio (LLR) vector associated with the received vector . For example, the terminal device 110 can determine the ratio of the probability that each element in the received vector takes the value 0 to the probability that the element takes the value 1, and then take the logarithm, to determine the LLR value of each element. The LLR values of the n elements in the received vector form an LLR vector, where the LLR vector contains n elements. For example, the LLR value of element x in the received vector may be determined based on the following:

[0072] where LLR(x) represents the LLR value of element x, P(x=0) represents the probability that element x takes the value 0, and P(x=1) represents the probability that element x takes the value 1.

[0073] At step 415, the terminal device 110 can sort the elements in the LLR vector corresponding to the systematic bit vector in ascending order after taking the absolute value. For example, the LLR vector is [r1, r2, …, r100], where ri represents the LLR value of the i-th element in the received vector , and the elements [r1, r2, …, r10] in the LLR vector corresponding to the systematic bit vector are sorted in ascending order after taking the absolute value to obtain the vector [rs1, rs2, …, rs10]. For example, the elements in the vector [rs1, rs2, …, rs10] can be arranged in ascending order or descending order.

[0074] At step 420, the terminal device 110 can divide the elements in the systematic bit vector into m groups in ascending order according to the sorting result described above. m Each group includes m1, m2, m3, …, m elements, where the absolute value of the LLR value corresponding to any element in the group is less than that of any element in the group , …, the absolute value of the LLR value corresponding to any element in the group is less than that of any element in the group . In this application, the groups are also referred to as the first group, the second group, …, the m-th group, respectively.

[0075] In step 425, the terminal device 110 can determine the flipping order of the bits in the m groups as non-increasing. For example, the flipping order of the bits in is determined as o1, the flipping order of the bits in is determined as o2, …, the flipping order of the bits in is determined as o m , such that o1≥o2≥…o m .

[0076] Consider a first example. In this example, the systematic bit vector is [u1, u2, u3, u4, u5, u6, …, u15], is [u1, u2, u3], is [u4, u5], is [u6, …, u15]. m1=3, o1=2; m2=2, o2=1; m3=10, o3=0. The method 400 will be described below in combination with the first example.

[0077] In step 430, the terminal device 110 can encode the systematic bit vector using the encoding matrix G to obtain a vector a0, where a0= Then, the terminal device 110 can determine the Euclidean distance x of the vector a0 and the LLR vector, and record a0 as the decoding result b, i.e., b=a0.

[0078] In step 435, the terminal device 110 can flip the first bit (e.g., u1) in (i.e., the first group) to obtain a flipped systematic bit vector, encode the flipped systematic bit vector using the encoding matrix G to obtain a current decoding result a0, and let a=a0.

[0079] In step 440, the terminal device 110 can determine the Euclidean distance x’ of the vector a0 and the LLR vector. If x’ is less than x, the terminal device 110 updates the decoding result b to a, and updates the minimum Euclidean distance x to x’.

[0080] In step 445, the terminal device 110 can flip the 2nd, 3rd, …, m1th bits (e.g., u2 and u3) in respectively to obtain corresponding flipped systematic bit vectors, encode the corresponding flipped systematic bit vectors using the encoding matrix G to obtain current decoding results a y , and let a=a yand repeat the operation of "encoding the flipped systematic bit vector with the encoding matrix G to obtain a current decoding result a0, and let a = a0" in step 435 and repeat step 440.

[0081] In step 450, the terminal device 110 can select two bits in respectively to flip, and repeat steps 435 and 440, and loop the steps until the combination of the number of bits is selected.

[0082] For example, first, the terminal device 110 can select u1 and u2 in to flip to obtain a flipped systematic bit vector, encode the flipped systematic bit vector with the encoding matrix G to obtain a current decoding result a0, and let a = a0. Further, the terminal device 110 can determine the Euclidean distance x' of the vector a0 and the LLR vector. If x' is less than x, the terminal device 110 updates the decoding result b to a, and updates the minimum Euclidean distance x to x'.

[0083] Then, the terminal device 110 can select u1 and u3 in to flip to obtain a flipped systematic bit vector, encode the flipped systematic bit vector with the encoding matrix G to obtain a current decoding result a0, and let a = a0. Further, the terminal device 110 can determine the Euclidean distance x' of the vector a0 and the LLR vector. If x' is less than x, the terminal device 110 updates the decoding result b to a, and updates the minimum Euclidean distance x to x'.

[0084] Finally, the terminal device 110 can select u2 and u3 in to flip to obtain a flipped systematic bit vector, encode the flipped systematic bit vector with the encoding matrix G to obtain a current decoding result a0, and let a = a0. Further, the terminal device 110 can determine the Euclidean distance x' of the vector a0 and the LLR vector. If x' is less than x, the terminal device 110 updates the decoding result b to a, and updates the minimum Euclidean distance x to x'.

[0085] In step 455, the terminal device 110 can select 3 …… o1 bits in respectively to flip, and repeat steps 425 and 430, and loop the steps until the combination of the number of bits is selected. It can be understood that in the above example, the flipping order o1 = 2 of the elements in , the terminal device 110 will not perform the step 455.

[0086] In step 460, the terminal device 110 can select 3 …… o1 bits in 1, 2, …, o2 bits in the second group are flipped, and steps 425 to 455 are repeated, cycling through the steps until the combination of the number of bits is selected.

[0087] For example, first, the terminal device 110 can select u4 in and u1 in to flip to obtain a flipped systematic bit vector, encode the flipped systematic bit vector using the encoding matrix G to obtain a current decoding result a0, and let a = a0. Further, the terminal device 110 can determine the Euclidean distance x’ of the vector a0 and the LLR vector. If x’ is less than x, the terminal device 110 updates the decoding result b to a, and updates the minimum Euclidean distance x to x’.

[0088] Then, the terminal device 110 can select u4 in and u2 in to flip to obtain a flipped systematic bit vector, encode the flipped systematic bit vector using the encoding matrix G to obtain a current decoding result a0, and let a = a0. Further, the terminal device 110 can determine the Euclidean distance x’ of the vector a0 and the LLR vector. If x’ is less than x, the terminal device 110 updates the decoding result b to a, and updates the minimum Euclidean distance x to x’.

[0089] Subsequently, the terminal device 110 can select u4 in and u3 in to flip to obtain a flipped systematic bit vector, encode the flipped systematic bit vector using the encoding matrix G to obtain a current decoding result a0, and let a = a0. Further, the terminal device 110 can determine the Euclidean distance x’ of the vector a0 and the LLR vector. If x’ is less than x, the terminal device 110 updates the decoding result b to a, and updates the minimum Euclidean distance x to x’.

[0090] Further, the terminal device 110 can select u5 in and u1 in to flip to obtain a flipped systematic bit vector, encode the flipped systematic bit vector using the encoding matrix G to obtain a current decoding result a0, and let a = a0. Further, the terminal device 110 can determine the Euclidean distance x’ of the vector a0 and the LLR vector. If x’ is less than x, the terminal device 110 updates the decoding result b to a, and updates the minimum Euclidean distance x to x’.

[0091] Then, the terminal device 110 can select u5 in and u1 in The terminal device 110 can flip the u2 in the vector a to obtain a flipped systematic bit vector, encode the flipped systematic bit vector using the encoding matrix G to obtain a current decoding result a0, and let a = a0. Further, the terminal device 110 can determine the Euclidean distance x' of the vector a0 and the LLR vector. If x' is less than x, the terminal device 110 updates the decoding result b to a, and updates the minimum Euclidean distance x to x'.

[0092] Subsequently, the terminal device 110 can select the u5 in the vector a to obtain a flipped systematic bit vector, encode the flipped systematic bit vector using the encoding matrix G to obtain a current decoding result a0, and let a = a0. Further, the terminal device 110 can determine the Euclidean distance x' of the vector a0 and the LLR vector. If x' is less than x, the terminal device 110 updates the decoding result b to a, and updates the minimum Euclidean distance x to x'. In step 465, the terminal device 110 can select 1, 2, …, o3 bits in the group

[0093] (i.e., the third group) to flip, respectively, and repeat steps 425 to 460, and cycle the steps until the combination of the number of bits is selected. It can be understood that in the above example, the flipping order o3 of the elements in the vector a is 0, so the terminal device 110 will not perform step 465.

[0094] In step 470, the terminal device 110 can take the current reserved decoding result b as the final decoding result.

[0095] In the method 400, under the same flipping maximum order o limitation, the maximum number of times of performance flipping by the method of flipping the systematic bits is less than the number of flipping the parity check matrix.

[0096] For example, after grouping the 106 bits in the (127, 106) BCH (Bose-Chaudhuri-Hocquenghem Code), the number of times of flipping is less than directly flipping the 106 bits, and the performance is better. If the 106 bits are directly flipped by the first order, the number of times of flipping is 1+106+106*(106-1) / 2 = 5672. After grouping the K bits into three groups, m1 = 10, m2 = 30, m3 = 66, o1 = 2, o2 = 1, o3 = 0, the number of times of flipping is (1+10+10*(10-1) / 2)*30 = 1680, and thus the complexity is lower.

[0097] ​Furthermore, if decoding is performed with the existing GRAND parity check matrix, the number of flips required is 1 + 127 + 127 * 126 / 2 = 8130. Thus, the complexity of the method 400 is lower than that of the GRAND decoding.

[0098] Alternatively, in a possible implementation, sorting the at least part of the elements in the LLR vector after taking absolute values of the at least part of the elements can include sorting all the elements in the LLR vector after taking absolute values of all the elements in the LLR vector. In this possible implementation, the terminal device 110 can divide the elements in the systematic bit vector in ascending order of the sorting result into the plurality of groups by: determining the smallest n-k elements in the LLR vector, where n represents the number of all the elements in the LLR vector; determining m1 elements from the n-k elements, the m1 elements corresponding to the m1 elements in the systematic bit vector, where m1 is an integer greater than or equal to 1; dividing the m1 elements in the systematic bit vector into a starting group in the plurality of groups; and dividing the other k-m1 elements in the systematic bit vector into subsequent groups after the starting group. This will be described with reference to FIG. 5.

[0099] FIG. 5 shows a flowchart of a communication method 500 according to a possible implementation of the present application. The method 500 can be regarded as another example implementation of the method 300. In a possible implementation, the method 500 can be implemented by the terminal device 110 in the example communication system 100, for example, by the processor or processing unit of the terminal device 110 in cooperation with other components (for example, the transceiver). In another possible implementation, the method 500 can be implemented by the network device 120 in the example communication system 100, for example, by the processor or processing unit of the network device 120 in cooperation with other components (for example, the transceiver). In the following, the possible implementation of the present application will be described taking the terminal device 110 as an example. In other possible implementations, the method 500 can also be implemented by other communication apparatuses independent of the example communication system 100.

[0100] In the method 500, the received vector received by the terminal device 110 from the network device 120 is represented by The received vector may be a sequence of modulation symbols (for example, a sequence of {-1, +1}). The received vector The number of elements in the received vector The first k elements in the received vector are systematic bits (also referred to as information bits), and the k systematic bits constitute a systematic bit vector where k is an integer greater than or equal to 1, for example, k = 10.

[0101] Further, in the method 500, the encoding matrix is denoted by G, which is a k*n matrix.

[0102] As shown in FIG. 5, at step 510, the terminal device 110 can determine a log-likelihood ratio (LLR) vector associated with the received vector The LLR vector contains n elements, for example. Step 510 is similar to step 410 in method 400, and thus will not be described again.

[0103] At step 515, the terminal device 110 can take absolute values of all elements in the LLR vector and sort them. For example, the LLR vector is [r1, r2, …, r100], where r represents the LLR value of the i-th element in the received vector The LLR vector is sorted to obtain a vector [rt1, rt2, …, rt100] after taking absolute values of all elements in the LLR vector.

[0104] At step 520, the terminal device 110 can determine the smallest n-k elements in the LLR vector. In other words, the terminal device 110 can determine the smallest n-k elements in the vector [rt1, rt2, …, rt100].

[0105] At step 525, the terminal device 110 can determine m1 elements from the n-k elements, where the m1 elements correspond to the m1 elements in the systematic bit vector , where m1 is an integer greater than or equal to 1. The terminal device 110 can divide the m1 elements in the systematic bit vector into a starting group in a plurality of groups. The starting group can be denoted by .

[0106] At step 530, the terminal device 110 can divide the other k-m1 elements in the systematic bit vector into subsequent groups after the starting group. For example, the terminal device 110 can divide the other k-m1 elements in the systematic bit vector into m-1 groups , each of which includes m2, m3, …, m m , where The absolute value of the LLR value corresponding to any element in is smaller than any one of The absolute value of the LLR value corresponding to any element in is smaller than any one of The absolute value of the LLR value corresponding to any element in is smaller than any one of

[0107] Subsequently, the terminal device 110 can perform steps 425 to 470 in the method 400 to determine the decoding result of the received vector. For simplicity, steps 425 to 470 are not shown in FIG. 5.

[0108] It can be appreciated that the main difference between the method 500 and the method 400 is that the value of m1 is not fixed, m1 is the number of corresponding elements in the systematic bit vector of the smallest n-k elements in the LLR vector. In other words, in the method 500, the terminal device 110 can dynamically group the elements in the systematic bit vector. Thus, the performance of the method 500 is superior to that of the method 400.

[0109] Alternatively, in the method 500, the terminal device 110 can determine the smallest n-k+x elements in the LLR vector, and then determine m1 elements from the n-k+x elements as the starting group, where x is an integer greater than zero. When the value of x is not large, its performance is approximately the same as that of the method 500.

[0110] Alternatively, in a possible implementation, sorting the at least part of the elements in the LLR vector after taking absolute values can include sorting all the elements in the LLR vector after taking absolute values. In this possible implementation, the terminal device 110 can divide the elements in the systematic bit vector into groups in ascending order of the sorting result by: determining the smallest n-k elements in the LLR vector, where n represents the number of all the elements in the LLR vector; determining x elements from the n-k elements, the x elements corresponding to x elements in the systematic bit vector, where x is an integer greater than or equal to 1; dividing the x elements in the systematic bit vector into y groups; and dividing the other k-x elements in the systematic bit vector into the subsequent m-y groups of the y groups. This will be described with reference to FIG. 6.

[0111] FIG. 6 shows a flow chart of a communication method 600 according to a possible implementation of the present application. The method 600 can be regarded as another example implementation of the method 300. In a possible implementation, the method 600 can be implemented by the terminal device 110 in the example communication system 100, for example, can be implemented by the processor or processing unit of the terminal device 110 in cooperation with other components (for example, the transceiver). In another possible implementation, the method 600 can be implemented by the network device 120 in the example communication system 100, for example, can be implemented by the processor or processing unit of the network device 120 in cooperation with other components (for example, the transceiver). In the following, the possible implementation of the present application will be described taking the terminal device 110 as an example. In other possible implementations, the method 600 can also be implemented by other communication apparatuses independent of the example communication system 100.

[0112] In the method 600, the received vector from the network device 120 received by the terminal device 110 is denoted by The received vector may be a sequence of modulation symbols (e.g., a sequence of {-1, +1}). The received vector has a number of elements denoted by n, e.g., n = 100. The first elements in the received vector

[0113] 1 to k elements are systematic bits (also referred to as information bits), and the k systematic bits form a systematic bit vector where k is an integer greater than or equal to 1, e.g., k = 10.

[0114] In addition, in the method 600, the encoding matrix is denoted by G, which is a k*n matrix.

[0115] As shown in FIG. 6, at step 610, the terminal device 110 can determine a log-likelihood ratio (LLR) vector associated with the received vector . For example, the LLR vector contains n elements. Step 610 is similar to step 410 in the method 400, and thus is not described again.

[0116] At step 615, the terminal device 110 can take absolute values of all elements in the LLR vector and sort the absolute values. For example, the LLR vector is [r1, r2, …, r100], where r denotes the LLR value of the i-th element in the received vector , and taking absolute values of all elements in the LLR vector and sorting the absolute values results in a vector [rt1, rt2, …, rt100]. Step 615 is similar to step 515 in the method 500.

[0117] At step 620, the terminal device 110 can determine the smallest n-k elements in the LLR vector. In other words, the terminal device 110 can determine the smallest n-k elements in the vector [rt1, rt2, …, rt100]. Step 620 is similar to step 520 in the method 500.

[0118] At step 625, the terminal device 110 can determine x elements from the n-k elements, where the x elements correspond to x elements in the systematic bit vector , and x is an integer greater than or equal to 1.

[0119] At step 630, the terminal device 110 can divide the x elements in the systematic bit vector into y groups , where each group includes m1, m2, …, m y elements.

[0120] At step 635, the terminal device 110 can divide the other k-x elements in the systematic bit vector into subsequent m-y groups of y groups. For example, the terminal device 110 can divide the other k-x elements in the systematic bit vector into m-y groups each group including m y+1 , m y+2 , …, m m elements, where the absolute value of the LLR value corresponding to any element in the group is less than any one of the absolute value of the LLR value corresponding to any element in the group is less than any one of the absolute value of the LLR value corresponding to any element in the group is less than any one of

[0121] Subsequently, the terminal device 110 can perform steps 425-470 in method 400 to determine the decoding result of the received vector. For simplicity, steps 425-470 are not shown in FIG. 6.

[0122] In method 600, the terminal device 110 can finely dynamically group the elements in the systematic bit vector, thus having lower complexity and better performance.

[0123] In one possible implementation, the terminal device 110 can further determine the Hamming distance between a second encoding vector in the plurality of encoding vectors and the LLR vector. The second encoding vector is the same as or different from the first encoding vector. If the Hamming distance is less than or equal to one half of the minimum distance of the code word space formed by or corresponding to the encoding matrix, the terminal device 110 can stop decoding the received vector.

[0124] For example, in step of method 400, the terminal device 110 can determine the Euclidean distance x' between the vector a0 and the LLR vector. If x' is less than x, the terminal device 110 updates the decoding result b to a and the minimum Euclidean distance x to x'. In addition, the terminal device 110 can further determine the Hamming distance h between the current decoding result a and the LLR vector. When h≤d / 2, the terminal device 110 can stop decoding the received vector and output the result with the minimum Euclidean distance as the decoding result, where d represents the minimum distance of the code word space formed by or corresponding to the encoding matrix G. Alternatively, the terminal device 110 can also determine the Hamming distance h between the recorded decoding result b with the minimum Euclidean distance and the LLR vector. When h≤d / 2, the terminal device 110 can stop decoding the received vector and output the result with the minimum Euclidean distance as the decoding result.

[0125] Since the terminal device 110 can stop decoding the received vector earlier when h≤d / 2, the complexity of the method can be reduced.

[0126] For example, taking a BCH code as an example, n=127, k=99, M (the base original order) =7, and T=4 (the maximum correctable bit number, equal to the minimum code distance (d-1) / 2). When the maximum flipping order is limited to 4, the performance is slightly better than the existing scheme, and the average flipping number is halved under each EsN0 condition compared with the existing scheme.

[0127] It should be understood that, although the implementation of the terminal device 110 stopping decoding earlier is described above in combination with the method 400, the implementation can be used in combination with any one of the methods 400, 500, and 600, and the protection scope of the present application is not limited in this respect.

[0128] FIG. 7 shows simulation results of decoding according to a possible implementation of the present application. The simulation results of FIG. 7 can be obtained, for example, by performing the method 500. In FIG. 7, o represents the total flipping order (or the maximum flipping order), and o=o1+o2+…o m , oh=o2.

[0129] When flipping is performed only using the encoding matrix, the total flipping order o is set to 5 orders (i.e., o=5), in which the minimum x bits in the system bit vector are flipped 5 times, and k-x bits are flipped 0 times, or the minimum x bits are flipped 4 times, and k-x bits are flipped 1 time. As can be seen from FIG. 7, the performance of decoding according to the possible implementation of the present application is 0.9 dB better than the existing GRAND decoding, and the complexity is basically 1 / 30 of the GRAND decoding.

[0130] In addition, if the total flipping order is set to 6 orders (i.e., o=6), in which the minimum x bits are flipped 6 times and k-x bits are flipped 0 times, or the minimum x bits are flipped 5 times and k-x bits are flipped 1 time, the performance of decoding according to the possible implementation of the present application is 1.2 dB better than the existing GRAND decoding, and the complexity is basically 1 / 10 of the GRAND decoding.

[0131] Compared with the OSD decoding which requires Gaussian elimination, the performance loss of decoding according to the possible implementation of the present application is about 0.25 dB, but decoding according to the possible implementation of the present application can eliminate the process of Gaussian elimination.

[0132] Fig. 8 shows a schematic block diagram of a communication apparatus 800 according to a possible implementation of the present application. The communication apparatus 800 can be implemented as a device or a chip in a device, and the scope of the present application is not limited in this respect. The communication apparatus 800 can comprise a number of units for performing the corresponding steps of the methods 300, 400, 500 and 600 as discussed in Figs. 3 to 6. The communication apparatus 800 can be implemented as or a part of the terminal device 110 as shown in Fig. 1. Alternatively, the communication apparatus 800 can be implemented as or a part of the network device 120 as shown in Fig. 1.

[0133] As shown in Fig. 8, the communication apparatus 800 comprises a processing unit 810.

[0134] The processing unit 810 is configured to determine a log-likelihood ratio (LLR) vector associated with the received vector; sort at least part of elements in the LLR vector after taking absolute values of the at least part of elements; divide elements in a systematic bit vector into a plurality of groups in ascending order of the sorting result, wherein the systematic bit vector comprises 1st to kth elements in the received vector, and k is an integer greater than or equal to 1; determine a flipping order of bits in each group of the plurality of groups as non-decreasing; flip the bits in each group based on the flipping order to obtain a plurality of flipped systematic bit vectors; determine a plurality of coded vectors based on the plurality of flipped systematic bit vectors and a coding matrix; and select a first coded vector with a minimum Euclidean distance to the LLR vector from the plurality of coded vectors as a decoding result of the received vector.

[0135] In a possible implementation, the sorting at least part of elements in the LLR vector after taking absolute values of the at least part of elements comprises: sorting elements in the LLR vector corresponding to the systematic bit vector after taking absolute values of the elements.

[0136] In a possible implementation, the sorting at least part of elements in the LLR vector after taking absolute values of the at least part of elements comprises: sorting all elements in the LLR vector after taking absolute values of the elements.

[0137] In a possible implementation, the dividing elements in the systematic bit vector into the plurality of groups in ascending order of the sorting result comprises: determining n-k smallest elements in the LLR vector, wherein n represents a number of all elements in the LLR vector; determining m1 elements from the n-k smallest elements, the m1 elements corresponding to m1 elements in the systematic bit vector, wherein m1 is an integer greater than or equal to 1; dividing the m1 elements in the systematic bit vector into a starting group of the plurality of groups; and dividing other k-m1 elements in the systematic bit vector into subsequent groups of the starting group.

[0138] In a possible implementation, dividing the elements in the systematic bit vector into groups in ascending order of the sorting result comprises: determining the smallest n-k elements in the LLR vector, where n represents the number of all elements in the LLR vector; determining x elements from the n-k elements, the x elements corresponding to x elements in the systematic bit vector, where x is an integer greater than or equal to 1; dividing the x elements in the systematic bit vector into y groups; and dividing the other k-x elements in the systematic bit vector into the subsequent m-y groups of the y groups.

[0139] In a possible implementation, the processing unit 810 is further configured to: determine a Hamming distance between a second encoding vector in the plurality of encoding vectors and the LLR vector, where the second encoding vector is the same as or different from the first encoding vector; and stop decoding the received vector if the Hamming distance is less than or equal to one half of a minimum distance of a code word space formed or corresponding to the encoding matrix.

[0140] FIG. 9 is a simplified block diagram of an example device 900 suitable for implementing possible implementations of the present application. The device 900 can be used to implement the terminal device 110 or the network device 120 as shown in FIG. 1 or the communication apparatus as shown in FIG. 8. As shown, the device 900 includes one or more processors (or processing units) 910, can further include one or more memories 920 coupled to the processors 910, and can further include a communication interface 940 coupled to the processors 910.

[0141] The communication interface 940 can be used for communication with other devices or apparatuses, such as transmission or reception of data and / or signals. The communication interface 940 can have at least one communication interface for communication. The communication interface can include any interface necessary to communicate with other devices. Illustratively, the communication interface can be a transceiver, a circuit, a bus, a module, or other types of communication interfaces.

[0142] The processor 910 can include, but is not limited to, at least one of the following: a general-purpose computer, a special-purpose computer, a microcontroller, a Digital Signal Processor (DSP), or one or more of a controller-based multi-core controller architecture. The device 900 can have multiple processors, such as application-specific integrated circuit chips, which are time-dependent on a clock synchronized with the main processor.

[0143] The memory 920 can include one or more non-volatile memories and one or more volatile memories. Examples of non-volatile memories include, but are not limited to, at least one of the following: Read-Only-Memory (ROM) 924, Electrically Programmable Read-Only-Memory (EPROM), flash memory, hard disk, Compact Disc (CD), Digital Video Disk (DVD), or other magnetic and / or optical storage. Examples of volatile memories include, but are not limited to, at least one of the following: Random Access Memory (RAM) 922, or other volatile memory that does not persist in the duration of a power failure.

[0144] The computer program 930 includes computer-executable instructions executed by the associated processor 910. The program 930 can be stored in the ROM 920. The processor 910 can perform any suitable actions and processes by loading the program 930 into the RAM 922.

[0145] Possible implementations of the present application can be realized by means of the program 930, such that the device 900 can carry out any processes discussed with reference to Figures 1 to 7. Possible implementations of the present application can also be realized in hardware or in a combination of software and hardware.

[0146] In some embodiments, the program 930 can be tangibly embodied in a computer- readable medium, which can include other storage devices in the device 900, such as in the memory 920, or other storage devices accessible by the device 900. The program 930 can be loaded from the computer-readable medium into the RAM 922 for execution. The computer-readable medium can include any type of tangible non-volatile memory, such as ROM, EPROM, flash memory, hard disk, CD, DVD, and the like.

[0147] The present application also provides a communication system. The communication system includes the communication apparatus 800 as described above.

[0148] In general, the various possible implementations of the application can be implemented in hardware or special-purpose circuits, software, logic or any combination thereof. Some aspects can be implemented in hardware, while other aspects can be implemented in firmware or software which can be executed by a controller, microprocessor or other computing device. While various aspects of possible implementations of the application are illustrated and described as block diagrams, flow charts, or using some other pictorial representation, it is well understood that these blocks, apparatus, systems, techniques or methods described herein can be implemented in, as non-limiting examples, hardware, software, firmware, special-purpose circuits or logic, general purpose hardware or controller or other computing devices, or some combination thereof.

[0149] The present application also provides at least one computer program product, which is tangibly stored on a non-transitory computer readable storage medium. The computer program product includes computer executable instructions, for example, instructions embodied in program modules, executed by devices at the target real or virtual processors to carry out the processes / methods as described above with reference to FIGS. 1-8. Generally, program modules include routines, programs, libraries, objects, classes, components, data structures, etc. that perform particular tasks or implement particular abstract data types. In various possible implementations, the functionality of program modules can be combined or split between program modules as desired. Machine executable instructions for program modules can be executed within a local or distributed device. In a distributed device, program modules can be located in local and remote memory storage devices.

[0150] Program code used to implement the method of the present application can be written in any combination of one or more programming languages. This program code can be provided to a processor or controller of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the program code, when executed by the processor or controller, produces the functions / operations specified in the flowcharts and / or the block diagrams. The program code can be executed entirely on a machine, partially on a machine, partially on a machine as a stand-alone software package, partially on a machine and partially on a remote machine or entirely on a remote machine or server.

[0151] In the context of this application, a machine-readable medium can be a tangible medium that contains or stores a program for use by or in connection with an instruction execution system, apparatus, or device. The machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can include but is not limited to an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples of a machine-readable storage medium will include one or more lines of electrical connections, portable computer disks, hard disk drives, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or Flash memory), optical fiber, portable compact disc read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination of the foregoing.

[0152] Moreover, while operations have been depicted in a particular order, this should not be understood as requiring such order nor that all illustrated operations be performed, to achieve desirable results. In certain circumstances, multitasking and parallel processing can be advantageous. Likewise, while several specific implementation details have been discussed, these should not be construed as limitations on the scope of the application, but rather as descriptions of specific implementations. Certain features that are described in the context of separate implementations can also be implemented in combination. Conversely, various features that are described in the context of a single implementation can also be implemented separately or in any suitable subcombination. It will be appreciated that various

[0153] Although the subject matter has been described in language specific to structural features and / or methodological acts, it is to be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are disclosed as example forms of implementing the claims.

Claims

1. A method of communication, comprising: determining a log likelihood ratio (LLR) vector associated with a received vector; ordering at least some elements of the LLR vector after taking absolute values of the at least some elements; dividing elements of a systematic bit vector into a plurality of groups in ascending order of the ordering, wherein the systematic bit vector comprises first to k-th elements of the received vector, and k is an integer greater than or equal to 1; determining flipping orders of bits in each of the plurality of groups to be non-decreasing; flipping the bits in the each of the plurality of groups based on the flipping orders to obtain a plurality of flipped systematic bit vectors; determining a plurality of encoded vectors based on the plurality of flipped systematic bit vectors and an encoding matrix; and selecting a first encoded vector with a minimum Euclidean distance to the LLR vector from the plurality of encoded vectors as a decoding result of the received vector. 2.The method of claim 1, wherein the ordering at least some elements of the LLR vector after taking absolute values of the at least some elements comprises: ordering elements of the LLR vector corresponding to the systematic bit vector after taking absolute values of the elements. 3.The method of claim 1, wherein the ordering at least some elements of the LLR vector after taking absolute values of the at least some elements comprises: ordering all elements of the LLR vector after taking absolute values of the elements. 4.The method of claim 3, wherein the dividing elements of the systematic bit vector into a plurality of groups in ascending order of the ordering comprises: determining n-k smallest elements of the LLR vector, wherein n represents a number of all elements of the LLR vector; determining m1 elements from the n-k smallest elements, wherein the m1 elements correspond to m1 elements of the systematic bit vector, and m1 is an integer greater than or equal to 1; dividing the m1 elements of the systematic bit vector into a starting group of the plurality of groups; and dividing other k-m1 elements of the systematic bit vector into subsequent groups of the starting group. 5.The method of claim 3, wherein the dividing elements of the systematic bit vector into a plurality of groups in ascending order of the ordering comprises: determining n-k smallest elements of the LLR vector, wherein n represents a number of all elements of the LLR vector; determining x elements from the n-k smallest elements, wherein the x elements correspond to x elements of the systematic bit vector, and x is an integer greater than or equal to 1; dividing the x elements of the systematic bit vector into y groups; and dividing other k-x elements of the systematic bit vector into subsequent m-y groups of the y groups. 6.The method of claim 1, further comprising: determining a Hamming distance between a second encoded vector of the plurality of encoded vectors and the LLR vector, wherein the second encoded vector is the same as or different from the first encoded vector; and stopping decoding of the received vector if the Hamming distance is less than or equal to one half of a minimum distance of a code word space formed or corresponding to the encoding matrix. ​ ​ ​ ​ ​ ​ ​ ​ ​ 7. A communication apparatus, comprising: a processor; and a memory including computer program code; the computer program code, when executed by the processor, causing the method according to any of claims 1-6 to be performed.

8. A computer readable storage medium having stored thereon a computer program, the computer program, when executed by a processor, implementing the method according to any of claims 1-6.

9. A chip, the chip comprising processing circuitry configured to cause the method according to any of claims 1-6 to be performed.

10. A computer program product, the computer program product comprising instructions configured to, when executed by a device, cause the device to perform the method according to any of claims 1-6. ​

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