Pixel circuit, pixel drive method, and display apparatus

Abstract

Provided in the present disclosure are a pixel circuit, a pixel drive method, and a display apparatus. The pixel circuit comprises a light-emitting element, a drive circuit, a data writing circuit, and a pre-charging circuit. A display period comprises a pre-charging stage and a data writing stage that are sequentially set. The data writing circuit provides in the data writing stage a data voltage to a writing node under the control of a first scanning signal, and the pre-charging circuit writes in the pre-charging stage a pre-charging voltage in the pre-charging node under the control of a second scanning signal. The pixel circuit described in the embodiments of the present disclosure incorporates pre-compensation, such that the compensation time of a threshold voltage is not limited by single-row scanning time, thereby improving image quality and relieving afterimage.

Description

Pixel circuits, pixel driving methods, and display devices Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to a pixel circuit, a pixel driving method, and a display device. Background Technology

[0002] The threshold voltage compensation time of the relevant pixel circuit is limited by the scanning time of one line. As the resolution and frame rate increase, the compensation effect decreases, and the overall uniformity (especially the low brightness uniformity) and afterimages also deteriorate.

[0003] Summary of the Invention

[0004] In one aspect, embodiments of this disclosure provide a pixel circuit, including a light-emitting element, a driving circuit, a data writing circuit, and a pre-charging circuit; the display cycle includes a pre-charging phase and a data writing phase that are set sequentially.

[0005] The control terminal of the driving circuit is electrically connected to the first node, the first terminal of the driving circuit is electrically connected to the second node, and the second terminal of the driving circuit is electrically connected to the third node. The driving circuit is used to generate a driving current to drive the light-emitting element under the control of the potential of the first node.

[0006] The data writing circuit is electrically connected to the first scanning end, the data line and the writing node respectively, and is used to write the data voltage provided by the data line to the writing node under the control of the first scanning signal provided by the first scanning end during the data writing stage.

[0007] The pre-charging circuit is electrically connected to the second scanning end, the pre-charging voltage end, and the pre-charging node, respectively, and is used to write the pre-charging voltage provided by the pre-charging voltage end into the pre-charging node under the control of the second scanning signal provided by the second scanning end during the pre-charging stage.

[0008] The write node is electrically connected to the second node or the third node;

[0009] The precharge node includes a second node and / or a third node.

[0010] In at least one embodiment of this disclosure, the precharge voltage is less than or equal to the minimum data voltage provided by the data line.

[0011] The pixel circuit described in at least one embodiment of this disclosure further includes a compensation control circuit; the display cycle further includes a compensation phase.

[0012] The compensation control circuit is electrically connected to the third scanning end, the first node, and the third node respectively, and is used to control the connection between the first node and the third node under the control of the third scanning signal provided by the third scanning end during the compensation stage.

[0013] The compensation phase includes at least a portion of the pre-charge phase.

[0014] In at least one embodiment of this disclosure, the compensation phase includes at least a portion of the data writing phase.

[0015] In at least one embodiment of this disclosure, the pre-charge circuit includes a first transistor;

[0016] The gate of the first transistor is electrically connected to the second scan terminal, the first terminal of the first transistor is electrically connected to the precharge voltage terminal, and the second terminal of the first transistor is electrically connected to the second node or the third node; or...

[0017] The pre-charge circuit includes a first transistor and a second first transistor;

[0018] The gate of the first transistor is electrically connected to the second scan terminal, the first electrode of the first transistor is electrically connected to the precharge voltage terminal, and the second electrode of the first transistor is electrically connected to the second node.

[0019] The gate of the second first transistor is electrically connected to the second scan terminal, the first terminal of the second first transistor is electrically connected to the precharge voltage terminal, and the second terminal of the second first transistor is electrically connected to the third node.

[0020] The pixel circuit described in at least one embodiment of this disclosure further includes a first initialization circuit; the display cycle includes a reset phase.

[0021] The first initialization circuit is electrically connected to the first reset control terminal, the first initial voltage terminal and the first node respectively, and is used to write the first initial voltage provided by the first initial voltage terminal into the first node under the control of the first reset control signal provided by the first reset control terminal during the reset phase.

[0022] The reset phase is set before the precharge phase.

[0023] The pixel circuit described in at least one embodiment of this disclosure further includes an energy storage circuit, a first light-emitting control circuit, and a second light-emitting control circuit; the display cycle includes a light-emitting phase; the light-emitting phase is disposed after the data writing phase;

[0024] The energy storage circuit is electrically connected to the first node and is used to maintain the potential of the first node;

[0025] The first light-emitting control circuit is electrically connected to the first light-emitting control terminal, the power supply voltage terminal, and the second node, respectively, and is used to control the connection between the power supply voltage terminal and the second node under the control of the first light-emitting control signal provided by the first light-emitting control terminal during the light-emitting stage.

[0026] The second light-emitting control circuit is electrically connected to the second light-emitting control terminal, the third node, and the first electrode of the light-emitting element, respectively, and is used to control the connection between the third node and the first electrode of the light-emitting element under the control of the second light-emitting control signal provided by the second light-emitting control terminal during the light-emitting stage.

[0027] The second electrode of the light-emitting element is electrically connected to the first voltage terminal.

[0028] The pixel circuit described in at least one embodiment of this disclosure further includes an energy storage circuit, a first light-emitting control circuit, and a second light-emitting control circuit; the display cycle includes a light-emitting phase; the light-emitting phase is disposed after the data writing phase;

[0029] The energy storage circuit is electrically connected to the first node and is used to maintain the potential of the first node;

[0030] The first electrode of the light-emitting element is electrically connected to the power supply voltage terminal;

[0031] The first light-emitting control circuit is electrically connected to the first light-emitting control terminal, the second electrode of the light-emitting element, and the second node, respectively, and is used to control the connection between the second electrode of the light-emitting element and the second node under the control of the first light-emitting control signal provided by the first light-emitting control terminal during the light-emitting stage.

[0032] The second light-emitting control circuit is electrically connected to the second light-emitting control terminal, the third node, and the first voltage terminal, respectively, and is used to control the connection between the third node and the first voltage terminal under the control of the second light-emitting control signal provided by the second light-emitting control terminal during the light-emitting stage.

[0033] The pixel circuit described in at least one embodiment of this disclosure further includes a second initialization circuit; the display cycle includes an initialization phase; the initialization phase is set before the light emission phase;

[0034] The second initialization circuit is electrically connected to the second reset control terminal, the second initial voltage terminal, and the first electrode of the light-emitting element, respectively, and is used to write the second initial voltage provided by the second initial voltage terminal into the first electrode of the light-emitting element under the control of the second reset control signal provided by the second reset control terminal during the initialization phase.

[0035] In at least one embodiment of this disclosure, the second reset control terminal and the first scanning terminal are the same signal terminal.

[0036] In a second aspect, embodiments of this disclosure provide a pixel driving method applied to the aforementioned pixel circuit, wherein the display cycle includes a pre-charge phase and a data writing phase set sequentially; the pixel driving method includes:

[0037] During the data writing phase, the data writing circuit provides the data voltage to the writing node under the control of the first scan signal;

[0038] During the pre-charge phase, the pre-charge circuit, under the control of the second scan signal, writes the pre-charge voltage into the pre-charge node.

[0039] In at least one embodiment of this disclosure, the pixel circuit further includes a compensation control circuit; the display cycle further includes a compensation phase; the pixel driving method includes:

[0040] During the compensation phase, the compensation control circuit controls the connection between the first node and the third node under the control of the third scanning signal;

[0041] The compensation phase includes at least a portion of the pre-charge phase.

[0042] In at least one embodiment of this disclosure, the compensation stage further includes a hysteresis improvement stage disposed before the pre-charge stage; the pixel driving method further includes:

[0043] During the hysteresis improvement stage, the compensation control circuit, under the control of the third scan signal, controls the connection between the first node and the third node so that the gate-source voltage of the driving transistor in the driving circuit gradually becomes Vth, where Vth is the threshold voltage of the driving transistor.

[0044] In at least one embodiment of this disclosure, the pixel circuit further includes a first initialization circuit; the display cycle includes N preparation time periods set before the pre-charge stage, where N is an integer greater than 1; the nth preparation time period includes an nth reset stage and an nth hysteresis improvement stage set sequentially; n is a positive integer less than or equal to N; the pixel driving method includes:

[0045] During the nth reset phase, the first initialization circuit, under the control of the first reset control signal, will write to the first node;

[0046] In the nth hysteresis improvement stage, the compensation control circuit, under the control of the third scan signal, controls the connection between the first node and the third node so that the gate-source voltage of the driving transistor in the driving circuit gradually becomes Vth, where Vth is the threshold voltage of the driving transistor.

[0047] In a third aspect, embodiments of this disclosure provide a display device including the pixel circuit described above. Attached Figure Description

[0048] Figure 1 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0049] Figure 2A is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0050] Figure 2B is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0051] Figure 2C is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0052] Figure 2D is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0053] Figure 2E is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0054] Figure 2F is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0055] Figure 3 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0056] Figure 4 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0057] Figure 5 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0058] Figure 6 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0059] Figure 7 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0060] Figure 8A is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0061] Figure 8B is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0062] Figure 9 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0063] Figure 10 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0064] Figure 11 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0065] Figure 12 is a timing diagram of at least one embodiment of the pixel circuit shown in Figure 11;

[0066] Figure 13 is a timing diagram of at least one embodiment of the pixel circuit shown in Figure 11;

[0067] Figure 14 is a timing diagram of at least one embodiment of the pixel circuit shown in Figure 11;

[0068] Figure 15 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure. Detailed Implementation

[0069] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this disclosure.

[0070] In all embodiments of this disclosure, the transistors used can be thin-film transistors, field-effect transistors, or other devices with similar characteristics. In the embodiments of this disclosure, to distinguish the two terminals of the transistor other than the gate, one terminal is referred to as the first terminal and the other as the second terminal.

[0071] In actual operation, when the transistor is a thin-film transistor or a field-effect transistor, the first electrode can be the drain and the second electrode can be the source; or, the first electrode can be the source and the second electrode can be the drain.

[0072] The pixel circuit described in this embodiment includes a light-emitting element, a driving circuit, a data writing circuit, and a pre-charging circuit; the display cycle includes a pre-charging stage and a data writing stage set sequentially.

[0073] The control terminal of the driving circuit is electrically connected to the first node, the first terminal of the driving circuit is electrically connected to the second node, and the second terminal of the driving circuit is electrically connected to the third node. The driving circuit is used to generate a driving current to drive the light-emitting element under the control of the potential of the first node.

[0074] The data writing circuit is electrically connected to the first scanning end, the data line and the writing node respectively, and is used to write the data voltage provided by the data line to the writing node under the control of the first scanning signal provided by the first scanning end during the data writing stage.

[0075] The pre-charging circuit is electrically connected to the second scanning end, the pre-charging voltage end, and the pre-charging node, respectively, and is used to write the pre-charging voltage provided by the pre-charging voltage end into the pre-charging node under the control of the second scanning signal provided by the second scanning end during the pre-charging stage.

[0076] The write node is electrically connected to the second node or the third node;

[0077] The precharge node includes the second node and / or the third node.

[0078] When the pixel circuit described in this embodiment is working, the display cycle includes a pre-charge stage and a data writing stage that are set sequentially.

[0079] During the pre-charge phase, the pre-charge circuit, under the control of the second scan signal, writes the pre-charge voltage into the pre-charge node. At this time, the threshold voltage of the driving transistor in the driving circuit can be compensated in advance for pre-compensation.

[0080] During the data writing phase, the data writing circuit, under the control of the first scan signal, writes the data voltage provided by the data line to the writing node, while simultaneously compensating for the threshold voltage of the driving transistor.

[0081] The pixel circuit described in this embodiment adds pre-compensation, so that the compensation time of the threshold voltage is not limited by the scanning time of one line, thereby improving image quality and reducing afterimages.

[0082] As shown in Figure 1, the pixel circuit of at least one embodiment of this disclosure includes a light-emitting element E1, a driving circuit 10, a data writing circuit 11, and a pre-charging circuit 12; the display cycle includes a pre-charging stage and a data writing stage set sequentially.

[0083] The control terminal of the driving circuit 10 is electrically connected to the first node N1, the first terminal of the driving circuit 10 is electrically connected to the second node N2, and the second terminal of the driving circuit 10 is electrically connected to the third node N3. The driving circuit 10 is used to generate a driving current to drive the light-emitting element E1 under the control of the potential of the first node N1.

[0084] The data writing circuit 11 is electrically connected to the first scanning terminal S1, the data line DL and the second node N2 respectively, and is used to write the data voltage Vdata provided by the data line DL into the second node N2 under the control of the first scanning signal provided by the first scanning terminal S1 during the data writing stage.

[0085] The pre-charging circuit 12 is electrically connected to the second scanning terminal S2, the pre-charging voltage terminal PreC, and the second node N2, respectively, and is used to write the pre-charging voltage provided by the pre-charging voltage terminal PreC into the second node N2 under the control of the second scanning signal provided by the second scanning terminal S2 during the pre-charging stage.

[0086] The precharge node includes the second node N2.

[0087] In at least one embodiment shown in Figure 1, the write node is electrically connected to the second node N2.

[0088] As shown in Figure 2A, the pixel circuit of at least one embodiment of this disclosure includes a light-emitting element E1, a driving circuit 10, a data writing circuit 11, and a pre-charging circuit 12; the display cycle includes a pre-charging stage and a data writing stage set sequentially.

[0089] The control terminal of the driving circuit 10 is electrically connected to the first node N1, the first terminal of the driving circuit 10 is electrically connected to the second node N2, and the second terminal of the driving circuit 10 is electrically connected to the third node N3. The driving circuit 10 is used to generate a driving current to drive the light-emitting element E1 under the control of the potential of the first node N1.

[0090] The data writing circuit 11 is electrically connected to the first scanning terminal S1, the data line DL and the second node N2 respectively, and is used to write the data voltage Vdata provided by the data line DL into the second node N2 under the control of the first scanning signal provided by the first scanning terminal S1 during the data writing stage.

[0091] The pre-charging circuit 12 is electrically connected to the second scanning terminal S2, the pre-charging voltage terminal PreC and the three-node N3 respectively, and is used to write the pre-charging voltage provided by the pre-charging voltage terminal PreC into the third node N3 under the control of the second scanning signal provided by the second scanning terminal S2 during the pre-charging stage.

[0092] The precharge node includes the third node N3.

[0093] In at least one embodiment shown in Figure 2A, the write node is electrically connected to the second node N2.

[0094] As shown in Figure 2B, the pixel circuit of at least one embodiment of this disclosure includes a light-emitting element E1, a driving circuit 10, a data writing circuit 11, and a pre-charging circuit 12; the display cycle includes a pre-charging stage and a data writing stage set sequentially.

[0095] The control terminal of the driving circuit 10 is electrically connected to the first node N1, the first terminal of the driving circuit 10 is electrically connected to the second node N2, and the second terminal of the driving circuit 10 is electrically connected to the third node N3. The driving circuit 10 is used to generate a driving current to drive the light-emitting element E1 under the control of the potential of the first node N1.

[0096] The data writing circuit 11 is electrically connected to the first scanning terminal S1, the data line DL and the second node N2 respectively, and is used to write the data voltage Vdata provided by the data line DL into the second node N2 under the control of the first scanning signal provided by the first scanning terminal S1 during the data writing stage.

[0097] The pre-charging circuit 12 is electrically connected to the second scanning terminal S2, the pre-charging voltage terminal PreC, the second node N2, and the third node N3, respectively. During the pre-charging stage, under the control of the second scanning signal provided by the second scanning terminal S2, the pre-charging voltage provided by the pre-charging voltage terminal PreC is written into the second node N2 and the third node N3.

[0098] In at least one embodiment shown in Figure 2B, the precharge node includes the second node N2 and the third node, and the write node is electrically connected to the second node N2.

[0099] As shown in Figure 2C, the pixel circuit of at least one embodiment of this disclosure includes a light-emitting element E1, a driving circuit 10, a data writing circuit 11, and a pre-charging circuit 12; the display cycle includes a pre-charging stage and a data writing stage set sequentially.

[0100] The control terminal of the driving circuit 10 is electrically connected to the first node N1, the first terminal of the driving circuit 10 is electrically connected to the second node N2, and the second terminal of the driving circuit 10 is electrically connected to the third node N3. The driving circuit 10 is used to generate a driving current to drive the light-emitting element E1 under the control of the potential of the first node N1.

[0101] The data writing circuit 11 is electrically connected to the first scanning terminal S1, the data line DL and the third node N3 respectively, and is used to write the data voltage Vdata provided by the data line DL into the third node N3 under the control of the first scanning signal provided by the first scanning terminal S1 during the data writing stage.

[0102] The pre-charging circuit 12 is electrically connected to the second scanning terminal S2, the pre-charging voltage terminal PreC, and the second node N2, respectively, and is used to write the pre-charging voltage provided by the pre-charging voltage terminal PreC into the second node N2 under the control of the second scanning signal provided by the second scanning terminal S2 during the pre-charging stage.

[0103] The precharge node includes the second node N2.

[0104] In at least one embodiment shown in Figure 2C, the write node is electrically connected to the second node N2.

[0105] As shown in Figure 2D, the pixel circuit of at least one embodiment of this disclosure includes a light-emitting element E1, a driving circuit 10, a data writing circuit 11, and a pre-charging circuit 12; the display cycle includes a pre-charging stage and a data writing stage set sequentially.

[0106] The control terminal of the driving circuit 10 is electrically connected to the first node N1, the first terminal of the driving circuit 10 is electrically connected to the second node N2, and the second terminal of the driving circuit 10 is electrically connected to the third node N3. The driving circuit 10 is used to generate a driving current to drive the light-emitting element E1 under the control of the potential of the first node N1.

[0107] The data writing circuit 11 is electrically connected to the first scanning terminal S1, the data line DL and the third node N3 respectively, and is used to write the data voltage Vdata provided by the data line DL into the third node N3 under the control of the first scanning signal provided by the first scanning terminal S1 during the data writing stage.

[0108] The pre-charging circuit 12 is electrically connected to the second scanning terminal S2, the pre-charging voltage terminal PreC and the third node N3 respectively, and is used to write the pre-charging voltage provided by the pre-charging voltage terminal PreC into the third node N3 under the control of the second scanning signal provided by the second scanning terminal S2 during the pre-charging stage.

[0109] The precharge node includes the third node N3.

[0110] In at least one embodiment shown in Figure 2D, the write node is electrically connected to the third node N3.

[0111] As shown in Figure 2E, the pixel circuit of at least one embodiment of this disclosure includes a light-emitting element E1, a driving circuit 10, a data writing circuit 11, and a pre-charging circuit 12; the display cycle includes a pre-charging stage and a data writing stage set sequentially.

[0112] The control terminal of the driving circuit 10 is electrically connected to the first node N1, the first terminal of the driving circuit 10 is electrically connected to the second node N2, and the second terminal of the driving circuit 10 is electrically connected to the third node N3. The driving circuit 10 is used to generate a driving current to drive the light-emitting element E1 under the control of the potential of the first node N1.

[0113] The data writing circuit 11 is electrically connected to the first scanning terminal S1, the data line DL and the third node N3 respectively, and is used to write the data voltage Vdata provided by the data line DL into the third node N3 under the control of the first scanning signal provided by the first scanning terminal S1 during the data writing stage.

[0114] The pre-charging circuit 12 is electrically connected to the second scanning terminal S2, the pre-charging voltage terminal PreC, the second node N2, and the third node N3, respectively. During the pre-charging stage, under the control of the second scanning signal provided by the second scanning terminal S2, the pre-charging voltage provided by the pre-charging voltage terminal PreC is written into the second node N2 and the third node N3.

[0115] In at least one embodiment shown in Figure 2E, the precharge node includes the second node N2 and the third node N3, and the write node is electrically connected to the second node N2.

[0116] Optionally, the pre-charge circuit may include a first transistor;

[0117] The gate of the first transistor is electrically connected to the second scan terminal, the first terminal of the first transistor is electrically connected to the precharge voltage terminal, and the second terminal of the first transistor is electrically connected to the second node or the third node; or...

[0118] The pre-charging circuit may include a first transistor and a second transistor;

[0119] The gate of the first transistor is electrically connected to the second scan terminal, the first electrode of the first transistor is electrically connected to the precharge voltage terminal, and the second electrode of the first transistor is electrically connected to the second node.

[0120] The gate of the second first transistor is electrically connected to the second scan terminal, the first terminal of the second first transistor is electrically connected to the precharge voltage terminal, and the second terminal of the second first transistor is electrically connected to the third node.

[0121] As shown in FIG2F, based on at least one embodiment of the pixel circuit shown in FIG2B, the pre-charging circuit may include a first first transistor T11 and a second first transistor T21;

[0122] The gate of the first transistor T11 is electrically connected to the second scan terminal S2, the source of the first transistor T11 is electrically connected to the precharge voltage terminal PreC, and the drain of the first transistor T11 is electrically connected to the second node N2.

[0123] The gate of the second first transistor T21 is electrically connected to the second scan terminal S2, the source of the second first transistor T21 is electrically connected to the precharge voltage terminal PreC, and the drain of the second first transistor T21 is electrically connected to the third node N3.

[0124] In at least one embodiment of this disclosure, the precharge voltage is less than or equal to the minimum data voltage provided by the data line.

[0125] In specific implementation, the pre-charge voltage is set to be less than or equal to the minimum data voltage provided by the data line, so as to prevent the pre-charge provided to the pre-charge node during the pre-charge stage from being greater than the data voltage provided by the data line to the second node during the data writing stage.

[0126] The pixel circuit described in at least one embodiment of this disclosure further includes a compensation control circuit;

[0127] The display cycle also includes a compensation phase;

[0128] The compensation control circuit is electrically connected to the third scanning end, the first node, and the third node respectively, and is used to control the connection between the first node and the third node under the control of the third scanning signal provided by the third scanning end during the compensation stage.

[0129] The compensation phase includes at least a portion of the pre-charge phase.

[0130] In at least one embodiment of this disclosure, the compensation phase includes at least a portion of the data writing phase.

[0131] In a specific implementation, the pixel circuit may further include a compensation control circuit. Under the control of the third scan signal, the compensation control circuit controls the connection between the first node and the third node during the compensation phase to perform threshold voltage compensation. The compensation phase may include at least a portion of the pre-charge phase and at least a portion of the data writing phase.

[0132] As shown in Figure 3, based on at least one embodiment of the pixel circuit shown in Figure 1, the pixel circuit of at least one embodiment of this disclosure further includes a compensation control circuit 30; the display cycle further includes a compensation phase;

[0133] The compensation control circuit 30 is electrically connected to the third scanning terminal S3, the first node N1 and the third node N3 respectively, and is used to control the connection between the first node N1 and the third node N3 under the control of the third scanning signal provided by the third scanning terminal S3 during the compensation stage.

[0134] The compensation phase includes at least a portion of the pre-charge phase; the compensation phase includes at least a portion of the data writing phase.

[0135] As shown in Figure 4, based on at least one embodiment of the pixel circuit shown in Figure 2, the pixel circuit of at least one embodiment of this disclosure further includes a compensation control circuit 30; the display cycle further includes a compensation phase;

[0136] The compensation control circuit 30 is electrically connected to the third scanning terminal S3, the first node N1 and the third node N3 respectively, and is used to control the connection between the first node N1 and the third node N3 under the control of the third scanning signal provided by the third scanning terminal S3 during the compensation stage.

[0137] The compensation phase includes at least a portion of the pre-charge phase; the compensation phase includes at least a portion of the data writing phase.

[0138] The pixel circuit described in at least one embodiment of this disclosure further includes a first initialization circuit; the display cycle includes a reset phase.

[0139] The first initialization circuit is electrically connected to the first reset control terminal, the first initial voltage terminal and the first node respectively, and is used to write the first initial voltage provided by the first initial voltage terminal into the first node under the control of the first reset control signal provided by the first reset control terminal during the reset phase.

[0140] The reset phase is set before the precharge phase.

[0141] In a specific implementation, the pixel circuit may further include a first initialization circuit. Before the pre-charging stage, the display cycle may also include a reset stage. In the reset stage, under the control of the first reset control signal, the first initialization circuit writes the first initial voltage into the first node to initialize the potential of the first node.

[0142] As shown in Figure 5, based on at least one embodiment of the pixel circuit shown in Figure 3, the pixel circuit of at least one embodiment of this disclosure further includes a first initialization circuit 31; the display cycle includes a reset phase;

[0143] The first initialization circuit 31 is electrically connected to the first reset control terminal R1, the first initial voltage terminal I1 and the first node N1 respectively, and is used to write the first initial voltage Vini1 provided by the first initial voltage terminal I1 into the first node N1 under the control of the first reset control signal provided by the first reset control terminal R1 during the reset phase.

[0144] The reset phase is set before the precharge phase.

[0145] As shown in Figure 6, based on at least one embodiment of the pixel circuit shown in Figure 4, the pixel circuit of at least one embodiment of this disclosure further includes a first initialization circuit 31; the display cycle includes a reset phase;

[0146] The first initialization circuit 31 is electrically connected to the first reset control terminal R1, the first initial voltage terminal I1 and the first node N1 respectively, and is used to write the first initial voltage Vini1 provided by the first initial voltage terminal I1 into the first node N1 under the control of the first reset control signal provided by the first reset control terminal R1 during the reset phase.

[0147] The reset phase is set before the precharge phase.

[0148] The pixel circuit described in at least one embodiment of this disclosure further includes an energy storage circuit, a first light-emitting control circuit, and a second light-emitting control circuit; the display cycle includes a light-emitting phase; the light-emitting phase is disposed after the data writing phase;

[0149] The energy storage circuit is electrically connected to the first node and is used to maintain the potential of the first node;

[0150] The first light-emitting control circuit is electrically connected to the first light-emitting control terminal, the power supply voltage terminal, and the second node, respectively, and is used to control the connection between the power supply voltage terminal and the second node under the control of the first light-emitting control signal provided by the first light-emitting control terminal during the light-emitting stage.

[0151] The second light-emitting control circuit is electrically connected to the second light-emitting control terminal, the third node, and the first electrode of the light-emitting element, respectively, and is used to control the connection between the third node and the first electrode of the light-emitting element under the control of the second light-emitting control signal provided by the second light-emitting control terminal during the light-emitting stage.

[0152] The second electrode of the light-emitting element is electrically connected to the first voltage terminal.

[0153] Optionally, the first voltage terminal can be a low voltage terminal or a ground terminal.

[0154] In a specific implementation, the pixel circuit may further include a first light-emitting control circuit and a second light-emitting control circuit, and the display cycle may include a light-emitting stage set after the data writing stage; in the light-emitting stage, the first light-emitting control circuit, under the control of a first light-emitting control signal, controls the connection between the power supply voltage terminal and the second node; the second light-emitting control circuit, under the control of a second light-emitting control signal, controls the connection between the third node and the first pole of the light-emitting element to perform light-emitting control.

[0155] As shown in Figure 7, based on at least one embodiment of the pixel circuit shown in Figure 5, the pixel circuit of at least one embodiment of this disclosure further includes an energy storage circuit 50, a first light-emitting control circuit 51, and a second light-emitting control circuit 52; the display cycle includes a light-emitting phase; the light-emitting phase is set after the data writing phase;

[0156] The energy storage circuit 50 is electrically connected to the first node N1 and is used to maintain the potential of the first node N1;

[0157] The first light-emitting control circuit 51 is electrically connected to the first light-emitting control terminal EM1, the power supply voltage terminal ELVDD, and the second node N2, respectively, and is used to control the connection between the power supply voltage terminal ELVDD and the second node N2 under the control of the first light-emitting control signal provided by the first light-emitting control terminal EM1 during the light-emitting stage.

[0158] The second light-emitting control circuit 52 is electrically connected to the second light-emitting control terminal EM2, the third node N3, and the first pole of the light-emitting element E1, respectively. It is used to control the connection between the third node N3 and the first pole of the light-emitting element E1 under the control of the second light-emitting control signal provided by the second light-emitting control terminal EM2 during the light-emitting stage.

[0159] The second electrode of the light-emitting element E1 is electrically connected to the first voltage terminal V1.

[0160] As shown in Figure 8A, based on at least one embodiment of the pixel circuit shown in Figure 6, the pixel circuit of at least one embodiment of this disclosure further includes an energy storage circuit 50, a first light-emitting control circuit 51, and a second light-emitting control circuit 52; the display cycle includes a light-emitting phase; the light-emitting phase is set after the data writing phase;

[0161] The energy storage circuit 50 is electrically connected to the first node N1 and is used to maintain the potential of the first node N1;

[0162] The first light-emitting control circuit 51 is electrically connected to the first light-emitting control terminal EM1, the power supply voltage terminal ELVDD, and the second node N2, respectively, and is used to control the connection between the power supply voltage terminal ELVDD and the second node N2 under the control of the first light-emitting control signal provided by the first light-emitting control terminal EM1 during the light-emitting stage.

[0163] The second light-emitting control circuit 52 is electrically connected to the second light-emitting control terminal EM2, the third node N3, and the first pole of the light-emitting element E1, respectively. It is used to control the connection between the third node N3 and the first pole of the light-emitting element E1 under the control of the second light-emitting control signal provided by the second light-emitting control terminal EM2 during the light-emitting stage.

[0164] The second electrode of the light-emitting element E1 is electrically connected to the first voltage terminal V1.

[0165] As shown in Figure 8B, based on at least one embodiment of the pixel circuit shown in Figure 5, the pixel circuit of at least one embodiment of this disclosure further includes an energy storage circuit 50, a first light-emitting control circuit 51, and a second light-emitting control circuit 52; the display cycle includes a light-emitting phase; the light-emitting phase is set after the data writing phase;

[0166] The energy storage circuit 50 is electrically connected to the first node N1 and is used to maintain the potential of the first node N1;

[0167] The first electrode of the light-emitting element E1 is electrically connected to the power supply voltage terminal ELVDD.

[0168] The first light-emitting control circuit 51 is electrically connected to the first light-emitting control terminal EM1, the second electrode of the light-emitting element E1, and the second node N2, respectively. It is used to control the connection between the second electrode of the light-emitting element E1 and the second node N2 under the control of the first light-emitting control signal provided by the first light-emitting control terminal EM1 during the light-emitting stage.

[0169] The second light-emitting control circuit 52 is electrically connected to the second light-emitting control terminal EM2, the third node N3 and the first voltage terminal V1 respectively, and is used to control the connection between the third node N3 and the first voltage terminal V1 under the control of the second light-emitting control signal provided by the second light-emitting control terminal EM2 during the light-emitting stage.

[0170] In at least one embodiment of the pixel circuit shown in Figure 8B, the first electrode of the light-emitting element E1 can be an anode, and the second electrode of the light-emitting element E1 can be a cathode.

[0171] The pixel circuit described in at least one embodiment of this disclosure further includes a second initialization circuit; the display cycle includes an initialization phase; the initialization phase is set before the light emission phase;

[0172] The second initialization circuit is electrically connected to the second reset control terminal, the second initial voltage terminal, and the first electrode of the light-emitting element, respectively, and is used to write the second initial voltage provided by the second initial voltage terminal into the first electrode of the light-emitting element under the control of the second reset control signal provided by the second reset control terminal during the initialization phase.

[0173] In a specific implementation, the pixel circuit may further include a second initialization circuit, and the display cycle may further include an initialization stage set before the light emission stage. In the initialization stage, under the control of the second reset control signal, the second initialization circuit writes a second initial voltage into the first electrode of the light emission element to clear the residual charge on the first electrode of the light emission element.

[0174] Optionally, the second reset control terminal and the first scan terminal are the same signal terminal.

[0175] In at least one embodiment of this disclosure, the second reset control terminal and the first scan terminal can be the same signal terminal to reduce the number of signal terminals used.

[0176] As shown in Figure 9, based on at least one embodiment of the pixel circuit shown in Figure 7, the pixel circuit of at least one embodiment of this disclosure further includes a second initialization circuit 32; the display cycle includes an initialization phase; the initialization phase is set before the light emission phase;

[0177] The second initialization circuit 32 is electrically connected to the second reset control terminal R2, the second initial voltage terminal I2 and the first pole of the light-emitting element E1, respectively. It is used to write the second initial voltage Vini2 provided by the second initial voltage terminal I2 into the first pole of the light-emitting element E1 under the control of the second reset control signal provided by the second reset control terminal R2 during the initialization phase.

[0178] As shown in Figure 10, based on at least one embodiment of the pixel circuit shown in Figure 8A, the pixel circuit of at least one embodiment of this disclosure further includes a second initialization circuit 32; the display cycle includes an initialization phase; the initialization phase is set before the light emission phase;

[0179] The second initialization circuit 32 is electrically connected to the second reset control terminal R2, the second initial voltage terminal I2, and the first electrode of the light-emitting element E1, respectively. During the initialization phase, under the control of the second reset control signal provided by the second reset control terminal R2, it writes the second initial voltage Vini2 provided by the second initial voltage terminal I2 into the first electrode of the light-emitting element E1. Optionally, the data writing circuit includes a second transistor, and the driving circuit includes a driving transistor.

[0180] The gate of the second transistor is electrically connected to the first scan terminal, the first terminal of the second transistor is electrically connected to the data line, and the second terminal of the second transistor is electrically connected to the second node.

[0181] The gate of the driving transistor is electrically connected to the first node, the first electrode of the driving transistor is electrically connected to the second node, and the second electrode of the driving transistor is electrically connected to the third node.

[0182] Optionally, the compensation control circuit includes a third transistor;

[0183] The gate of the third transistor is electrically connected to the third scanning terminal, the first terminal of the third transistor is electrically connected to the first node, and the second terminal of the third transistor is electrically connected to the third node.

[0184] Optionally, the first initialization circuit includes a fourth transistor;

[0185] The gate of the fourth transistor is electrically connected to the first reset control terminal, the first terminal of the fourth transistor is electrically connected to the first initial voltage terminal, and the second terminal of the fourth transistor is electrically connected to the first node.

[0186] Optionally, the first light-emitting control circuit includes a fifth transistor, and the second light-emitting control circuit includes a sixth transistor;

[0187] The gate of the fifth transistor is electrically connected to the first light-emitting control terminal, the first electrode of the fifth transistor is electrically connected to the power supply voltage terminal, and the second electrode of the fifth transistor is electrically connected to the second node.

[0188] The gate of the sixth transistor is electrically connected to the second light-emitting control terminal, the first electrode of the sixth transistor is electrically connected to the third node, and the second electrode of the sixth transistor is electrically connected to the first electrode of the light-emitting element.

[0189] Optionally, the second initialization circuit includes a seventh transistor;

[0190] The gate of the seventh transistor is electrically connected to the second reset control terminal, the first terminal of the seventh transistor is electrically connected to the second initial voltage terminal, and the second terminal of the seventh transistor is electrically connected to the first terminal of the light-emitting element.

[0191] As shown in Figure 11, based on at least one embodiment of the pixel circuit shown in Figure 9, the pre-charging circuit includes a first transistor T1; the light-emitting element is an organic light-emitting diode O1;

[0192] The gate of the first transistor T1 is electrically connected to the second scan terminal S2, the source of the first transistor T1 is electrically connected to the precharge voltage terminal PreC, and the drain of the first transistor T1 is electrically connected to the precharge node NP; NP is electrically connected to N2.

[0193] The data writing circuit includes a second transistor T2, and the driving circuit includes a driving transistor DT;

[0194] The gate of the second transistor T2 is electrically connected to the first scan terminal S1, the source of the second transistor T2 is electrically connected to the data line DL, and the drain of the second transistor T2 is electrically connected to the second node N2; the data line DL is used to provide the data voltage Vdata;

[0195] The gate of the driving transistor DT is electrically connected to the first node N1, the source of the driving transistor DT is electrically connected to the second node N2, and the drain of the driving transistor DT is electrically connected to the third node N3.

[0196] The compensation control circuit includes a third transistor T3;

[0197] The gate of the third transistor T3 is electrically connected to the third scanning terminal S3, the source of the third transistor T3 is electrically connected to the first node N1, and the drain of the third transistor T3 is electrically connected to the third node N3.

[0198] The first initialization circuit includes a fourth transistor T4;

[0199] The gate of the fourth transistor T4 is electrically connected to the first reset control terminal R1, the source of the fourth transistor T4 is electrically connected to the first initial voltage terminal I1, and the drain of the fourth transistor T4 is electrically connected to the first node N1; the first initial voltage terminal I1 is used to provide the first initial voltage Vini1.

[0200] The energy storage circuit includes a first capacitor C1; the first light-emitting control circuit includes a fifth transistor T5; and the second light-emitting control circuit includes a sixth transistor T6.

[0201] The first terminal of C1 is electrically connected to the first node N1, and the second terminal of C1 is electrically connected to the power supply voltage terminal ELVDD.

[0202] The gate of the fifth transistor T5 is electrically connected to the first light-emitting control terminal EM1, the source of the fifth transistor T5 is electrically connected to the power supply voltage terminal ELVDD, and the drain of the fifth transistor T5 is electrically connected to the second node N2.

[0203] The gate of the sixth transistor T6 is electrically connected to the second light-emitting control terminal EM2, the source of the sixth transistor T6 is electrically connected to the third node N3, and the drain of the sixth transistor T6 is electrically connected to the anode of O1.

[0204] The second initialization circuit includes a seventh transistor T7;

[0205] The gate of the seventh transistor T7 is electrically connected to the second reset control terminal R2, the source of the seventh transistor T7 is electrically connected to the second initial voltage terminal I2, and the drain of the seventh transistor T7 is electrically connected to the anode of O1.

[0206] The cathode of O1 is electrically connected to the low-voltage terminal ELVSS.

[0207] In at least one embodiment of the pixel circuit shown in Figure 11, all transistors are p-type transistors, but this is not a limitation.

[0208] In at least one embodiment of the pixel circuit shown in Figure 11, the voltage value of Vini1 is greater than or equal to -5V and less than or equal to -3V, the voltage value of Vini2 is greater than or equal to Vss-0.5 and less than or equal to Vss+Vo1, the voltage value of Vdata can be greater than or equal to 1V and less than or equal to 7V, and the voltage value of the pre-charge voltage Vp provided by PreC can be less than or equal to 1V; wherein, Vss is the voltage value of the low voltage signal provided by ELVSS, and Vo1 is the turn-on voltage of O1.

[0209] As shown in Figure 12, at least one embodiment of the pixel circuit shown in Figure 11 of this disclosure, when in operation, displays a cycle including a reset phase t1, a compensation phase t2, and a light emission phase t3, which are set sequentially.

[0210] The compensation phase t2 includes a pre-charge phase t21 and a data writing phase t22; the data writing phase t22 is the same phase as the initialization phase.

[0211] During the reset phase t1, R1 provides a low voltage signal, EM1 and EM2 provide high voltage signals, S1 and S2 both provide high voltage signals, S3 provides a high voltage signal, R2 provides a high voltage signal, T4 is turned on, and I1 provides the first initial voltage Vini1 to N1;

[0212] During the precharge phase t21, EM1 and EM2 both provide high voltage signals, R1 provides a high voltage signal, S1 provides a high voltage signal, R2 provides a high voltage signal, S2 and S3 both provide low voltage signals, T1 and T3 are turned on, N1 and N3 are connected, and PreC provides the precharge voltage Vp to N2.

[0213] At the start of the pre-charge phase t21, DT is turned on and charges C1 through Vp until DT is turned off. At this time, the potential of N1 is Vp + Vth, and threshold voltage pre-compensation is performed; Vth is the threshold voltage of DT.

[0214] During the data writing phase t22, EM1 and EM2 both provide high voltage signals, R1 provides a high voltage signal, S1 and R2 provide low voltage signals, S3 provides a low voltage signal, S2 provides a high voltage signal, T3 is turned on, T2 is turned on, DL provides the data voltage Vdata to N2; T7 is turned on, I2 provides the second initial voltage Vini2 to the anode of O1 to clear the residual charge on the anode of O1;

[0215] At the start of the data writing phase t22, DT is turned on, and Vdata charges C1 until DT is turned off. At this time, the gate potential of DT is Vdata+Vth, and threshold voltage compensation is performed.

[0216] During the light-emitting stage t3, EM1 and EM2 provide low voltage signals, R1 and R2 provide high voltage signals, S1, S2 and S3 provide high voltage signals, T5 and T6 are turned on, and DT drives O1 to emit light.

[0217] At least one embodiment of the pixel circuit shown in Figure 11 of this disclosure, during operation, enables T1 to write Vp before T2 is turned on to write the data voltage Vdata to N2, thereby achieving a longer compensation time and solving the problem of uniformity and afterimage aberration caused by the charging compensation time of the related pixel circuit being limited by one line scan time.

[0218] As shown in FIG13, at least one embodiment of the pixel circuit shown in FIG11 of this disclosure, when in operation, displays a cycle including a reset phase t1, a compensation phase t2, and a light emission phase t3 arranged sequentially.

[0219] The compensation phase t2 includes a hysteresis improvement phase t20, a pre-charge phase t21, and a data writing phase t22; the data writing phase t22 is the same phase as the initialization phase.

[0220] During the reset phase t1, R1 provides a low voltage signal, EM1 and EM2 provide high voltage signals, S1 and S2 both provide high voltage signals, S3 provides a high voltage signal, R2 provides a high voltage signal, T4 is turned on, and I1 provides the first initial voltage Vini1 to N1;

[0221] During the hysteresis improvement phase t20, EM1 and EM2 both provide high voltage signals, R1 provides a high voltage signal, S1 and R2 both provide high voltage signals, S3 provides a low voltage signal, and S2 provides a high voltage signal; when T3 is turned on, the gate-source voltage of DT gradually becomes Vth, where Vth is the threshold voltage of DT.

[0222] During the hysteresis improvement stage t20, the hysteresis phenomenon of DT can be improved by controlling and changing the gate-source voltage of DT.

[0223] During the precharge phase t21, EM1 and EM2 both provide high voltage signals, R1 provides a high voltage signal, S1 provides a high voltage signal, R2 provides a high voltage signal, S2 and S3 both provide low voltage signals, T1 and T3 are turned on, N1 and N3 are connected, and PreC provides the precharge voltage Vp to N2.

[0224] At the start of the pre-charge phase t21, DT is turned on and charges C1 through Vp until DT is turned off. At this time, the potential of N1 is Vp + Vth, and threshold voltage pre-compensation is performed; Vth is the threshold voltage of DT.

[0225] During the data writing phase t22, EM1 and EM2 both provide high voltage signals, R1 provides a high voltage signal, S1 and R2 provide low voltage signals, S3 provides a low voltage signal, S2 provides a high voltage signal, T3 is turned on, T2 is turned on, DL provides the data voltage Vdata to N2; T7 is turned on, I2 provides the second initial voltage Vini2 to the anode of O1 to clear the residual charge on the anode of O1;

[0226] At the start of the data writing phase t22, DT is turned on, and Vdata charges C1 until DT is turned off. At this time, the gate potential of DT is Vdata+Vth, and threshold voltage compensation is performed.

[0227] During the light-emitting stage t3, EM1 and EM2 provide low voltage signals, R1 and R2 provide high voltage signals, S1, S2 and S3 provide high voltage signals, T5 and T6 are turned on, and DT drives O1 to emit light.

[0228] As shown in Figure 14, at least one embodiment of the pixel circuit shown in Figure 11 of this disclosure, when in operation, displays a cycle including a first reset stage tr1, a first hysteresis improvement stage tc1, a second reset stage tr2, a second hysteresis improvement stage tc2, a precharge stage t21, a data writing stage t22, and a light emission stage t3, which are set sequentially.

[0229] During the first reset phase tr1, R1 provides a low voltage signal, EM1 and EM2 provide high voltage signals, S1 and S2 both provide high voltage signals, S3 provides a high voltage signal, R2 provides a high voltage signal, T4 is turned on, and I1 provides the first initial voltage Vini1 to N1;

[0230] In the first hysteresis improvement stage, tc1, EM1 and EM2 both provide high voltage signals, R1 provides a high voltage signal, S1 and R2 both provide high voltage signals, S3 provides a low voltage signal, and S2 provides a high voltage signal; T3 is turned on, and the gate-source voltage of DT gradually becomes Vth, where Vth is the threshold voltage of DT.

[0231] In the first hysteresis improvement stage tc1, the hysteresis phenomenon of DT can be improved by controlling and changing the gate-source voltage of DT.

[0232] During the second reset phase tr2, R1 provides a low voltage signal, EM1 and EM2 provide high voltage signals, S1 and S2 both provide high voltage signals, S3 provides a high voltage signal, R2 provides a high voltage signal, T4 is turned on, and I1 provides the first initial voltage Vini1 to N1.

[0233] In the second hysteresis improvement stage tc2, EM1 and EM2 both provide high voltage signals, R1 provides a high voltage signal, S1 and R2 both provide high voltage signals, S3 provides a low voltage signal, and S2 provides a high voltage signal; T3 is turned on, and the gate-source voltage of DT gradually becomes Vth, where Vth is the threshold voltage of DT.

[0234] In the second hysteresis improvement stage tc2, the hysteresis phenomenon of DT can be improved by controlling and changing the gate-source voltage of DT.

[0235] During the precharge phase t21, EM1 and EM2 both provide high voltage signals, R1 provides a high voltage signal, S1 provides a high voltage signal, R2 provides a high voltage signal, S2 and S3 both provide low voltage signals, T1 and T3 are turned on, N1 and N3 are connected, and PreC provides the precharge voltage Vp to N2.

[0236] At the start of the pre-charge phase t21, DT is turned on and charges C1 through Vp until DT is turned off. At this time, the potential of N1 is Vp + Vth, and threshold voltage pre-compensation is performed; Vth is the threshold voltage of DT.

[0237] During the data writing phase t22, EM1 and EM2 both provide high voltage signals, R1 provides a high voltage signal, S1 and R2 provide low voltage signals, S3 provides a low voltage signal, S2 provides a high voltage signal, T3 is turned on, T2 is turned on, DL provides the data voltage Vdata to N2; T7 is turned on, I2 provides the second initial voltage Vini2 to the anode of O1 to clear the residual charge on the anode of O1;

[0238] At the start of the data writing phase t22, DT is turned on, and Vdata charges C1 until DT is turned off. At this time, the gate potential of DT is Vdata+Vth, and threshold voltage compensation is performed.

[0239] During the light-emitting stage t3, EM1 and EM2 provide low voltage signals, R1 and R2 provide high voltage signals, S1, S2 and S3 provide high voltage signals, T5 and T6 are turned on, and DT drives O1 to emit light.

[0240] As shown in Figure 15, based on at least one embodiment of the pixel circuit shown in Figure 8B, the pre-charging circuit includes a first transistor T1; the light-emitting element is an organic light-emitting diode O1.

[0241] The gate of the first transistor T1 is electrically connected to the second scan terminal S2, the source of the first transistor T1 is electrically connected to the precharge voltage terminal PreC, and the drain of the first transistor T1 is electrically connected to the precharge node NP; NP is electrically connected to N2.

[0242] The data writing circuit includes a second transistor T2, and the driving circuit includes a driving transistor DT;

[0243] The gate of the second transistor T2 is electrically connected to the first scan terminal S1, the source of the second transistor T2 is electrically connected to the data line DL, and the drain of the second transistor T2 is electrically connected to the second node N2; the data line DL is used to provide the data voltage Vdata;

[0244] The gate of the driving transistor DT is electrically connected to the first node N1, the source of the driving transistor DT is electrically connected to the second node N2, and the drain of the driving transistor DT is electrically connected to the third node N3.

[0245] The compensation control circuit includes a third transistor T3;

[0246] The gate of the third transistor T3 is electrically connected to the third scanning terminal S3, the source of the third transistor T3 is electrically connected to the first node N1, and the drain of the third transistor T3 is electrically connected to the third node N3.

[0247] The first initialization circuit includes a fourth transistor T4;

[0248] The gate of the fourth transistor T4 is electrically connected to the first reset control terminal R1, the source of the fourth transistor T4 is electrically connected to the first initial voltage terminal I1, and the drain of the fourth transistor T4 is electrically connected to the first node N1; the first initial voltage terminal I1 is used to provide the first initial voltage Vini1.

[0249] The energy storage circuit includes a first capacitor C1; the first light-emitting control circuit includes a fifth transistor T5; and the second light-emitting control circuit includes a sixth transistor T6.

[0250] The first terminal of C1 is electrically connected to the first node N1, and the second terminal of C1 is electrically connected to the power supply voltage terminal ELVDD.

[0251] The anode of O1 is electrically connected to the power supply voltage terminal ELVDD;

[0252] The gate of the fifth transistor T5 is electrically connected to the first light-emitting control terminal EM1, the source of the fifth transistor T5 is electrically connected to the cathode of O1, and the drain of the fifth transistor T5 is electrically connected to the second node N2.

[0253] The gate of the sixth transistor T6 is electrically connected to the second light-emitting control terminal EM2, the source of the sixth transistor T6 is electrically connected to the third node N3, and the drain of the sixth transistor T6 is electrically connected to the low-voltage terminal ELVSS.

[0254] In at least one embodiment of the pixel circuit shown in Figure 15, all transistors are p-type transistors, but this is not a limitation.

[0255] The pixel driving method described in this embodiment is applied to the pixel circuit described above, and the display cycle includes a pre-charge stage and a data writing stage set sequentially; the pixel driving method includes:

[0256] During the data writing phase, the data writing circuit provides the data voltage to the writing node under the control of the first scan signal;

[0257] During the pre-charge phase, the pre-charge circuit, under the control of the second scan signal, writes the pre-charge voltage into the pre-charge node.

[0258] In at least one embodiment of this disclosure, the precharge voltage is less than or equal to the minimum data voltage provided by the data line.

[0259] In at least one embodiment of this disclosure, the pixel circuit further includes a compensation control circuit; the display cycle further includes a compensation phase; the pixel driving method includes:

[0260] During the compensation phase, the compensation control circuit controls the connection between the first node and the third node under the control of the third scanning signal;

[0261] The compensation phase includes at least a portion of the pre-charge phase.

[0262] In at least one embodiment of this disclosure, the compensation stage further includes a hysteresis improvement stage disposed before the pre-charge stage; the pixel driving method further includes:

[0263] During the hysteresis improvement stage, the compensation control circuit, under the control of the third scan signal, controls the connection between the first node and the third node so that the gate-source voltage of the driving transistor in the driving circuit gradually becomes Vth, where Vth is the threshold voltage of the driving transistor.

[0264] In at least one embodiment of this disclosure, the pixel circuit further includes a first initialization circuit; the display cycle includes N preparation time periods set before the pre-charge stage, where N is an integer greater than 1; the nth preparation time period includes an nth reset stage and an nth hysteresis improvement stage set sequentially; n is a positive integer less than or equal to N; the pixel driving method includes:

[0265] During the nth reset phase, the first initialization circuit, under the control of the first reset control signal, will write to the first node;

[0266] In the nth hysteresis improvement stage, the compensation control circuit, under the control of the third scan signal, controls the connection between the first node and the third node so that the gate-source voltage of the driving transistor in the driving circuit gradually becomes Vth, where Vth is the threshold voltage of the driving transistor.

[0267] Optionally, N can be less than or equal to 6.

[0268] The display device described in this disclosure includes the pixel circuit described above.

[0269] The above description represents the preferred embodiments of this disclosure. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles described herein, and these improvements and modifications should also be considered within the scope of protection of this disclosure.

Claims

1. A pixel circuit, comprising a light-emitting element, a driving circuit, a data writing circuit, and a pre-charging circuit; the display cycle includes a pre-charging stage and a data writing stage set sequentially. The control terminal of the driving circuit is electrically connected to the first node, the first terminal of the driving circuit is electrically connected to the second node, and the second terminal of the driving circuit is electrically connected to the third node. The driving circuit is used to generate a driving current to drive the light-emitting element under the control of the potential of the first node. The data writing circuit is electrically connected to the first scanning end, the data line and the writing node respectively, and is used to write the data voltage provided by the data line to the writing node under the control of the first scanning signal provided by the first scanning end during the data writing stage. The pre-charging circuit is electrically connected to the second scanning end, the pre-charging voltage end, and the pre-charging node, respectively, and is used to write the pre-charging voltage provided by the pre-charging voltage end into the pre-charging node under the control of the second scanning signal provided by the second scanning end during the pre-charging stage. The write node is electrically connected to the second node or the third node; The precharge node includes a second node and / or a third node.

2. The pixel circuit as described in claim 1, wherein, The precharge voltage is less than or equal to the minimum data voltage provided by the data line.

3. The pixel circuit as described in claim 1, wherein, It also includes a compensation control circuit; The display cycle also includes a compensation phase; The compensation control circuit is electrically connected to the third scanning end, the first node, and the third node respectively, and is used to control the connection between the first node and the third node under the control of the third scanning signal provided by the third scanning end during the compensation stage. The compensation phase includes at least a portion of the pre-charge phase.

4. The pixel circuit as described in claim 3, wherein, The compensation phase includes at least a portion of the data writing phase.

5. The pixel circuit according to any one of claims 1 to 4, wherein, The pre-charging circuit includes a first transistor; The gate of the first transistor is electrically connected to the second scan terminal, the first terminal of the first transistor is electrically connected to the precharge voltage terminal, and the second terminal of the first transistor is electrically connected to the second node or the third node; or... The pre-charge circuit includes a first transistor and a second first transistor; The gate of the first transistor is electrically connected to the second scan terminal, the first electrode of the first transistor is electrically connected to the precharge voltage terminal, and the second electrode of the first transistor is electrically connected to the second node. The gate of the second first transistor is electrically connected to the second scan terminal, the first terminal of the second first transistor is electrically connected to the precharge voltage terminal, and the second terminal of the second first transistor is electrically connected to the third node.

6. The pixel circuit as described in claim 1, wherein, It also includes a first initialization circuit; the display cycle includes a reset phase; The first initialization circuit is electrically connected to the first reset control terminal, the first initial voltage terminal and the first node respectively, and is used to write the first initial voltage provided by the first initial voltage terminal into the first node under the control of the first reset control signal provided by the first reset control terminal during the reset phase. The reset phase is set before the precharge phase.

7. The pixel circuit according to any one of claims 1 to 4, wherein, It also includes an energy storage circuit, a first light-emitting control circuit, and a second light-emitting control circuit; the display cycle includes a light-emitting phase; the light-emitting phase is set after the data writing phase; The energy storage circuit is electrically connected to the first node and is used to maintain the potential of the first node; The first light-emitting control circuit is electrically connected to the first light-emitting control terminal, the power supply voltage terminal, and the second node, respectively, and is used to control the connection between the power supply voltage terminal and the second node under the control of the first light-emitting control signal provided by the first light-emitting control terminal during the light-emitting stage. The second light-emitting control circuit is electrically connected to the second light-emitting control terminal, the third node, and the first electrode of the light-emitting element, respectively, and is used to control the connection between the third node and the first electrode of the light-emitting element under the control of the second light-emitting control signal provided by the second light-emitting control terminal during the light-emitting stage. The second electrode of the light-emitting element is electrically connected to the first voltage terminal.

8. The pixel circuit as described in claim 1, wherein, It also includes an energy storage circuit, a first light-emitting control circuit, and a second light-emitting control circuit; the display cycle includes a light-emitting phase; the light-emitting phase is set after the data writing phase; The energy storage circuit is electrically connected to the first node and is used to maintain the potential of the first node; The first electrode of the light-emitting element is electrically connected to the power supply voltage terminal; The first light-emitting control circuit is electrically connected to the first light-emitting control terminal, the second electrode of the light-emitting element, and the second node, respectively, and is used to control the connection between the second electrode of the light-emitting element and the second node under the control of the first light-emitting control signal provided by the first light-emitting control terminal during the light-emitting stage. The second light-emitting control circuit is electrically connected to the second light-emitting control terminal, the third node, and the first voltage terminal, respectively, and is used to control the connection between the third node and the first voltage terminal under the control of the second light-emitting control signal provided by the second light-emitting control terminal during the light-emitting stage.

9. The pixel circuit as described in claim 7, wherein, It also includes a second initialization circuit; the display cycle includes an initialization phase; the initialization phase is set before the light emission phase; The second initialization circuit is electrically connected to the second reset control terminal, the second initial voltage terminal, and the first electrode of the light-emitting element, respectively, and is used to write the second initial voltage provided by the second initial voltage terminal into the first electrode of the light-emitting element under the control of the second reset control signal provided by the second reset control terminal during the initialization phase.

10. The pixel circuit as claimed in claim 9, wherein, The second reset control terminal and the first scan terminal are the same signal terminal.

11. A pixel driving method, applied to a pixel circuit as described in any one of claims 1 to 10, wherein the display cycle includes a pre-charge phase and a data writing phase set sequentially; The pixel driving method includes: During the data writing phase, the data writing circuit provides the data voltage to the writing node under the control of the first scan signal; During the pre-charge phase, the pre-charge circuit, under the control of the second scan signal, writes the pre-charge voltage into the pre-charge node.

12. The pixel driving method as described in claim 11, wherein, The pixel circuit also includes a compensation control circuit; The display cycle also includes a compensation phase; the pixel driving method includes: During the compensation phase, the compensation control circuit controls the connection between the first node and the third node under the control of the third scanning signal; The compensation phase includes at least a portion of the pre-charge phase.

13. The pixel driving method as described in claim 12, wherein, The compensation phase also includes a hysteresis improvement phase set before the pre-charge phase; The pixel driving method further includes: During the hysteresis improvement stage, the compensation control circuit, under the control of the third scan signal, controls the connection between the first node and the third node so that the gate-source voltage of the driving transistor in the driving circuit gradually becomes Vth, where Vth is the threshold voltage of the driving transistor.

14. The pixel driving method as described in claim 12, wherein, The pixel circuit further includes a first initialization circuit; the display cycle includes N preparation time periods set before the pre-charge stage, where N is an integer greater than 1; the nth preparation time period includes the nth reset stage and the nth hysteresis improvement stage set sequentially. n is a positive integer less than or equal to N; The pixel driving method includes: During the nth reset phase, the first initialization circuit, under the control of the first reset control signal, will write to the first node; In the nth hysteresis improvement stage, the compensation control circuit, under the control of the third scan signal, controls the connection between the first node and the third node so that the gate-source voltage of the driving transistor in the driving circuit gradually becomes Vth, where Vth is the threshold voltage of the driving transistor.

15. A display device comprising a pixel circuit as claimed in any one of claims 1 to 14.

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