Display device

Abstract

A display device, comprising a display panel (DP) and a plurality of driver chips (DIC). Each driver chip (DIC) generates gamma point voltages (iGM) on the basis of a plurality of power supply reference voltages (VGM), and the gamma point voltages (iGM) are used as shared voltages (SGM) and used by other driver chips (DIC); gray scales correspondingly mapped by the gamma point voltages (iGM) that are generated by at least two driver chips (DIC) and used as the shared voltages (SGM) are different; and each driver chip (DIC) can generate a plurality of polarity data signals on the basis of the plurality of gamma point voltages (iGM) and the plurality of received shared voltages (SGM) so as to output the polarity data signals to corresponding data lines (DL).

Description

Display device

[0001] This application claims priority to Chinese Patent Application No. 202411215735.6, filed on August 30, 2024, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] This application relates to the field of display technology, and more specifically to a display device. Background Technology

[0003] To achieve optimal color reproduction in a display panel, multiple binding point voltages are typically used to correct the gamma value to a target value (e.g., 2.2). The more binding point voltages used, the easier the gamma correction becomes. However, as the display panel size increases, the gamma voltage transmission path becomes longer, the line impedance increases, and the voltage drop increases. To maintain good display performance, it's necessary to increase the number of binding point voltages or add a voltage amplification circuit to avoid brightness inconsistencies caused by excessive gamma voltage drop. However, increasing the number of binding point voltages and adding a voltage amplification circuit increases the size and power consumption of the driver chip by at least 10%, and also increases cost. Invention Overview

[0004] This application provides a display device that can improve the problem of increased driver chip size, power consumption, and cost caused by increasing the number of bonding point voltages and voltage amplification circuits.

[0005] This application provides a display device including a display panel and a plurality of driver chips. The display panel includes multiple data lines. The plurality of driver chips are electrically connected to the display panel. Each driver chip is configured to receive multiple power supply reference voltages to generate multiple gamma binding point voltages, and to share the multiple gamma binding point voltages as multiple shared voltages with at least one other driver chip. Furthermore, it generates multiple polarity data signals based on the multiple gamma binding point voltages and the received multiple shared voltages, and outputs them to the corresponding data lines. The grayscale maps corresponding to the gamma binding point voltages generated by at least two of the driver chips as shared voltages are different. Attached Figure Description

[0006] Figures 1A and 1B are schematic diagrams of the structure of the display device provided in the embodiments of this application;

[0007] Figure 2 is a schematic block diagram of the driver chip provided in an embodiment of this application;

[0008] Figures 3A to 3D are schematic diagrams of the structure of the driver chip provided in the embodiments of this application. Embodiments of the present invention

[0009] To make the objectives, technical solutions, and effects of this application clearer and more explicit, the following detailed description of this application is provided with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to limit it. Various embodiments can be combined with each other, but will not be described in detail here. Terms involving circuit modules, ordinal numbers such as "first" and "second" do not indicate logical time or importance order; including a word is not exclusive; computer non-volatile storage media storing instructions / code for executing such method steps; and any combination of embodiments is feasible. Those skilled in the art should understand that modifications or equivalent substitutions can be made to the embodiments of this application without departing from the spirit and scope of this application, and such modifications or equivalent substitutions should be covered within the scope of this application.

[0010] This application provides a display device including a display panel and multiple driver chips. Because the gamma binding voltage generated by each driver chip based on multiple power supply reference voltages can be used as a shared voltage by other driver chips, and the grayscale corresponding to the shared gamma binding voltages generated by at least two driver chips is different, each driver chip can generate multiple polarity data signals based on the multiple gamma binding voltages and the received multiple shared voltages, and output them to corresponding data lines. Therefore, the number of gamma binding voltages that each driver chip needs to generate is reduced, and the number of voltage amplification modules required is also reduced, which helps to reduce the size, power consumption, and cost of the driver chips.

[0011] Figures 1A and 1B are schematic diagrams of the display device provided in the embodiments of this application. The display device shown in Figure 1B is only used for comparison with the display device shown in Figure 1A, and the driver chip shown in Figure 1B should not be construed as prior art.

[0012] This application provides a display device, which includes a display panel (DP) and multiple driver chips (DIC). The display device includes computers, televisions, mobile phones, virtual reality display devices, augmented reality display devices, etc.

[0013] The display panel (DP) includes multiple data lines (DL) and multiple sub-pixels (Spi). The data lines (DL) are electrically connected to their corresponding sub-pixels (Spi). The sub-pixels (Spi) are configured to receive polarity data signals transmitted by their respective data lines (DL) to enable the display function of the display panel (DP).

[0014] Multiple driver chips (DICs) are electrically connected to the display panel (DP). Each driver chip (DIC) is configured to receive multiple power supply reference voltages (VGM) to generate multiple gamma binding point voltages (iGM), and share these multiple gamma binding point voltages (iGM) as multiple shared voltages (SGM) with at least one other driver chip (DIC). Furthermore, based on the multiple gamma binding point voltages (iGM) and the received multiple shared voltages (SGM), multiple polarity data signals are generated and output to the corresponding data lines (DL). Notably, the gamma binding point voltages (iGM) generated by at least two driver chips (DICs) as shared voltages (SGM) correspond to different grayscale levels.

[0015] Because the gamma-binding voltage iGM generated by each driver chip DIC can be used as a shared voltage SGM by other driver chip DICs, and the grayscale mappings corresponding to the gamma-binding voltage iGM generated as the shared voltage SGM by at least two driver chip DICs are different, the number of gamma-binding voltages iGM that each driver chip DIC needs to generate is reduced, and the number of voltage amplification modules that need to be applied is also reduced, which helps to reduce the size, power consumption and cost of the driver chip DIC.

[0016] Figure 2 is a schematic block diagram of the driver chip provided in an embodiment of this application, and Figures 3A to 3D are schematic structural diagrams of the driver chip provided in an embodiment of this application. Figures 3A to 3C can be used to implement the design shown in Figure 1A, and Figure 3D can be used to implement the design shown in Figure 1B. It should be noted that the driver chip shown in Figure 3D is only used for comparison with the driver chips shown in Figures 3A and 3B, and should not be construed as prior art.

[0017] Please refer to Figures 2 and 3A. Each driver chip DIC includes a gamma power module 10. The gamma power module 10 is configured to receive multiple power supply reference voltages VGM and generate multiple gamma reference voltages.

[0018] Optionally, the power supply reference voltage VGM can be supplied by the power management chip PMIC.

[0019] Optionally, the multiple gamma reference voltages include multiple first gamma reference voltages VA and multiple second gamma reference voltages VB. The power supply reference voltage VGM includes a first power supply reference voltage UH, a second power supply reference voltage UL, a third power supply reference voltage LH, and a fourth power supply reference voltage LL. The first power supply reference voltage UH is greater than the second power supply reference voltage UL, and the third power supply reference voltage LH is greater than the fourth power supply reference voltage LL. The gamma power module 10 is configured to generate multiple first gamma reference voltages VA based on the first power supply reference voltage UH and the second power supply reference voltage UL, and to generate multiple second gamma reference voltages VB based on the third power supply reference voltage LH and the fourth power supply reference voltage LL.

[0020] Optionally, multiple first gamma reference voltages VA and multiple second gamma reference voltages VB can be generated by two gamma power supply units of the gamma power supply module 10. As shown in FIG3A, the gamma power supply module 10 includes a first gamma power supply unit 101 and a second gamma power supply unit 102.

[0021] The first gamma power supply unit 101 is configured to receive a first power supply reference voltage UH and a second power supply reference voltage UL, and generate a plurality of first gamma reference voltages VA.

[0022] The second gamma power supply unit 102 is configured to receive the third power supply reference voltage LH and the fourth power supply reference voltage LL, and generate a plurality of second gamma reference voltages VB.

[0023] Optionally, the first gamma power supply unit 101 is configured to generate p1 first gamma reference voltages VA, and the second gamma power supply unit 102 is configured to generate p2 second gamma reference voltages VB. Here, p1 equals 256, 512, 1024, etc., and p1 = p2. As shown in Figure 3A, VG1~VG256 can represent the first gamma reference voltage VA, and VG257~VG512 can represent the second gamma reference voltage VB.

[0024] Optionally, the gamma power module 10 includes an operational amplifier OP and multiple resistors in series to generate multiple gamma reference voltages.

[0025] Referring again to Figure 3A, the first gamma power supply unit 101 includes a first operational amplifier OP1, a second operational amplifier OP2, and multiple first resistors R1. The non-inverting input of the first operational amplifier OP1 is configured to receive a first power supply reference voltage UH, and the inverting input of the first operational amplifier OP1 is electrically connected to its output. The non-inverting input of the second operational amplifier OP2 is configured to receive a second power supply reference voltage UL, and the inverting input of the second operational amplifier OP2 is electrically connected to its output. Multiple first resistors R1 are connected in series between the outputs of the first operational amplifier OP1 and the outputs of the second operational amplifier OP2.

[0026] The second gamma power supply unit 102 includes a third operational amplifier OP3, a fourth operational amplifier OP4, and multiple second resistors R2. The non-inverting input of the third operational amplifier OP3 is configured to receive a third power supply reference voltage LH, and the inverting input of the third operational amplifier OP3 is electrically connected to its output. The non-inverting input of the fourth operational amplifier OP4 is configured to receive a fourth power supply reference voltage LL, and the inverting input of the fourth operational amplifier OP4 is electrically connected to its output. Multiple second resistors R2 are connected in series between the outputs of the third operational amplifier OP3 and the fourth operational amplifier OP4.

[0027] Because each driver chip DIC's gamma power module 10 needs to generate multiple gamma reference voltages based on multiple power reference voltages VGM, the gamma binding voltages corresponding to the minimum gray level (e.g., gray level 0) and the maximum gray level (e.g., gray level 255) among the multiple gamma binding voltages iGM (as shown in Figure 3A) can be directly obtained from the output of the operational amplifier OP in the gamma power module 10, without needing to be obtained through resistor series voltage division. Therefore, each driver chip DIC can directly generate the gamma binding voltages iGM corresponding to the minimum and maximum gray levels based on the received multiple power reference voltages VGM, without having to share the gamma binding voltages iGM corresponding to the minimum and maximum gray levels as a shared voltage SGM. In this way, each driver chip DIC generates the gamma binding voltages corresponding to the minimum and maximum gray levels while generating the binding voltages that need to be shared, which can reduce the number of traces for transmitting the shared voltage SGM.

[0028] Because each driver chip DIC generates gamma binding voltages corresponding to the minimum and maximum gray levels while generating the shared gamma binding voltage iGM, when the display device includes Y driver chips DIC, and each driver chip DIC is configured to output X gamma binding voltages iGM used as the shared voltage SGM, the Y driver chips DIC will output a total of Z gamma binding voltages iGM. Where X > 1, Y > 1, and Z = 4 + XY.

[0029] Please refer to Figures 2 and 3A. Each driver chip DIC includes a voltage generation module 20, which is electrically connected to the gamma power module 10. The voltage generation module 20 is configured to generate multiple gamma binding point voltages iGM based on multiple gamma reference voltages, and to generate multiple polarity gamma voltages based on the multiple gamma binding point voltages iGM and multiple shared voltages SGM.

[0030] Optionally, the multiple polarity gamma voltages include multiple positive gamma voltages VP and multiple negative gamma voltages VN, which can be generated by two voltage generation units in the voltage generation module 20. As shown in FIG3A, the voltage generation module 20 includes a first voltage generation unit 201 and a second voltage generation unit 202.

[0031] The first voltage generation unit 201 is configured to generate at least one first gamma binding point voltage iGMA based on a plurality of first gamma reference voltages VA, and share the first gamma binding point voltage iGMA as a first shared voltage SGMA with at least one other driver chip DIC, and generate a plurality of positive polarity gamma voltages VP based on the first gamma binding point voltage iGMA and the received plurality of first shared voltages SGMA.

[0032] The second voltage generation unit 202 is configured to generate at least one second gamma binding point voltage iGMB based on a plurality of second gamma reference voltages VB, and share the second gamma binding point voltage iGMB as a second shared voltage SGMB with at least one other driver chip DIC, and generate a plurality of negative polarity gamma voltages VN based on the second gamma binding point voltage iGMB and the received plurality of second shared voltages SGMB.

[0033] Among them, the multiple gamma binding point voltages iGM include the first gamma binding point voltage iGMA and the second gamma binding point voltage iGMB, and the shared voltage SGM includes the first shared voltage SGMA and the second shared voltage SGMB.

[0034] Since both the first voltage generation unit 201 and the second voltage generation unit 202 generate at least one gamma binding point voltage iGM, and receive the gamma binding point voltage iGM output by other driver chips DIC as a shared voltage SGM, the number of gamma binding point voltages iGM that the first voltage generation unit 201 and the second voltage generation unit 202 in each driver chip DIC need to generate is reduced.

[0035] Optionally, the first voltage generation unit 201 is electrically connected to the first gamma power supply unit 101, and the second voltage generation unit 202 is electrically connected to the second gamma power supply unit 102, so that the first voltage generation unit 201 generates a first gamma binding point voltage iGMA and a positive gamma voltage VP based on a plurality of first gamma reference voltages VA output by the first gamma power supply unit 101, and the second voltage generation unit 202 generates a second gamma binding point voltage iGMB and a negative gamma voltage VN based on a plurality of second gamma reference voltages VB output by the second gamma power supply unit 102.

[0036] Optionally, each driver chip DIC is configured to output X gamma-binding point voltages iGM as shared voltage SGM, where X > 1. Correspondingly, each voltage generation unit outputs V gamma-binding point voltages iGM as shared voltage SGM, where V < X.

[0037] For example, if the voltage generation module 20 includes two voltage generation units (i.e., X=2), and each driver chip DIC outputs two gamma binding point voltages iGM used as a shared voltage SGM, the first voltage generation unit 201 outputs a first gamma binding point voltage iGMA used as a shared voltage SGM, and the second voltage generation unit 202 outputs a second gamma binding point voltage iGMB (i.e., V=1) used as a shared voltage SGM.

[0038] Please continue to refer to Figure 3A. At least one of the first voltage generation unit 201 and the second voltage generation unit 202 includes at least one first digital-to-analog converter circuit DAC1, at least one voltage amplifier circuit GOP, and a polarity voltage generation circuit GR.

[0039] The first digital-to-analog converter circuit DAC1 is electrically connected to the corresponding gamma power supply module 10. The first digital-to-analog converter circuit DAC1 is configured to generate a binding point voltage based on multiple gamma reference voltages.

[0040] The voltage amplifier circuit GOP is electrically connected to the corresponding first digital-to-analog converter circuit DAC1. The voltage amplifier circuit GOP is configured to generate a gamma binding voltage iGM based on the binding voltage.

[0041] The polarity voltage generation circuit GR is electrically connected to the voltage amplifier circuit GOP. The polarity voltage generation circuit GR is configured to generate multiple polarity gamma voltages based on multiple gamma binding point voltages iGM and multiple shared voltages SGM.

[0042] Optionally, the voltage amplifier circuit GOP can be a voltage follower to amplify the gamma voltage to obtain the gamma binding point voltage iGM. The polarity voltage generation circuit GR can be a resistor series.

[0043] Optionally, the driver chip DIC outputs X gamma-binding voltages iGM, which are used as a shared voltage SGM. The voltage generation module 20 of the driver chip DIC includes X first digital-to-analog converter circuits DAC1 and X voltage amplifier circuits GOP. Where X > 1. Because the number of gamma-binding voltages iGM output by the driver chip DIC is reduced, the number of first digital-to-analog converter circuits DAC1 and voltage amplifier circuits GOP included in the voltage generation module 20 is also reduced, which is beneficial to reducing the size, power consumption and cost of the driver chip DIC.

[0044] Please refer to Figure 3A. Taking the voltage generation module 20 as having two voltage generation units and each driver chip DIC outputting two gamma binding voltages iGM used as a shared voltage SGM as an example, the first voltage generation unit 201 includes a first digital-to-analog converter circuit DAC1 and a voltage amplifier circuit GOP. The first digital-to-analog converter circuit DAC1 generates a first binding voltage based on multiple first gamma reference voltages VA. The voltage amplifier circuit GOP amplifies the first binding voltage to obtain a first gamma binding voltage iGMA that is multiplexed as a shared voltage SGM. The first gamma binding voltage iGMA is then output to the corresponding polarity voltage generation circuit GR and shared with other driver chips DIC. The second voltage generation unit 202 includes a first digital-to-analog converter (DAC1) and a voltage amplifier circuit (GOP). The DAC1 generates a second binding point voltage based on multiple second gamma reference voltages VB. The GOP amplifies this second binding point voltage to obtain a second gamma binding point voltage iGMB, which is then multiplexed as a shared voltage SGM. This second gamma binding point voltage iGMB is output to the corresponding polarity voltage generation circuit GR and shared with other driver chips (DIC). Therefore, the voltage generation module 20 of the driver chip (DIC) includes two first digital-to-analog converters (DAC1) and two voltage amplifier circuits (GOP).

[0045] Optionally, when the voltage generation module 20 includes two voltage generation units, X can be an even number.

[0046] Optionally, the first gray level mapped to the first gamma binding voltage iGMA generated by the same driver chip DIC is equal to the second gray level mapped to the second gamma binding voltage iGMB, so that the same driver chip DIC can provide other driver chip DICs with the first gamma binding voltage iGMA and the second gamma binding voltage iGMB mapped to the same gray level, while the gamma binding voltage iGM corresponding to multiple driver chip DICs maps to different gray levels.

[0047] Taking a display device comprising multiple driver chips (DICs), each driver chip (DIC) outputting two gamma-binding voltages (iGM) used as a shared voltage (SGM), as an example: In the multiple driver chips (DICs), the first grayscale corresponding to the first gamma-binding voltage (iGM) output by the first driver chip (DIC1) is equal to the second grayscale corresponding to its second gamma-binding voltage (iGMB), and both the first and second grayscales correspond to low grayscales. The first grayscale corresponding to the first gamma-binding voltage (iGM) output by the second driver chip (DIC2) is equal to the second grayscale corresponding to its second gamma-binding voltage (iGMB), and both the first and second grayscales corresponding to the second driver chip (DIC2) are greater than those corresponding to the first driver chip (DIC1).

[0048] Because signal loss occurs during signal transmission, the signal transmission loss of the shared voltage SGM mapping to low grayscale has a greater impact than that of the shared voltage SGM mapping to high grayscale, which has the same level of signal transmission loss. Therefore, multiple output gamma binding point voltages iGM can be set in the display device to correspond to the driver chip DIC mapping to low grayscale, in order to ensure the signal quality of the shared voltage SGM mapping to low grayscale.

[0049] Accordingly, please continue to refer to Figure 1A, where multiple driver chips DIC include multiple first driver chips DICA and multiple second driver chips DICB.

[0050] The first gray levels mapped to the DICA of multiple first driver chips are the same, the second gray levels mapped to the DICA of multiple first driver chips are the same, the first gray levels mapped to the DICB of multiple second driver chips are different, and the second gray levels mapped to the DICB of multiple second driver chips are different.

[0051] Among them, the first gray level and / or the second gray level mapped by the multiple second driver chips DICB are greater than the first gray level and the second gray level mapped by the multiple first driver chips DICA.

[0052] By setting up multiple first driver chips (DICA), the source of the shared voltage SGM corresponding to the mapped low grayscale is increased, thereby maintaining the signal quality of the shared voltage SGM corresponding to the mapped low grayscale.

[0053] Optionally, to further improve the signal quality of the shared voltage SGM corresponding to the low grayscale mapping, multiple second driver chips DICB can be disposed between two first driver chips DICA to reduce the signal quality difference of the shared voltage SGM corresponding to the low grayscale mapping received by the multiple second driver chips DICB.

[0054] Optionally, to improve the signal quality of the shared voltage SGM corresponding to the low grayscale mapping, multiple voltage amplifier circuits (GOPs) can be set in the branch containing the binding point voltage corresponding to the low grayscale mapping in the voltage generation unit, so that the binding point voltage is processed by multiple voltage amplifier circuits (GOPs) to obtain the gamma binding point voltage iGM corresponding to the low grayscale mapping. Optionally, the gamma binding point voltage iGM obtained after being processed by multiple voltage amplifier circuits (GOPs) is used as the shared voltage SGM, as shown in Figure 3B. Optionally, after the gamma binding point voltage iGM obtained after being processed by a voltage amplifier circuit (GOP) is shared as the shared voltage SGM to other driver chips, the driver chip receiving the shared voltage SGM is also equipped with a voltage amplifier circuit (GOP) to process the shared voltage again before outputting it to the corresponding polarity voltage generation circuit GR, as shown in Figure 3C.

[0055] Referring to Figure 1A, the display device includes multiple shared lines SL, which are electrically connected to multiple driver chips DIC. Each shared line SL is configured to transmit a shared voltage SGM. Between two first driver chips DICA, multiple second driver chips DICB are provided, electrically connected to the shared lines SL, so that the first driver chips DICA form a bilateral drive, thereby providing the required shared voltage SGM to the multiple second driver chips DICB.

[0056] Please refer to Figures 2 and 3A. Each driver chip DIC also includes a signal generation module 30. The signal generation module 30 is electrically connected to the voltage generation module 20. The signal generation module 30 is configured to receive multiple polarity gamma voltages and generate multiple polarity data signals.

[0057] Optionally, the signal generation module 30 includes a shift register SR, a latch LU, a level conversion circuit LS, a second digital-to-analog converter circuit DAC2, and an output buffer OB.

[0058] The shift register SR is configured to generate a sampling signal based on the clock control signal CK.

[0059] The latch LU is electrically connected to the shift register SR. The latch LU is configured to generate multiple first data voltages based on the sampled signal and the received image signal FD, and to latch or release the multiple first data voltages according to the data latch control signal TP.

[0060] The level shifting circuit LS is electrically connected to the latch LU, and the level shifting circuit LS is configured to generate multiple second data voltages based on multiple first data voltages.

[0061] The second digital-to-analog converter circuit DAC2 is electrically connected to the level conversion circuit LS and the voltage generation module 20. The second digital-to-analog converter circuit DAC2 is configured to generate multiple polarity grayscale voltages based on multiple second data voltages and polarity gamma voltages.

[0062] The output buffer OB is electrically connected to the second digital-to-analog converter circuit DAC2. The output buffer OB is configured to generate multiple polarity data signals based on multiple polarity grayscale voltages.

[0063] The second digital-to-analog converter circuit DAC2 is configured to generate multiple positive grayscale voltages based on multiple second data voltages and a positive gamma voltage VP; and to generate multiple negative grayscale voltages based on multiple second data voltages and multiple negative gamma voltages VN. The output buffer OB is configured to generate multiple positive data signals based on the multiple positive grayscale voltages, and to generate multiple negative data signals based on the multiple negative grayscale voltages.

[0064] Optionally, the timing controller Tcon can be used to provide the signal generation module 30 with the clock control signal CK, the image signal FD, and the data latch control signal TP.

[0065] Optionally, the number of driver chips (DICs) included in the display device can be determined based on the number of output channels of the driver chip (DIC) and the resolution of the display panel (DP).

[0066] Optionally, if the resolution of the display panel DP is R*S and the number of output channels of the driver chip DIC is T, then the number of driver chips DIC is 3R / T. Where R > 0, S > 0, and T > 0. For example, if the resolution of the display panel DP is 3840*2160 and the number of output channels of the driver chip DIC is 960, then the number of driver chips DIC is 3840*3 / 960 = 12.

[0067] It should be noted that each output channel of the driver chip DIC can be used to output a polarity data signal to the corresponding data line DL.

[0068] Please refer to Figures 1A, 2, and 3A. The working principle of the display device is explained by taking as an example that the display device includes multiple driver chips (DIC), each driver chip (DIC) generates two shared gamma binding point voltages (iGM), and each driver chip (DIC) generates polarity data signals based on 14 gamma binding point voltages (iGM).

[0069] Each driver chip (DIC) generates the shared gamma binding voltage iGM, and simultaneously generates the first gamma binding voltage iGMA (denoted as the seventh gamma binding voltage iGM7) corresponding to the minimum gray level, the first gamma binding voltage iGMA (denoted as the first gamma binding voltage iGM1) corresponding to the maximum gray level, the second gamma binding voltage iGMB (denoted as the eighth gamma binding voltage iGM8) corresponding to the minimum gray level, and the second gamma binding voltage iGMB (denoted as the fourteenth gamma binding voltage iGM) corresponding to the maximum gray level.

[0070] In the first driver chip DIC1, the first gamma power supply unit 101 generates multiple first gamma reference voltages VA based on the first power reference voltage UH and the second power reference voltage UL, and outputs them to the first voltage generation unit 201. The first digital-to-analog converter circuit DAC1 in the first voltage generation unit 201 generates a binding point voltage based on the multiple first gamma reference voltages VA. The binding point voltage is amplified by the voltage amplifier circuit GOP in the first voltage generation unit 201 to obtain the sixth gamma binding point voltage iGM6. The sixth gamma binding point voltage iGM6 is output to the polarity voltage generation circuit GR in the first voltage generation unit 201 and shared with other driver chips DIC. The second gamma power supply unit 102 generates multiple second gamma reference voltages VB based on the third power reference voltage LH and the fourth power reference voltage LL, and outputs them to the second voltage generation unit 202. The first digital-to-analog converter circuit DAC1 in the second voltage generation unit 202 generates another binding point voltage based on the multiple second gamma reference voltages VB. This binding point voltage is amplified by the voltage amplifier circuit GOP in the second voltage generation unit 202 to obtain the ninth gamma binding point voltage iGM9. The ninth gamma binding point voltage iGM9 is output to the polarity voltage generation circuit GR in the second voltage generation unit 202 and shared with other driver chips DIC.

[0071] In the second driver chip DIC2, the first gamma power supply unit 101 generates multiple first gamma reference voltages VA based on the first power supply reference voltage UH and the second power supply reference voltage UL, and outputs them to the first voltage generation unit 201. The first digital-to-analog converter circuit DAC1 in the first voltage generation unit 201 generates a binding point voltage based on the multiple first gamma reference voltages VA. The binding point voltage is amplified by the voltage amplifier circuit GOP in the first voltage generation unit 201 to obtain the fifth gamma binding point voltage iGM5. The fifth gamma binding point voltage iGM5 is output to the polarity voltage generation circuit GR in the first voltage generation unit 201 and shared with other driver chips DIC. The second gamma power supply unit 102 generates multiple second gamma reference voltages VB based on the third power reference voltage LH and the fourth power reference voltage LL, and outputs them to the second voltage generation unit 202. The first digital-to-analog converter circuit DAC1 in the second voltage generation unit 202 generates another binding point voltage based on the multiple second gamma reference voltages VB. This binding point voltage is amplified by the voltage amplifier circuit GOP in the second voltage generation unit 202 to obtain the tenth gamma binding point voltage iGM10. The tenth gamma binding point voltage iGM10 is output to the polarity voltage generation circuit GR in the second voltage generation unit 202 and shared with other driver chips DIC.

[0072] Similarly, the voltage generation module 20 in the third driver chip DIC3 generates the fourth gamma binding point voltage iGM4 and the eleventh gamma binding point voltage iGM11 and shares them with other driver chips DIC; the voltage generation module 20 in the fourth driver chip DIC4 generates the third gamma binding point voltage iGM3 and the twelfth gamma binding point voltage iGM12 and shares them with other driver chips DIC; the voltage generation module 20 in the fifth driver chip DIC5 generates the second gamma binding point voltage iGM2 and the thirteenth gamma binding point voltage iGM13 and shares them with other driver chips DIC.

[0073] In the first driver chip DIC1, the polarity voltage generation circuit GR in the first voltage generation unit 201 generates multiple positive polarity gamma voltages VP based on the first gamma binding point voltage iGM1, the sixth gamma binding point voltage iGM6, the seventh gamma binding point voltage iGM7, and the shared voltage SGM (i.e., the second gamma binding point voltage iGM2 to the fifth gamma binding point voltage iGM5), and outputs them to the second digital-to-analog converter circuit DAC2 of the signal generation module 30. The second digital-to-analog converter circuit DAC2 generates multiple positive polarity grayscale voltages based on the multiple second data voltages and the positive polarity gamma voltages VP. The output buffer OB of the signal generation module 30 receives the multiple positive polarity grayscale voltages and generates multiple positive polarity data signals, which are output to the corresponding data lines DL through multiple output channels so that the corresponding sub-pixel Spi receives the positive polarity data signals. The polarity voltage generation circuit GR in the second voltage generation unit 202 generates multiple negative polarity gamma voltages VN based on the eighth gamma binding point voltage iGM8, the ninth gamma binding point voltage iGM9, the fourteenth gamma binding point voltage iGM14, and the shared voltage SGM (i.e., the tenth gamma binding point voltage iGM10 to the thirteenth gamma binding point voltage iGM13). These voltages are then output to the second digital-to-analog converter circuit DAC2 in the signal generation module 30. The second digital-to-analog converter circuit DAC2 generates multiple negative polarity grayscale voltages based on the multiple second data voltages and the negative polarity gamma voltages VN. The output buffer OB of the signal generation module 30 receives the multiple negative polarity grayscale voltages and generates multiple negative polarity data signals, which are then output to the corresponding data lines DL through multiple output channels, so that the corresponding sub-pixel Spi receives the negative polarity data signals.

[0074] In the second driver chip DIC2, the polarity voltage generation circuit GR in the first voltage generation unit 201 generates multiple positive polarity gamma voltages VP based on the first gamma binding point voltage iGM1, the fifth gamma binding point voltage iGM5, the seventh gamma binding point voltage iGM7, and the shared voltage SGM (i.e., the second gamma binding point voltage iGM2 to the fourth gamma binding point voltage iGM4 and the sixth gamma binding point voltage iGM6). These voltages are then output to the second digital-to-analog converter circuit DAC2 of the signal generation module 30. The second digital-to-analog converter circuit DAC2 generates multiple positive polarity grayscale voltages based on the multiple second data voltages and the positive polarity gamma voltages VP. The output buffer OB of the signal generation module 30 receives the multiple positive polarity grayscale voltages and generates multiple positive polarity data signals, which are then output to the corresponding data lines DL through multiple output channels, so that the corresponding sub-pixel Spi receives the positive polarity data signals. The polarity voltage generation circuit GR in the second voltage generation unit 202 generates multiple negative polarity gamma voltages VN based on the eighth gamma binding point voltage iGM8, the tenth gamma binding point voltage iGM10, the fourteenth gamma binding point voltage iGM14, and the shared voltage SGM (i.e., the ninth gamma binding point voltage iGM9, the eleventh gamma binding point voltage iGM11 to the thirteenth gamma binding point voltage iGM13). These voltages are then output to the second digital-to-analog converter circuit DAC2 in the signal generation module 30. The second digital-to-analog converter circuit DAC2 generates multiple negative polarity grayscale voltages based on the multiple second data voltages and the negative polarity gamma voltages VN. The output buffer OB of the signal generation module 30 receives the multiple negative polarity grayscale voltages and generates multiple negative polarity data signals, which are then output to the corresponding data lines DL through multiple output channels, so that the corresponding sub-pixel Spi receives the negative polarity data signals.

[0075] Similarly, the working principle of the third driver chip DIC3 to the fifth driver chip DIC5 is also obtained. Based on the multiple gamma binding point voltages iGM generated by itself and the multiple shared voltages SGM received, multiple polarity data signals are generated and received by multiple sub-pixels Spi.

[0076] Therefore, when each driver chip DIC generates two gamma-binding point voltages iGM for use as a shared voltage SGM, only one voltage amplifier circuit GOP needs to be set in the first voltage generation unit 201 and the second generation unit, respectively. Thus, only two voltage amplifier circuit GOPs are needed in each driver chip DIC. Therefore, compared to the 10 voltage amplifier circuit GOPs required in each driver chip DIC shown in Figure 3D, the design shown in Figure 3A significantly reduces the number of voltage amplifier circuit GOPs included in the driver chip DIC, which is beneficial for reducing the size, power consumption, and cost of the driver chip DIC.

[0077] Furthermore, each driver chip DIC generates polarity data signals based on 14 gamma binding point voltages iGM. Since each driver chip DIC generates two gamma binding point voltages iGM used as a shared voltage SGM, only 5 driver chip DICs are needed to meet the requirements. That is, 5 driver chip DICs generate a total of 10 gamma binding point voltages iGM used as a shared voltage SGM. Each driver chip DIC also generates 4 gamma binding point voltages iGM corresponding to the minimum and maximum gray levels based on multiple power supply reference voltages VGM, thus making Z = 4 + XY = 4 + 2 * 5 = 14.

[0078] Therefore, using the design shown in Figure 3A, when the display device includes 12 driver chips (DICs), and each driver chip (DIC) generates two gamma binding voltages (iGMs) used as a shared voltage (SGM), the 12 driver chips (DICs) can support the output of 28 (i.e., 4 + 2 * 12 = 28) different gamma binding voltages (iGMs). However, using the design shown in Figure 3D, multiple driver chips (DICs) generate 14 identical gamma binding voltages (iGMs). Therefore, compared to the driver chip (DIC) shown in Figure 3D, the design shown in Figure 3A can increase the number of gamma binding voltages (iGMs) without increasing cost. This helps to alleviate the cost increase caused by the need to adapt different driver chips (DICs) for different display panels (DPs) due to differences between them, thus broadening the application range of driver chips (DICs) and improving their versatility.

[0079] Because the higher the resolution of the display panel (DP), the longer the signal transmission path and the greater the signal transmission loss. Therefore, to adapt to the resolution of the display panel (DP), when the number of driver chips (DIC) is greater than the required number (i.e., the required number is 5), in order to improve the signal quality of the shared voltage SGM corresponding to the low grayscale mapping, the sixth driver chip (DIC6) can also generate a sixth gamma binding voltage iGM6 and a ninth gamma binding voltage iGM9, as shown in Figure 3A. The grayscale mapped by the sixth gamma binding voltage iGM6 and the ninth gamma binding voltage iGM9 is smaller than the grayscale mapped by the second to fifth gamma binding voltages iGM2 to iGM5 and the tenth to thirteenth gamma binding voltages iGM10 to iGM10. Accordingly, the first driver chip DIC1 and the sixth driver chip DIC6 correspond to the first driver chip DICA mentioned above, and the second driver chip DIC2 to the fifth driver chip DIC5 correspond to the second driver chip DICB mentioned above.

[0080] To further improve the signal quality of the shared voltage SGM corresponding to the low grayscale mapping, the first driver chip DIC1 and the sixth driver chip DIC6 are set on opposite sides of the second driver chip DIC2 to the fifth driver chip DIC5, as shown in Figure 1A.

[0081] To further improve the signal quality of the shared voltage SGM corresponding to the low gray level of the mapping, at least one of the fourth gamma binding point voltages iGM4 to iGM6 and at least one of the ninth gamma binding point voltages iGM9 to iGM11 corresponding to the low gray level of the mapping are obtained by the action of two voltage amplifier circuits GOP, as shown in Figures 3B to 3C.

[0082] In some embodiments, to adapt to the resolution of the display panel DP and reduce signal attenuation, the first driver chip DICA and the second driver chip DICB can be repeatedly set in groups. As shown in Figure 1A, there are also the eighth driver chip DIC8 to the tenth driver chip DIC10 corresponding to the generated second gamma binding voltage iGM2 to the fifth gamma binding voltage iGM5 and the tenth gamma binding voltage iGM10 to the thirteenth gamma binding voltage iGM13, and the seventh driver chip DIC7 and the twelfth driver chip DIC12 corresponding to the generated sixth gamma binding voltage iGM6 and the ninth gamma binding voltage iGM9. The first driver chip DIC1 to the sixth driver chip DIC6 form a chip group, and the seventh driver chip DIC7 to the twelfth driver chip DIC12 form another chip group. The shared voltage SGM between multiple chip groups can be shared.

[0083] Please refer to Figure 1A. The display panel DP includes liquid crystal display panels. Display panel DP includes horizontal electric field inversion liquid crystal display panels, vertical alignment liquid crystal display panels, low temperature polycrystalline silicon display panels, etc.

[0084] Because different types of liquid crystal display (DP) panels use different materials and have different structural designs, the optical performance of DP panels also varies. Inconsistent material optical curves lead to differences in the grayscale variation capabilities of DP panels. For example, in a horizontal electric field inversion type liquid crystal display panel, the resistor string in the polarity voltage generation circuit GR is sensitive to changes in the corresponding low grayscale levels. If the horizontal electric field inversion type liquid crystal display panel directly uses the driver chip DIC shown in Figure 3D, which is applied to a vertical alignment type liquid crystal display panel, the low grayscale brightness gradient will change too quickly, causing the gamma binding voltage iGM corresponding to the low grayscale to exceed the lower limit, resulting in display problems such as color shift and noise in the DP panel.

[0085] By adopting the design shown in Figure 3A and sharing the gamma binding voltage iGM among multiple driver chips (DICs), it is possible to increase the gamma binding grayscale voltage and polarity gamma voltage corresponding to the mapped low grayscale without increasing the number of driver chips (DICs). For example, in a vertically aligned liquid crystal display panel, the corresponding polarity gamma voltages are ±G0, ±G1, ±G31, ±G127, ±G223, ±G254, and ±G255. In a horizontally aligned inverted liquid crystal display panel, applying the design shown in Figure 3A increases the gamma binding voltage iGM, resulting in polarity gamma voltages of ±G0, ±G1, ±G8, ±G16, ±G31, ±G127, ±G223, ±G254, and ±G255. Therefore, the gamma binding point voltage iGM generated by the driver chip DIC shown in Figure 3A can meet the application requirements of both vertical alignment liquid crystal display (DP) and horizontal electric field inversion liquid crystal display (DP) applications. This reduces the number of driver chips (DIC) and improves their versatility. Here, + indicates positive polarity and - indicates negative polarity.

[0086] It should be noted that in some embodiments, multiple first gamma reference voltages VA and multiple second gamma reference voltages VB can also be generated by a single gamma power supply unit. That is, by using a timing controller Tcon, a logic controller, and other control modules in conjunction with register settings, the same gamma power supply module can generate the first gamma reference voltage VA and the second gamma reference voltage VB in a 10-minute time-sharing manner, thereby further reducing the number of operational amplifiers included in the driver chip DIC. For example, the gamma power supply module 10 may include only one gamma power supply unit, which includes a first operational amplifier OP1, a second operational amplifier OP2, and multiple resistors connected in series. The non-inverting input of the first operational amplifier OP1 is configured to receive either a first power reference voltage UH or a third power reference voltage LH, and the inverting input of the first operational amplifier OP1 is electrically connected to its output. The non-inverting input of the second operational amplifier OP2 is configured to receive either a second power reference voltage UL or a fourth power reference voltage LL, and the inverting input of the second operational amplifier OP2 is electrically connected to its output. Multiple resistors are connected in series between the outputs of the first operational amplifier OP1 and the second operational amplifier OP2. This reduces the number of operational amplifiers in the driver chip DIC to two.

[0087] Optionally, when multiple first gamma reference voltages VA and multiple second gamma reference voltages VB are generated by the same gamma power supply unit, the first voltage generation unit 201 and the second voltage generation unit 202 can be electrically connected to the gamma power supply unit in a time-sharing manner by using control modules such as timing controllers and logic controllers in conjunction with register settings.

[0088] Optionally, the positive gamma voltage VP and the negative gamma voltage VN can also be generated by the same voltage generation unit. That is, through the timing controller, logic controller and other control modules, in conjunction with the register settings, a voltage generation unit can generate the first gamma binding point voltage iGMA and the positive gamma voltage VP, the second gamma binding point voltage iGMB and the negative gamma voltage VN in a time-division manner.

[0089] Optionally, each driver chip DIC is configured to output X gamma-binding voltages iGM used as a shared voltage SGM. The first gamma reference voltage VA and the second gamma reference voltage VB are generated by the same voltage generation unit, and when each driver chip DIC outputs V gamma-binding voltages iGM used as a shared voltage SGM, V=X. If the first gamma reference voltage VA and the second gamma reference voltage VB are generated by the same voltage generation unit, and each driver chip DIC outputs two gamma-binding voltages iGM used as a shared voltage SGM (i.e., X=2), the voltage generation unit outputs a first gamma-binding voltage iGMA and a second gamma-binding voltage iGMB used as a shared voltage SGM in a time-division manner (i.e., V=2).

[0090] Understandably, when the first gamma binding point voltage iGMA and the second gamma binding point voltage iGMB are generated through the same voltage generation unit, the number of the first digital-to-analog converter circuit DAC1 and the voltage amplifier circuit GOP included in the voltage generation module 20 will be further reduced.

[0091] This document uses specific examples to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only for the purpose of helping to understand the methods and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A display device, wherein, include: Display panel, including multiple data cables; Multiple driver chips are electrically connected to the display panel. Each driver chip is configured to receive multiple power supply reference voltages to generate multiple gamma binding point voltages, and share the multiple gamma binding point voltages as multiple shared voltages with at least one other driver chip. It also generates multiple polarity data signals based on the multiple gamma binding point voltages and the received multiple shared voltages and outputs them to the corresponding data lines. Among them, the grayscale corresponding to the gamma binding point voltage generated by at least two of the driving chips and used as the shared voltage is different.

2. The display device according to claim 1, wherein, Each of the aforementioned driver chips includes: A gamma power module is configured to receive multiple power reference voltages and generate multiple gamma reference voltages; A voltage generation module, electrically connected to the gamma power module, is configured to generate multiple gamma binding point voltages based on multiple gamma reference voltages, and to generate multiple polarity gamma voltages based on the multiple gamma binding point voltages and multiple shared voltages. The signal generation module, electrically connected to the voltage generation module, is configured to receive multiple polarity gamma voltages and generate multiple polarity data signals.

3. The display device according to claim 2, wherein, The power supply reference voltage includes a first power supply reference voltage, a second power supply reference voltage, a third power supply reference voltage, and a fourth power supply reference voltage; The gamma power module includes: The first gamma power supply unit is configured to receive the first power supply reference voltage and the second power supply reference voltage, and generate a plurality of first gamma reference voltages; as well as The second gamma power supply unit is configured to receive the third power supply reference voltage and the fourth power supply reference voltage, and generate a plurality of second gamma reference voltages.

4. The display device according to claim 3, wherein, The voltage generation module includes: A first voltage generation unit, electrically connected to the first gamma voltage unit, is configured to generate at least one first gamma binding point voltage based on a plurality of first gamma reference voltages, and share the first gamma binding point voltage as a first shared voltage with at least one other driver chip, and generate a plurality of positive gamma voltages based on the first gamma binding point voltage and the received plurality of first shared voltages; and The second voltage generation unit, electrically connected to the second gamma voltage unit, is configured to generate at least one second gamma binding point voltage based on a plurality of second gamma reference voltages, and share the second gamma binding point voltage as a second shared voltage with at least one other driver chip, and generate a plurality of negative voltages based on the second gamma binding point voltage and the received plurality of second shared voltages. The plurality of gamma binding point voltages include the first gamma binding point voltage and the second gamma binding point voltage, the polarity gamma voltages include the positive polarity gamma voltage and the negative polarity gamma voltage, and the shared voltages include the first shared voltage and the second shared voltage.

5. The display device according to claim 4, wherein, At least one of the first voltage generating unit and the second voltage generating unit includes: At least one first digital-to-analog converter circuit is electrically connected to the corresponding gamma power module and is configured to generate a binding point voltage based on a plurality of gamma reference voltages; At least one voltage amplifier circuit, electrically connected to the corresponding first digital-to-analog converter circuit, is configured to generate the gamma bind-point voltage based on the bind-point voltage; and A polarity voltage generation circuit, electrically connected to the voltage amplification circuit, is configured to generate a plurality of polarity gamma voltages based on a plurality of gamma binding point voltages and a plurality of shared voltages.

6. The display device according to claim 5, wherein, The driver chip outputs X gamma binding point voltages used as the shared voltage; The voltage generation module of the driving chip includes X first digital-to-analog conversion circuits and X voltage amplification circuits; X > 1.

7. The display device according to claim 4, wherein, The first gray level mapped to the first gamma binding point voltage is equal to the second gray level mapped to the second gamma binding point voltage.

8. The display device according to claim 7, wherein, The plurality of driving chips includes a plurality of first driving chips and a plurality of second driving chips; the plurality of first driving chips correspond to the same first gray level, the plurality of first driving chips correspond to the same second gray level, the plurality of second driving chips correspond to different first gray levels, and the plurality of second driving chips correspond to different second gray levels. Wherein, the first gray level and / or the second gray level mapped to the plurality of second driver chips are greater than the first gray level and the second gray level mapped to the plurality of first driver chips.

9. The display device according to claim 8, wherein, include: Multiple shared lines are electrically connected to multiple driver chips, and each shared line is configured to transmit a shared voltage; Among them, between the two first driving chips, there are multiple second driving chips that are electrically connected to the shared line.

10. The display device according to claim 2, wherein, The signal generation module includes: The shift register is configured to generate a sampling signal based on a clock control signal; A latch, electrically connected to the shift register, is configured to generate a plurality of first data voltages based on the sampled signal and the received image signal, and to latch or release the plurality of first data voltages based on a data latch control signal. A level conversion circuit, electrically connected to the latch, is configured to generate a plurality of second data voltages based on a plurality of first data voltages; A second digital-to-analog converter circuit, electrically connected to the level conversion circuit and the voltage generation module, is configured to generate multiple polarity grayscale voltages based on multiple second data voltages and the polarity gamma voltage; and The output buffer, electrically connected to the second digital-to-analog converter circuit, is configured to generate multiple polarity data signals based on multiple polarity grayscale voltages.

11. The display device according to claim 1, wherein, The display device includes Y driving chips, each driving chip being configured to output X gamma binding point voltages used as the shared voltage; Among them, Y of the driving chips output Z of the gamma binding point voltages, X>1, Y>1, Z=4+XY.

12. The display device according to claim 1, wherein, The display panel includes a horizontal electric field inversion type liquid crystal display panel and a vertical alignment type liquid crystal display panel.

13. The display device according to claim 3, wherein, The first gamma power supply unit includes: A first operational amplifier, wherein the non-inverting input of the first operational amplifier is configured to receive the first power supply reference voltage, and the inverting input of the first operational amplifier is electrically connected to the output of the first operational amplifier. A second operational amplifier, wherein the non-inverting input of the second operational amplifier is configured to receive the second power supply reference voltage, and the inverting input of the second operational amplifier is electrically connected to the output of the second operational amplifier; and Multiple first resistors are connected in series between the output terminals of the first operational amplifier and the output terminals of the second operational amplifier.

14. The display device according to claim 3, wherein, The second gamma power supply unit includes: A third operational amplifier, wherein the non-inverting input of the third operational amplifier is configured to receive the third power supply reference voltage, and the inverting input of the third operational amplifier is electrically connected to the output of the third operational amplifier; A fourth operational amplifier, wherein the non-inverting input of the fourth operational amplifier is configured to receive the fourth power supply reference voltage, and the inverting input of the fourth operational amplifier is electrically connected to the output of the fourth operational amplifier; and Multiple second resistors are connected in series between the output terminals of the third operational amplifier and the output terminals of the fourth operational amplifier.

15. The display device according to claim 3, wherein, Each of the driving chips is configured to output X gamma binding point voltages used as the shared voltage, and at least one of the first voltage generation unit and the second voltage generation unit outputs V gamma binding point voltages used as the shared voltage; wherein, X > 1, V < X.

16. The display device according to claim 3, wherein, The first gamma power supply unit is configured to generate p1 first gamma reference voltages, and the second gamma power supply unit is configured to generate p2 second gamma reference voltages; wherein, p1 = 256, 512 or 1024; p1 = p2.

17. The display device according to claim 5, wherein, The driver chip outputs X gamma binding point voltages used as the shared voltage, and the voltage generation module of the driver chip includes X first digital-to-analog conversion circuits and X voltage amplification circuits.

18. The display device according to claim 1, wherein, include: The power management chip is configured to output the power reference voltage.

19. The display device according to claim 2, wherein, The power supply reference voltage includes a first power supply reference voltage, a second power supply reference voltage, a third power supply reference voltage, and a fourth power supply reference voltage; The gamma power module includes: The gamma power supply unit is configured to receive the first power supply reference voltage, the second power supply reference voltage, the third power supply reference voltage, and the fourth power supply reference voltage to generate a plurality of first gamma reference voltages and a plurality of second gamma reference voltages.

20. The display device according to claim 19, wherein, The gamma power supply unit includes: A first operational amplifier, wherein the non-inverting input of the first operational amplifier is configured to receive the first power supply reference voltage or the third power supply reference voltage, and the inverting input of the first operational amplifier is electrically connected to the output of the first operational amplifier. A second operational amplifier, wherein the non-inverting input of the second operational amplifier is configured to receive either the second power supply reference voltage or the fourth power supply reference voltage, and the inverting input of the second operational amplifier is electrically connected to its output; and Multiple resistors are connected in series between the output terminals of the first operational amplifier and the output terminals of the second operational amplifier.

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