Image refresh method and apparatus

Abstract

An image refresh method and an apparatus. The method comprises: after setting the value of a first target bit of an image display on the basis of a first image, a processor receives an image display instruction (S701); the processor sets the value of a second target bit of the image display on the basis of a second image, the second target bit being a first bit on M bit planes corresponding to the image display other than the first target bit (S702); and the processor sets the value of the first bit of the image display on the basis of the second image (S703).

Description

An image refresh method and apparatus

[0001] Cross-reference to related applications

[0002] This application claims priority to Chinese Patent Application No. 202411207274.8, filed on August 29, 2024, entitled "An Image Refreshing Method and Apparatus", the entire contents of which are incorporated herein by reference. Technical Field

[0003] This application relates to the field of optical communication technology, and in particular to an image refresh method and apparatus. Background Technology

[0004] In the field of image display, image displays (such as liquid crystal displays) can be used to display images. During the display of image A, under certain circumstances, the image display needs to display image B as quickly as possible. Currently, the image display displays image A completely before displaying image B. It can be seen that this process of switching from image A to image B takes a significant amount of time. Improving the efficiency of image displays in switching between different images is a pressing technical problem that needs to be solved. Summary of the Invention

[0005] This application provides an image refresh method and apparatus to solve the problem of excessive time spent when switching between different images on an image display.

[0006] In a first aspect, embodiments of this application provide an image refresh method. The execution subject of this method is a processor, a module, or a chip in an image display. Here, the processor is used as the execution subject for example. The method includes: after setting the value of a first target bit of the image display based on a first image, the processor receives an image display instruction, which is used to instruct the display of a second image; the first target bit is a first bit in a bit plane corresponding to the image display, the image display includes N liquid crystal units, each of the N liquid crystal units corresponds to M first bits, the image display corresponds to M bit planes, and each bit plane includes a first bit corresponding to each liquid crystal unit; N and M are both integers greater than 0; the processor sets the value of a second target bit of the image display based on the second image, the second target bit is a first bit in the M bit planes corresponding to the image display other than the first target bit, and the value of the second target bit is not set by the first image.

[0007] In the above method, if a second image needs to be displayed as soon as possible while the image display is displaying the first image, there is no need to wait for the image display to fully display the first image before displaying the second image. Instead, the second image is used to set the value of the first bit that was not set by the first image, which helps to improve the efficiency of the image display switching from the first image to the second image.

[0008] In one possible design, the M bit planes have a first setting order, and the first bit in each bit plane has a second setting order. After setting the value of the first target bit of the image display based on the first image, the processor receives an image display instruction, which may include: the processor setting the M bit planes based on the first image and in the first setting order, and setting the first bit in each bit plane in the second setting order; after setting the value of the i-th first bit in the x-th bit plane corresponding to the image display based on the first image, the processor receives an image display instruction; wherein, the first target bit includes all the first bits in the bit planes before the x-th bit plane in the first setting order, the first bit in the second setting order before the i-th first bit in the x-th bit plane, and the i-th first bit in the x-th bit plane, where x is any integer between [1, M] and i is any integer between [1, N]. With this design, after receiving the second image, the processor can directly use the second image to set the bit value of the first bit that was not set by the first image on the image display, which helps to improve the efficiency of the image display switching from the first image to the second image for display.

[0009] In one possible design, the second target bit includes all the first bits in the bit planes following the x-th bit plane in the first setting order, and the first bit in the second setting order following the i-th first bit in the x-th bit plane. This design provides a method for determining the second target bit.

[0010] In one possible design, a pixel value in the second image corresponds to M second bits, and a pixel value is determined based on the values ​​of the M second bits. The processor sets the value of the second target bit of the image display based on the second image, which may include: setting the value of the second target bit of the image display based on the value of the second bit corresponding to the pixel value in the second image.

[0011] In one possible design, the above method may further include: the processor setting the value of a first bit of the image display based on the second image. With this design, the processor can quickly display the second image on the image display.

[0012] Secondly, embodiments of this application also provide an image refreshing device, which includes the method provided in the first aspect above.

[0013] Thirdly, embodiments of this application also provide an image refresh device, which includes a memory and a processor, wherein the memory is used to store a computer program, and the processor is used to call the computer program and execute the method provided in the first aspect above.

[0014] Fourthly, embodiments of this application also provide a computing device, which includes a processor and a memory, wherein the processor of the computing device is used to execute instructions stored in the memory of the computing device to cause the computing device to perform the method provided in the first aspect above.

[0015] Fifthly, embodiments of this application also provide a computer program product containing instructions that, when executed by a computing device, cause the computing device to perform the method provided in the first aspect above.

[0016] In a sixth aspect, embodiments of this application also provide a computer-readable storage medium including computer program instructions, which, when executed by a computing device, enable the computing device to perform the method provided in the first aspect above.

[0017] In a seventh aspect, embodiments of this application also provide a chip containing instructions that, when executed by a computing device, cause the computing device to perform the method provided in the first aspect above.

[0018] Eighthly, embodiments of this application provide a chip system containing instructions that, when executed by a computing device, cause the computing device to perform the method provided in the first aspect above. This chip system may be composed of chips or may include chips and other discrete devices. Attached Figure Description

[0019] Figure 1 is a schematic diagram of a wavelength selective switching device provided in an embodiment of this application;

[0020] Figure 2A is a schematic diagram of a light spot array provided in an embodiment of this application;

[0021] Figure 2B is a structural schematic diagram of an image A provided in an embodiment of this application;

[0022] Figure 2C is a structural schematic diagram of image B provided in an embodiment of this application;

[0023] Figure 2D is a schematic diagram of a process for updating a light spot array according to an embodiment of this application;

[0024] Figure 3 is a structural schematic diagram of an arrangement of N liquid crystal cells provided in an embodiment of this application;

[0025] Figure 4 is a schematic diagram of a bit plane structure provided in an embodiment of this application;

[0026] Figure 5 is a flowchart illustrating an image refresh method provided in an embodiment of this application;

[0027] Figure 6 is a flowchart illustrating a refreshed liquid crystal unit according to an embodiment of this application;

[0028] Figure 7 is a flowchart illustrating an image refresh method provided in an embodiment of this application;

[0029] Figure 8 is a schematic diagram of the structure of an image display provided in an embodiment of this application;

[0030] Figure 9A is a flowchart illustrating a refreshed liquid crystal unit according to an embodiment of this application;

[0031] Figure 9B is a flowchart illustrating a refreshed liquid crystal unit according to an embodiment of this application;

[0032] Figure 10 is a flowchart illustrating an image refresh method provided in an embodiment of this application;

[0033] Figure 11 is a flowchart illustrating a refreshed liquid crystal unit according to an embodiment of this application;

[0034] Figure 12 is a flowchart illustrating an image refresh method provided in an embodiment of this application;

[0035] Figure 13 is a flowchart illustrating a refreshed liquid crystal unit according to an embodiment of this application;

[0036] Figure 14 is a schematic diagram of an image refresh device provided in an embodiment of this application. Detailed Implementation

[0037] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. The terms "first," "second," and corresponding reference numerals in the specification, claims, and drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such terms can be used interchangeably where appropriate; this is merely a way of distinguishing objects with the same attributes in the embodiments of this application. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion, so that a process, method, system, product, or apparatus that comprises a series of units is not necessarily limited to those units, but may include other units not explicitly listed or inherent to these processes, methods, products, or apparatuses.

[0038] In one possible application scenario, as shown in Figure 1, a wavelength selective switch (WSS) device includes at least S1 input ports, a first beam-splitting grating, a first-stage liquid crystal on silicon (LCOS), a second-stage LCOS, a second beam-splitting grating, and S2 output ports, where S1 and S2 are both integers greater than 0. Through the WSS device, arbitrary pairing of input and output ports can be achieved for all-optical connections; that is, for any wavelength optical signal from the S1 input ports, it can be output from any one of the S2 output ports.

[0039] It should be understood that the first beam splitter and the second beam splitter can be two separate devices in the WSS device, or they can be combined into a single device depending on different optical designs; this is not limited here. The first-stage LCOS and the second-stage LCOS can independently deflect the beam. For example, the first-stage LCOS can independently deflect the beam from different input ports, and the second-stage LCOS can independently deflect the beam from different output ports.

[0040] In the WSS device shown in Figure 1, if each input port supports W wavelength channels, an S1*W spot array can be formed, which is the LCOS image of the WSS device. When the output port of the WSS device is switched, the LCOS image will also change accordingly.

[0041] Specifically, for any wavelength of optical signal from any input port of the WSS device, different LCOS images can be displayed depending on whether the optical signal is output from different output ports. For example, when an optical signal with wavelength λ from the s1st input port of the WSS device is output from the s2-1st output port, the LCOS image displayed by the optical signal with wavelength λ from the s1st input port is image A. When the optical signal with wavelength λ from the s1st input port is switched to the s2-2nd output port, the LCOS image displayed by the optical signal with wavelength λ from the s1st input port is image B. Here, the s1st input port is any input port of the WSS device, the s2-1st and s2-2nd output ports are any two different output ports of the WSS device, and λ is any one of the W wavelengths supported by the s1st input port.

[0042] When the optical signal with wavelength λ is output from the (s2-1)th output port, the displayed LCOS image is image A. This means the WSS device needs to sequentially update each spot in the S1*W spot array to make the LCOS image image A. During the update process of the S1*W1 spot array, the optical signal with wavelength λ switches to the (s2-2)th output port, and the WSS device needs to sequentially update each spot in the S1*W spot array to make the LCOS image image B. Currently, after the S1*W spot array is updated to image A according to the LCOS image, it is then updated to image B according to the LCOS image.

[0043] For example, as shown in Figure 2A, the light spot array is 2*2 in size. For ease of description later, the coordinates of each light spot in the light spot matrix are (1,1), (1,2), (2,1), and (2,2), respectively. When the WSS device determines that the light signal with wavelength λ is output from the (s2-1)th output port, the light spot array should display image A. Image A can be seen in Figure 2B, where the pixel values ​​of each pixel in image A are A1, A2, A3, and A4, respectively. When the light spot array is updated to coordinates (1,2) according to image A, the WSS device determines that the light signal with wavelength λ is switched to the (s2-2)th output port. At this time, the WSS device needs to update the light spot array according to image A, and then update it according to image B. Image B can be seen in Figure 2C, where the pixel values ​​of each pixel in image B are B1, B2, B3, and B4, respectively.

[0044] The specific update process can be seen in Figure 2D. After the WSS device determines that the spot array should display image A, it updates the spot at coordinate (1,1) to A1, and then updates the spot at coordinate (1,2) to A2. While updating the spot at coordinate (1,2), the WSS device determines that the spot array should display image B. Then, the WSS device updates the spot at coordinate (2,1) to A3 and the spot at coordinate (2,2) to A4. At this point, the spot array has completed the display of image A. Next, the WSS device updates the spot at coordinate (1,1) to B1, the spot at coordinate (1,2) to B2, the spot at coordinate (2,1) to B3, and the spot at coordinate (2,2) to B4. At this point, the spot array has completed the display of image B.

[0045] As can be seen from the above update process of the light spot matrix, if there is an image B that needs to be displayed as soon as possible during the process of displaying image A by the light spot array, then image B needs to be displayed after the light spot array has fully displayed image A. Therefore, the process of switching image A to image B for display will take a lot of time. How the WSS device can quickly switch from image A to image B for display is a technical problem that urgently needs to be solved.

[0046] In another possible application scenario, the monitor can refresh the image at a fixed refresh rate. For example, in a game, the monitor can display image A based on the user's current mouse position. While image A is being displayed, if the user quickly moves the mouse, the monitor needs to display image B based on the changed mouse position. Currently, the monitor displays image A first, and then image B. The specific update process can be seen in Figure 2D, and will not be elaborated here.

[0047] In this embodiment, the display can be a twisted nematic (TN) liquid crystal display, a super twisted nematic (STN) liquid crystal display, a dual-scan tortuosity nomograph (DSTN) liquid crystal display, a thin film transistor (TFT) liquid crystal display, an organic light-emitting diode (OLED) display, etc., and is not limited thereto.

[0048] As can be seen from the above display process, if there is an image B that needs to be displayed as soon as possible while the monitor is displaying image A, then the monitor needs to display image A completely before displaying image B. Therefore, the process of switching from image A to image B will take a lot of time, which will cause serious lag in game scenes. How to quickly switch the monitor from image A to image B is a technical problem that urgently needs to be solved.

[0049] In order to solve the technical problem of quickly switching from image A to image B for display in WSS devices / displays, this application provides an image refresh method and apparatus.

[0050] Based on the WSS device shown in Figure 1 and the display described above, this application provides an image refresh method. This image refresh method can be applied to the refresh of liquid crystal cells in an image display. The image display can be an S1*W light spot array in the WSS device, or it can be the display described above, without limitation. The image display includes N liquid crystal cells, where N is an integer greater than 0. The arrangement of the N liquid crystal cells can be in the S1*W matrix form shown in Figure 3, i.e., N = S1*W.

[0051] In this embodiment of the application, each of the N liquid crystal cells is set to correspond to M first bits, and the grayscale value of each liquid crystal cell is determined according to the bit values ​​of the M first bits corresponding to each liquid crystal cell, where M is an integer greater than 0.

[0052] For any liquid crystal cell among N liquid crystal cells, the M first bits corresponding to that liquid crystal cell form a high-low bit sequence. This high-low bit sequence includes the sequence numbers corresponding to the M first bits, each with a different sequence number. For example, referring to the image display shown in Figure 2A, the liquid crystal cell at coordinate (1,2) corresponds to four first bits, namely 1-1, 1-2, 1-3, and 1-4. The sequence number corresponding to first bit 1-1 is 1, first bit 1-2 is 2, first bit 1-3 is 3, and first bit 1-4 is 4. Therefore, the high-low bit sequence corresponding to the four first bits (i.e., 1-1, 1-2, 1-3, and 1-4) of the liquid crystal cell at coordinate (1,2) is 1234.

[0053] It should be understood that the high and low bit sequences corresponding to the M first bits of each liquid crystal cell can be directly set in each of the first bits of the liquid crystal cell, or other setting methods can be used, which are not limited here.

[0054] Generally speaking, the first bit with the same serial number corresponding to each of the N liquid crystal cells can form a bit plane (BP). Therefore, the M first bits corresponding to each of the N liquid crystal cells can form M bit planes, and each bit plane includes N first bits.

[0055] For example, an image display includes 2*2 liquid crystal units. The coordinates of each liquid crystal unit in the image display can be seen with reference to Figure 2A, which are (1,1), (1,2), (2,1), and (2,2) respectively. As shown in Figure 4, each liquid crystal unit is assigned 4 first bits. Specifically, the 4 first bits corresponding to the liquid crystal unit at coordinate (1,1) are 1-1, 1-2, 1-3, and 1-4 respectively, and the corresponding numbers are 1, 2, 3, and 4 respectively; the 4 first bits corresponding to the liquid crystal unit at coordinate (1,2) are 2-1, 2-2, 2-3, and 2-4 respectively, and the corresponding numbers are 1, 2, 3, and 4 respectively. 4; The four first bits corresponding to the liquid crystal cell at coordinate (2,1) are 3-1, 3-2, 3-3 and 3-4 respectively, and the serial numbers corresponding to these four first bits (i.e. 3-1, 3-2, 3-3 and 3-4) are 1, 2, 3 and 4 respectively; The four first bits corresponding to the liquid crystal cell at coordinate (2,2) are 4-1, 4-2, 4-3 and 4-4 respectively, and the serial numbers corresponding to these four first bits (i.e. 4-1, 4-2, 4-3 and 4-4) are 1, 2, 3 and 4 respectively.

[0056] As shown in Figure 4, the first bit of each liquid crystal cell, numbered 1, can form a bit plane, namely, bits 1-1, 2-1, 3-1, and 4-1, which is denoted as bit plane 1. The first bit of each liquid crystal cell, numbered 2, can form a bit plane, namely, bits 1-2, 2-2, 3-2, and 4-2, which is denoted as bit plane 2. The first bit of each liquid crystal cell, numbered 3, can form a bit plane, namely, bits 1-3, 2-3, 3-3, and 4-3, which is denoted as bit plane 3. The first bit of each liquid crystal cell, numbered 4, can form a bit plane, namely, bits 1-4, 2-4, 3-4, and 4-4, which is denoted as bit plane 4. Therefore, this image display corresponds to 4 bit planes.

[0057] The process of displaying an image on the image display involves setting the values ​​of the first bits in the M bit planes corresponding to the image display based on the image. During this process, the M bit planes have a setting order; that is, based on the image (such as pixel values ​​in the image), the values ​​of the first bits in each of the M bit planes are set sequentially according to the setting order. For ease of explanation, this setting order of the M bit planes is referred to as the first setting order. Specifically, for any one of the M bit planes, this bit plane includes N first bits, and these N first bits have a setting order. When setting the first bits in this bit plane, based on the image, the values ​​of each first bit in this bit plane are set sequentially according to the setting order of the N first bits. For ease of explanation, this setting order of the N first bits is referred to as the second setting order.

[0058] The embodiments of this application do not limit the specific content of the first setting order and the second setting order, and the second setting order of N first bits in different bit planes may be the same or different, which is not limited here. For ease of explanation later, the second setting order of N first bits in different bit planes is the same.

[0059] In one possible implementation, the first setting order can be determined based on the index of the first bit in the M bit planes. For example, the first setting order can be the ascending order of the indexes of the first bits in the M bit planes. For instance, referring to Figure 4, the index of the first bit in bit plane 1 is 1, the index of the first bit in bit plane 2 is 2, the index of the first bit in bit plane 3 is 3, and the index of the first bit in bit plane 4 is 4. Therefore, the first setting order can be bit plane 1, bit plane 2, bit plane 3, and bit plane 4. According to this first setting order, bit plane 1 can also be called the first bit plane, bit plane 2 can also be called the second bit plane, bit plane 3 can also be called the third bit plane, and bit plane 4 can also be called the fourth bit plane.

[0060] In one possible implementation, the second setting order can be determined based on the positional relationship of N first bits in a bit plane. For example, the second setting order is: for first bits with different row coordinates, the first bit with the smaller row coordinate is updated first; for first bits with different column coordinates, the first bit with the smaller column coordinate is updated first. For instance, referring to Figure 4, bit plane 1 includes four first bits, namely first bits 1-1, 2-1, 3-1, and 4-1. The second setting order of these four first bits can be first bit 1-1, first bit 2-1, first bit 3-1, and first bit 4-1. According to this second setting order, first bit 1-1 can also be called the first first bit, first bit 2-1 can also be called the second first bit, first bit 3-1 can also be called the third first bit, and first bit 4-1 can also be called the fourth first bit.

[0061] It should be understood that the "xth" bit plane mentioned later in this application is configured based on the first configuration order. The "ith" first bit is configured based on the second configuration order, which will not be elaborated hereafter.

[0062] Based on the image display described above, embodiments of this application provide a method for refreshing an image display using any image. This method can be executed by a processor in the image display, a module in the processor, or a chip in the processor, and is not limited thereto. For ease of description, the processor in the image display will be used as the execution entity below.

[0063] In this embodiment of the application, the processor may use a first image to refresh the image display, wherein the first image includes N pixel values, the length and width of the first image may be S1 and W respectively, and the size of the first image may be S1*W, that is, N=S1*W.

[0064] In the first image, each pixel value corresponds to M third bits, and each pixel value is determined based on the values ​​of these M third bits. For example, if each pixel value in the first image is determined by the values ​​of four third bits (1, 0, 0, 1), then the corresponding pixel value is 1001. Each pixel value in the first image corresponds to a high-low bit sequence, which includes the indices of the M third bits, each with a different indice. For example, if a pixel value has four third bits with values ​​of 1, 0, 0, 1, then the indices of these four third bits are 1, 2, 3, and 4, respectively, meaning the high-low bit sequence is 1234.

[0065] It should be understood that the "xth" third bit mentioned later in this application is determined based on the first setting order to determine the order of the third bit.

[0066] In one possible implementation, after determining that the first image is used to refresh the image display, the processor can set the values ​​of the first bits in the M bit planes corresponding to the image display using the N pixel values ​​in the first image. That is, the processor can set the M bit planes corresponding to the image display based on the N pixel values ​​in the first image in a first setting order, and set the first bits in each bit plane in a second setting order. Specifically, the processor sets the M bit planes according to the first setting order based on the values ​​of the M third bits corresponding to the N pixel values ​​in the first image, and sets the first bits in the x-th bit plane according to the second setting order based on the values ​​of the x-th third bits corresponding to the N pixel values ​​in the first image. Here, the x-th bit plane is the setting order of the bit plane determined based on the first setting order, x is any integer between [1, M], and the index of the x-th third bit is the same as the index of the first bit in the x-th bit plane. The processor repeats the above process until the first image is displayed on the image display. For specific implementation, please refer to the steps shown in Figure 5.

[0067] S501, the processor sets variable z = 1.

[0068] S502, the processor sets variable k=1.

[0069] In S503, the processor determines whether z is greater than M. If not, it jumps to S504; if so, it ends, meaning that S504 to S508 are no longer executed.

[0070] In S504, the processor determines whether k is greater than N. If not, it jumps to S505; if so, it jumps to S508.

[0071] S505, the processor determines the value of the third bit corresponding to the k-th pixel value in the first image.

[0072] S506, the processor sets the value of the kth first bit in the zth bit plane corresponding to the image display based on the value of the zth third bit corresponding to the kth pixel value.

[0073] In the embodiment of the application, the processor directly sets the value of the kth first bit in the zth bit plane corresponding to the image display to the value of the zth third bit corresponding to the kth pixel value. Here, the kth first bit is the first bit located in the zth bit plane of the kth liquid crystal cell.

[0074] In S507, the processor sets k++, then jumps to S504. Here, k++ can be understood as k incrementing by 1.

[0075] In S508, the processor sets z++, then jumps to S502. Here, z++ can be understood as z incrementing by 1.

[0076] The steps shown in Figure 5 above provide a method for quickly displaying a first image on an image display.

[0077] For example, as shown in Figure 6, after the processor determines that image A should be displayed, image A includes four pixel values, namely A1, A2, A3, and A4. The values ​​of the four third bits corresponding to A1 are A1-1, A1-2, A1-3, and A1-4, respectively; the values ​​of the four third bits corresponding to A2 are A2-1, A2-2, A2-3, and A2-4, respectively; the values ​​of the four third bits corresponding to A3 are A3-1, A3-2, A3-3, and A3-4, respectively; and the values ​​of the four third bits corresponding to A4 are A4-1, A4-2, A4-3, and A4-4, respectively.

[0078] The processor first sets the value of the first bit in the first bit plane corresponding to the image display. Specifically, the processor first sets the bit value of the first bit in the first bit plane of the liquid crystal cell at coordinate (1,1) to A1-1, then sets the bit value of the first bit in the first bit plane of the liquid crystal cell at coordinate (1,2) to A2-1, then sets the bit value of the first bit in the first bit plane of the liquid crystal cell at coordinate (2,1) to A3-1, and then sets the bit value of the first bit in the first bit plane of the liquid crystal cell at coordinate (2,2) to A4-1.

[0079] Then, the processor sets the value of the first bit in the second bit plane corresponding to the image display. The process of setting the value of the first bit in the second bit plane can refer to the process of setting the value of the first bit in the first bit plane, and will not be described in detail here.

[0080] Then, the processor sets the value of the first bit in the third bit plane corresponding to the image display. The process of setting the value of the first bit in the third bit plane can refer to the process of setting the value of the first bit in the first bit plane, and will not be repeated here.

[0081] Finally, the processor sets the value of the first bit in the fourth bit plane corresponding to the image display. The process of setting the value of the first bit in the fourth bit plane can refer to the process of setting the value of the first bit in the first bit plane, and will not be repeated here.

[0082] Example 1

[0083] If a second image needs to be displayed as soon as possible while the image display is showing the first image, the image display can quickly switch from the first image to the second image for display, which may include the following steps as shown in Figure 7.

[0084] S701, after setting the value of the first target bit of the image display based on the first image, the processor receives the image display instruction. The first target bit is the first bit in the bit plane corresponding to the image display.

[0085] In Embodiment 1, when the processor receives an image display instruction, the processor may also receive a second image, wherein the second image is different from the first image, and the image display instruction is used to instruct the display of the second image.

[0086] It should be understood that when the image display instruction includes a second image, the processor can obtain the second image from the image display instruction; when the image display instruction does not include a second image, the processor can obtain the second image in other ways, which will not be elaborated here.

[0087] In Embodiment 1, the second image includes N pixel values. The length and width of the second image can be S1 and W, respectively, and the size of the second image can be S1*W, i.e., N = S1*W.

[0088] In the second image, each pixel value corresponds to M second bits, and each pixel value is determined by the values ​​of these M second bits. For example, if each pixel value in the second image is determined by the values ​​of four second bits (1, 0, 0, 1), then the corresponding pixel value is 1001. The M second bits corresponding to each pixel value in the second image form a high-low bit sequence, which includes the indices of the M second bits, each with a different indice. For example, if the values ​​of the four second bits are 1, 0, 0, 1, then the indices are 1, 2, 3, and 4, respectively, meaning the high-low bit sequence is 1234.

[0089] It should be understood that the "xth" second bit mentioned later in this application is determined based on the first setting order to determine the order of the second bit.

[0090] In Embodiment 1, the processor can receive an image display instruction through the following implementation: after setting the value of the i-th first bit in the x-th bit plane corresponding to the image display based on the first image, the processor receives the image display instruction; wherein, the first target bit includes all the first bits in the bit planes before the x-th bit plane in the first setting order, the first bit in the second setting order within the x-th bit plane before the i-th first bit, and the i-th first bit in the x-th bit plane, where x is any integer between [1, M] and i is any integer between [1, N].

[0091] It should be understood that all first bits in the bit plane preceding the x-th bit plane in the first setting order can be understood as all first bits from the 1st bit plane to the (x-1)th bit plane; the first bit in the second setting order within the x-th bit plane preceding the ith first bit can be understood as the 1st first bit to the (i-1)th first bit in the x-th bit plane.

[0092] For example, as shown in Figure 8, after the processor determines that image A should be displayed, image A can be understood as the first image. Image A includes four pixel values, namely A1, A2, A3, and A4. The values ​​of the four third bits corresponding to A1 are A1-1, A1-2, A1-3, and A1-4, respectively; the values ​​of the four third bits corresponding to A2 are A2-1, A2-2, A2-3, and A2-4, respectively; the values ​​of the four third bits corresponding to A3 are A3-1, A3-2, A3-3, and A3-4, respectively; and the values ​​of the four third bits corresponding to A4 are A4-1, A4-2, A4-3, and A4-4, respectively.

[0093] After setting the value of the second first bit in the second bit plane corresponding to the image display based on image A, the processor receives the image display instruction. Specifically, the values ​​of all first bits in the first bit plane are set by image A; that is, the values ​​of first bits 1-1, 2-1, 3-1, and 4-1 in the first bit plane are set to A1-1, A2-1, A3-1, and A4-1, respectively. The values ​​of the first first bits 1-2 and 2-2 in the second bit plane are set to A1-2 and A2-2, respectively.

[0094] S702, the processor sets the value of the second target bit of the image display based on the second image. The second target bit is the first bit in the M bit planes corresponding to the image display, excluding the first target bit, and its value has not been set by the first image.

[0095] In Embodiment 1, after setting the value of the i-th first bit in the x-th bit plane corresponding to the image display based on the first image, the processor receives an image display instruction; wherein, the first target bit includes all the first bits in the bit plane before the x-th bit plane in the first setting order, the first bit in the second setting order within the x-th bit plane before the i-th first bit, and the i-th first bit in the x-th bit plane, where x is any integer between [1, M] and i is any integer between [1, N]; the second target bit includes all the first bits in the bit plane after the x-th bit plane in the first setting order, and the first bit in the second setting order within the x-th bit plane after the i-th first bit.

[0096] It should be understood that all first bits in the bit planes following the xth bit plane in the first setting order can be understood as all first bits from the (x+1)th bit plane to the Mth bit plane; the first bit in the second setting order within the xth bit plane following the ith first bit can be understood as the ith first bit to the Nth first bit in the xth bit plane.

[0097] In this embodiment, the processor can set the value of the second target bit of the image display based on the value of the second bit corresponding to the pixel value in the second image. Specifically, the processor can set the second target bit based on the values ​​of the second bits corresponding to the N pixel values ​​in the second image, combined with a first setting order and a second setting order. More specifically, the processor can set the xth to Mth bit planes according to the first setting order, based on the values ​​of the xth to Mth second bits corresponding to the N pixel values ​​in the second image. For any bit plane among the xth to Mth bit planes, taking the xth bit plane as an example, the processor can set the second target bit in the xth bit plane according to the second setting order, based on the values ​​of the xth third bits corresponding to the N pixel values ​​in the second image.

[0098] The following details how the processor sets the value of the second target bit of the image display based on the second image, for different ranges of i, including Case 1 and Case 2.

[0099] In the first case, when i is any integer between [1, N-1], the second target bit includes all the first bits in the bit plane after the x-th bit plane in the first setting order, and the i-th to N-th first bits in the second setting order in the x-th bit plane.

[0100] For example, as shown in Figure 9A, during the display of image A, when the processor uses the value A2-1 of the first third bit corresponding to the pixel value at coordinate (1,2) in image A to set the value of the first bit in the first bit plane of the liquid crystal unit at coordinate (1,2) in the image display, the processor acquires image B. Then, the processor uses the value B3-1 of the first second bit corresponding to the pixel value at coordinate (2,1) in image B to set the value of the first bit in the first bit plane of the liquid crystal unit at coordinate (2,1) in the image display. The processor then uses the value B4-1 of the first second bit corresponding to the pixel value at coordinate (2,2) in image B to set the value of the first bit in the first bit plane of the liquid crystal unit at coordinate (2,2) in the image display.

[0101] Next, the processor uses the value B1-2 of the second bit corresponding to the pixel value at coordinate (1,1) in image B to set the value of the first bit in the second bit plane of the liquid crystal unit at coordinate (1,1) in the image display. The processor uses the value B2-2 of the second bit corresponding to the pixel value at coordinate (1,2) in image B to set the value of the first bit in the second bit plane of the liquid crystal unit at coordinate (1,2) in the image display. The processor uses the value B3-2 of the second bit corresponding to the pixel value at coordinate (2,1) in image B to set the value of the first bit in the second bit plane of the liquid crystal unit at coordinate (2,1) in the image display. The processor uses the value B4-2 of the second bit corresponding to the pixel value at coordinate (2,2) in image B to set the value of the first bit in the second bit plane of the liquid crystal unit at coordinate (2,2) in the image display.

[0102] Then, the processor sets the value of the first bit in the third bit plane corresponding to the image display. The process of setting the value of the first bit in the third bit plane can refer to the process of setting the value of the first bit in the second bit plane, and will not be described in detail here.

[0103] Finally, the processor sets the value of the first bit in the fourth bit plane corresponding to the image display. The process of setting the value of the first bit in the fourth bit plane can refer to the process of setting the value of the first bit in the second bit plane, and will not be repeated here.

[0104] In the second scenario, when i is N, the second target bit includes all the first bits in the bit plane following the xth bit plane in the first setting order.

[0105] For example, as shown in Figure 9B, when the processor is displaying image A, it uses the value A4-1 of the third bit corresponding to the first bit of the pixel value at coordinate (2,2) in image A to set the value of the first bit in the first bit plane of the liquid crystal cell at coordinate (2,2) in the image display, and then the processor acquires image B.

[0106] Next, the processor uses the value B1-2 of the second bit corresponding to the pixel value at coordinate (1,1) in image B to set the value of the first bit in the second bit plane of the liquid crystal unit at coordinate (1,1) in the image display. The processor uses the value B2-2 of the second bit corresponding to the pixel value at coordinate (1,2) in image B to set the value of the first bit in the second bit plane of the liquid crystal unit at coordinate (1,2) in the image display. The processor uses the value B3-2 of the second bit corresponding to the pixel value at coordinate (2,1) in image B to set the value of the first bit in the second bit plane of the liquid crystal unit at coordinate (2,1) in the image display. The processor uses the value B4-2 of the second bit corresponding to the pixel value at coordinate (2,2) in image B to set the value of the first bit in the second bit plane of the liquid crystal unit at coordinate (2,2) in the image display.

[0107] Then, the processor sets the value of the first bit in the third bit plane corresponding to the image display. The process of setting the value of the first bit in the third bit plane can refer to the process of setting the value of the first bit in the second bit plane, and will not be described in detail here.

[0108] Finally, the processor sets the value of the first bit in the fourth bit plane corresponding to the image display. The process of setting the value of the first bit in the fourth bit plane can refer to the process of setting the value of the first bit in the second bit plane, and will not be repeated here.

[0109] Optionally, the method shown in Figure 7 above may also include S703.

[0110] S703, the processor sets the value of the first bit of the image display based on the second image.

[0111] In the above S703, the processor uses the second image to sequentially set the value of the first bit in the M bit planes corresponding to the image display. This can be done by referring to the steps shown in Figure 5, which will not be repeated here.

[0112] In the steps shown in Figure 7, if there is a second image that needs to be displayed as soon as possible while the image display is displaying the first image, there is no need to wait for the image display to fully display the first image before displaying the second image. Instead, the second image is used directly to set the value of the first bit that was not set by the first image, which helps to improve the efficiency of the image display switching from the first image to the second image.

[0113]

Example 2

[0114] If a second image needs to be displayed as soon as possible while the image display is showing the first image, the image display can quickly switch from the first image to the second image for display, which may include the following steps as shown in Figure 10.

[0115] S1001, after setting the value of the first target bit of the image display based on the first image, the processor receives the image display instruction. The first target bit is the first bit in the bit plane corresponding to the image display.

[0116] The image display instructions in Embodiment 2 can refer to the image display instructions in Embodiment 1, and will not be repeated here.

[0117] In Embodiment 2, the values ​​of the first target bits of the image display are all set by the first image, and the first bits of the image display, except for the first target bits, are not set by the first image.

[0118] The implementation method for the processor to receive image display instructions can refer to the implementation method in Embodiment 1, and will not be repeated here.

[0119] S1002, the processor sets the value of the first bit of the image display based on the second image.

[0120] In Embodiment 2, the processor sets all the first bits in the M bit planes corresponding to the image display based on the values ​​of the second bits corresponding to the N pixel values ​​in the second image, combined with the first setting order and the second setting order.

[0121] For example, as shown in Figure 11, when the processor is displaying image A, it uses the value A2-1 of the third bit corresponding to the first bit of the pixel value at coordinate (1,2) in image A to set the value of the first bit in the first bit plane of the liquid crystal cell at coordinate (1,2) in the image display, and then the processor acquires image B.

[0122] Next, the processor refreshes the value of the first bit in the first bit plane of each liquid crystal cell using image B. Specifically, the processor uses the value B1-1 of the first second bit corresponding to the pixel value at coordinate (1,1) in image B to set the value of the first bit in the first bit plane of the liquid crystal cell at coordinate (1,1) in the image display. The processor uses the value B2-1 of the first second bit corresponding to the pixel value at coordinate (1,2) in image B to set the value of the first bit in the first bit plane of the liquid crystal cell at coordinate (1,2) in the image display. The processor uses the value B3-1 of the first second bit corresponding to the pixel value at coordinate (2,1) in image B to set the value of the first bit in the first bit plane of the liquid crystal cell at coordinate (2,1) in the image display. The processor uses the value B4-1 of the first second bit corresponding to the pixel value at coordinate (2,2) in image B to set the value of the first bit in the first bit plane of the liquid crystal unit at coordinate (2,2) in the image display.

[0123] Then, the processor sets the value of the first bit in the second bit plane corresponding to the image display. The process of setting the value of the first bit in the third bit plane can refer to the process of setting the value of the first bit in the first bit plane, and will not be described in detail here.

[0124] Then, the processor sets the value of the first bit in the third bit plane corresponding to the image display. The process of setting the value of the first bit in the third bit plane can refer to the process of setting the value of the first bit in the first bit plane, and will not be repeated here.

[0125] Finally, the processor sets the value of the first bit in the fourth bit plane corresponding to the image display. The process of setting the value of the first bit in the fourth bit plane can refer to the process of setting the value of the first bit in the first bit plane, and will not be repeated here.

[0126] In the steps shown in Figure 10, if there is a second image that needs to be displayed as soon as possible while the image display is displaying the first image, there is no need to wait for the image display to fully display the first image before displaying the second image. Instead, the second image is directly used to refresh the display starting from the value of the first bit in the first bit plane corresponding to the image display. This helps to improve the efficiency of the image display in switching from the first image to the second image.

[0127]

Example 3

[0128] If a second image needs to be displayed as soon as possible while the image display is showing the first image, the image display can quickly switch from the first image to the second image for display, which may include the following steps as shown in Figure 12.

[0129] S1201, after setting the value of the first target bit of the image display based on the first image, the processor receives the image display instruction. The first target bit is the first bit in the bit plane corresponding to the image display.

[0130] The image display instructions in Embodiment 3 can refer to the image display instructions in Embodiment 1, and will not be repeated here.

[0131] In Embodiment 3, the values ​​of the first target bits of the image display are all set by the first image, and the first bits of the image display, except for the first target bits, are not set by the first image.

[0132] The implementation method for the processor to receive image display instructions can refer to the implementation method in Embodiment 1, and will not be repeated here.

[0133] S1202, the processor sets the value of the second target bit of the image display based on the second image. The second target bit includes the first bit (excluding the first target bit) and at least one first target bit in the M bit planes corresponding to the image display.

[0134] In Embodiment 3, after setting the value of the i-th first bit in the x-th bit plane corresponding to the image display based on the first image, the processor receives an image display instruction; wherein, the first target bit includes all the first bits in the bit plane before the x-th bit plane in the first setting order, the first bit in the second setting order within the x-th bit plane before the i-th first bit, and the i-th first bit in the x-th bit plane, where x is any integer between [1, M] and i is any integer between [1, N]; the second target bit includes all the first bits in the x-th bit plane in the first setting order and in the bit plane after the x-th bit plane.

[0135] It should be understood that all first bits in the bit planes preceding the x-th bit plane in the first setting order can be understood as all first bits from the 1st bit plane to the (x-1th)th bit plane; the first bits in the second setting order within the x-th bit plane preceding the ith first bit can be understood as the 1st first bit to the (i-1th)th first bit in the x-th bit plane. All first bits in the bit planes following the x-th bit plane in the first setting order can be understood as all first bits from the (x+1th)th bit plane to the Mth bit plane.

[0136] For example, as shown in Figure 13, when the processor is displaying image A, it uses the value A2-2 of the second third bit corresponding to the pixel value at coordinate (1,2) in image A to set the value of the first bit in the second bit plane of the liquid crystal cell at coordinate (1,2) in the image display, and then the processor acquires image B.

[0137] Next, the processor uses image B to set the value of the first bit in the second bit plane. Specifically, the processor uses the value B1-2 of the second bit corresponding to the pixel value at coordinate (1,1) in image B to set the value of the first bit in the second bit plane of the liquid crystal cell at coordinate (1,1) in the image display. The processor uses the value B2-2 of the second bit corresponding to the pixel value at coordinate (1,2) in image B to set the value of the first bit in the second bit plane of the liquid crystal cell at coordinate (1,2) in the image display. The processor uses the value B3-2 of the second bit corresponding to the pixel value at coordinate (2,1) in image B to set the value of the first bit in the second bit plane of the liquid crystal cell at coordinate (2,1) in the image display. The processor uses the value B4-2 of the second bit corresponding to the pixel value at coordinate (2,2) in image B to set the value of the first bit in the second bit plane of the liquid crystal unit at coordinate (2,2) in the image display.

[0138] Then, the processor sets the value of the first bit in the third bit plane corresponding to the image display. The process of setting the value of the first bit in the third bit plane can refer to the process of setting the value of the first bit in the second bit plane, and will not be described in detail here.

[0139] Finally, the processor sets the value of the first bit in the fourth bit plane corresponding to the image display. The process of setting the value of the first bit in the fourth bit plane can refer to the process of setting the value of the first bit in the second bit plane, and will not be repeated here.

[0140] Optionally, the method shown in Figure 12 may also include S1203.

[0141] S1203, the processor sets the value of the first bit of the image display based on the second image.

[0142] In the above S1203, the processor uses the second image to sequentially set the value of the first bit in the M bit planes corresponding to the image display. This can be done by referring to the steps shown in Figure 5, which are not repeated here.

[0143] In the steps shown in Figure 12, if there is a second image that needs to be displayed as soon as possible while the image display is displaying the first image, there is no need to wait for the image display to fully display the first image before displaying the second image. Instead, the second image is directly used to refresh the bit value of the first bit in the bit plane of the image display that is currently displaying the first image. This helps to improve the efficiency of the image display in switching from the first image to the second image.

[0144] Based on the above embodiments, this application also provides an image refresh device, which is applied to the WSS device shown in FIG1 and the display described above, to implement the image refresh method provided in the embodiments shown in FIG7, FIG10, or FIG12. Referring to FIG14, the image refresh device includes: a receiving module 1401 and a refresh module 1402. Wherein:

[0145] The receiving module 1401 is configured to receive an image display instruction after setting the value of the first target bit of the image display based on the first image. The image display instruction is used to instruct the display of a second image. The first target bit is the first bit in the bit plane corresponding to the image display. The image display includes N liquid crystal units, each of the N liquid crystal units corresponds to M first bits, and the image display corresponds to M bit planes. Each bit plane includes one first bit corresponding to each liquid crystal unit. N and M are both integers greater than 0.

[0146] The refresh module 1402 is used to set the value of the second target bit of the image display based on the second image. The second target bit is the first bit in the M bit planes corresponding to the image display, excluding the first target bit. The value of the second target bit is not set by the first image.

[0147] In one possible implementation, the M bit planes have a first setting order, and the first bit in each bit plane has a second setting order;

[0148] The receiving module 1401 is specifically used for: setting M bit planes based on the first image and in a first setting order, setting the first bit in each bit plane in a second setting order; after setting the value of the i-th first bit in the x-th bit plane corresponding to the image display based on the first image, receiving an image display instruction; the first target bit includes all the first bits in the bit planes before the x-th bit plane in the first setting order, the first bit in the x-th bit plane before the i-th first bit in the second setting order, and the i-th first bit in the x-th bit plane, where x is any integer between [1, M] and i is any integer between [1, N].

[0149] In one possible implementation, the second target bit includes all the first bits in the bit plane following the x-th bit plane in the first setting order, and the first bit in the second setting order following the i-th first bit in the x-th bit plane.

[0150] In one possible implementation, a pixel value in the second image corresponds to M second bits, and a pixel value is determined based on the values ​​of the M second bits.

[0151] The refresh module 1402 is specifically used to: set the value of the second target bit of the image display based on the value of the second bit corresponding to the pixel value in the second image.

[0152] In one possible implementation, the refresh module 1402 is also used to: set the value of the first bit of the image display based on the second image.

[0153] In the embodiments of this application, both the receiving module and the refreshing module can be implemented in software or in hardware. For example, the implementation of the refreshing module will be described below. Similarly, the implementation of the receiving module can refer to the implementation of the refreshing module.

[0154] As an example of a software functional unit, a refresh module may include code running on a compute instance. A compute instance may include at least one of a physical host (computing device), a virtual machine, or a container. Furthermore, the aforementioned compute instance may be one or more. For example, a refresh module may include code running on multiple hosts / virtual machines / containers. It should be noted that the multiple hosts / virtual machines / containers used to run the code may be distributed within the same region or in different regions. Further, the multiple hosts / virtual machines / containers used to run the code may be distributed within the same availability zone (AZ) or in different AZs, each AZ comprising one or more geographically proximate data centers. Typically, a region may include multiple AZs.

[0155] Similarly, multiple hosts / virtual machines / containers used to run this code can be distributed within the same Virtual Private Cloud (VPC) or across multiple VPCs. Typically, a VPC is set up within a region. Communication between two VPCs within the same region, as well as between VPCs in different regions, requires a communication gateway to be set up within each VPC to enable interconnection between VPCs.

[0156] As an example of a hardware functional unit, a refresh module may include at least one computing device, such as a server. Alternatively, a refresh module may also be a device implemented using an application-specific integrated circuit (ASIC) or a programmable logic device (PLD). The PLD can be implemented using a complex programmable logical device (CPLD), a field-programmable gate array (FPGA), generic array logic (GAL), or any combination thereof.

[0157] The refresh module includes multiple computing devices that can be distributed within the same region or in different regions. Similarly, the refresh module includes multiple computing devices that can be distributed within the same Availability Zone (AZ) or in different AZs. Likewise, the refresh module includes multiple computing devices that can be distributed within the same Virtual Private Cloud (VPC) or multiple VPCs. These multiple computing devices can be any combination of computing devices such as servers, ASICs, PLDs, CPLDs, FPGAs, and GALs.

[0158] It should be noted that, in other embodiments, the receiving module is used to receive an image display instruction after setting the value of the first target bit of the image display based on the first image. The image display instruction is used to instruct the display of the second image. The first target bit is the first bit in the bit plane corresponding to the image display. The image display includes N liquid crystal units, each of the N liquid crystal units corresponds to M first bits, and the image display corresponds to M bit planes. Each bit plane includes one first bit corresponding to each liquid crystal unit. N and M are both integers greater than 0. The refresh module is used to set the value of the second target bit of the image display based on the second image. The second target bit is the first bit in the multiple bit planes corresponding to the image display other than the first target bit. The value of the second target bit has not been set by the first image.

[0159] The steps implemented by the receiving module and the refresh module can be specified as needed. By implementing different steps in the image refresh method through the receiving module and the refresh module, the full functionality of the image refresh device can be achieved.

[0160] This application also provides a computing device, which includes a processor and a memory, wherein the processor of the computing device is used to execute instructions stored in the memory of the computing device to cause the computing device to perform an image refresh method.

[0161] This application also provides a computer program product containing instructions. The computer program product may be a software or program product containing instructions, capable of running on a computing system or stored on any usable medium. When the computer program product is run on at least one computing device, it causes the at least one computing device to perform an image refresh method.

[0162] This application also provides a computer-readable storage medium. The computer-readable storage medium can be any available medium that a computing device can store, or a data storage device such as a data center containing one or more available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid-state drive). The computer-readable storage medium includes instructions that instruct a computing device to perform an image refresh method.

[0163] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the protection scope of the technical solutions of the embodiments of the present invention.

[0164] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0165] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to this application. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in one or more blocks of the flowchart illustrations and / or one or more blocks of the block diagrams.

[0166] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means that implement the functions specified in one or more flowcharts and / or one or more block diagrams.

[0167] These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process, such that the instructions, which execute on the computer or other programmable apparatus, provide steps for implementing the functions specified in one or more flowcharts and / or one or more block diagrams.

[0168] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

Claims

1. An image refresh method, characterized in that, include: After setting the value of the first target bit of the image display based on the first image, an image display instruction is received, which is used to instruct the display of the second image; The first target bit is the first bit in the bit plane corresponding to the image display. The image display includes N liquid crystal units, and each of the N liquid crystal units corresponds to M first bits. The image display corresponds to M bit planes, and each bit plane includes one first bit corresponding to each liquid crystal unit. N and M are both integers greater than 0. The value of the second target bit of the image display is set based on the second image. The second target bit is the first bit in the M bit planes corresponding to the image display, excluding the first target bit. The value of the second target bit is not set by the first image.

2. The method as described in claim 1, characterized in that, The M bit planes have a first setting order, and the first bit in each bit plane has a second setting order; After setting the value of the first target bit of the image display based on the first image, receiving the image display instruction includes: Based on the first image, the M bit planes are set according to the first setting order, and the first bit in each bit plane is set according to the second setting order. After setting the value of the i-th first bit in the x-th bit plane corresponding to the image display based on the first image, the image display instruction is received; the first target bit includes all the first bits in the bit planes before the x-th bit plane in the first setting order, the first bit in the second setting order before the i-th first bit in the x-th bit plane, and the i-th first bit in the x-th bit plane, where x is any integer between [1, M] and i is any integer between [1, N].

3. The method as described in claim 2, characterized in that, The second target bit includes all the first bits in the bit planes following the xth bit plane in the first setting order, and the first bit in the second setting order following the i-th first bit in the xth bit plane.

4. The method according to any one of claims 1-3, characterized in that, In the second image, one pixel value corresponds to M second bits, and the pixel value is determined based on the values ​​of the M second bits. The step of setting the value of the second target bit of the image display based on the second image includes: Based on the value of the second bit corresponding to the pixel value in the second image, the value of the second target bit of the image display is set.

5. The method according to any one of claims 1-4, characterized in that, The method further includes: The value of the first bit of the image display is set based on the second image.

6. An image refresh device, characterized in that, include: The receiving module is configured to receive an image display instruction after setting the value of the first target bit of the image display based on the first image. The image display instruction is used to instruct the display of a second image. The first target bit is the first bit in the bit plane corresponding to the image display. The image display includes N liquid crystal units, each of the N liquid crystal units corresponds to M first bits, and the image display corresponds to M bit planes. Each bit plane includes one first bit corresponding to each liquid crystal unit. N and M are both integers greater than 0. The refresh module is used to set the value of the second target bit of the image display based on the second image. The second target bit is the first bit in the M bit planes corresponding to the image display, excluding the first target bit. The value of the second target bit has not been set by the first image.

7. The apparatus as claimed in claim 6, characterized in that, The M bit planes have a first setting order, and the first bit in each bit plane has a second setting order; The receiving module is specifically used for: Based on the first image, the M bit planes are set according to the first setting order, and the first bit in each bit plane is set according to the second setting order. After setting the value of the i-th first bit in the x-th bit plane corresponding to the image display based on the first image, the image display instruction is received; the first target bit includes all the first bits in the bit planes before the x-th bit plane in the first setting order, the first bit in the second setting order before the i-th first bit in the x-th bit plane, and the i-th first bit in the x-th bit plane, where x is any integer between [1, M] and i is any integer between [1, N].

8. The apparatus as claimed in claim 7, characterized in that, The second target bit includes all the first bits in the bit planes following the xth bit plane in the first setting order, and the first bit in the second setting order following the i-th first bit in the xth bit plane.

9. The apparatus as claimed in claim 8, characterized in that, In the second image, one pixel value corresponds to M second bits, and the pixel value is determined based on the values ​​of the M second bits. The refresh module is specifically used for: Based on the value of the second bit corresponding to the pixel value in the second image, the value of the second target bit of the image display is set.

10. The apparatus according to any one of claims 6-9, characterized in that, The refresh module is also used for: The value of the first bit of the image display is set based on the second image.

11. A computing device, characterized in that, The device includes a processor and a memory; the memory stores computer-executable instructions; the processor executes the computer-executable instructions stored in the memory to cause the computing device to perform the method as described in any one of claims 1-5.

12. A computer-readable storage medium, characterized in that, It includes computer program instructions, which, when executed by a computing system, perform the method as described in any one of claims 1-5.

13. A computer program product containing instructions, characterized in that, When the instruction is executed by the computing system, it causes the computing system to perform the method as described in any one of claims 1-5.

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