Shift register unit, shift register and display apparatus

Abstract

A shift register unit, a shift register and a display apparatus. The shift register unit comprises a first transistor (T1) to a ninth transistor (T9), a first capacitor (C1) and a second capacitor (C2), wherein the first transistor (T1) switches a connection relationship between an input voltage signal and a third node (N3), the second transistor (T2) switches a connection relationship between an operating voltage signal (VDD) and the third node (N3), the third transistor (T3) switches a connection relationship between the operating voltage signal (VDD) and a fourth node (N4), the fourth transistor (T4) switches a connection relationship between the fourth node (N4) and a second node (N2), the fifth transistor (T5) switches a connection relationship between a ground signal (VEE) and a first node (N1), the sixth transistor (T6) switches a connection relationship between the second node (N2) and the third node (N3), the seventh transistor (T7) switches a connection relationship between a third clock signal (CKV3) and the first node (N1), the eighth transistor (T8) switches a connection relationship between the operating voltage signal (VDD) and an output voltage signal (Gout), and the ninth transistor (T9) switches a connection relationship between a second clock signal (CKV2) and the output voltage signal (Gout). Therefore, fluctuations such as those in IC power supply signal noise and long-term operation can be effectively suppressed, thereby improving the display quality.

Description

Shift register unit, shift register and display device Technical Field

[0001] This invention relates to the field of OLED devices, and particularly to shift register units, shift registers, and display devices. Background Technology

[0002] Recently, various flat panel displays with smaller weight and volume compared to cathode ray tube displays have been developed, including liquid crystal displays, field emission displays, plasma display panels, and organic light-emitting displays.

[0003] In flat panel displays, organic light-emitting displays (OLEDs) use organic light-emitting diodes (OLEDs) to display images, which generate light through the recombination of electrons and holes. OLEDs have a fast response time and are driven with low power consumption. A typical OLED uses transistors formed in pixels to supply current to the OLED light-emitting device according to a data signal, thereby causing the OLED light-emitting device to emit light.

[0004] Organic light-emitting displays can be classified into passive-matrix OLED (PMOLED) and active-matrix OLED (AMOLED) based on their driving type. Passive-matrix OLEDs do not use thin-film transistor substrates, while active-matrix OLEDs do.

[0005] Each pixel in an actively driven organic light-emitting diode (OLED) display is equipped with a low-temperature polycrystalline silicon thin-film transistor (LTS) that functions as a switch, and each pixel also has a storage capacitor. The peripheral driving circuitry and display components are integrated on the same glass substrate. Each pixel generates a driving current based on a data signal, and the brightness of the organic light-emitting diode is controlled by adjusting the driving current of the OLED light-emitting device. Due to inevitable fluctuations in the manufacturing process, the threshold voltages of the driving transistors in different pixel circuits vary, which can easily lead to IC power supply signal noise and uneven display.

[0006] The information disclosed in this background section is only intended to enhance the understanding of the background technology of this invention, and therefore may contain information that is unknown to those skilled in the art and does not constitute prior art. Summary of the Invention

[0007] In view of the problems in the prior art, the purpose of this invention is to provide a shift register unit, a shift register, and a display device, which overcomes the difficulties of the prior art, can effectively suppress IC power signal noise, fluctuations during long-term operation, and improve display quality.

[0008] Embodiments of the present invention provide a shift register unit, comprising:

[0009] The first transistor is used to switch the current path between the input voltage signal and the third node in response to the voltage signal of the first clock signal.

[0010] The second transistor is used to switch the current path between the operating voltage signal and the third node in response to the voltage signal of the third clock signal.

[0011] The third transistor is used to switch the current path between the operating voltage signal and the fourth node in response to the voltage signal of the second clock signal.

[0012] The fourth transistor is used to switch the current path between the fourth node and the second node in response to the voltage signal of the first node;

[0013] The fifth transistor is used to switch the current path between the ground signal and the first node in response to the voltage signal of the third clock signal;

[0014] The sixth transistor is used to switch the current path between the second node and the third node in response to the voltage signal of the ground signal;

[0015] The seventh transistor is used to switch the current path between the third clock signal and the first node in response to the voltage signal of the third node;

[0016] The eighth transistor is used to switch the current path between the operating voltage signal and the output voltage signal in response to the voltage signal of the first node;

[0017] The ninth transistor is used to switch the current path between the second clock signal and the output voltage signal in response to the voltage signal of the second node;

[0018] A first capacitor is coupled between the first node and the operating voltage signal; and

[0019] The second capacitor is coupled between the second node and the output voltage signal.

[0020] Optionally, the first clock signal, the second clock signal, and the third clock signal have the same waveform, the first clock signal is one-third of a clock signal cycle ahead of the second clock signal in phase, and the second clock signal is one-third of a clock signal cycle ahead of the third clock signal in phase.

[0021] Optionally, the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, and the ninth transistor are all N-type thin-film transistors.

[0022] Optionally, the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, and the ninth transistor are all P-type thin-film transistors.

[0023] Optionally, the input voltage signal is a vertical synchronization signal or the output voltage signal of the previous shift register unit.

[0024] Optionally, the input voltage signal is the output voltage signal of the previous shift register unit or the vertical synchronization signal.

[0025] Embodiments of the present invention also provide a shift register unit, comprising:

[0026] The first transistor is used to switch the current path between the input voltage signal and the third node in response to the voltage signal of the first clock signal.

[0027] The second transistor is used to switch the current path between the operating voltage signal and the third node in response to the voltage signal of the third clock signal.

[0028] The third transistor is used to switch the current path between the operating voltage signal and the fourth node in response to the voltage signal of the second clock signal.

[0029] The fourth transistor is used to switch the current path between the fourth node and the third node in response to the voltage signal of the first node;

[0030] The fifth transistor is used to switch the current path between the ground signal and the first node in response to the voltage signal of the third clock signal;

[0031] The sixth transistor is used to switch the current path between the second node and the third node in response to the voltage signal of the ground signal;

[0032] The seventh transistor is used to switch the current path between the third clock signal and the first node in response to the voltage signal of the third node;

[0033] The eighth transistor is used to switch the current path between the operating voltage signal and the output voltage signal in response to the voltage signal of the first node;

[0034] The ninth transistor is used to switch the current path between the second clock signal and the output voltage signal in response to the voltage signal of the second node;

[0035] A first capacitor is coupled between the first node and the operating voltage signal; and

[0036] The second capacitor is coupled between the second node and the output voltage signal.

[0037] Embodiments of the present invention also provide a shift register unit, comprising:

[0038] The first transistor is used to switch the current path between the input voltage signal and the third node in response to the voltage signal of the first clock signal.

[0039] The second transistor is used to switch the current path between the operating voltage signal and the third node in response to the voltage signal of the third clock signal.

[0040] The third transistor is used to switch the current path between the operating voltage signal and the fourth node in response to the voltage signal of the second clock signal.

[0041] The fourth transistor is used to switch the current path between the fourth node and the second node in response to the voltage signal of the first node;

[0042] The fifth transistor is used to switch the current path between the ground signal and the first node in response to the voltage signal of the third clock signal;

[0043] The sixth transistor is used to switch the current path between the second node and the third node in response to the voltage signal of the ground signal;

[0044] The seventh transistor is used to switch the current path between the first clock signal and the first node in response to the voltage signal of the third node;

[0045] The eighth transistor is used to switch the current path between the operating voltage signal and the output voltage signal in response to the voltage signal of the first node;

[0046] The ninth transistor is used to switch the current path between the second clock signal and the output voltage signal in response to the voltage signal of the second node;

[0047] A first capacitor is coupled between the first node and the operating voltage signal; and

[0048] The second capacitor is coupled between the second node and the output voltage signal.

[0049] Optionally, it also includes:

[0050] The tenth transistor is used to switch the current path between the first node and the ground signal in response to the voltage signal of the first clock signal.

[0051] Embodiments of the present invention also provide a gate driving circuit, comprising:

[0052] In a series of cascaded shift register units as described above, the input voltage signal of the first-stage shift register unit is a vertical synchronization signal, and the input voltage signal of the remaining shift register units is the output voltage signal of the previous-stage shift register unit.

[0053] Optionally, it further includes: a clock signal generating unit, used to generate a first clock pulse signal, a second clock pulse signal and a third clock pulse signal whose phases are successively differed by 1 / 3 of a signal cycle;

[0054] The first to third clock signals in the [3n+1]th stage shift register unit are the first clock pulse signal, the second clock pulse signal, and the third clock pulse signal generated by the clock signal generation unit, respectively.

[0055] The first to third clock signals in the [3n+2]th stage shift register unit are the second clock pulse signal, the third clock pulse signal, and the first clock pulse signal generated by the clock signal generation unit, respectively.

[0056] The first to third clock signals in the [3n+3]th stage shift register unit are the third clock signal, the first clock signal, and the second clock signal generated by the clock signal generation unit, respectively, where n is a natural number.

[0057] Embodiments of the present invention also provide a display device, including: the gate driving circuit as described above.

[0058] This invention can effectively suppress IC power signal noise and fluctuations caused by prolonged operation, thereby improving display quality. Based on common knowledge in the field, the above-mentioned optional conditions can be combined arbitrarily to obtain various preferred embodiments of this invention.

[0059] To further understand the features and technical content of this application, please refer to the following detailed description and drawings. However, the detailed description and drawings are only for illustrating this application and are not intended to limit the scope of the claims in any way. Attached Figure Description

[0060] The above and other features and advantages of this application will become more apparent from a detailed description of exemplary embodiments thereof with reference to the accompanying drawings.

[0061] Figure 1 is a circuit diagram of the shift register unit of the first embodiment of the present invention.

[0062] Figure 2 is a schematic diagram of the conduction state of the shift register unit under the first timing of the first embodiment of the present invention.

[0063] Figure 3 is a timing diagram of the shift register unit of the first embodiment of the present invention under the first timing.

[0064] Figure 4 is a schematic diagram of the conduction state of the shift register unit under the second timing of the first embodiment of the present invention.

[0065] Figure 5 is a timing diagram of the shift register unit of the first embodiment of the present invention under the second timing.

[0066] Figure 6 is a schematic diagram of the conduction state of the shift register unit under the third timing of the first embodiment of the present invention.

[0067] Figure 7 is a timing diagram of the shift register unit of the first embodiment of the present invention under the third timing.

[0068] Figure 8 is a schematic diagram of the conduction state of the shift register unit under the fourth timing of the first embodiment of the present invention.

[0069] Figure 9 is a timing diagram of the shift register unit of the first embodiment of the present invention under the fourth timing.

[0070] Figure 10 is a schematic diagram of the conduction state of the shift register unit under the fifth timing of the first embodiment of the present invention.

[0071] Figure 11 is a timing diagram of the shift register unit of the first embodiment of the present invention under the fifth timing.

[0072] Figure 12 is a schematic diagram of the conduction state of the shift register unit under the sixth timing of the first embodiment of the present invention.

[0073] Figure 13 is a timing diagram of the sixth timing of the shift register unit of the first embodiment of the present invention.

[0074] Figure 14 is a circuit diagram of the shift register unit of the second embodiment of the present invention.

[0075] Figure 15 is a circuit diagram of the shift register unit of the third embodiment of the present invention.

[0076] Figure 16 is a circuit diagram of the shift register unit according to the fourth embodiment of the present invention.

[0077] Figure 17 is a circuit diagram of the shift register according to the fifth embodiment of the present invention. Detailed Implementation

[0078] The following specific examples illustrate the implementation methods of this application. Those skilled in the art can easily understand the other advantages and effects of this application from the content disclosed herein. This application can also be implemented or applied through other different specific embodiments, and various details in this application can be modified or changed according to different viewpoints and application systems without departing from the spirit of this application. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of this application can be combined with each other.

[0079] The embodiments of this application will now be described in detail with reference to the accompanying drawings, so that those skilled in the art can easily implement the application. This application may be embodied in many different forms and is not limited to the embodiments described herein.

[0080] In this application, the terms "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics represented in connection with that embodiment or example, which are included in at least one embodiment or example of this application. Furthermore, the specific features, structures, materials, or characteristics represented may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate different embodiments or examples represented in this application, as well as features of different embodiments or examples.

[0081] Furthermore, the terms "first" and "second" are used for illustrative purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the representation of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0082] To clearly illustrate this application, devices unrelated to the description are omitted, and the same or similar constituent elements throughout the specification are given the same reference numerals.

[0083] Throughout this specification, when it is said that a device is "connected" to another device, this includes not only "direct connection" but also "indirect connection" by placing other components in between. Furthermore, when it is said that a device "comprises" a certain constituent element, unless otherwise stated otherwise, this does not exclude other constituent elements, but rather implies that other constituent elements may be included.

[0084] When we say that a device is "above" another device, this can mean that it is directly above the other device, or it can mean that other devices are present in between. Conversely, when we say that a device is "directly" "above" another device, there are no other devices present in between.

[0085] The technical terms used herein are used only in reference to specific embodiments and are not intended to limit this application. The singular form used herein includes the plural form unless the statement explicitly indicates otherwise. As used herein, the singular forms “a,” “an,” and “the” are intended to also include the plural forms unless the context indicates otherwise. The word “comprising” as used in the specification means to specify a particular feature, region, integer, step, operation, element, and / or component, and does not exclude the presence or addition of other features, regions, integers, steps, operations, elements, and / or components. It should be further understood that the terms “comprising” or “including” indicate the presence of a feature, step, operation, component, element, type, and / or group, but do not exclude the presence, occurrence, or addition of one or more other features, steps, operations, components, elements, types, and / or groups. The terms “or” and “and / or” as used herein are interpreted as inclusive, or mean any one or any combination thereof. Therefore, "A, B, or C" or "A, B, and / or C" means "any one of the following: A; B; C; A and B; A and C; B and C; A, B, and C". Exceptions to this definition will only occur if the combination of components, functions, steps, or operations is inherently mutually exclusive in some way.

[0086] Although not explicitly defined, all terms, including technical and scientific terms used herein, shall have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. Terms defined in commonly used dictionaries shall be further interpreted as having a meaning consistent with the relevant technical literature and the content of this present application, and shall not be over-interpreted as having an ideal or overly formulaic meaning unless otherwise defined.

[0087] Figure 1 is a circuit diagram of the shift register unit according to the first embodiment of the present invention. As shown in Figure 1, the pixel driving circuit of the first embodiment of the present invention includes: a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, a first capacitor C1, and a second capacitor C2. The first transistor T1 is used to switch the current path between the input voltage signal and the third node N3 in response to the voltage signal of the first clock signal CKV1. The second transistor T2 is used to switch the current path between the working voltage signal VDD and the third node N3 in response to the voltage signal of the third clock signal CKV3. The third transistor T3 is used to switch the current path between the working voltage signal VDD and the fourth node N4 in response to the voltage signal of the second clock signal CKV2. The fourth transistor T4 is used to switch the current path between the fourth node N4 and the second node N2 in response to the voltage signal of the first node N1. The fifth transistor T5 is used to switch the current path between the ground signal VEE and the first node N1 in response to the voltage signal of the third clock signal CKV3. The sixth transistor T6 switches the current path between the second node N2 and the third node N3 in response to the voltage signal of the ground signal VEE. The seventh transistor T7 switches the current path between the third clock signal CKV3 and the first node N1 in response to the voltage signal of the third node N3. The eighth transistor T8 switches the current path between the working voltage signal VDD and the output voltage signal Gout in response to the voltage signal of the first node N1. The ninth transistor T9 switches the current path between the second clock signal CKV2 and the output voltage signal Gout in response to the voltage signal of the second node N2. The first capacitor C1 is coupled between the first node N1 and the working voltage signal VDD. The second capacitor C2 is coupled between the second node N2 and the output voltage signal Gout, but is not limited thereto.

[0088] In one optional embodiment, the waveforms of the first clock signal CKV1, the second clock signal CKV2, and the third clock signal CKV3 are the same. The first clock signal CKV1 is one-third of a clock signal cycle ahead of the second clock signal CKV2 in phase, and the second clock signal CKV2 is one-third of a clock signal cycle ahead of the third clock signal CKV3 in phase (see Figures 3, 5, 7, 9, 11, and 13 below), but this is not a limitation.

[0089] In one alternative embodiment, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, and the ninth transistor T9 are all N-type thin-film transistors, but are not limited thereto.

[0090] In one alternative embodiment, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, and the ninth transistor T9 are all P-type thin-film transistors, but are not limited thereto.

[0091] In one alternative embodiment, the input voltage signal is either the vertical synchronization signal STV or the output voltage signal Gout of the previous shift register unit, but is not limited thereto.

[0092] In one alternative embodiment, the input voltage signal is the output voltage signal Gout of the previous shift register unit or the vertical synchronization signal STV, but is not limited thereto.

[0093] The shift register unit of this invention adopts a 9T2C structure and uses 3 sets of clock signals. When node N1 outputs a high level from Gout, node N2 will have a voltage source to keep the ninth transistor T9 at a high level, thus eliminating the floating time (i.e., not being grounded to maintain its independence or reduce sensitivity to external interference), thereby effectively providing a stable output signal waveform.

[0094] The working principle of the shift register unit of the present invention under various timing conditions will be specifically described below with reference to Figures 2 to 13.

[0095] Figure 2 is a schematic diagram of the conduction state of the shift register unit under the first timing of the first embodiment of the present invention. Figure 3 is a timing diagram of the shift register unit under the first timing of the first embodiment of the present invention. Referring to Figures 2 and 3, when the shift register unit of the first embodiment of the present invention is in the first timing, the states of each transistor are as follows: the first transistor T1, the sixth transistor T6, the seventh transistor T7, and the ninth transistor T9 are all turned on, and the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the eighth transistor T8 are all turned off. At this time, the first transistor T1 is turned on due to the low potential of the first clock signal CKV1, the second node N2 and the third node N3 are respectively written to the low potential of STV, the seventh transistor T7 and the ninth transistor T9 are turned on, the first node N1 is written to the high potential of the third clock signal CKV3 due to the turning on of the seventh transistor T7, the eighth transistor T8 is turned off, and Gout outputs the high potential of the second clock signal CKV2.

[0096] Figure 4 is a schematic diagram of the conduction state of the shift register unit under the second timing of the first embodiment of the present invention. Figure 5 is a timing diagram of the shift register unit under the second timing of the first embodiment of the present invention. Referring to Figures 4 and 5, when the shift register unit of the first embodiment of the present invention is in the second timing, the states of each transistor are as follows: the third transistor T3, the sixth transistor T6, the seventh transistor T7, and the ninth transistor T9 are all turned on; the first transistor T1, the second transistor T2, the fourth transistor T4, the fifth transistor T5, and the eighth transistor T8 are all turned off; the seventh transistor T7 is continuously turned on due to the low potential of the third node N3; the first node N1 writes the third clock signal CKV3 to a high potential; the eighth transistor T8 is turned off; the second node N2 remains at a low potential; the ninth transistor T9 is turned on; and the output voltage signal Gout outputs the second clock signal CKV2 at a low potential.

[0097] Figure 6 is a schematic diagram of the conduction state of the shift register unit under the third timing of the first embodiment of the present invention. Figure 7 is a timing diagram of the shift register unit under the third timing of the first embodiment of the present invention. Referring to Figures 6 and 7, when the shift register unit of the first embodiment of the present invention is in the third timing, the states of each transistor are as follows: the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the eighth transistor T8 are all turned on, and the first transistor T1, the third transistor T3, the seventh transistor T7, and the ninth transistor T9 are all turned off. The second transistor T2 is turned on due to the low potential of the third clock signal CKV3, the second node N2 and the third node N3 are written with the high potential VDD, the seventh transistor T7 and the ninth transistor T9 are turned off, the fifth transistor T5 is turned on due to the low potential of the third clock signal CKV3, the first node N1 is written with the low potential VEE, the eighth transistor T8 is turned on, and the output voltage signal Gout outputs the working voltage signal VDD with the high potential.

[0098] Figure 8 is a schematic diagram of the conduction state of the shift register unit under the fourth timing of the first embodiment of the present invention. Figure 9 is a timing diagram of the shift register unit under the fourth timing of the first embodiment of the present invention. Referring to Figures 8 and 9, when the shift register unit of the first embodiment of the present invention is in the fourth timing, the states of each transistor are as follows: the first transistor T1, the fourth transistor T4, the sixth transistor T6, and the eighth transistor T8 are all turned on; the second transistor T2, the third transistor T3, the fifth transistor T5, the seventh transistor T7, and the ninth transistor T9 are all turned off; the first transistor T1 is turned on due to the low potential of the first clock signal CKV1; the second node N2 and the third node N3 write the vertical synchronization signal STV to a high potential; the seventh transistor T7 and the ninth transistor T9 are turned off; the first node N1 remains at a low potential; the eighth transistor T8 is turned on; and the output voltage signal Gout outputs the working voltage signal VDD to a high potential.

[0099] Figure 10 is a schematic diagram of the conduction state of the shift register unit under the fifth timing sequence of the first embodiment of the present invention. Figure 11 is a timing diagram of the shift register unit under the fifth timing sequence of the first embodiment of the present invention. Referring to Figures 10 and 11, when the shift register unit of the first embodiment of the present invention is in the fifth timing sequence, the states of each transistor are as follows: the third transistor T3, the fourth transistor T4, the sixth transistor T6, and the eighth transistor T8 are all turned on, while the first transistor T1, the second transistor T2, the fifth transistor T5, the seventh transistor T7, and the ninth transistor T9 are all turned off. The first node N1 remains at a low potential, the fourth transistor T4 is turned on, and the third transistor T3 is turned on due to the low potential of the second clock signal CKV2. The second node N2 and the third node N3 write the working voltage signal VDD to a high potential because the third transistor T3 and the fourth transistor T4 are turned on. The seventh transistor T7 and the ninth transistor T9 are turned off, and the eighth transistor T8 is turned on due to the low potential of the first node N1. The output voltage signal Gout outputs the working voltage signal VDD to a high potential.

[0100] Figure 12 is a schematic diagram of the conduction state of the shift register unit under the sixth timing sequence of the first embodiment of the present invention. Figure 13 is a timing diagram of the shift register unit under the sixth timing sequence of the first embodiment of the present invention. Referring to Figures 12 and 13, when the shift register unit of the first embodiment of the present invention is in the sixth timing sequence, the states of each transistor are as follows: the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the eighth transistor T8 are all turned on, while the first transistor T1, the third transistor T3, the seventh transistor T7, and the ninth transistor T9 are all turned off. The second transistor T2 is turned on due to the low potential of the third clock signal CKV3, and the second and third nodes are written with the high potential of the working voltage signal VDD. The seventh transistor T7 and the ninth transistor T9 are turned off, and the fifth transistor T5 is also turned on due to the low potential of the third clock signal CKV3. The first node N1 is written with the low potential of the ground signal VEE, the eighth transistor T8 is turned on, and the output voltage signal Gout outputs the high potential of VDD.

[0101] After the sixth timing sequence, the circuit will repeat the first to sixth timing sequences until the vertical synchronization signal STV / in reaches a low frequency, and then re-enter the first timing sequence of the next round.

[0102] Figure 14 is a circuit diagram of the shift register unit of the second embodiment of the present invention. As shown in Figure 14, the pixel driving circuit of the second embodiment of the present invention includes: a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, a first capacitor C1, and a second capacitor C2. The first transistor T1 is used to switch the current path between the input voltage signal and the third node N3 in response to the voltage signal of the first clock signal CKV1. The second transistor T2 is used to switch the current path between the working voltage signal VDD and the third node N3 in response to the voltage signal of the third clock signal CKV3. The third transistor T3 is used to switch the current path between the working voltage signal VDD and the fourth node N4 in response to the voltage signal of the second clock signal CKV2. The fourth transistor T4 is used to switch the current path between the fourth node N4 and the third node N3 in response to the voltage signal of the first node N1. The fifth transistor T5 is used to switch the current path between the ground signal VEE and the first node N1 in response to the voltage signal of the third clock signal CKV3. The sixth transistor T6 is used to switch the current path between the second node N2 and the third node N3 in response to the voltage signal of the ground signal VEE. The seventh transistor T7 is used to switch the current path between the third clock signal CKV3 and the first node N1 in response to the voltage signal of the third node N3. The eighth transistor T8 is used to switch the current path between the working voltage signal VDD and the output voltage signal Gout in response to the voltage signal of the first node N1. The ninth transistor T is used to switch the current path between the second clock signal CKV2 and the output voltage signal Gout in response to the voltage signal of the second node N2. The first capacitor C1 is coupled between the first node N1 and the working voltage signal VDD. The second capacitor C2 is coupled between the second node N2 and the output voltage signal Gout. The difference between the second embodiment and the first embodiment is that one end of the fourth transistor T4 is connected to the third node N3. This circuit operates the same as the first embodiment and can operate normally, but it is not limited thereto.

[0103] Figure 15 is a circuit diagram of the shift register unit according to the third embodiment of the present invention. As shown in Figure 15, the pixel driving circuit of the third embodiment of the present invention includes: a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, a first capacitor C1, and a second capacitor C2. The first transistor T1 is used to switch the current path between the input voltage signal and the third node N3 in response to the voltage signal of the first clock signal CKV1. The second transistor T2 is used to switch the current path between the working voltage signal VDD and the third node N3 in response to the voltage signal of the third clock signal CKV3. The third transistor T3 is used to switch the current path between the working voltage signal VDD and the fourth node N4 in response to the voltage signal of the second clock signal CKV2. The fourth transistor T4 is used to switch the current path between the fourth node N4 and the second node N2 in response to the voltage signal of the first node N1. The fifth transistor T5 is used to switch the current path between the ground signal VEE and the first node N1 in response to the voltage signal of the third clock signal CKV3. The sixth transistor T6 is used to switch the current path between the second node N2 and the third node N3 in response to the voltage signal of the ground signal VEE. The seventh transistor T7 is used to switch the current path between the first clock signal CKV1 and the first node N1 in response to the voltage signal of the third node N3. The eighth transistor T8 is used to switch the current path between the working voltage signal VDD and the output voltage signal Gout in response to the voltage signal of the first node N1. The ninth transistor T9 is used to switch the current path between the second clock signal CKV2 and the output voltage signal Gout in response to the voltage signal of the second node N2. The first capacitor C1 is coupled between the first node N1 and the working voltage signal VDD. The second capacitor C2 is coupled between the second node N2 and the output voltage signal Gout. The difference between the third embodiment and the first embodiment is that one end of the seventh transistor T7 is connected to the first clock signal CKV1. This circuit operates the same as the first embodiment and can operate normally, but it is not limited thereto.

[0104] Figure 16 is a circuit diagram of the shift register unit according to the fourth embodiment of the present invention. As shown in Figure 16, the pixel driving circuit of the fourth embodiment of the present invention includes: a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, a first capacitor C1, and a second capacitor C2. The first transistor T1 is used to switch the current path between the input voltage signal and the third node N3 in response to the voltage signal of the first clock signal CKV1. The second transistor T2 is used to switch the current path between the working voltage signal VDD and the third node N3 in response to the voltage signal of the third clock signal CKV3. The third transistor T3 is used to switch the current path between the working voltage signal VDD and the fourth node N4 in response to the voltage signal of the second clock signal CKV2. The fourth transistor T4 is used to switch the current path between the fourth node N4 and the second node N2 in response to the voltage signal of the first node N1. The fifth transistor T5 switches the current path between the ground signal VEE and the first node N1 in response to the voltage signal of the third clock signal CKV3. The sixth transistor T6 switches the current path between the second node N2 and the third node N3 in response to the voltage signal of the ground signal VEE. The seventh transistor T7 switches the current path between the first clock signal CKV1 and the first node N1 in response to the voltage signal of the third node N3. The eighth transistor T8 switches the current path between the working voltage signal VDD and the output voltage signal Gout in response to the voltage signal of the first node N1. The ninth transistor T9 switches the current path between the second clock signal CKV2 and the output voltage signal Gout in response to the voltage signal of the second node N2. The tenth transistor T10 switches the current path between the first node N1 and the ground signal VEE in response to the voltage signal of the first clock signal CKV1. The first capacitor C1 is coupled between the first node N1 and the working voltage signal VDD. The second capacitor C2 is coupled between the second node N2 and the output voltage signal Gout. Example 4 is an improvement on Example 3, employing a 10-transistor & 2-capacitor circuit architecture (10T2C). The circuit operation and timing are the same as in Example 1, but a tenth transistor T10 component is added. This reduces the time the first node N1 holds the voltage from the two-line time (2H) in Example 1 to 1H, thereby further increasing circuit stability. Examples 1 to 3 all use pure PMOS as an example; this circuit can also be driven normally using pure NMOS with the opposite timing.

[0105] Figure 17 is a circuit diagram of the shift register according to the fifth embodiment of the present invention. As shown in Figure 17, the present invention also provides a gate driving circuit, including: a clock signal generating unit, and multiple cascaded shift register units as described above (see the first to fourth embodiments). The input voltage signal of the first-stage shift register unit is a vertical synchronization signal (STV), and the input voltage signals of the remaining shift register units are the output voltage signals (Gout) of the previous-stage shift register unit. The clock signal generating unit is used to generate a first clock pulse signal, a second clock pulse signal, and a third clock pulse signal with phases differing by 1 / 3 of a signal period. The first to third clock signals in the [3n+1]th stage shift register unit are the first clock pulse signal, the second clock pulse signal, and the third clock pulse signal generated by the clock signal generating unit, respectively. The first to third clock signals in the [3n+2]th stage shift register unit are the second clock pulse signal, the third clock pulse signal, and the first clock pulse signal generated by the clock signal generating unit, respectively. The first to third clock signals in the [3n+3]th stage shift register unit are the third clock signal, the first clock signal, and the second clock signal generated by the clock signal generation unit, respectively, where n is a natural number. Referring to Figure 17, the effective connection method of the three sets of clock signals in the block diagram of this embodiment, according to the software simulation results, ensures that the output signal can be output correctly and effectively.

[0106] This embodiment also provides a display device, such as an OLED panel, including the pixel driving circuit described above. The display device of the present invention incorporates the structural features, techniques, and effects of the pixel driving circuit described above, which will not be repeated here.

[0107] In summary, the shift register unit, shift register, and display device of the present invention adopt a 9T2C structure and use three sets of clock signals. When the first node N1 outputs a high level at Gout, node N2 will have a voltage source that keeps the ninth transistor T9 at a high level, thus eliminating the floating time and providing a stable output signal waveform. This effectively suppresses fluctuations such as IC power signal noise and long-term operation, thereby improving display quality.

[0108] The above description, in conjunction with specific optional embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A shift register unit, characterized in that, include: The first transistor (T1) is used to switch the current path between the input voltage signal and the third node (N3) in response to the voltage signal of the first clock signal (CKV1). The second transistor (T2) is used to switch the current path between the operating voltage signal (VDD) and the third node (N3) in response to the voltage signal of the third clock signal (CKV3); The third transistor (T3) is used to switch the current path between the operating voltage signal (VDD) and the fourth node (N4) in response to the voltage signal of the second clock signal (CKV2). The fourth transistor (T4) is used to switch the current path between the fourth node (N4) and the second node (N2) in response to the voltage signal of the first node (N1); The fifth transistor (T5) is used to switch the current path between the ground signal (VEE) and the first node (N1) in response to the voltage signal of the third clock signal (CKV3); The sixth transistor (T6) is used to switch the current path between the second node (N2) and the third node (N3) in response to the voltage signal of the ground signal (VEE); The seventh transistor (T7) is used to switch the current path between the third clock signal (CKV3) and the first node (N1) in response to the voltage signal of the third node (N3); The eighth transistor (T8) is used to switch the current path between the operating voltage signal (VDD) and the output voltage signal (Gout) in response to the voltage signal of the first node (N1); The ninth transistor (T9) is used to switch the current path between the second clock signal (CKV2) and the output voltage signal (Gout) in response to the voltage signal of the second node (N2); A first capacitor (C1) is coupled between the first node (N1) and the operating voltage signal (VDD); and The second capacitor (C2) is coupled between the second node (N2) and the output voltage signal (Gout).

2. The shift register unit as described in claim 1, characterized in that, The first clock signal (CKV1), the second clock signal (CKV2), and the third clock signal (CKV3) have the same waveform. The first clock signal (CKV1) is one-third of a clock signal cycle ahead of the second clock signal (CKV2) in phase, and the second clock signal (CKV2) is one-third of a clock signal cycle ahead of the third clock signal (CKV3) in phase.

3. The shift register unit as described in claim 1, characterized in that, The first transistor (T1), the second transistor (T2), the third transistor (T3), the fourth transistor (T4), the fifth transistor (T5), the sixth transistor (T6), the seventh transistor (T7), the eighth transistor (T8), and the ninth transistor (T9) are all N-type thin-film transistors.

4. The shift register unit as described in claim 1, characterized in that, The first transistor (T1), the second transistor (T2), the third transistor (T3), the fourth transistor (T4), the fifth transistor (T5), the sixth transistor (T6), the seventh transistor (T7), the eighth transistor (T8), and the ninth transistor (T9) are all P-type thin-film transistors.

5. The shift register unit as described in claim 1, characterized in that, The input voltage signal is either the vertical synchronization signal (STV) or the output voltage signal (Gout) of the previous shift register unit.

6. The shift register unit as described in claim 1, characterized in that, The input voltage signal is the output voltage signal (Gout) of the previous shift register unit or the vertical synchronization signal (STV).

7. A shift register unit, characterized in that, include: The first transistor (T1) is used to switch the current path between the input voltage signal and the third node (N3) in response to the voltage signal of the first clock signal (CKV1). The second transistor (T2) is used to switch the current path between the operating voltage signal (VDD) and the third node (N3) in response to the voltage signal of the third clock signal (CKV3); The third transistor (T3) is used to switch the current path between the operating voltage signal (VDD) and the fourth node (N4) in response to the voltage signal of the second clock signal (CKV2). The fourth transistor (T4) is used to switch the current path between the fourth node (N4) and the third node (N3) in response to the voltage signal of the first node (N1); The fifth transistor (T5) is used to switch the current path between the ground signal (VEE) and the first node (N1) in response to the voltage signal of the third clock signal (CKV3); The sixth transistor (T6) is used to switch the current path between the second node (N2) and the third node (N3) in response to the voltage signal of the ground signal (VEE); The seventh transistor (T7) is used to switch the current path between the third clock signal (CKV3) and the first node (N1) in response to the voltage signal of the third node (N3); The eighth transistor (T8) is used to switch the current path between the operating voltage signal (VDD) and the output voltage signal (Gout) in response to the voltage signal of the first node (N1); The ninth transistor (T9) is used to switch the current path between the second clock signal (CKV2) and the output voltage signal (Gout) in response to the voltage signal of the second node (N2); A first capacitor (C1) is coupled between the first node (N1) and the operating voltage signal (VDD); and The second capacitor (C2) is coupled between the second node (N2) and the output voltage signal (Gout).

8. A shift register unit, characterized in that, include: The first transistor (T1) is used to switch the current path between the input voltage signal and the third node (N3) in response to the voltage signal of the first clock signal (CKV1). The second transistor (T2) is used to switch the current path between the operating voltage signal (VDD) and the third node (N3) in response to the voltage signal of the third clock signal (CKV3); The third transistor (T3) is used to switch the current path between the operating voltage signal (VDD) and the fourth node (N4) in response to the voltage signal of the second clock signal (CKV2). The fourth transistor (T4) is used to switch the current path between the fourth node (N4) and the second node (N2) in response to the voltage signal of the first node (N1); The fifth transistor (T5) is used to switch the current path between the ground signal (VEE) and the first node (N1) in response to the voltage signal of the third clock signal (CKV3); The sixth transistor (T6) is used to switch the current path between the second node (N2) and the third node (N3) in response to the voltage signal of the ground signal (VEE); The seventh transistor (T7) is used to switch the current path between the first clock signal (CKV1) and the first node (N1) in response to the voltage signal of the third node (N3); The eighth transistor (T8) is used to switch the current path between the operating voltage signal (VDD) and the output voltage signal (Gout) in response to the voltage signal of the first node (N1); The ninth transistor (T9) is used to switch the current path between the second clock signal (CKV2) and the output voltage signal (Gout) in response to the voltage signal of the second node (N2); A first capacitor (C1) is coupled between the first node (N1) and the operating voltage signal (VDD); and The second capacitor (C2) is coupled between the second node (N2) and the output voltage signal (Gout).

9. The shift register unit as described in claim 8, characterized in that, Also includes: The tenth transistor (T10) is used to switch the current path between the first node (N1) and the ground signal (VEE) in response to the voltage signal of the first clock signal (CKV1).

10. A shift register, characterized in that, include: In a series of cascaded shift register units as described in any one of claims 1 to 9, the input voltage signal of the first-stage shift register unit is a vertical synchronization signal (STV), and the input voltage signals of the remaining shift register units are the output voltage signals (Gout) of the previous-stage shift register unit.

11. The shift register as claimed in claim 10, characterized in that, Also includes: A clock signal generating unit is used to generate a first clock pulse signal, a second clock pulse signal, and a third clock pulse signal whose phases differ by 1 / 3 of a signal cycle. The first to third clock signals in the [3n+1]th stage shift register unit are the first clock pulse signal, the second clock pulse signal, and the third clock pulse signal generated by the clock signal generation unit, respectively. The first to third clock signals in the [3n+2]th stage shift register unit are the second clock pulse signal, the third clock pulse signal, and the first clock pulse signal generated by the clock signal generation unit, respectively. The first to third clock signals in the [3n+3]th stage shift register unit are the third clock signal, the first clock signal, and the second clock signal generated by the clock signal generation unit, respectively, where n is a natural number.

12. A display device, characterized in that, include: The shift register as described in claim 10 or 11.

Images