Shift register unit, shift register, and display device

Abstract

A shift register unit, a shift register, and a display device. A first transistor of the shift register unit switches the circuit between an input voltage signal and a fifth node; a second transistor switches the circuit between a negative voltage signal and a fourth node; a third transistor switches the circuit between the fourth node and a second node; a fourth transistor switches the circuit between a positive voltage signal and the second node; a fifth transistor switches the circuit between a first node and the fifth node; a sixth transistor switches the circuit between the negative voltage signal and an output voltage signal; a seventh transistor switches the circuit between the positive voltage signal and the output voltage signal; an eighth transistor switches the circuit between a second clock signal and a third node; a ninth transistor switches the circuit between the negative voltage signal and the third node; a tenth transistor switches the circuit between the third node and a sixth node; a first capacitor is coupled between the first node and the output voltage signal; a second capacitor is coupled between the second node and the positive voltage signal; and a third capacitor is coupled between a first clock signal and the sixth node. Thus, the problem of output anomalies can be solved and voltage fluctuations can be optimized.

Description

Shift register unit, shift register and display device Technical Field

[0001] This invention relates to the field of OLED devices, and particularly to shift register units, shift registers, and display devices. Background Technology

[0002] Recently, various flat panel displays, including liquid crystal displays (LCDs), field emission displays (FETs), plasma display panels, and organic light-emitting diode (OLEDs), have been developed that are significantly lighter and smaller than cathode ray tube (CRT) displays. Among flat panel displays, OLEDs use organic light-emitting diodes (OLEDs) to display images, generating light through the recombination of electrons and holes. OLEDs offer faster response times and are driven with lower power consumption. A typical OLED uses transistors formed in pixels to supply current to the OLED light-emitting device according to a data signal, thereby causing the OLED to emit light.

[0003] Figure 1 shows a scanning circuit diagram from a prior art patent CN105741749A. This circuit has a risk point: when the manufacturing process, such as aging test, causes the device's Vth offset, or when process fluctuations cause changes in the aspect ratio of the TFT, transistors M3 and M7 will interfere with each other, resulting in abnormal out output, thus causing the panel to display an abnormal image.

[0004] The information disclosed in this background section is only intended to enhance the understanding of the background technology of this invention, and therefore may contain information that is unknown to those skilled in the art and does not constitute prior art. Summary of the Invention

[0005] In view of the problems in the prior art, the purpose of the present invention is to provide a shift register unit, a shift register and a display device, which overcomes the difficulties of the prior art, can solve the output abnormality problem caused by the mutual restraint relationship between the third transistor and the seventh transistor in the scanning circuit of the prior art, and optimizes the voltage fluctuation problem of the second node.

[0006] Embodiments of the present invention provide a shift register unit, comprising:

[0007] The first transistor is used to switch the current path between the input voltage signal and the fifth node in response to the voltage signal of the first clock signal.

[0008] The second transistor is used to switch the current path between the negative voltage signal and the fourth node in response to the voltage signal of the first clock signal.

[0009] The third transistor is used to switch the current path between the fourth and second nodes in response to the voltage signal of the sixth node.

[0010] The fourth transistor is used to switch the current path between the positive voltage signal and the second node in response to the voltage signal of the fifth node;

[0011] The fifth transistor is used to switch the current path between the first node and the fifth node in response to a voltage signal that is in response to a negative voltage signal.

[0012] The sixth transistor is used to switch the current path between the negative voltage signal and the output voltage signal in response to the voltage signal of the first node;

[0013] The seventh transistor is used to switch the current path between the positive voltage signal and the output voltage signal in response to the voltage signal of the second node;

[0014] The eighth transistor is used to switch the current path between the second clock signal and the third node in response to the voltage signal of the input voltage signal.

[0015] The ninth transistor is used to switch the current path between the negative voltage signal and the third node in response to the voltage signal of the second clock signal.

[0016] The tenth transistor is used to switch the current path between the third and sixth nodes in response to a negative voltage signal.

[0017] A first capacitor is coupled between the first node and the output voltage signal;

[0018] A second capacitor is coupled between the second node and the positive voltage signal; and

[0019] The third capacitor is coupled between the first clock signal and the sixth node.

[0020] Optionally, the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, the ninth transistor, and the tenth transistor are all N-type thin-film transistors.

[0021] Optionally, the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, the ninth transistor, and the tenth transistor are all P-type thin-film transistors.

[0022] Embodiments of the present invention also provide a gate driving circuit, including: a plurality of cascaded shift register units as described above;

[0023] The input voltage signal of the first-stage shift register unit is a pulse signal, and the input voltage signal of the remaining shift register units is the output voltage signal of the previous-stage shift register unit.

[0024] Optionally, the first clock signal and the second clock signal have the same waveform, and the first clock signal is 1 / 2 clock signal cycle ahead of the second clock signal in phase.

[0025] Optionally, the duty cycle of both the first clock signal and the second clock signal is 75%.

[0026] Optionally, the combination of the high level and the falling edge of the high level within one cycle of the pulse signal is time-aligned with two adjacent cycles of the first clock signal.

[0027] Optionally, when the pulse signal is triggered to a high level, the first clock signal is triggered to a low level.

[0028] Optionally, it further includes: a clock signal generating unit, used to generate a first clock pulse signal and a second clock pulse signal whose phases differ by 1 / 2 signal period in sequence;

[0029] Wherein, the first clock signal and the second clock signal in the [2n+1]th stage shift register unit are the first clock pulse signal and the second clock pulse signal generated by the clock signal generating unit, respectively;

[0030] The first clock signal and the second clock signal in the [2n+2]th stage shift register unit are the second clock pulse signal and the first clock pulse signal generated by the clock signal generation unit, respectively, where n is a natural number.

[0031] Embodiments of the present invention also provide a display device, including the gate driving circuit as described above.

[0032] This invention solves the output anomaly problem caused by the mutual constraint between the third and seventh transistors in the existing scanning circuit, and optimizes the voltage fluctuation problem at the second node. Based on common knowledge in the field, the above-mentioned optional conditions can be arbitrarily combined to obtain various preferred embodiments of this invention.

[0033] To further understand the features and technical content of this application, please refer to the following detailed description and drawings. However, the detailed description and drawings are only for illustrating this application and are not intended to limit the scope of the claims in any way. Attached Figure Description

[0034] The above and other features and advantages of this application will become more apparent from a detailed description of exemplary embodiments thereof with reference to the accompanying drawings.

[0035] Figure 1 is a circuit diagram of the prior art CN105741749.

[0036] Figure 2 is a circuit diagram of the shift register unit of the first embodiment of the present invention.

[0037] Figure 3 is a timing diagram of the shift register unit of the first embodiment of the present invention.

[0038] Figure 4 is a schematic diagram of the conduction state of the shift register unit under the first timing of the first embodiment of the present invention.

[0039] Figure 5 is a timing diagram of the shift register unit of the first embodiment of the present invention under the first timing.

[0040] Figure 6 is a schematic diagram of the conduction state of the shift register unit under the second timing of the first embodiment of the present invention.

[0041] Figure 7 is a timing diagram of the shift register unit of the first embodiment of the present invention under the second timing.

[0042] Figure 8 is a schematic diagram of the conduction state of the shift register unit under the third timing of the first embodiment of the present invention.

[0043] Figure 9 is a timing diagram of the shift register unit of the first embodiment of the present invention under the third timing.

[0044] Figure 10 is a schematic diagram of the conduction state of the shift register unit in the fourth timing of the first embodiment of the present invention.

[0045] Figure 11 is a timing diagram of the shift register unit of the first embodiment of the present invention under the fourth timing.

[0046] Figure 12 is a schematic diagram of the conduction state of the shift register unit in the fifth timing of the first embodiment of the present invention.

[0047] Figure 13 is a timing diagram of the shift register unit of the first embodiment of the present invention under the fifth timing.

[0048] Figure 14 is a schematic diagram of the conduction state of the shift register unit under the sixth timing of the first embodiment of the present invention.

[0049] Figure 15 is a timing diagram of the shift register unit of the first embodiment of the present invention under the sixth timing.

[0050] Figure 16 is a schematic diagram of the conduction state of the shift register unit in the seventh timing of the first embodiment of the present invention.

[0051] Figure 17 is a timing diagram of the shift register unit of the first embodiment of the present invention under the seventh timing.

[0052] Figure 18 is a circuit diagram of the shift register according to the second embodiment of the present invention. Detailed Implementation

[0053] The following specific examples illustrate the implementation methods of this application. Those skilled in the art can easily understand the other advantages and effects of this application from the content disclosed herein. This application can also be implemented or applied through other different specific embodiments, and various details in this application can be modified or changed according to different viewpoints and application systems without departing from the spirit of this application. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of this application can be combined with each other.

[0054] The embodiments of this application will now be described in detail with reference to the accompanying drawings, so that those skilled in the art can easily implement the application. This application may be embodied in many different forms and is not limited to the embodiments described herein.

[0055] In this application, the terms "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics represented in connection with that embodiment or example, which are included in at least one embodiment or example of this application. Furthermore, the specific features, structures, materials, or characteristics represented may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate different embodiments or examples represented in this application, as well as features of different embodiments or examples.

[0056] Furthermore, the terms "first" and "second" are used for illustrative purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the representation of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0057] To clearly illustrate this application, devices unrelated to the description are omitted, and the same or similar constituent elements throughout the specification are given the same reference numerals.

[0058] Throughout this specification, when it is said that a device is "connected" to another device, this includes not only "direct connection" but also "indirect connection" by placing other components in between. Furthermore, when it is said that a device "comprises" a certain constituent element, unless otherwise stated otherwise, this does not exclude other constituent elements, but rather implies that other constituent elements may be included.

[0059] When we say that a device is "above" another device, this can mean that it is directly above the other device, or it can mean that other devices are present in between. Conversely, when we say that a device is "directly" "above" another device, there are no other devices present in between.

[0060] The technical terms used herein are used only in reference to specific embodiments and are not intended to limit this application. The singular form used herein includes the plural form unless the statement explicitly indicates otherwise. As used herein, the singular forms “a,” “an,” and “the” are intended to also include the plural forms unless the context indicates otherwise. The word “comprising” as used in the specification means to specify a particular feature, region, integer, step, operation, element, and / or component, and does not exclude the presence or addition of other features, regions, integers, steps, operations, elements, and / or components. It should be further understood that the terms “comprising” or “including” indicate the presence of a feature, step, operation, component, element, type, and / or group, but do not exclude the presence, occurrence, or addition of one or more other features, steps, operations, components, elements, types, and / or groups. The terms “or” and “and / or” as used herein are interpreted as inclusive, or mean any one or any combination thereof. Therefore, "A, B, or C" or "A, B, and / or C" means "any one of the following: A; B; C; A and B; A and C; B and C; A, B, and C". Exceptions to this definition will only occur if the combination of components, functions, steps, or operations is inherently mutually exclusive in some way.

[0061] Although not explicitly defined, all terms, including technical and scientific terms used herein, shall have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. Terms defined in commonly used dictionaries shall be further interpreted as having a meaning consistent with the relevant technical literature and the content of this present application, and shall not be over-interpreted as having an ideal or overly formulaic meaning unless otherwise defined.

[0062] Figure 2 is a circuit diagram of the shift register unit of the first embodiment of the present invention. Figure 3 is a timing diagram of the shift register unit of the first embodiment of the present invention. As shown in Figures 2 and 3, the pixel driving circuit of the first embodiment of the present invention includes: a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, a first capacitor C1, a second capacitor C2, and a third capacitor C3. The first transistor T1 is used to switch the current path between the input voltage signal IN and the fifth node N5 in response to the voltage signal of the first clock signal CKE1. The second transistor T2 is used to switch the current path between the negative voltage signal VEE and the fourth node N4 in response to the voltage signal of the first clock signal CKE1. The third transistor T3 is used to switch the current path between the fourth node N4 and the second node N2 in response to the voltage signal of the sixth node N6. The fourth transistor T4 is used to switch the current path between the positive voltage signal VDD and the second node N2 in response to the voltage signal of the fifth node N5. The fifth transistor T5 switches the current path between the first node N1 and the fifth node N5 in response to the voltage signal VEE (negative voltage signal). The sixth transistor T6 switches the current path between the negative voltage signal VEE and the output voltage signal Eout in response to the voltage signal of the first node N1. The seventh transistor T7 switches the current path between the positive voltage signal VDD and the output voltage signal Eout in response to the voltage signal of the second node N2. The eighth transistor T8 switches the current path between the second clock signal CKE2 and the third node N3 in response to the voltage signal of the input voltage signal IN. The ninth transistor T9 switches the current path between the negative voltage signal VEE and the third node N3 in response to the voltage signal of the second clock signal CKE2. The tenth transistor T10 switches the current path between the third node N3 and the sixth node N6 in response to the voltage signal VEE (negative voltage signal). The first capacitor C1 is coupled between the first node N1 and the output voltage signal Eout. The second capacitor C2 is coupled between the second node N2 and the positive voltage signal VDD. The third capacitor C3 is coupled between the first clock signal CKE1 and the sixth node N6.

[0063] In one alternative embodiment, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9, and the tenth transistor T10 are all N-type thin-film transistors, but are not limited thereto.

[0064] In one alternative embodiment, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9, and the tenth transistor T10 are all P-type thin-film transistors, but are not limited thereto.

[0065] In one optional embodiment, the input voltage signal IN of the first-stage shift register unit is the pulse signal STE, and the input voltage signal IN of the other shift register units is the output voltage signal Eout of the previous-stage shift register unit, but this is not a limitation.

[0066] In one optional embodiment, the waveforms of the first clock signal CKE1 and the second clock signal CKE2 are the same, and the first clock signal CKE1 is 1 / 2 clock signal cycle ahead of the second clock signal CKE2 in phase, but this is not a limitation.

[0067] In one alternative embodiment, the duty cycle of the first clock signal CKE1 and the duty cycle of the second clock signal CKE2 are both 75%, but this is not a limitation.

[0068] In one alternative embodiment, the timing combination of a high level within one cycle of the pulse signal STE and the falling edge of that high level is aligned with two adjacent cycles of the first clock signal CKE1, but is not limited thereto.

[0069] In one alternative embodiment, the first clock signal CKE1 is triggered to a low level when the pulse signal STE is triggered to a high level, but this is not a limitation.

[0070] The shift register unit of the present invention can solve the output abnormality problem caused by the mutual restraint relationship between the third transistor and the seventh transistor in the scanning circuit of the prior art, and optimize the voltage fluctuation problem of the second node.

[0071] The working principle of the shift register unit of the present invention under various timing conditions will be specifically described below with reference to Figures 4 to 17.

[0072] Figure 4 is a schematic diagram of the conduction state of the shift register unit under the first timing sequence of the first embodiment of the present invention. Figure 5 is a timing diagram of the shift register unit under the first timing sequence of the first embodiment of the present invention. As shown in Figures 4 and 5, when the shift register unit of the first embodiment of the present invention is in the first timing sequence, the states of each transistor are as follows: the first transistor T1, the second transistor T2, the seventh transistor T7, and the eighth transistor T8 are all off, while the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the ninth transistor T9, and the tenth transistor T10 are all on. Among them, the ninth transistor T9 is turned on at the third node N3 because the second clock signal CKE2 is at a low potential and the pulse signal STE is at a high potential, and the third transistor T3 is turned on when the negative voltage signal VEE is written to the third node N3 at a low potential. The first transistor T1 is turned off at the first node N1 because the first clock signal CKE1 is at a high potential, and the sixth transistor T6 is turned on when the first node N1 remains at a low potential from the previous moment. The first clock signal CKE1 goes high, causing T2 to turn off. The second node N2 turns on the fourth transistor T4 because the first node N1 goes low. The positive voltage signal VDD goes high, causing the seventh transistor T7 to turn off. Finally, the output voltage signal Eout outputs the negative voltage signal VEE at a low level.

[0073] Figure 6 is a schematic diagram of the conduction state of the shift register unit under the second timing of the first embodiment of the present invention. Figure 7 is a timing diagram of the shift register unit under the second timing of the first embodiment of the present invention. As shown in Figures 6 and 7, when the shift register unit of the first embodiment of the present invention is in the second timing, the states of each transistor are as follows: the first transistor T1, the second transistor T2, the third transistor T3, the fifth transistor T5, the seventh transistor T7, and the tenth transistor T10 are all turned on, while the fourth transistor T4, the sixth transistor T6, the eighth transistor T8, and the ninth transistor T9 are all turned off. Among them, the eighth transistor T8 and the ninth transistor T9 are turned off due to the high potential of the second clock signal CKE2 and the pulse signal STE at the third node N3, and the third node N3 maintains the low potential of the previous moment, while the third transistor T3 is turned on. The first transistor T1 is turned on due to the low potential of the first clock signal CKE1, and the sixth transistor T6 is turned off when the pulse signal STE is written to the high potential. The second node N2 is activated by the low potential of the first clock signal CKE1, which turns on the second transistor T2. Because both the second and third transistors T3 are activated, a negative voltage signal VEE is written to the second node N2 at a low potential, and the seventh transistor T7 is activated. The output voltage signal Eout outputs a positive voltage signal VDD at a high potential.

[0074] Figure 8 is a schematic diagram of the conduction state of the shift register unit in the third timing sequence of the first embodiment of the present invention. Figure 9 is a timing diagram of the shift register unit in the third timing sequence of the first embodiment of the present invention. As shown in Figures 8 and 9, when the shift register unit of the first embodiment of the present invention is in the third timing sequence, the states of each transistor are as follows: the third transistor T3, the fifth transistor T5, the seventh transistor T7, the ninth transistor T9, and the tenth transistor T10 are all turned on, while the first transistor T1, the second transistor T2, the fourth transistor T4, the sixth transistor T6, and the eighth transistor T8 are all turned off. Specifically, the ninth transistor T9 is turned on at the third node N3 due to the low potential of the second clock signal CKE2, and the third transistor T3 is turned on when the negative voltage signal VEE is written to the third node N3. The first transistor T1 is turned off at the first node N1 due to the high potential of the first clock signal CKE1, and the sixth transistor T6 is turned off when the first node N1 remains at the high potential of the previous moment. The second transistor T2 is turned off at the second node N2 due to the high potential of the first clock signal CKE1, and the seventh transistor T7 is turned on when the second node N2 remains at the low potential of the previous moment. The output voltage signal Eout outputs a positive voltage signal VDD at a high potential.

[0075] Figure 10 is a schematic diagram of the conduction state of the shift register unit under the fourth timing sequence of the first embodiment of the present invention. Figure 11 is a timing diagram of the shift register unit under the fourth timing sequence of the first embodiment of the present invention. As shown in Figures 10 and 11, when the shift register unit of the first embodiment of the present invention is in the fourth timing sequence, the states of each transistor are as follows: the first transistor T1, the second transistor T2, the third transistor T3, the fifth transistor T5, the seventh transistor T7, and the tenth transistor T10 are all turned on, while the fourth transistor T4, the sixth transistor T6, the eighth transistor T8, and the ninth transistor T9 are all turned off. Among them, the third node N3 is turned off because the second clock signal CKE2 / pulse signal STE is at a high potential, causing the eighth transistor T8 and the ninth transistor T9 to be turned off, the third node N3 remains at a low potential from the previous moment, and the third transistor T3 is turned on. The first node N1 is turned on because the first clock signal CKE1 is at a low potential, and the sixth transistor T6 is turned off when the write pulse signal STE is at a high potential. Because the first clock signal CKE1 is low, transistor T2 turns on at node N2. With transistors T2 and T3 also on, a negative voltage signal VEE is written to node N2 at a low level, and transistor T7 turns on. The output voltage signal Eout outputs a positive voltage signal VDD at a high level.

[0076] Figure 12 is a schematic diagram of the conduction state of the shift register unit under the fifth timing sequence of the first embodiment of the present invention. Figure 13 is a timing diagram of the shift register unit under the fifth timing sequence of the first embodiment of the present invention. As shown in Figures 12 and 13, when the shift register unit of the first embodiment of the present invention is in the fifth timing sequence, the states of each transistor are as follows: the third transistor T3, the fifth transistor T5, the seventh transistor T7, the ninth transistor T9, and the tenth transistor T10 are all turned on, while the first transistor T1, the second transistor T2, the fourth transistor T4, the sixth transistor T6, and the eighth transistor T8 are all turned off. Among them, the ninth transistor T9 is turned on at the third node N3 due to the low potential of the second clock signal CKE2, and the third transistor T3 is turned on when the negative voltage signal VEE is written to the third node N3. The first transistor T1 is turned off at the first node N1 due to the high potential of the first clock signal CKE1, and the first node N1 remains at the high potential of the previous moment, while the sixth transistor T6 is turned off. The second transistor T2 is turned off at the second node N2 due to the high potential of the first clock signal CKE1, and the second node N2 remains at the low potential of the previous moment, while the seventh transistor T7 is turned on. The output voltage signal Eout outputs a positive voltage signal VDD at a high potential.

[0077] Figure 14 is a schematic diagram of the conduction state of the shift register unit under the sixth timing sequence of the first embodiment of the present invention. Figure 15 is a timing diagram of the shift register unit under the sixth timing sequence of the first embodiment of the present invention. As shown in Figures 14 and 15, when the shift register unit of the first embodiment of the present invention is in the sixth timing sequence, the states of each transistor are as follows: the first transistor T1, the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the eighth transistor T8, and the tenth transistor T10 are all turned on, while the third transistor T3, the seventh transistor T7, and the ninth transistor T9 are all turned off. Among them, the ninth transistor T9 is turned off at the third node N3 due to the high potential of the second clock signal CKE2 and the low potential of the pulse signal STE, and the eighth transistor T8 is turned on. The positive voltage signal VDD is written to the node at a high potential, which turns off the third transistor T3. The first transistor T1 is turned on at the first node N1 due to the low potential of the first clock signal CKE1 and the low potential of the pulse signal STE, and the sixth transistor T6 is turned on. The second node N2 is turned off by the third transistor T3, and the second node N2 is turned on by the fourth transistor T4 due to the low potential of the first node N1. This writes a positive voltage signal VDD to a high potential, causing the seventh transistor T7 to turn off. The output voltage signal Eout outputs a negative voltage signal VEE to a low potential.

[0078] Figure 16 is a schematic diagram of the conduction state of the shift register unit under the seventh timing sequence of the first embodiment of the present invention. Figure 17 is a timing diagram of the shift register unit under the seventh timing sequence of the first embodiment of the present invention. As shown in Figures 16 and 17, when the shift register unit of the first embodiment of the present invention is in the seventh timing sequence, the states of each transistor are as follows: the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the eighth transistor T8, the ninth transistor T9, and the tenth transistor T10 are all turned on, while the first transistor T1, the second transistor T2, and the seventh transistor T7 are all turned off. Among them, the third node N3 is turned on because the second clock signal CKE2 / pulse signal STE is at a low potential, causing the eighth transistor T8 and the ninth transistor T9 to turn on. The third node N3 is turned on because the second clock signal CKE2 / negative voltage signal VEE is at a low potential. The first node N1 is turned off because the first clock signal CKE1 is at a high potential, and the first node N1 remains at a low potential from the previous moment, causing the sixth transistor T6 to turn on. Because the first clock signal CKE1 is at a high potential, the second transistor T2 is turned off at the second node N2. Because the first node N1 is at a low potential, the fourth transistor T4 is turned on at the second node N2, writing a positive voltage signal VDD at a high potential. The seventh transistor T7 is turned off, and the output voltage signal Eout outputs a negative voltage signal VEE at a low potential.

[0079] After this point, the circuit will repeat timing sequence 6 and timing sequence 7 until the pulse signal STE reaches a high level again, and then re-enter the first timing sequence of the next round, thus cycling in this way.

[0080] Figure 18 is a circuit diagram of a shift register according to a second embodiment of the present invention. As shown in Figure 18, the present invention also provides a shift register, including: a plurality of cascaded shift register units as described above. The input voltage signal IN of the first-stage shift register unit is a pulse signal STE, and the input voltage signal IN of the remaining shift register units is the output voltage signal Eout of the previous-stage shift register unit, but is not limited thereto.

[0081] In one optional embodiment, the waveforms of the first clock signal CKE1 and the second clock signal CKE2 are the same, and the first clock signal CKE1 is 1 / 2 clock signal cycle ahead of the second clock signal CKE2 in phase, but this is not a limitation.

[0082] In one alternative embodiment, the duty cycle of the first clock signal CKE1 and the duty cycle of the second clock signal CKE2 are both 75%, but this is not a limitation.

[0083] In one alternative embodiment, the timing combination of a high level within one cycle of the pulse signal STE and the falling edge of that high level is aligned with two adjacent cycles of the first clock signal CKE1, but is not limited thereto.

[0084] In one alternative embodiment, the first clock signal CKE1 is triggered to a low level when the pulse signal STE is triggered to a high level, but this is not a limitation.

[0085] In an optional embodiment, the system further includes a clock signal generating unit for generating a first clock pulse signal and a second clock pulse signal whose phases differ sequentially by 1 / 2 signal period. The first clock signal and the second clock signal in the [2n+1]th stage shift register unit are respectively the first clock pulse signal and the second clock pulse signal generated by the clock signal generating unit. The first clock signal and the second clock signal in the [2n+2]th stage shift register unit are respectively the second clock pulse signal and the first clock pulse signal generated by the clock signal generating unit, where n is a natural number, but not limited to this.

[0086] This embodiment also provides a display device, such as an OLED panel, including the pixel driving circuit described above. The display device of the present invention incorporates the structural features, techniques, and effects of the pixel driving circuit described above, which will not be repeated here.

[0087] In summary, the shift register unit, shift register, and display device of the present invention can solve the output abnormality problem caused by the mutual restraint relationship between the third transistor and the seventh transistor in the scanning circuit of the prior art, and optimize the voltage fluctuation problem of the second node.

[0088] The above description, in conjunction with specific optional embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A shift register unit, characterized in that, include: The first transistor (T1) is used to switch the current path between the input voltage signal (IN) and the fifth node (N5) in response to the voltage signal of the first clock signal (CKE1). The second transistor (T2) is used to switch the current path between the negative voltage signal (VEE) and the fourth node (N4) in response to the voltage signal of the first clock signal (CKE1). The third transistor (T3) is used to switch the current path between the fourth node (N4) and the second node (N2) in response to the voltage signal of the sixth node (N6); The fourth transistor (T4) is used to switch the current path between the positive voltage signal (VDD) and the second node (N2) in response to the voltage signal of the fifth node (N5); The fifth transistor (T5) is used to switch the current path between the first node (N1) and the fifth node (N5) in response to the voltage signal of the negative voltage signal (VEE); The sixth transistor (T6) is used to switch the current path between the negative voltage signal (VEE) and the output voltage signal (Eout) in response to the voltage signal of the first node (N1); The seventh transistor (T7) is used to switch the current path between the positive voltage signal (VDD) and the output voltage signal (Eout) in response to the voltage signal of the second node (N2); The eighth transistor (T8) is used to switch the current path between the second clock signal (CKE2) and the third node (N3) in response to the voltage signal of the input voltage signal (IN); The ninth transistor (T9) is used to switch the current path between the negative voltage signal (VEE) and the third node (N3) in response to the voltage signal of the second clock signal (CKE2). The tenth transistor (T10) is used to switch the current path between the third node (N3) and the sixth node (N6) in response to the voltage signal of the negative voltage signal (VEE); The first capacitor (C1) is coupled between the first node (N1) and the output voltage signal (Eout); A second capacitor (C2) is coupled between the second node (N2) and the positive voltage signal (VDD); and The third capacitor (C3) is coupled between the first clock signal (CKE1) and the sixth node (N6).

2. The shift register unit as described in claim 1, characterized in that, The first transistor (T1), the second transistor (T2), the third transistor (T3), the fourth transistor (T4), the fifth transistor (T5), the sixth transistor (T6), the seventh transistor (T7), the eighth transistor (T8), the ninth transistor (T9), and the tenth transistor (T10) are all N-type thin-film transistors.

3. The shift register unit as described in claim 1, characterized in that, The first transistor (T1), the second transistor (T2), the third transistor (T3), the fourth transistor (T4), the fifth transistor (T5), the sixth transistor (T6), the seventh transistor (T7), the eighth transistor (T8), the ninth transistor (T9), and the tenth transistor (T10) are all P-type thin-film transistors.

4. A shift register, characterized in that, include: Multiple cascaded shift register units as described in claim 1; The input voltage signal (IN) of the first-stage shift register unit is a pulse signal (STE), and the input voltage signal (IN) of the remaining shift register units is the output voltage signal (Eout) of the previous-stage shift register unit.

5. The shift register as described in claim 4, characterized in that, The first clock signal (CKE1) and the second clock signal (CKE2) have the same waveform, and the first clock signal (CKE1) is 1 / 2 clock signal cycle ahead of the second clock signal (CKE2) in phase.

6. The shift register as described in claim 5, characterized in that, The duty cycle of the first clock signal (CKE1) and the duty cycle of the second clock signal (CKE2) are both 75%.

7. The shift register as described in claim 5, characterized in that, The timing combination of the high level of the pulse signal (STE) within one cycle and the falling edge of that high level is aligned with the timing of two adjacent cycles of the first clock signal (CKE1).

8. The shift register as described in claim 5, characterized in that, When the pulse signal (STE) goes high, the first clock signal (CKE1) goes low.

9. The shift register as described in claim 5, characterized in that, Also includes: A clock signal generating unit is used to generate a first clock pulse signal and a second clock pulse signal whose phases differ by 1 / 2 signal period. Wherein, the first clock signal and the second clock signal in the [2n+1]th stage shift register unit are the first clock pulse signal and the second clock pulse signal generated by the clock signal generating unit, respectively; The first clock signal and the second clock signal in the [2n+2]th stage shift register unit are the second clock pulse signal and the first clock pulse signal generated by the clock signal generation unit, respectively, where n is a natural number.

10. A display device, characterized in that, include: The shift register as described in claim 4.

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