Data processing method and apparatus

Abstract

Provided in the embodiments of the present application are a data processing method and an apparatus. The method comprises: a first device acquiring N digital signals, N being a positive integer; then, the first device performing first processing on the basis of the N digital signals to obtain M first analog signals, and performing second processing on the basis of the N digital signals to obtain N second analog signals, M being a positive integer less than or equal to N; and then, on the basis of the M first analog signals and the N second analog signals, obtaining N analog signals. In the method, during the quantization process of converting the digital signals into the analog signals, a transmitting end may perform two types of processing on the N digital signals to separately obtain quantization results and then, on the basis of the quantization results obtained by means of the two types of processing, finally obtain the N analog signals. It can be seen therefrom that the method combines different processing means to quantize the signals, thereby improving the quantization accuracy of the signals, and further improving system performance.

Description

A data processing method and apparatus

[0001] Cross-reference to related applications

[0002] This application claims priority to Chinese Patent Application No. 202411227702.3, filed on September 2, 2024, entitled "A Data Processing Method and Apparatus", the entire contents of which are incorporated herein by reference. Technical Field

[0003] This application relates to the field of communication technology, and in particular to a data processing method and apparatus. Background Technology

[0004] A digital-to-analog converter (DAC) acts as a bridge between digital circuits and analog radio frequency circuits, and its performance directly impacts the overall system performance. Large-scale antenna array systems with all-digital channels typically employ hundreds or thousands of antennas. Due to the all-digital architecture, the number of DACs is the same as the number of antennas, reaching an astonishing hundreds or thousands. On the other hand, the power consumption and accuracy of DACs increase exponentially. Therefore, considering system power consumption and cost, large-scale antenna array systems with all-digital channels usually only deploy low-precision DACs.

[0005] Typically, one-bit DACs offer the lowest accuracy due to their low power consumption and cost, making it feasible to equip large-scale antenna array systems with a significant number of one-bit DACs. However, using one-bit DACs results in severe loss of signal amplitude information after quantization, leading to large errors and significantly impacting system performance (e.g., transmission rate in communication systems). Therefore, effectively improving system performance while processing signals with lower power consumption and cost has become a pressing issue. Summary of the Invention

[0006] This application proposes a data processing method and apparatus that can process signals with low power consumption and low cost while effectively improving system performance.

[0007] In a first aspect, embodiments of this application provide a data processing method. This method can be applied to a transmitting node, which may be a first device, or a component of the first device (e.g., a processor, chip, or chip system), or a logic node, logic module, or software capable of implementing all or part of the functions of the first device, or a device used in conjunction with the first device. Taking the application of this method to a first device as an example, the method includes: the first device acquiring N digital signals; N being a positive integer; the first device performing a first processing based on the N digital signals to obtain M first analog signals, and performing a second processing based on the N digital signals to obtain N second analog signals; M being a positive integer less than or equal to N; and the first device further obtaining N analog signals based on the M first analog signals and the N second analog signals.

[0008] For example, the first device can be a device in wide area communication (such as a base station or terminal device) or a device in local area communication (such as an access point (AP) or station (STA)).

[0009] In this application, during the quantization process of converting digital signals into analog signals, the transmitting end can obtain quantization results from N digital signals through two different processing methods. Then, based on the quantization results obtained from these two processing methods, N analog signals are finally obtained. It can be seen that this method combines different processing methods to quantize signals, thereby improving the quantization accuracy of the signals and thus improving system performance.

[0010] For example, the method in this application embodiment can convert / quantize N digital signals into N analog signals by combining / cooperating high-precision DAC and low-precision DAC.

[0011] In one possible implementation, the method further includes: a first device sorting the N digital signals according to their amplitude values ​​to obtain sorted N digital signals; then, the first device grouping the sorted N digital signals into M groups, each group including at least one digital signal; and the first device then obtaining a target digital signal for each group based on the at least one digital signal.

[0012] With this implementation, the transmitting end can group digital signals with similar amplitudes into one group based on the amplitude values ​​of N digital signals, thereby obtaining one or more groups. Then, based on at least one digital signal in each group, the target digital signal corresponding to each group is obtained, that is, the common amplitude of the signals in each group is determined, so as to reduce the quantization error between signals in the group.

[0013] In one possible implementation, the first device performs a first processing based on N digital signals to obtain M first analog signals, including: the first device performs a first processing on the aforementioned M grouped target digital signals to obtain M first analog signals.

[0014] This implementation method can effectively convert the target digital signals corresponding to each group into corresponding analog signals, and the quantization error of the signals within each group is low.

[0015] Based on the steps of the first device performing the first processing described above, in one possible implementation, the first device performs a second processing based on N digital signals to obtain N second analog signals, including: the first device performs a second processing on the sorted N digital signals to obtain N second analog signals.

[0016] With this implementation, the transmitting end can effectively obtain N second analog signals; these N second analog signals can be used as the final symbol (positive or negative) information and assigned to the corresponding first analog signal (i.e., the N second analog signals are multiplied with the corresponding first analog signal respectively) to finally obtain N analog signals with low quantization error.

[0017] Furthermore, in one possible implementation, the first device obtains N analog signals based on M first analog signals and N second analog signals, including: the first device first determines the first analog signals corresponding to the sorted N digital signals according to the group to which the sorted N digital signals belong; then, based on the first analog signals corresponding to the sorted N digital signals, it determines the first analog signals corresponding to the N second analog signals; further, the first device multiplies the N second analog signals with their corresponding first analog signals to obtain the N analog signals. Through this implementation, the first device can effectively obtain N analog signals with low quantization error.

[0018] Based on the above implementation, in one possible implementation, the method further includes: the first device performs sorting recovery processing on the N analog signals according to the sorting information of the N digital signals to obtain the sorted N analog signals; and then the first device sends the sorted N analog signals to the second device.

[0019] This implementation method can effectively solve the problem of data order change caused by the sorting and grouping of N digital signals, so as to ensure that the order of the N analog signals transmitted by the first device is consistent with the order when the first device receives the N digital signals.

[0020] In another possible implementation of the first device performing the first processing step described above, the first device performs a second processing based on N digital signals to obtain N second analog signals, including: the first device performs a second processing on the N digital signals to obtain N second analog signals.

[0021] Compared to the first device described above, which performs a second process on the sorted N digital signals to obtain N analog signals, in this implementation, the first device does not need to perform a subsequent step of restoring the order.

[0022] In this implementation, the transmitting end converts the original N digital signals into N second analog signals. These N second analog signals can be used as the final symbol (positive or negative) information and assigned to the corresponding first analog signals (i.e., the N second analog signals are multiplied with the corresponding first analog signals respectively) to finally obtain N analog signals with low quantization error.

[0023] Furthermore, in one possible implementation, the first device obtains N analog signals based on M first analog signals and N second analog signals, including: the first device determining the group to which the N digital signals belong based on the sorting information of the N digital signals; then determining the first analog signals corresponding to the N digital signals based on the group to which the N signals belong; next, determining the first analog signals corresponding to the N second analog signals based on the first analog signals corresponding to the N digital signals; and finally, multiplying the N second analog signals with their corresponding first analog signals to obtain the N analog signals. Through this implementation, the first device can effectively obtain N analog signals with low quantization error.

[0024] In one possible implementation, the method further includes: the first device sending N analog signals to the second device. Through this implementation, the first device completes the transmission of N analog signals.

[0025] Secondly, embodiments of this application also provide an apparatus that can be used to perform the method of the first aspect. The apparatus can be a first device, or a component in the first device (e.g., a chip, a chip system, or a circuit), or a logic module or software corresponding to the first device, or an apparatus that can be used in conjunction with the first functional network element.

[0026] In one possible implementation, the device may include modules or units that perform the methods / operations / steps / actions described in the first aspect. These modules or units may be hardware circuits, software, or a combination of hardware circuits and software.

[0027] In one possible implementation, the device may include: a communication module (also referred to as a communication unit), a first processing module (also referred to as a first processing unit), a second processing module (also referred to as a second processing unit), and a third processing module (also referred to as a third processing unit).

[0028] The communication module is used to acquire N digital signals; N is a positive integer.

[0029] The first processing module is used to perform a first processing on the N digital signals to obtain M first analog signals; M is a positive integer less than or equal to N;

[0030] The second processing module is used to perform a second processing on the N digital signals to obtain N second analog signals;

[0031] The third processing module is used to obtain N analog signals based on the M first analog signals and the N second analog signals.

[0032] In one possible design, the third processing module can also be used to: sort the N digital signals according to their amplitude values ​​to obtain sorted N digital signals; group the sorted N digital signals into M groups, each group including at least one digital signal; and obtain a target digital signal for each group based on the at least one digital signal.

[0033] In one possible design, when the first processing module performs the first processing based on the N digital signals to obtain M first analog signals, it can specifically be used to: perform the first processing on the M grouped target digital signals to obtain the M first analog signals.

[0034] In one possible design, the second processing module, when performing the second processing based on the N digital signals to obtain N second analog signals, can specifically be used to: perform the second processing on the sorted N digital signals to obtain the N second analog signals.

[0035] In one possible design, when the third processing module obtains N analog signals based on the M first analog signals and the N second analog signals, it can specifically be used to: determine the first analog signal corresponding to the sorted N digital signals according to the group to which the sorted N digital signals belong; determine the first analog signal corresponding to the N second analog signals according to the first analog signal corresponding to the sorted N digital signals; and multiply the N second analog signals with their corresponding first analog signals to obtain the N analog signals.

[0036] In one possible design, the third processing module can also be used to: perform sorting recovery processing on the N analog signals according to the sorting information of the N digital signals to obtain sorted N analog signals; the communication module is also used to send the sorted N analog signals.

[0037] In one possible design, the second processing module, when performing the second processing on the N digital signals to obtain N second analog signals, can specifically be used to: perform the second processing on the N digital signals to obtain the N second analog signals.

[0038] In one possible design, the third processing module, when obtaining N analog signals based on the M first analog signals and the N second analog signals, may specifically be used to: determine the group to which the N digital signals belong based on the sorting information of the N digital signals; determine the first analog signal corresponding to the N digital signals based on the group to which the N signals belong; determine the first analog signal corresponding to the N second analog signals based on the first analog signal corresponding to the N digital signals; and multiply the N second analog signals with their corresponding first analog signals to obtain the N analog signals.

[0039] In one possible design, the communication module is also used to transmit the N analog signals.

[0040] Thirdly, an apparatus is provided, including a processor and an interface circuit, the interface circuit being configured to receive signals from other devices outside the apparatus and transmit them to the processor or to send signals from the processor to other devices outside the apparatus, the processor being configured to implement the methods of the first aspect and any of the possible implementations thereof via logic circuitry or execution code instructions.

[0041] Fourthly, a computer-readable storage medium is provided that stores a computer program or instructions which, when executed by a computer, implement the methods described in the first aspect and any of the possible implementations thereof.

[0042] Fifthly, a computer program product storing instructions is provided, which, when executed on a computer, implement the methods described in the first aspect and any of the possible implementations thereof.

[0043] Sixthly, a chip system is provided, comprising a processor and potentially a memory, for implementing the methods of the first aspect and any of the possible embodiments described above. The chip system may be composed of chips or may include chips and other discrete devices.

[0044] In a seventh aspect, a communication system is provided, the communication system including the transmitting node described in the first aspect.

[0045] It should be noted that the technical effects that can be achieved by any of the second to seventh aspects or any of the second to seventh aspects can be referred to the description of the technical effects that can be achieved by any of the first aspects and any of the first aspects, which will not be repeated here. Attached Figure Description

[0046] Figure 1 is a schematic diagram of a communication system architecture to which the method of this application embodiment can be applied;

[0047] Figure 2A is a schematic diagram of a digital signal quantization process to which the method of the embodiments of this application can be applied;

[0048] Figure 2B is a schematic diagram of a digital audio quantization process to which the method of the embodiments of this application can be applied;

[0049] Figure 3A is a schematic flowchart of a data processing method provided in an embodiment of this application;

[0050] Figure 3B is a schematic diagram of an exemplary processing flow of the method according to an embodiment of this application;

[0051] Figure 4A is a schematic diagram of the method flow of Embodiment 1 of this application;

[0052] Figure 4B is a schematic diagram of the processing flow of Embodiment 1 of this application;

[0053] Figure 5A is a schematic flowchart of the method of Embodiment 2 of this application;

[0054] Figure 5B is a schematic diagram of the processing flow of Embodiment 2 of this application;

[0055] Figure 6 is a schematic diagram of the structure of a device according to an embodiment of this application;

[0056] Figure 7 is a schematic diagram of another device according to an embodiment of this application;

[0057] Figure 8 is a schematic diagram of a chip device structure according to an embodiment of this application. Detailed Implementation

[0058] The scenarios described in the embodiments of this application are for the purpose of more clearly illustrating the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions provided in the embodiments of this application. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0059] To better understand the solutions provided in the embodiments of this application, some terms, concepts, or processes involved in the embodiments of this application will be explained below. It should be noted that these explanations are intended to make the embodiments of this application easier to understand and should not be regarded as limiting the scope of protection claimed by this application.

[0060] (1) Digital signals: Digital signals are discrete, and their values ​​can only take on a finite number of discrete values. They are usually represented using binary, which contains only two states: 0 and 1. For example, the signals used in digital audio, digital images, and computer data transmission are all digital signals.

[0061] (2) Analog signals: Analog signals are continuous, and their values ​​can take any value within a certain range. For example, continuously changing signals such as sound, light intensity, and temperature are all analog signals.

[0062] (3) Quantization: In the embodiments of this application, the meaning of "quantization" is not limited to the meaning in the field of digital signal processing. The "quantization" of the signal in this application can be equivalent to the meaning of "conversion" or "processing" of the signal.

[0063] For example, the process of converting an analog signal into a digital signal and the process of converting a digital signal into an analog signal can both be called quantization. In the embodiments of this application, "signal quantization" can also be replaced by terms such as "signal conversion".

[0064] (4) Switching Network (Connection Network): This network can include multiple inputs and multiple outputs. The switching network can realize the connection relationship between inputs and outputs. For example, when the first input is connected to the third output, the first input is disconnected from other outputs.

[0065] The correspondence between multiple inputs can be one-to-one, many-to-one, or one-to-many, without any specific limitations.

[0066] (5) Reverse connection network: In this embodiment of the application, the reverse connection network can also be understood as a switch network. That is, through the switch network (or reverse connection network), the connection relationship between input and output can be realized in a certain order, which is equivalent to sorting (or reversing) the input signals / data and then outputting them.

[0067] (6) All-digital channel: That is, one antenna is connected to one radio frequency channel and equipped with a digital-to-analog converter (DAC). The number of antennas is the same as the number of radio frequency channels and the number of DACs.

[0068] It should be noted that in the embodiments of this application, "at least one" refers to one or more, and "more than one" refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can represent: a, b, c, a and b, a and c, b and c, or a and b and c, where a, b, and c can be single or multiple.

[0069] Furthermore, unless otherwise stated, the ordinal numbers such as "first" and "second" mentioned in the embodiments of this application are used to distinguish multiple objects and are not used to limit the size, content, order, timing, priority, or importance of the multiple objects. For example, "first device" and "second device" are only used to distinguish different devices and do not indicate that the two devices have different priorities or importance.

[0070] It should be noted that, in this application, the terms "exemplary" or "for example" are used to indicate that something is being described as an example, illustration, or illustration. Any embodiment or design described as "exemplary" or "for example" in this application should not be construed as being more preferred or advantageous than other embodiments or design solutions. Specifically, the use of terms such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0071] The terms "comprising" and "having," and any variations thereof, used in the following description of embodiments of this application are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but may optionally include other steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or devices. Furthermore, the term "for indicating" used in the description of embodiments of this application can include both direct and indirect indication. When describing an indication message for indicating A, it may include whether the indication message directly indicates A or indirectly indicates A, but does not necessarily mean that the indication message carries A.

[0072] In this application, "send" and "receive" refer to the direction of information / data / signal transmission. For example, "send information to XX" can be understood as the destination of the information being XX, and "send information" can include direct transmission or indirect transmission through other units or modules. "Receive information from YY" can be understood as the source of the information being YY, and "receive information" can include direct reception from YY or indirect reception from YY through other units or modules. Furthermore, "send" can also be understood as the "output" of a chip interface, and "receive" can be understood as the "input" of a chip interface. In other words, "send" or "receive" can occur between nodes / devices, such as a base station and a terminal transmitting or receiving data via an air interface. "Send" or "receive" can also occur within a device, such as between components, modules, chips, software modules, or hardware modules within the device via a bus, wiring, or interface.

[0073] The preceding text introduced some terms, concepts, or processes involved in the embodiments of this application. The following text introduces the application scenarios and devices involved in the embodiments of this application.

[0074] Digital-to-analog converters (DACs) act as a bridge between digital and analog radio frequency (RF) circuits, and their performance directly impacts the overall system performance. Large-scale antenna array (MLA) systems with all-digital channels typically employ hundreds or thousands of antennas. Due to the all-digital architecture, the number of DACs is the same as the number of antennas, reaching an astonishing hundreds or thousands. On the other hand, the power consumption and accuracy of DACs increase exponentially. Therefore, considering system power consumption and cost, all-digital MLA systems usually only deploy low-precision DACs.

[0075] Typically, one-bit DACs offer the lowest accuracy due to their low power consumption and cost, making it feasible to equip large-scale antenna array systems with a significant number of one-bit DACs. However, using one-bit DACs results in severe loss of signal amplitude information and significant errors after quantization, severely impacting system performance (e.g., transmission rate in communication systems). Therefore, effectively improving system performance while processing signals with lower power consumption and cost has become a pressing issue.

[0076] Therefore, this application proposes a data processing method and apparatus that can process signals with low power consumption and cost while effectively improving system performance. The method and apparatus are based on the same inventive concept. Since the principles by which the method and apparatus solve the problem are similar, implementations of the apparatus and method can be mutually referenced, and repeated details will not be elaborated further.

[0077] The technologies provided in this application can be applied to various communication systems, such as Universal Mobile Telecommunications System (UMTS), Wireless Local Area Network (WLAN), Wireless Fidelity (Wi-Fi) systems, Internet of Things (IoT), Narrow Band Internet of Things (NB-IoT), 4th generation (4G) mobile communication systems (such as Long Term Evolution (LTE) systems), 5th generation (5G) mobile communication systems (such as New Radio (NR) systems), and future communication systems. They can also be LTE and NR hybrid architectures, or new communication systems emerging in future communication developments. Communication systems can also include machine-to-machine (M2M) networks, machine-type communication (MTC) networks, or other networks.

[0078] Exemplarily, Figure 1 illustrates a possible, non-limiting communication system architecture to which embodiments of this application may be applied. As shown in Figure 1, the communication system 1000 includes a radio access network (RAN) 100 and a core network (CN) 200. Optionally, the communication system 1000 may also include an Internet 300. The RAN 100 includes at least one network device (110a and 110b in Figure 1, collectively referred to as 110) and at least one terminal device (120a-120j in Figure 1, collectively referred to as 120). The RAN 100 may also include other RAN nodes, such as wireless relay devices and / or wireless backhaul devices (not shown in Figure 1). The terminal device 120 is wirelessly connected to the network device 110. The network device 110 is connected to the core network 200 wirelessly or via a wired connection. The core network equipment in core network 200 and the network equipment 110 in RAN 100 can be different physical devices, or they can be the same physical device that integrates core network logical functions and radio access network logical functions.

[0079] RAN 100 can be a cellular system related to the 3rd Generation Partnership Project (3GPP), such as a 4th generation (4G), 5th generation (5G) mobile communication system, or an evolutionary system beyond 5G or a future mobile communication system. RAN 100 can also be an open RAN (O-RAN or ORAN), a cloud radio access network (CRAN), or a WiFi system. RAN 100 can also be a communication system that integrates two or more of the above systems.

[0080] It is understood that Figure 1 only shows one possible communication system architecture that can be applied to the embodiments of this application, and other devices may also be included in the communication system architecture in other possible scenarios.

[0081] Network device 110 is an entity on the network side used for transmitting or receiving signals. In this embodiment, the network device can be a device in a wireless network. Network device 110 helps terminal devices achieve wireless access, such as connecting a terminal to a RAN node in a wireless network. Multiple network devices 110 in the communication system 1000 can be nodes of the same type or different types. In some scenarios, the roles of network device 110 and terminal device 120 are relative. For example, network element 120i in Figure 1 can be a helicopter or drone, which can be configured as a mobile base station. For terminal devices 120j accessing RAN 100 through network element 120i, network element 120i is a base station; but for base station 110a, network element 120i is a terminal device. Network device 110 and terminal device 120 are sometimes referred to as communication devices. For example, network elements 110a and 110b in Figure 1 can be understood as communication devices with base station functions, and network elements 120a-120j can be understood as communication devices with terminal device functions.

[0082] In one possible scenario, network equipment can be a base station, an evolved NodeB (eNodeB), a transmission reception point (TRP), a transmission point (TP), a next-generation NodeB (gNB), a base station in a future mobile communication system, a future base station in a future mobile communication system, an access point (AP) in a satellite or WiFi system, an integrated access and backhaul (IAB) node, or network equipment in a mobile switching center non-terrestrial network (NTN) communication system, i.e., it can be deployed on a high-altitude platform or satellite, etc. Network equipment can be a macro base station (as shown in Figure 1, 110a), a micro base station or indoor station (as shown in Figure 1, 110b), a relay node or donor node, or a radio controller in a CRAN scenario. Network equipment can also act as a base station in device-to-device (D2D) communication, vehicle-to-everything (V2X) communication, drone communication, and machine-to-machine (M2M) communication. Optionally, network equipment can also be a server, wearable device, vehicle, or in-vehicle equipment, etc. For example, the access network equipment in vehicle-to-everything (V2X) technology can be a roadside unit (RSU). The network equipment can cover one or more cells.

[0083] In another possible scenario, multiple network devices collaborate to assist terminal devices in achieving wireless access, with each network device performing a portion of the base station's functions. For example, network devices can be central units (CUs), distributed units (DUs), CU-control plane (CPs), CU-user plane (UPs), or radio units (RUs). CUs and DUs can be separate entities or included in the same network element, such as a baseband unit (BBU). RUs can be included in radio equipment or radio units, such as remote radio units (RRUs), active antenna units (AAUs), or remote radio heads (RRHs). It is understood that network devices can be CU nodes, DU nodes, or devices comprising both CU and DU nodes. Furthermore, CUs can be classified as network devices in the access network (RAN) or the core network (CN), without limitation.

[0084] In one possible implementation, a radio access network (RAN) device (a type of network device) can be divided into a Control Unit (CU) and at least one Utility Unit (DU). The CU can be used to manage or control at least one DU, or it can be described as the CU being connected to at least one DU. This structure can separate the protocol layers of the RAN device in the communication system, with some protocol layers centrally controlled by the CU, and the remaining part or all of the protocol layer functions distributed in the DU, which is centrally controlled by the CU. Taking a gNB as an example, the protocol layers of a gNB include a radio resource control (RRC) layer, a service data adaptation protocol (SDAP) layer, a packet data convergence protocol (PDCP) layer, a radio link control (RLC) layer, a media access control (MAC) sublayer, and a physical layer. Exemplarily, the CU can be used to implement the functions of the RRC, SDAP, and PDCP layers, and the DU can be used to implement the functions of the RLC, MAC, and physical layers. This application does not specifically limit the protocol stacks included in the CU and DU.

[0085] For example, the CU in this embodiment can be further divided into one control plane (CU-CP) network element and multiple user plane (CU-UP) network elements. The CU-CP can be used for control plane management, and the CU-UP can be used for user plane data transmission. The interface between the CU-CP and CU-UP can be an E1 port. The interface between the CU-CP and DU can be an F1-C port for control plane signaling transmission. The interface between the CU-UP and DU can be an F1-U port for user plane data transmission. CU-UPs can be connected to each other via an Xn-U port for user plane data transmission.

[0086] For example, network devices and UEs can interact with RRC signaling through the RRC module. Network devices and UEs can interact with Media Access Control (MAC) control element (MAC CE) signaling through the MAC module. Network devices and UEs can interact with uplink / downlink control signaling, such as Physical Uplink Control Channel (PUCCH) / Physical Downlink Control Channel (PDCCH), and uplink / downlink data signaling, such as Physical Uplink Shared Channel (PUSCH) / Physical Downlink Shared Channel (PDSCH), through the PHY module.

[0087] Terminal equipment 120, also known as terminal, user equipment (UE), mobile station (MS), mobile terminal (MT), etc., is a device used to provide voice or data connectivity to users, and can also be an Internet of Things (IoT) device. For example, terminal equipment includes handheld devices with wireless connectivity, vehicle-mounted devices, etc. Currently, terminal devices can include: mobile phones, tablets, laptops, PDAs, mobile internet devices (MIDs), wearable devices (such as smartwatches, smart bracelets, pedometers, etc.), in-vehicle equipment (such as cars, bicycles, electric vehicles, airplanes, ships, trains, high-speed trains, etc.), satellite terminals, virtual reality (VR) devices, augmented reality (AR) devices, smart point-of-sale (POS) machines, customer-premises equipment (CPE), wireless terminals in industrial control, smart home devices (such as refrigerators, televisions, air conditioners, electricity meters, etc.), smart robots, robotic arms, workshop equipment, wireless terminals in autonomous driving, wireless terminals in telemedicine, wireless terminals in smart grids, wireless terminals in transportation safety, wireless terminals in smart cities, or wireless terminals in smart homes, and flying equipment (such as smart robots, hot air balloons, drones, airplanes), etc. Terminal devices can also be other devices with terminal functions; for example, a terminal device can also be a device that performs terminal functions in D2D communication. The terminal device can also be a terminal device that appears in the future evolution of PLMN, etc., and the embodiments of this application are not limited to this.

[0088] Furthermore, in this embodiment, the terminal device can also be a terminal device in an IoT system. IoT is an important component of future information technology development, and its main technical feature is connecting objects to networks through communication technology, thereby realizing an intelligent network of human-machine interconnection and machine-to-machine interconnection. In this embodiment, IoT technology can achieve massive connectivity, deep coverage, and low terminal power consumption through technologies such as narrowband (NB). The terminal device can also include sensors such as smart printers, train detectors, and gas station sensors, whose main functions include collecting data (for some terminal devices), receiving control information and downlink data from network devices, and transmitting uplink data to network devices by sending electromagnetic waves.

[0089] For example, the first device in this application embodiment may be a network device or a terminal device in the system architecture shown in FIG1.

[0090] The method of this application embodiment can be applied to the quantization process of converting digital signals into analog signals. In other words, the application scenarios of the method of this application embodiment can be, but are not limited to, DAC application scenarios. For example, the application scenarios applicable to this application embodiment may include: digital audio quantization transmission process, digital communication system base station transmitter signal quantization process, digital communication system terminal transmitter equipment signal quantization process, router transmitter signal quantization process, vehicle communication system transmitter signal quantization process, satellite communication system transmitter signal quantization process, etc.

[0091] For example, Figure 2A shows a schematic diagram of a quantization process of a transmitter signal to which the method of an embodiment of this application can be applied. Referring to the scenario shown in Figure 2A, the digital signal of the transmitter is quantized by the method provided in the embodiment of this application (e.g., the quantization of a mixed-precision DAC proposed in this application) to obtain a transmitted radio frequency analog signal. The transmitter can transmit the radio frequency analog signal in a way that is not limited to wired or wireless. Correspondingly, the receiver can receive the radio frequency analog signal transmitted by the transmitter in a wired or wireless manner.

[0092] Figure 2B illustrates a schematic diagram of a digital audio quantization process at a transmitting end, to which the method of an embodiment of this application can be applied. Referring to Figure 2B, the digital audio is quantized using the method provided in this embodiment (e.g., the quantization of a mixed-precision DAC proposed in this application) to obtain analog audio. Further, the analog audio is processed and / or transmitted.

[0093] The communication system architecture and application scenarios described in the embodiments of this application are for the purpose of more clearly illustrating the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions provided in the embodiments of this application. As those skilled in the art will know, with the evolution of communication systems and the emergence of new application scenarios (or business scenarios), the technical solutions provided in the embodiments of this application can also be applied to similar technical problems.

[0094] The terms "first device" and "second device" in this application will be described below.

[0095] In this document, the first device can be an entity capable of transmitting and / or receiving signals and having management functions. Exemplarily, the first device can be a network device (e.g., a base station), a master node, a grant (G) node, an access station (e.g., an AP or an AP multi-link device MLD), etc. Alternatively, the first device can be any type of terminal capable of transmitting and / or receiving signals. Exemplarily, the first device can be a terminal device, a slave node, a T node, or a site (e.g., a Non-AP STA or a Non-AP MLD). The terminal can be a machine-type communication user equipment or a cockpit domain controller (CDC), a fifth-generation mobile communication terminal, or other types of terminals, etc.

[0096] In the above, CDC can be abbreviated as vehicle infotainment system. Currently, in addition to traditional functions such as radio, music playback, and navigation, vehicle infotainment systems now have cellular communication capabilities (3G, 4G, etc.). They can be combined with the vehicle's controller area network (CAN)-bus (BUS) technology to enable information communication between people and vehicles, and between vehicles and the outside world, thereby enhancing user experience and providing service and safety-related functions.

[0097] In the above, master nodes and slave nodes refer to two types of nodes distinguished by their logical functions. The master node manages the slave nodes and has the function of allocating resources, being responsible for allocating resources to the slave nodes. The slave nodes communicate using the resources allocated by the master node according to its scheduling. Nodes can be various devices; for example, the master node could be a mobile phone, and the slave node could be a headset. The mobile phone and headset establish a communication connection to achieve data interaction. The mobile phone manages the headset, and the mobile phone has the function of allocating resources to the headset.

[0098] The above description of the "first device" is exemplary. As the communication scenarios or systems in which the technical solutions of the embodiments of this application are applied change, the first device may have other names, which will not be listed here. In this document, the second device is described in the same way as the first device, and will not be repeated here.

[0099] In the embodiments of this application, the "first device" can be either a sender or a receiver; the "second device" can also be either a sender or a receiver. In the following description, the "first device" as the sender and the "second device" as the receiver are used as examples to illustrate the scheme of the embodiments of this application. Furthermore, the "first device" can be replaced by "first communication device" or "transmitting device," etc., and the "second device" can be replaced by "second communication device" or "receiving device," etc.

[0100] It should be understood that the names of the various information (or data, signals, etc.) in the following processes in this application are merely examples. As communication technology evolves, the names of the various information (or data, signals, etc.) in the following processes may change. However, no matter how the names change, as long as their meaning is the same as the function or meaning of the information (or data, signals, etc.) in this application, they all fall within the protection scope of this application.

[0101] The technical solution of this application is described below with reference to specific embodiments.

[0102] This application provides a data processing method, which can be applied to, but is not limited to, the network architecture shown in Figure 1, and can be applied to, but is not limited to, the quantization process / scenario shown in Figures 2A and 2B. The method can be applied to a sending node (also called a data processing device), which can be a first device, a module of the first device (e.g., a processor, chip, or chip system), or a logic node, logic module, or software capable of implementing all or part of the functions of the first device. Furthermore, this application does not specifically limit the specific structure and number of the first and second devices in the method of this application embodiment, as long as communication can be performed by running a program that records the code of the method provided in this application embodiment. For ease of description, the first device is used as an example in the following description. The order of steps in the following processes is merely an example; in actual applications, the execution order of steps in each process can be adjusted, and all or part of the following steps can be adaptively executed.

[0103] Referring to Figure 3A, the method provided in this application embodiment may include the following steps:

[0104] S301A: The first device acquires N digital signals; N is a positive integer.

[0105] In this embodiment, the N digital signals can be digital signals to be quantized and transmitted at the transmitting end.

[0106] S302A: The first device performs a first processing based on N digital signals to obtain M first analog signals, and performs a second processing based on N digital signals to obtain N second analog signals; M is a positive integer less than or equal to N.

[0107] In one possible implementation, the method may further include: a first device sorting the N digital signals according to their amplitude values ​​to obtain sorted N digital signals; then grouping the sorted N digital signals into M groups, each group including at least one digital signal; and finally obtaining a target digital signal for each group based on the at least one digital signal. Optionally, this implementation can be performed after S301A and before S302A.

[0108] In this implementation, the transmitting end (i.e., the first device) can group digital signals with similar amplitudes into one group based on the amplitude values ​​of N digital signals, thereby obtaining one or more groups. Then, based on at least one digital signal in each group, the target digital signal corresponding to each group is obtained, that is, the common amplitude of the signals in each group is determined, so as to reduce the quantization error between signals in the group.

[0109] In this embodiment of the application, when the first device performs S302A (performs first processing based on N digital signals to obtain M first analog signals, and performs second processing based on N digital signals to obtain N second analog signals), it may include, but is not limited to, the following possible implementations:

[0110] Implementation Method 1:

[0111] In implementation method one, the first device performs a first process based on N digital signals to obtain M first analog signals. This can include: the first device performs a first process on M grouped target digital signals to obtain M first analog signals. Through this implementation method, the transmitting end (i.e., the first device) can effectively convert the target digital signals corresponding to each group into corresponding analog signals, and the quantization error within each group is low.

[0112] In one possible implementation, the first device can perform first processing on the M grouped target digital signals through a first processing module to obtain M first analog signals.

[0113] In this embodiment, the first processing module may be, but is not limited to, a high-precision DAC or a module with the processing capability of a high-precision DAC. For example, the first processing module may be a 4-bit or 5-bit DAC.

[0114] In the above, the first processing module may be located inside or outside the first device to perform the first processing corresponding to the first device. This application does not limit the specific location of the first processing module.

[0115] Furthermore, the first device performs a second processing on the N digital signals to obtain N second analog signals, which may include: the first device performing a second processing on the sorted N digital signals to obtain N second analog signals.

[0116] In one possible implementation, the first device can perform a second processing on the sorted N digital signals to obtain N second analog signals through a second processing module.

[0117] In the embodiments of this application, the second processing module may be, but is not limited to, a low-precision and low-overhead DAC or a module with the processing capability of a low-precision and low-overhead DAC. For example, the second processing module is a 1-bit DAC.

[0118] In the above, the second processing module can be located inside or outside the first device to perform the second processing corresponding to the first device. This application does not limit the specific location of the second processing module.

[0119] Implementation Method Two:

[0120] In implementation method two, the first device performs the first processing based on N digital signals, which can refer to the content of the first device performing the first processing based on N digital signals in implementation method one above, so as to obtain M first analog signals, which will not be repeated here.

[0121] Furthermore, the first device performs a second processing on the N digital signals to obtain N second analog signals, which may include: the first device performs a second processing on the N digital signals to obtain N second analog signals.

[0122] In one possible implementation, the first device can perform a second processing on the N digital signals to obtain N second analog signals through a second processing module.

[0123] In the embodiments of this application, the second processing module may be, but is not limited to, a low-precision and low-overhead DAC or a module with the processing capability of a low-precision and low-overhead DAC. For example, the second processing module is a 1-bit DAC.

[0124] In the above, the second processing module can be located inside or outside the first device to perform the second processing corresponding to the first device. This application does not limit the specific location of the second processing module.

[0125] S303A: The first device obtains N analog signals based on M first analog signals and N second analog signals.

[0126] Based on the first implementation of S302A above, in one possible implementation, the first device obtains N analog signals based on M first analog signals and N second analog signals, including: the first device first determines the first analog signal corresponding to the sorted N digital signals according to the group to which the sorted N digital signals belong; then, based on the first analog signal corresponding to the sorted N digital signals, it determines the first analog signal corresponding to the N second analog signals; and then multiplies the N second analog signals with the corresponding first analog signals to obtain the N analog signals.

[0127] Based on the above, in one possible implementation, the method may further include: a first device performing sorting recovery processing on N analog signals according to the sorting information of N digital signals to obtain sorted N analog signals; and then sending the sorted N analog signals to a second device.

[0128] For example, Figure 3B(1) shows the processing flow of the transmitting end corresponding to the first implementation. Referring to Figure 3B(1), firstly, the N digital signals are sorted to obtain the sorted N digital signals; based on the sorted N digital signals, the first device executes the following first and second processes:

[0129] In the first process: the sorted N digital signals are grouped to obtain M groups, and the target digital signal corresponding to each group is determined to obtain the target digital signals corresponding to the M groups. Further, the target digital signals corresponding to the M groups are processed to obtain M first analog signals.

[0130] In the second process: the sorted N digital signals are processed to obtain N second analog signals.

[0131] Based on the M first analog signals obtained from the first process and the N second analog signals obtained from the second process, N analog signals are obtained by multiplying the N second analog signals with their corresponding first analog signals.

[0132] Finally, the N analog signals are sorted and restored to obtain the sorted and restored N analog signals, which are then sent to the second device.

[0133] The first and second processes described above can be executed simultaneously or asynchronously, and there is no specific limitation on the order of execution. Furthermore, there is no specific limitation on the order of execution between the processing steps in the first process and the processing steps in the second process.

[0134] Based on the second implementation method in S302A above, in one possible implementation, the first device obtains N analog signals based on M first analog signals and N second analog signals, including: the first device first determines the group to which the N digital signals belong according to the sorting information of the N digital signals; then, according to the group to which the N signals belong, it determines the first analog signal corresponding to the N digital signals; next, according to the first analog signal corresponding to the N digital signals, it determines the first analog signal corresponding to the N second analog signals; finally, it multiplies the N second analog signals with the corresponding first analog signals to obtain the N analog signals.

[0135] Based on the above, in one possible implementation, the method may further include: the first device sending N analog signals to the second device.

[0136] For example, Figure 3B(2) shows the processing flow of the transmitting end corresponding to the second implementation method. Referring to Figure 3B(2), based on N digital signals, the first device executes the following first and second processes respectively:

[0137] In the first process: firstly, the N digital signals are sorted to obtain sorted N digital signals; then, the sorted N digital signals are grouped to obtain M groups; then, the target digital signal corresponding to each group is determined to obtain the target digital signals corresponding to the M groups; further, the target digital signals corresponding to the M groups are processed in the first process to obtain M first analog signals.

[0138] In the second process: the N digital signals are processed to obtain N second analog signals.

[0139] Based on the M first analog signals obtained from the first process and the N second analog signals obtained from the second process, the first analog signals corresponding to the N second analog signals are determined. Finally, the N second analog signals are multiplied with the corresponding first analog signals to obtain N analog signals, which are then sent to the second device.

[0140] The first and second processes described above can be executed simultaneously or asynchronously, and there is no specific limitation on the order of execution. Furthermore, there is no specific limitation on the order of execution between the processing steps in the first process and the processing steps in the second process.

[0141] Based on the above scheme, in the process of converting digital signals into analog signals, the transmitting end (i.e., the first device) can obtain quantization results for N digital signals through two different processing methods. Then, based on the quantization results obtained from these two processing methods, N analog signals are finally obtained. It can be seen that this method combines different processing methods to quantize signals, thereby improving the quantization accuracy of the signals and thus improving the system performance.

[0142] Based on the method shown in FIG. 3A above, the method of the embodiment of the present application will be introduced in detail through several specific implementation manners below.

[0143] Embodiment 1:

[0144] In Embodiment 1, based on the method shown in FIG. 3A above, taking the example that N digital signals are processed by a DAC to obtain N analog signals, the method of the embodiment of the present application will be introduced in detail by adopting Implementation Manner 1 in the solution shown in FIG. 3A. Among them, the first device is taken as a base station, the first processing module is taken as a high-precision DAC, and the second processing module is taken as a low-precision DAC.

[0145] Referring to FIG. 4A, the method flow of Embodiment 1 may include the following:

[0146] S400A: The base station obtains the signal to be transmitted

[0147] Among them, N r indicates that there are N r paths of the digital signal to be transmitted, the subscript r represents the meaning of reception, and the symbol indicates that the digital signal is a complex number.

[0148] S401A: The base station performs precoding processing on the signal to be transmitted to obtain the digital signal

[0149] In a possible implementation manner, the base station multiplies the precoding matrix by the signal to be transmitted to obtain the digital signal (i.e., an example of N digital signals in the solution shown in FIG. 3A above), which is expressed as w = Ps.

[0150] Above, N t indicates that there are N t paths of the encoded digital signal, and the subscript t represents the meaning of transmission.

[0151] S402A: The base station sorts and groups the digital signal to obtain the grouped signal

[0152] In a possible implementation manner, the base station sorts and groups the digital signal (i.e., an example of N digital signals in the solution shown in FIG. 3A above), which may specifically include the following steps:

[0153] Step 1: Let w represent the real vector of the digital signal. Sort the signal w according to its amplitude. The sorted signal is represented as follows:

[0154] In step 1, since the encoded digital signal is complex, the base station needs to process the encoded N... t The digital signal is processed by extracting its real and imaginary parts to obtain 2N. t Real number signal. The above symbols Used to indicate that the signal is a real number.

[0155] Step 2: Sort the signals Divide the signal into N groups, and the grouped signal is represented as follows:

[0156] In step 2, N is different from the N mentioned above. r The meaning of .

[0157] in, This indicates the first group of signals. This represents the second group of signals, and so on. Let N represent the Nth group of signals, where each group contains M elements (i.e., M digital signals), and M is a positive integer. NM = 2N t .

[0158] S403A: Base station processes packets of signal Low-precision DAC quantization is performed, and an adjustable amplitude is applied to obtain the quantized analog signal.

[0159] In this first implementation method, the base station processes the grouped signals. Performing low-precision DAC quantization and assigning an adjustable amplitude can specifically include the following steps:

[0160] Step 1: Calculate the grouped signal Each group of signals The corresponding quantized amplitude λ n , n∈[1,N].

[0161] in,

[0162] For example, the first The quantized amplitude λ of the group signal n It can satisfy the following formula:

[0163] Step 2: Convert each group of signals The corresponding quantized amplitude λ nEach is quantized and converted into analog amplitude by a high-precision DAC.

[0164] For example, a high-precision DAC can occupy 4 bits or 5 bits in size.

[0165] Steps 1 and 2 above are specific implementation examples of the first device in the second implementation method of S302A above performing first processing based on N digital signals to obtain M first analog signals.

[0166] Step 3: For each group of signals After low-precision DAC quantization, the quantized signal b is obtained. n .

[0167] For example, the first After each of the M elements (M digital signals) in the signal group is quantized by a 1-bit DAC (i.e., an example of a low-precision DAC), the quantized signal b is obtained. n Each element, after quantization, is represented as... n∈[1,N], m∈[1,M].

[0168] Step 3 is a specific implementation example of the first device in the first implementation method of S302A above performing second processing based on N digital signals to obtain N second analog signals.

[0169] Step 4: Convert each group of signals The corresponding quantized simulated amplitude With the corresponding quantized signal b n Multiply to obtain the mixed precision quantization result for each group.

[0170] That is, the signal after final grouping. The corresponding quantization result is expressed as

[0171] Step 4 is a specific implementation example of how the first device in S303A (based on implementation method one) obtains N analog signals based on M first analog signals and N second analog signals.

[0172] For example, the grouped signals have 3 groups (N=3), namely the first group of signals. Group 2 signals Group 3 signals Each group includes 2 digital signals (i.e., an example with M elements). Referring to step 1 above, the quantized amplitude of the first group of signals is calculated as λ1, the quantized amplitude of the second group of signals is calculated as λ2, and the quantized amplitude of the third group of signals is calculated as λ3.

[0173] Then, following the method in step 2 above, the quantized amplitude λ1 corresponding to the first group of signals is converted into a high-precision DAC quantization. The quantized amplitude λ2 corresponding to the second group of signals is converted into a high-precision DAC signal. The quantized amplitude λ3 corresponding to the third group of signals is converted into a high-precision DAC signal.

[0174] Furthermore, referring to step 3 above, the first group of signals... After low-precision DAC quantization processing, the quantized signal b1 is obtained. Specifically, the first group of signals... The first digital signal in the process is quantized by a 1-bit DAC to obtain... The second digital signal is also quantized by another 1-bit DAC to obtain... Similarly, referring to step 3 above, the second group of signals... After low-precision DAC quantization processing, the quantized signal b2 is obtained. Specifically, the second group of signals... The first digital signal in the process is quantized by a 1-bit DAC to obtain... The second digital signal is also quantized by another 1-bit DAC to obtain... Referring to step 3 above, the third group of signals... After low-precision DAC quantization, the quantized signal b3 is obtained; specifically, the third group of signals. The first digital signal in the process is quantized by a 1-bit DAC to obtain... The second digital signal is also quantized by another 1-bit DAC to obtain...

[0175] Finally, referring to step 4 above, the signals corresponding to the first group are... Multiply the signals by [b1]1 corresponding to the first signal and [b1]2 corresponding to the second signal in the first group of signals respectively to obtain two analog signals after mixed-precision quantization, which are represented as follows: Referring to step 4 above, the signal corresponding to the second group is... Multiply the signals by [b2]1 corresponding to the first signal and [b2]2 corresponding to the second signal in the second group, respectively, to obtain two analog signals after mixed-precision quantization, which are represented as follows: Referring to step 4 above, the signal corresponding to the third group is... Multiplying these signals by [b3]1 corresponding to the first signal and [b3]2 corresponding to the second signal in the third group of signals yields two analog signals after mixed-precision quantization, which are represented as follows:

[0176] That is, the final result of quantizing these three signals can be expressed as:

[0177] S404A: The base station quantizes the analog signals according to the original order of the signals to be transmitted (s). The sorting is then restored.

[0178] Following S404A, base stations can use existing communication technologies / methods to reconstruct the sorted analog signals. The transmission to the terminal device will not be detailed here.

[0179] For example, according to the steps described in S400A-S4004A above, Figure 4B shows a schematic diagram of the processing flow corresponding to Embodiment 1. Referring to Figure 4B, starting from the left, input N r (r represents the received) channels of digital signals, which are represented as follows: Use this N r The digital signal is pre-encoded to obtain the encoded N. t (t represents the number of) digital signals transmitted, which are represented sequentially as follows: Encode N t Each digital signal is processed by extracting real and imaginary numbers separately; that is, each digital signal includes a real part and an imaginary part. The 2N... t The digital signals are sorted and grouped (as described in S402A above) (taking M elements per group as an example). The sorted and grouped signals are output as shown in Figure 4B. The first group of signals includes... The second group of signals includes And so on, for a total of N groups of signals (N is different from N0). r (meaning).

[0180] For the first group of signals, based on M signals within it... λ1 is calculated, and then λ1 is quantized using a high-precision DAC to obtain... In addition, these M signals Each of these is quantized by a corresponding 1-bit DAC (the quantization function is sign() as shown in Figure 4B) to obtain b1, b2, ..., b M Furthermore, b1, b2...b M respectively with Perform product processing (as shown in Figure 4B) (where the product symbol is used) to obtain

[0181] For the second group of signals, based on M signals... λ2 is calculated, and then λ2 is quantized using a high-precision DAC to obtain... The amplitudes for each group are calculated in the manner described above, until the λ corresponding to the Nth group is obtained. N , λ N After high-precision DAC quantization processing, the result is... In addition, these M signals Each of these steps involves quantization using a corresponding 1-bit DAC (the quantization function is sign() as shown in Figure 4B) to obtain b. M+1 b M+2 ...b 2M Furthermore, b M+1 b M+2 ...b 2M respectively with Perform product processing (as shown in Figure 4B) (where the product symbol is used) to obtain

[0182] Similarly, following the processing methods of Group 1 and Group 2 above, other groups of signals are processed in a similar manner, which will not be detailed here.

[0183] After the above processing, we obtain 2N t The analog signals are represented as follows: Then take this 2N t analog signal (i.e.) The network is then reversed (i.e., the sorting is restored) to allow the data to be sent out in subsequent iterations.

[0184] In Implementation Method 1, the quantization precision of the low-precision DAC is usually lower than that of the high-precision DAC. The overhead generated by the low-precision DAC processing is obviously less than that generated by the high-precision DAC processing. In this implementation method, the base station (transmitter) can perform joint quantization processing of the signal to be transmitted by the high-precision DAC and the low-precision DAC (or perform quantization processing by the mixed-precision DAC). Compared with the method of using only the low-precision DAC for quantization, the quantization method adopted in Implementation Method 1 can effectively reduce the quantization error of the precoded signal transmitted by the base station, thereby improving the precoding performance. Moreover, compared with the method of using only the high-precision DAC for quantization, the quantization method adopted in Implementation Method 1 can also save quantization overhead.

[0185] Implementation Method Two:

[0186] In the second implementation method, based on the method shown in FIG3A above, taking the processing of N digital signals into N analog signals by a DAC as an example, the method of this application embodiment is described in detail using the second implementation method of the scheme shown in FIG3A. Here, the first device is exemplified by a base station, the first processing module by a high-precision DAC, and the second processing module by a low-precision DAC.

[0187] Referring to Figure 5A, the method flow of Implementation Method Two may include the following:

[0188] S500A: Base station receives signal to be transmitted.

[0189] Where, N r This indicates that there are N digital signals to be transmitted. r The term "path" (i.e., an example of N digital signals in the scheme shown in Figure 3A above) is used, where the subscript r indicates the meaning of reception, and the symbol... This indicates that the digital signal is a complex number.

[0190] S501A: Base station awaiting transmission of signals Precoding is performed to obtain a digital signal.

[0191] S502A: Base station for digital signals Sort and group the signals to obtain the grouped signals.

[0192] S500A, S501A, and S502A can be implemented one-to-one with the content described in S400A, S401A, and S402A above, and will not be repeated here.

[0193] S503A: Base station handles packetized signals High-precision DAC quantization is performed to obtain the quantized analog amplitude.

[0194] That is, the base station will transmit each group of signals The corresponding quantized amplitude λ n Each is quantized and converted into analog amplitude by a high-precision DAC. S503A can be implemented by referring to steps 1 and 2 in S403A above, as well as the corresponding examples of steps 1 and 2, which will not be repeated here.

[0195] S504A: The base station will transmit digital signals After low-precision DAC quantization processing, the quantized signal b is obtained.

[0196] In one possible implementation, the base station will transmit these N via the aforementioned S501A.r The digital signal is pre-encoded to obtain the encoded N. t (t represents the number of transmitted) digital signals. In the S504A, the base station will encode the N... t After extracting real and imaginary numbers from the digital signals, 2N is obtained. t The path signal will be this 2N t Each signal in the channel signal After quantization by a low-precision DAC (e.g., a 1-bit DAC), the quantized signal b is obtained. n .

[0197] S505A: The base station will quantize the analog amplitude. The corresponding signals are assigned to signal b respectively to obtain the quantized analog signals.

[0198] In one possible implementation, the base station can sort and group the signal b in the same way as the digital signal w in S502A, and then quantize the analog amplitude. Each signal is matched to its corresponding group, and then multiplied with the signal b in the corresponding group to obtain the quantized analog signal.

[0199] For example, based on the steps described in S500A-S505A above, Figure 5B shows a corresponding processing flow diagram. Referring to Figure 5B, starting from the left, input N r (r represents the received) channels of digital signals, which are represented as follows: Use this N r The digital signal is pre-encoded to obtain the encoded N. t (t represents the number of) digital signals transmitted, which are represented sequentially as follows: Encode N t Each of the N digital signals undergoes separate real and imaginary number extraction processing; that is, each digital signal includes both a real and an imaginary part. t After extraction and processing, the digital signals of the 2N channels total 2N. t The road signal is represented as: Furthermore, the following two main steps are performed respectively:

[0200] Step 1: When calculating the quantization amplitude for each group of signals, the following may be included:

[0201] First, the above 2N tThe signal path is sorted and grouped (as described in S402A above) (taking M elements per group as an example). The sorted and grouped signals are output as shown in Figure 4B. The first group of signals includes... The second group of signals includes And so on, for a total of N groups of signals (N is different from N0). r (meaning).

[0202] Then, for the first group of signals, based on M signals within it... λ1 is calculated, and then λ1 is quantized using a high-precision DAC to obtain... For the second group of signals, based on M signals... λ2 is calculated, and then λ2 is quantized using a high-precision DAC to obtain... The amplitudes for each group are calculated in the manner described above, until the λ corresponding to the Nth group is obtained. N , λ N After high-precision DAC quantization processing, the result is...

[0203] Step Two: Each step involves a 1-bit DAC quantization process (the quantization function shown in Figure 5B is sign(), where the value of sign() is typically 0, 1, or +1), resulting in...

[0204] Furthermore, compared to the processing flow described in Figure 4B above, the signal in Figure 5B that has undergone low-precision DAC (i.e., 1-bit DAC) quantization is a signal that has not undergone sorting processing.

[0205] Finally, after the processing in steps one and two above, the amplitudes (i.e., λ1...λ) of the N groups of signals obtained in step one are quantized. N ) and the corresponding 2N obtained in step two t The signal is processed by a sorting and grouping connection network (or switching network) (see the specific processing method of S505A), and the processed 2N signal is output. t The analog signals are represented as follows:

[0206] In the processing flow shown in Figure 4B of Embodiment 1, since both high-precision DAC quantization and low-precision DAC quantization require processing based on the sorted signals, the reverse-order connection network in Figure 4B needs to be placed later to restore the signal order. However, in the processing flow shown in Figure 5B of Embodiment 2, since low-precision DAC quantization of the digital signal does not involve sorting, and the signal is only sorted and grouped during high-precision DAC quantization, the sorting and grouping connection network can be placed in the middle.

[0207] Compared to Implementation Method 1, Implementation Method 2 differs in that the process of low-precision DAC processing is different. That is, the digital signal to be quantized by the low-precision DAC is not sorted. In the subsequent process, the signal after low-precision DAC processing can be assigned the corresponding amplitude, which can effectively realize the function of sorting and grouping.

[0208] Of course, the processing flow of quantizing signals by using high-precision DAC and low-precision DAC in combination in the embodiments of this application is not limited to the processing flow of the above-described embodiments one and two. Various modifications of the processing flow similar to the above-described embodiments one and two to achieve the final quantization result are also applicable in this application.

[0209] Regarding the above-described implementation methods one and two, it should be noted that:

[0210] (1) The above-mentioned implementation method one and implementation method two can be implemented separately or in combination, and no specific limitation is made in this regard.

[0211] (2) The above focuses on describing the differences between Implementation Method 1 and Implementation Method 2. Apart from the differences, Implementation Method 1 and Implementation Method 2 can be referred to each other.

[0212] (3) The step numbers of the flowcharts described in Embodiment 1 and Embodiment 2 above are merely examples of the execution flow and do not constitute a restriction on the order of execution of the steps. There are no temporal dependencies between the steps in the various implementations of this application, and there is no strict execution order between them. In addition, not all the steps shown in the flowcharts are mandatory steps, and some steps can be added or deleted based on the actual needs of each flowchart.

[0213] In the embodiments provided above, the methods provided by the embodiments of this application have been described from the perspective of interaction between various devices. To implement the functions of the methods provided in the embodiments or implementations of this application above, the first device may include a hardware structure and / or a software module, implementing the above functions in the form of a hardware structure, a software module, or a hardware structure plus a software module. Whether a particular function is executed in the form of a hardware structure, a software module, or a hardware structure plus a software module depends on the specific application and design constraints of the technical solution.

[0214] The module division in this embodiment is illustrative and represents only one logical functional division; in actual implementation, other division methods may be used. Furthermore, the functional modules in the various embodiments or implementations of this application can be integrated into a single processor, exist as separate physical entities, or be integrated into a single module. The integrated modules described above can be implemented in hardware or as software functional modules.

[0215] Similar to the above concept, as shown in FIG6, this application embodiment also provides a device 600 for implementing the function of the first device in the above method. For example, the device 600 can be a software module or a chip system. In this application embodiment, the chip system can be composed of chips or can include chips and other discrete devices. The device 600 may include: a communication unit 601 and a processing unit 602.

[0216] In this embodiment, the communication unit 601, also referred to as the transceiver unit, may include a sending unit and / or a receiving unit, respectively used to perform the sending and receiving steps of the first device in the above method embodiments. The processing unit 602 may be used to read instructions and / or data from the storage module so that the device 600 implements the aforementioned method embodiments.

[0217] Optionally, the device 600 may further include a storage unit 603, which is equivalent to a storage module and can be used to store instructions and / or data.

[0218] The communication device provided in the embodiments of this application will be described in detail below with reference to Figures 6 and 7. It should be understood that the description of the device embodiments corresponds to the description of the method embodiments. Therefore, the contents not described in detail can be implemented by referring to the manner shown in Figures 3A, 4A and 5A above. For the sake of brevity, they will not be repeated here.

[0219] The communication unit 601 can also be called a transceiver, transceiver, or transceiver device. The processing unit can also be called a processor, processing board, processing module, or processing device. Optionally, the device in the communication unit 601 used to implement the receiving function can be considered a receiving unit, and the device in the communication unit 601 used to implement the transmitting function can be considered a transmitting unit; that is, the communication unit 601 includes both a receiving unit and a transmitting unit. The communication unit can sometimes also be called a transceiver, transceiver circuit, or transceiver unit. The receiving unit can sometimes be called a receiver, receiver, or receiving circuit. The transmitting unit can sometimes be called a transmitter, transmitter, or transmitting circuit.

[0220] When device 600 is applied to the first device in the process shown in Figure 3A of the above embodiment:

[0221] In one possible implementation, the processing unit 602 may include a first processing unit, a second processing unit, and a third processing unit.

[0222] The communication unit 601 is used to acquire N digital signals; N is a positive integer;

[0223] The first processing unit is used to perform a first processing based on the N digital signals to obtain M first analog signals; the second processing unit is used to perform a second processing based on the N digital signals to obtain N second analog signals; M is a positive integer less than or equal to N;

[0224] The third processing unit is used to obtain N analog signals based on the M first analog signals and the N second analog signals.

[0225] The above are just examples. Processing unit 602 and communication unit 601 can also perform other functions. For a more detailed description, please refer to the relevant descriptions in the method embodiments shown in Figures 3A, 4A and 5A, which will not be repeated here.

[0226] Figure 7 shows a device 700 provided in an embodiment of this application. The device shown in Figure 7 can be a hardware circuit implementation of the device shown in Figure 6. This device 700 can be applied to the flowcharts shown above to perform the functions of the first or second device in the above method embodiments. For ease of explanation, Figure 7 only shows the main components of the device.

[0227] As shown in Figure 7, the device 700 includes a communication interface 701 and a processor 702. The communication interface 701 and the processor 702 are coupled to each other. It is understood that the communication interface 701 can be a transceiver or an input / output interface, or an interface circuit such as a transceiver circuit. Optionally, the device 700 may further include a memory 703 for storing instructions executed by the processor 702, or storing input data required by the processor 702 to execute instructions, or storing data generated after the processor 702 executes instructions.

[0228] When the device 700 is used to implement the methods shown in FIG3A, FIG4A and FIG5A, the communication interface 701 is used to implement the function of the communication unit 601, and the processor 702 is used to implement the function of the processing unit 602.

[0229] This embodiment does not limit the specific connection medium between the communication interface 701, processor 702, and memory 703. In Figure 7, the memory 703, processor 702, and communication interface 701 are connected via a communication bus 704, which is represented by a thick line. The connection methods between other components are merely illustrative and not intended to be limiting. The communication bus 704 can be divided into address bus, data bus, control bus, etc. For ease of illustration, only one thick line is used in Figure 7, but this does not indicate that there is only one bus or one type of bus.

[0230] When the aforementioned communication device is a chip, Figure 8 shows a simplified schematic diagram of the chip's device structure. The chip 800 includes an interface circuit 801 and one or more processors 802. Optionally, the chip 800 may also include a bus. Wherein:

[0231] The processor 802 may be an integrated circuit chip with signal processing capabilities. In implementation, each step of the method for determining the service node information described above can be completed through integrated logic circuits in the hardware of the processor 802 or through software instructions. The processor 802 may be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. It can implement or execute the methods and steps disclosed in the embodiments of this application. The general-purpose processor may be a microprocessor or any conventional processor.

[0232] The interface circuit 801 can be used to send or receive data, instructions or information. The processor 802 can use the data, instructions or other information received by the interface circuit 801 to process the data, instructions or other information, and can send the processed information out through the interface circuit 801.

[0233] Optionally, chip 800 also includes memory 803, which may include read-only memory and random access memory, and provides operation instructions and data to the processor. A portion of memory 803 may also include non-volatile random access memory (NVRAM).

[0234] Optionally, the memory stores executable software modules or data structures, and the processor can execute corresponding operations by calling the operation instructions stored in the memory (which may be stored in the operating system).

[0235] Optionally, the chip can be used in the first device involved in the embodiments of this application. Optionally, the interface circuit 801 can be used to output the execution result of the processor 802. For the data processing methods provided by one or more embodiments of this application, please refer to the foregoing embodiments, which will not be repeated here.

[0236] It should be noted that the functions of the interface circuit 801 and the processor 802 can be implemented through hardware design, software design, or a combination of hardware and software; no restrictions are imposed here.

[0237] This application also provides a computer-readable storage medium storing computer instructions for implementing the method executed by the first device in the above method embodiments.

[0238] For example, when the computer program is executed by the computer, it enables the computer to implement the method executed by the first device in the above method embodiments.

[0239] This application also provides a computer program product containing instructions that, when executed by a computer, cause the computer to perform the method executed by the first device in the above method embodiments.

[0240] This application also provides a chip, including a processor, for calling computer programs or computer instructions stored in the memory, so that the processor executes the data processing method of the implementation shown in FIG3A, FIG4A and FIG5A.

[0241] In one possible implementation, the input of the chip corresponds to the receiving operation in the implementations shown in Figures 3A, 4A, and 5A, and the output of the chip corresponds to the transmitting operation in the implementations shown in Figures 3A, 4A, and 5A.

[0242] Optionally, the processor is coupled to the memory via an interface.

[0243] Optionally, the chip also includes a memory that stores computer programs or computer instructions.

[0244] The processor mentioned above can be a general-purpose central processing unit (CPU), a microprocessor (ASIC), or one or more integrated circuits used to control the execution of a program for a data processing method as shown in Figures 3A, 4A, and 5A. The memory mentioned above can be read-only memory (ROM) or other types of static storage devices capable of storing static information and instructions, such as random access memory (RAM).

[0245] It should be noted that, for the sake of convenience and brevity, the explanations and beneficial effects of the relevant content in any of the communication devices provided above can be referred to the corresponding service node information determination method embodiments provided above, and will not be repeated here.

[0246] In this application, the communication devices may further include a hardware layer, an operating system layer running on top of the hardware layer, and an application layer running on the operating system layer. The hardware layer may include hardware such as a CPU, a memory management unit (MMU), and memory (also known as main memory). The operating system layer may be any one or more computer operating systems that implement business processing through processes, such as Linux, Unix, Android, iOS, or Windows. The application layer may include applications such as browsers, address books, word processing software, and instant messaging software.

[0247] The module division in this embodiment is illustrative and represents only one logical functional division. In actual implementation, other division methods may be used. Furthermore, the functional modules in each embodiment of this application can be integrated into a single processor, exist as separate physical entities, or be integrated into a single module. The integrated modules described above can be implemented in hardware or as software functional modules.

[0248] Through the above description of the embodiments, those skilled in the art will clearly understand that the embodiments of this application can be implemented in hardware, firmware, or a combination thereof. When implemented in software, the above functions can be stored in a computer-readable medium or transmitted as one or more instructions or code on a computer-readable medium. Computer-readable media include computer storage media and communication media, wherein communication media include any medium that facilitates the transfer of a computer program from one place to another. Storage media can be any available medium accessible to a computer. For example, but not limited to, computer-readable media can include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), compact disc read-only memory (CD-ROM) or other optical disc storage, magnetic disk storage media, or other magnetic storage devices, or any other medium capable of carrying or storing desired program code in the form of instructions or data structures and accessible to a computer. Furthermore, any connection can suitably be a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of the medium. As used in embodiments of this application, disks and discs include compact discs (CDs), laser discs, optical discs, digital video discs (DVDs), floppy disks, and Blu-ray discs, wherein disks typically magnetically copy data, while discs optically copy data using lasers. The combinations above should also be included within the scope of protection for computer-readable media.

[0249] In summary, the above descriptions are merely embodiments of this application and are not intended to limit the scope of protection of this application. Any modifications, equivalent substitutions, improvements, etc., made based on the disclosure of this application should be included within the scope of protection of this application.

Claims

1. A data processing method, characterized in that, include: Acquire N digital signals; N is a positive integer; Based on the N digital signals, a first processing is performed to obtain M first analog signals, and based on the N digital signals, a second processing is performed to obtain N second analog signals. M is a positive integer less than or equal to N; Based on the M-channel first analog signals and the N-channel second analog signals, N-channel analog signals are obtained.

2. The method according to claim 1, characterized in that, Also includes: Based on the amplitude values ​​of the N digital signals, the N digital signals are sorted to obtain the sorted N digital signals. The sorted N digital signals are grouped into M groups, each group containing at least one digital signal; Based on the at least one digital signal, the target digital signal for each group is obtained.

3. The method according to claim 2, characterized in that, The step of performing the first processing based on the N digital signals to obtain M first analog signals includes: performing the first processing on the M grouped target digital signals to obtain the M first analog signals.

4. The method according to claim 2 or 3, characterized in that, The step of performing a second processing on the N digital signals to obtain N second analog signals includes: performing the second processing on the sorted N digital signals to obtain the N second analog signals.

5. The method according to any one of claims 2-4, characterized in that, The process of obtaining N analog signals based on the M first analog signals and the N second analog signals includes: Based on the group to which the sorted N digital signals belong, determine the first analog signal corresponding to the sorted N digital signals; Based on the first analog signal corresponding to the sorted N digital signals, determine the first analog signal corresponding to the N second analog signals; The N-channel second analog signals are multiplied by their corresponding first analog signals to obtain the N-channel analog signals.

6. The method according to any one of claims 2-5, characterized in that, Also includes: Based on the sorting information of the N digital signals, the N analog signals are sorted and restored to obtain the sorted and restored N analog signals. Send the N analog signals after the sorting is restored.

7. The method according to claim 2 or 3, characterized in that, The step of performing a second processing on the N digital signals to obtain N second analog signals includes: performing the second processing on the N digital signals to obtain the N second analog signals.

8. The method according to claim 7, characterized in that, The process of obtaining N analog signals based on the M first analog signals and the N second analog signals includes: Based on the sorting information of the N digital signals, determine the group to which the N digital signals belong; Based on the group to which the N signals belong, determine the first analog signal corresponding to the N digital signals; Based on the first analog signal corresponding to the N digital signals, determine the first analog signal corresponding to the N second analog signals; The N-channel second analog signals are multiplied by their corresponding first analog signals to obtain the N-channel analog signals.

9. The method according to any one of claims 2-3 and 7-8, characterized in that, Also includes: Send the N analog signals.

10. A data processing apparatus, characterized in that, include: The system includes a communication module, a first processing module, a second processing module, and a third processing module. The communication module is used to acquire N digital signals; N is a positive integer; The first processing module is used to perform a first processing on the N digital signals to obtain M first analog signals; M is a positive integer less than or equal to N; The second processing module is used to perform a second processing on the N digital signals to obtain N second analog signals; The third processing module is used to obtain N analog signals based on the M first analog signals and the N second analog signals.

11. The apparatus according to claim 10, characterized in that, The third processing module is also used for: Based on the amplitude values ​​of the N digital signals, the N digital signals are sorted to obtain the sorted N digital signals. The sorted N digital signals are grouped into M groups, each group containing at least one digital signal; Based on the at least one digital signal, the target digital signal for each group is obtained.

12. The apparatus according to claim 11, characterized in that, The first processing module, when performing the first processing based on the N digital signals to obtain M first analog signals, is specifically used to: perform the first processing on the M grouped target digital signals to obtain the M first analog signals.

13. The apparatus according to claim 11 or 12, characterized in that, The second processing module, when performing second processing on the N digital signals to obtain N second analog signals, is specifically used for: The sorted N digital signals are subjected to the second processing to obtain the N second analog signals.

14. The apparatus according to any one of claims 11-13, characterized in that, The third processing module, when obtaining N analog signals based on the M first analog signals and the N second analog signals, is specifically used for: Based on the group to which the sorted N digital signals belong, determine the first analog signal corresponding to the sorted N digital signals; Based on the first analog signal corresponding to the sorted N digital signals, determine the first analog signal corresponding to the N second analog signals; The N-channel second analog signals are multiplied by their corresponding first analog signals to obtain the N-channel analog signals.

15. The apparatus according to any one of claims 11-14, characterized in that, The third processing module is further configured to perform sorting and recovery processing on the N analog signals according to the sorting information of the N digital signals, so as to obtain the sorted and recovered N analog signals. The communication module is also used to send the N analog signals after the sorting is restored.

16. The apparatus according to claim 11 or 12, characterized in that, The second processing module, when performing the second processing on the N digital signals to obtain N second analog signals, is specifically used to: perform the second processing on the N digital signals to obtain the N second analog signals.

17. The apparatus according to claim 16, characterized in that, The third processing module, when obtaining N analog signals based on the M first analog signals and the N second analog signals, is specifically used for: Based on the sorting information of the N digital signals, determine the group to which the N digital signals belong; Based on the group to which the N signals belong, determine the first analog signal corresponding to the N digital signals; Based on the first analog signal corresponding to the N digital signals, determine the first analog signal corresponding to the N second analog signals; The N-channel second analog signals are multiplied by their corresponding first analog signals to obtain the N-channel analog signals.

18. The apparatus according to any one of claims 11-12, 16-17, characterized in that, The communication module is also used to transmit the N analog signals.

19. A chip, characterized in that, The chip is used to read and execute computer programs or instructions in a memory to implement the method as described in any one of claims 1 to 9.

20. A communication device, characterized in that, Includes a processor, the processor being configured to cause the communication device to perform the method as described in any one of claims 1 to 9 by executing a computer program or instructions, or by using logic circuitry.

21. The communication device according to claim 20, characterized in that, It also includes a memory for storing the computer program or instructions.

22. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program or instructions that, when executed on a computer, cause the method as described in any one of claims 1 to 9 to be performed.

23. A computer program product, characterized in that, It includes instructions that, when executed on a computer, cause the method as described in any one of claims 1 to 9 to be performed.

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