Data acquisition circuit, data acquisition device, and automobile

Abstract

A data acquisition circuit, a data acquisition device, and an automobile, relating to the field of data acquisition. The data acquisition circuit comprises: a GPIO acquisition interface used for receiving an external current signal; an internal balancing module electrically connected to the GPIO acquisition interface, and used for conducting the external current signal when the external current signal is at a high level or releasing an internal current signal when the external current signal is at a low level; and a current acquisition module electrically connected to the internal balancing module, and used for acquiring the current signal released by the internal balancing module and determining target data on the basis of the current signal released by the internal balancing module. The present application can construct an acquisition circuit having consistent power consumption.

Description

Data acquisition circuit, data acquisition device and automobile

[0001] Cross-reference to related applications

[0002] This application claims priority to Chinese Patent Application No. 202422114664.2, filed on August 29, 2024, the contents of which are incorporated herein by reference. Technical Field

[0003] This application relates to the field of data acquisition, and in particular to a data acquisition circuit, a data acquisition device, and an automobile. Background Technology

[0004] Currently, when using multiple AFE (Automatic Factor Transfer) chips to collect data, if the number of acquisition circuits connected to each AFE chip is inconsistent, the power consumption of each AFE chip needs to be balanced according to the AFE chip with the largest number of connected acquisition circuits. Otherwise, voltage differences will occur in the battery cells. If the voltage difference is too large, the terminal will report a fault, affecting vehicle operation. Designing the power consumption of each AFE chip individually increases the design complexity of the entire battery management system. Therefore, how to construct acquisition circuits with consistent power consumption has become an urgent problem to be solved. Summary of the Invention

[0005] The main objective of this application is to propose a data acquisition circuit, a data acquisition device, and an automobile, with the aim of constructing an acquisition circuit with consistent power consumption.

[0006] To achieve the above objectives, a first aspect of this application provides a data acquisition circuit, comprising:

[0007] GPIO acquisition interface, used to receive external current signals;

[0008] An internal balancing module is electrically connected to the GPIO acquisition interface and is used to turn on the external current signal when the external current signal is high, or to release the internal current signal when the external current signal is low.

[0009] The internal balancing module includes a first control MOSFET, a second control MOSFET, a signal control unit, a balancing voltage divider unit, a first conducting MOSFET, and a second conducting MOSFET;

[0010] The source of the first conducting MOSFET is electrically connected to the power supply, and the drain is electrically connected to the source of the second conducting MOSFET.

[0011] The drain of the second conducting MOSFET is grounded and electrically connected to the source of the second control MOSFET;

[0012] The signal control unit is electrically connected to the gate of the first control MOS transistor and the gate of the second control MOS transistor, and is used to release the internal balancing signal when the external current signal is low, so as to turn on the first control MOS transistor and the second control MOS transistor.

[0013] The drain of the second control MOS transistor is electrically connected to the balancing voltage divider unit, and is used to conduct current to the balancing voltage divider unit after receiving the internal balancing signal;

[0014] The source of the first control MOS transistor is electrically connected to the power supply, and the drain is electrically connected to the voltage division and balancing unit, so as to conduct current to the voltage division and balancing unit after receiving the internal balancing signal;

[0015] The voltage balancing unit is used to divide the voltage and release the internal current signal;

[0016] The current acquisition module is electrically connected to the internal balancing module and is used to acquire the current signal released by the internal balancing module and determine the target data based on the current signal released by the internal balancing module.

[0017] In some embodiments, the circuit includes at least one of the GPIO acquisition interfaces and at least one of the internal balancing modules, and one of the GPIO acquisition interfaces is electrically connected to one of the internal balancing modules.

[0018] In some embodiments, the voltage divider unit includes a first balancing resistor and a second balancing resistor;

[0019] The first balancing resistor is electrically connected to the first control MOSFET and the current acquisition module;

[0020] The second balancing resistor is electrically connected to the second control MOS transistor and the current acquisition module.

[0021] In some embodiments, the current acquisition module includes a circuit protection unit and a current acquisition unit;

[0022] The circuit protection unit is electrically connected to the first balancing resistor and the second balancing resistor, and is used to protect the circuit and conduct current.

[0023] The current acquisition unit is electrically connected to the circuit protection unit and is used to determine the target data based on the current signal released by the internal balancing module.

[0024] In some embodiments, the circuit protection unit includes a first bidirectional breakdown diode and a first diode;

[0025] The first bidirectional breakdown diode is electrically connected to the first balancing resistor, the second balancing resistor, and the current acquisition unit;

[0026] The first diode is electrically connected to the first balancing resistor, the second balancing resistor, and the current acquisition unit.

[0027] In some embodiments, the circuit further includes a data acquisition module electrically connected to the GPIO acquisition interface, used to acquire target data and release the external current signal based on the target data.

[0028] In some embodiments, the data acquisition module includes a data acquisition unit and a data voltage divider unit;

[0029] The data acquisition unit is used to acquire the target data and determine different currents based on the target data;

[0030] The data voltage divider unit is electrically connected to the data acquisition unit and the GPIO acquisition interface. It is used to turn on the current and divide the voltage of the data acquisition unit, and output the external current signal representing the target data based on the current released by the data acquisition unit.

[0031] In some embodiments, the data acquisition unit includes a thermistor electrically connected to the power supply and the data voltage divider unit, the thermistor being used to acquire temperature and determine different resistance values ​​based on the temperature.

[0032] To achieve the above objectives, a second aspect of this application provides a data acquisition device, comprising:

[0033] Data display circuitry;

[0034] The data acquisition circuit as described in the first aspect above.

[0035] To achieve the above objectives, a third aspect of this application proposes a new energy vehicle, comprising:

[0036] Body;

[0037] Car door;

[0038] Battery;

[0039] A vehicle control system, wherein the vehicle control system includes the data acquisition device described in the second aspect above.

[0040] The data acquisition circuit, data acquisition device, and automobile illustrated in this application embodiment receive external current signals through the GPIO acquisition interface and transmit the external current signals to the internal balancing module. When the external current signal is low, i.e., when there is no external circuit connected to the GPIO acquisition interface, the signal control unit of the internal balancing module controls the first and second control MOSFETs to conduct, and releases the internal current signal to the current acquisition module through the first and second conducting MOSFETs, the first and second control MOSFETs, and the balancing voltage divider unit, so that the current acquisition module is in working state. When the external current signal is high, i.e., when there is an external circuit connected to the GPIO acquisition interface, the signal control unit of the internal balancing module controls the first and second control MOSFETs to deconduct, and the current flows through the internal balancing module and the current acquisition module. The current acquisition module determines the target data based on the acquired current, thereby realizing that the data acquisition circuit is in working state even when there is no external circuit, that is, realizing the control of the power consumption of AFE, and thus realizing that when multiple AFE chips work together, the power consumption of multiple AFE chips can be set to be consistent, that is, a data acquisition circuit with consistent power consumption is constructed. Attached Figure Description

[0041] Figure 1 is a block diagram of the data acquisition circuit provided in an embodiment of this application;

[0042] Figure 2 is the circuit diagram of the internal balancing module in Figure 1;

[0043] Figure 3 is a circuit diagram of the internal balancing module provided in another embodiment of Figure 1;

[0044] Figure 4 is a block diagram of a data acquisition circuit provided in another embodiment of this application;

[0045] Figure 5 is the circuit diagram of the current protection unit in Figure 4;

[0046] Figure 6 is a block diagram of a data acquisition circuit provided in another embodiment of this application;

[0047] Figure 7 is a block diagram of a data acquisition circuit provided in another embodiment of this application;

[0048] Figure 8 is the circuit schematic of the data acquisition unit in Figure 7;

[0049] Figure 9 is a circuit diagram of a data acquisition circuit provided in another embodiment of this application;

[0050] Figure 10 is a block diagram of the data acquisition device provided in an embodiment of this application;

[0051] Figure 11 is a block diagram of a car provided in an embodiment of this application. Detailed Implementation

[0052] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0053] It should be noted that although functional modules are divided in the device schematic diagram and a logical order is shown in the flowchart, in some cases, the steps shown or described may be performed in a different order than the module division in the device or the order in the flowchart. The terms "first," "second," etc., in the specification, claims, and the aforementioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0054] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of this application only and is not intended to limit this application.

[0055] The data acquisition circuit, data acquisition device, and automobile provided in this application are specifically described through the following embodiments. First, the data acquisition circuit in the embodiments of this application is described.

[0056] The data acquisition circuit provided in this application can be applied to a terminal, a server, or software running on either a terminal or a server. In some embodiments, the terminal can be a smartphone, tablet, laptop, desktop computer, etc.; the server can be configured as an independent physical server, a server cluster or distributed system composed of multiple physical servers, or a cloud server providing basic cloud computing services such as cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communication, middleware services, domain name services, security services, CDN, and big data and artificial intelligence platforms; the software can be an application that implements the data acquisition circuit, but is not limited to the above forms.

[0057] This application can be used in a wide variety of general-purpose or special-purpose computer system environments or configurations. Examples include: personal computers, server computers, handheld or portable devices, tablet devices, multiprocessor systems, microprocessor-based systems, set-top boxes, programmable consumer electronics, network PCs, minicomputers, mainframe computers, and distributed computing environments including any of the above systems or devices. This application can be described in the general context of computer-executable instructions executed by a computer, such as program modules. Generally, program modules include routines, programs, objects, components, data structures, etc., that perform specific tasks or implement specific abstract data types. This application can also be practiced in distributed computing environments where tasks are performed by remote processing devices connected via a communication network. In distributed computing environments, program modules can reside in local and remote computer storage media, including storage devices.

[0058] Please refer to Figures 1 and 2. In some embodiments, the data acquisition circuit includes:

[0059] The GPIO acquisition interface 100 is used to receive external current signals.

[0060] The internal balancing module 200 is electrically connected to the GPIO acquisition interface 100, and is used to turn on the external current signal when the external current signal is high level, or to release the internal current signal when the external current signal is low level.

[0061] The internal balancing module 200 includes a first control MOSFET, a second control MOSFET, a signal control unit, a balancing voltage divider unit, a first conducting MOSFET, and a second conducting MOSFET;

[0062] The source of the first conducting MOSFET is electrically connected to the power supply V, and the drain is electrically connected to the source of the second conducting MOSFET.

[0063] The drain of the second conducting MOSFET is grounded and electrically connected to the source of the second control MOSFET;

[0064] The signal control unit is electrically connected to the gate of the first control MOS transistor and the gate of the second control MOS transistor, and is used to release the internal balancing signal when the external current signal is low, so as to turn on the first control MOS transistor and the second control MOS transistor.

[0065] The drain of the second control MOSFET is electrically connected to the balancing voltage divider unit, which is used to receive the internal balancing signal and then conduct current to the balancing voltage divider unit.

[0066] The source of the first control MOSFET is electrically connected to the power supply V, and the drain is electrically connected to the balancing voltage divider unit. It is used to conduct current to the balancing voltage divider unit after receiving the internal balancing signal.

[0067] The voltage divider unit is used to divide the voltage and release the internal current signal;

[0068] The current acquisition module 300 is electrically connected to the internal balancing module 200 and is used to acquire the current signal released by the internal balancing module 200 and determine the target data based on the current signal released by the internal balancing module 200.

[0069] The beneficial effects of the embodiments of this application include, but are not limited to:

[0070] The GPIO acquisition interface 100 receives external current signals and transmits them to the internal balancing module 200. When the external current signal is low (i.e., when the GPIO acquisition interface 100 has no external circuit connected), the signal control unit of the internal balancing module 200 controls the first and second control MOSFETs to turn on. The internal current signal is then released to the current acquisition module 300 through the first and second conducting MOSFETs, the first and second control MOSFETs, and the balancing voltage divider unit, thus putting the current acquisition module 300 into operation. When the external current signal... When the signal is high (i.e., when the GPIO acquisition interface 100 is connected to an external circuit), the signal control unit of the internal balancing module 200 controls the first and second control MOSFETs to be off-state. Current flows through the internal balancing module 200 and then through the current acquisition module 300. The current acquisition module 300 determines the target data based on the acquired current, thus enabling the data acquisition circuit to operate even without an external circuit. This allows for control of the AFE's power consumption, and further enables the power consumption of multiple AFE chips to be set to be consistent when multiple AFE chips are working together, thus constructing a data acquisition circuit with consistent power consumption. The GPIO acquisition interface 100 is the GPIO acquisition interface of the AFE chip.

[0071] In this embodiment, the first control MOS transistor, the second control MOS transistor, the first conduction MOS transistor, and the second conduction MOS transistor are MOS transistors.

[0072] Referring to Figure 1, in some embodiments, the circuit includes at least one GPIO acquisition interface 100 and at least one internal balancing module 200, and one GPIO acquisition interface 100 is electrically connected to one internal balancing module 200.

[0073] The advantage of this embodiment is that by equipping each GPIO acquisition interface 100 with an internal balancing module 200, when the acquisition quantities of multiple AFE acquisition chips are inconsistent, the power consumption of each AFE can be made consistent through the internal balancing module 200, thereby realizing a data acquisition circuit with consistent power consumption.

[0074] For example, in one embodiment, the first AFE chip needs to collect the temperature of three battery packs, and the second AFE chip needs to collect the temperature of one battery pack. Specifically, the first GPIO acquisition interface 100 of the second AFE chip collects the temperature, while the second and third GPIO acquisition interfaces do not need to collect temperature. Instead, the second internal current signal is released by the internal balancing module 200 of the second GPIO acquisition interface 100, and the third internal current signal is released by the internal balancing module 200 of the third GPIO acquisition interface 100. This ensures that the second AFE chip is also in a state of collecting three current signals, consistent with the operating state of the first AFE chip. This makes the power consumption of the first and second AFE chips consistent, eliminating the need to set power consumption individually for each AFE chip.

[0075] Please refer to Figures 1 and 3. In some embodiments, the voltage divider unit includes a first balancing resistor and a second balancing resistor.

[0076] The first balancing resistor is electrically connected to the first control MOSFET and the current acquisition module 300;

[0077] The second balancing resistor is electrically connected to the second control MOSFET and the current acquisition module 300.

[0078] Specifically, the first end of the first balancing resistor is electrically connected to the drain of the first control MOS transistor, the second end of the first balancing resistor is electrically connected to the first end of the second balancing resistor, and the second end of the first balancing resistor is also electrically connected to the current acquisition module; the second end of the second balancing resistor is electrically connected to the drain of the second control MOS transistor.

[0079] The advantage of this embodiment is that by controlling the first control MOS transistor to close, current flows through the first balancing resistor, and by controlling the second control MOS transistor to close, current flows through the second balancing resistor. The first balancing resistor and the second balancing resistor divide the voltage and release the internal current signal.

[0080] Please refer to Figure 4. In some embodiments, the current acquisition module 300 includes a circuit protection unit 310 and a current acquisition unit 320.

[0081] The circuit protection unit 310 is electrically connected to the first balancing resistor and the second balancing resistor to protect the circuit and conduct current.

[0082] The current acquisition unit 320 is electrically connected to the circuit protection unit 310 and is used to determine the target data based on the current signal released by the internal balancing module 200.

[0083] Specifically, the circuit protection unit 310 is electrically connected to the second end of the first balancing resistor and the first end of the second balancing resistor, respectively.

[0084] The advantage of this embodiment is that the circuit protection unit 310 protects the electrical connection between the first and second balancing resistors, limits the current flowing into the current acquisition unit 320, and the current acquisition unit 320 determines the target data based on the acquired current, thereby enabling the current acquisition unit 320 to determine the target data based on the acquired current while protecting the circuit.

[0085] Please refer to Figures 4 and 5. In some embodiments, the circuit protection unit 310 includes a first bidirectional breakdown diode and a first diode.

[0086] The first bidirectional breakdown diode is electrically connected to the first balancing resistor, the second balancing resistor, and the current acquisition unit 320;

[0087] The first diode is electrically connected to the first balancing resistor, the second balancing resistor, and the current acquisition unit 320.

[0088] Specifically, the first end of the first bidirectional breakdown diode is electrically connected to the second end of the first balancing resistor and the first end of the second balancing resistor, and the second end of the first bidirectional breakdown diode is electrically connected to the current acquisition unit 320; the anode of the first diode is electrically connected to the second end of the first balancing resistor and the first end of the second balancing resistor, and the cathode of the first diode is electrically connected to the current acquisition unit 320.

[0089] The advantage of this embodiment is that the direction of the current flowing into the current acquisition channel is limited by the first diode, and the circuit is protected from the effects of static electricity and surge current by the first bidirectional breakdown diode, thus achieving circuit protection.

[0090] Please refer to Figure 6. In some embodiments, the circuit also includes a data acquisition module 400, which is electrically connected to the GPIO acquisition interface 100, for acquiring target data and releasing an external current signal based on the target data.

[0091] The advantage of this embodiment is that the target data is acquired by the data acquisition module 400, and an external current signal is released based on the target data. The external current signal flows through the internal balancing module 200 through the GPIO acquisition interface 100. When the internal balancing module 200 receives a high-level external current signal, it controls the first control MOS transistor and the second control MOS transistor to not close through the signal control unit, so that the external current signal flows through the circuit protection unit 310 to the current acquisition unit 320. The current acquisition unit 320 determines the target data based on the external current signal.

[0092] Please refer to Figure 7. In some embodiments, the data acquisition module 400 includes a data acquisition unit 410 and a data voltage divider unit 420.

[0093] The data acquisition unit 410 is used to acquire target data and determine different currents based on the target data;

[0094] The data voltage divider unit 420 is electrically connected to the data acquisition unit 410 and the GPIO acquisition interface 100. It is used to turn on the current and divide the voltage of the data acquisition unit 410, and output an external current signal representing the target data based on the current released by the data acquisition unit 410.

[0095] Referring to Figure 8, in some embodiments, the data voltage divider unit 420 includes a first resistor, a second resistor, a first capacitor, and a second capacitor; the first end of the first resistor is electrically connected to the power supply, and the second end of the first resistor is grounded through the thermistor and the first capacitor respectively; the second end of the first resistor is also electrically connected to the first end of the second capacitor through the second resistor, the second end of the second capacitor is grounded, and the second end of the first resistor is also electrically connected to the GPIO acquisition interface 100.

[0096] The advantage of this embodiment is that the data acquisition unit 410 is used to acquire target data and determine different currents based on the target data. The data acquisition unit 410 and the GPIO acquisition interface 100 are electrically connected through the data voltage divider unit 420. The data voltage divider unit 420 outputs an external current signal representing the target data based on the current released by the data acquisition unit 410, thereby realizing the conversion of target data to external current signal. After the current acquisition unit 320 acquires the external current signal, it determines the target data and realizes the acquisition of target data.

[0097] Please refer to Figures 1 and 7. In some embodiments, the data acquisition unit 410 includes a thermistor, which is electrically connected to the power supply V and the data voltage divider unit 420. The thermistor is used to acquire temperature and determine different resistance values ​​based on the temperature.

[0098] The advantage of this embodiment is that by determining different resistance values ​​of the thermistor at different temperatures, the data voltage divider unit 420 divides the voltage into different values ​​based on the different resistance values, thereby determining the external current signal released to the current acquisition module 300 based on the temperature. After receiving the external current signal, the current acquisition unit 320 determines the target temperature and realizes the acquisition of the target temperature.

[0099] Please refer to Figures 7 and 9. In some embodiments, when the GPIO acquisition interface 100 is electrically connected to the data acquisition module 400, the signal control unit controls the first control MOSFET and the second control MOSFET to remain open, so that the external current signal flows into the current acquisition unit 320 to acquire the target temperature.

[0100] Please refer to Figure 10. This application embodiment also provides a data acquisition device, including a data display circuit and a data acquisition circuit, wherein the data display circuit is electrically connected to the data acquisition circuit.

[0101] The specific implementation of the data acquisition circuit in this data acquisition device is basically the same as the specific embodiment of the data acquisition circuit described above, and will not be repeated here.

[0102] Referring to Figure 11, this application embodiment also provides an automobile, including a body, doors, a battery, and a vehicle control system, wherein the vehicle control system includes a battery acquisition device. Exemplarily, the automobile is a new energy vehicle.

[0103] The specific implementation of the vehicle control system in this car is basically the same as the specific implementation of the data acquisition device described above, and will not be repeated here.

[0104] The data acquisition circuit, data acquisition device, and automobile provided in this application embodiment receive external current signals through the GPIO acquisition interface 100 and transmit the external current signals to the internal balancing module 200. When the external current signal is low, that is, when there is no external circuit connected to the GPIO acquisition interface 100, the signal control unit of the internal balancing module 200 controls the first control MOSFET and the second control MOSFET to conduct, and releases the internal current signal to the current acquisition module 300 through the first conducting MOSFET, the second conducting MOSFET, the first control MOSFET, the second control MOSFET, and the balancing voltage divider unit, so that the current acquisition module 300... In the working state, when the external current signal is high, that is, when the GPIO acquisition interface 100 is connected to an external circuit, the signal control unit of the internal balancing module 200 controls the first control MOSFET and the second control MOSFET to not conduct. The current flows through the internal balancing module 200 and then through the current acquisition module 300. The current acquisition module 300 determines the target data based on the acquired current, thereby realizing that the data acquisition circuit is in working state even when there is no external circuit, that is, realizing the control of the power consumption of AFE. In addition, when multiple AFE chips work together, the power consumption of multiple AFE chips can be set to be consistent, that is, a data acquisition circuit with consistent power consumption is constructed.

[0105] In embodiments of this application, the data acquisition circuit further includes a processor and a memory, wherein the processor is used to execute the following program units stored in the memory: the signal control unit and the current acquisition unit.

[0106] The embodiments described in this application are for the purpose of more clearly illustrating the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions provided by the embodiments of this application. As those skilled in the art will know, with the evolution of technology and the emergence of new application scenarios, the technical solutions provided by the embodiments of this application are also applicable to similar technical problems.

[0107] Those skilled in the art will understand that the technical solutions shown in the figures do not constitute a limitation on the embodiments of this application, and may include more or fewer steps than shown, or combine certain steps, or different steps.

[0108] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0109] Those skilled in the art will understand that all or some of the steps in the methods disclosed above, as well as the functional modules / units in the systems and devices, can be implemented as software, firmware, hardware, or suitable combinations thereof.

[0110] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0111] It should be understood that in this application, "at least one (item)" means one or more, and "more than" means two or more. "And / or" is used to describe the relationship between related objects, indicating that three relationships can exist. For example, "A and / or B" can represent three cases: only A exists, only B exists, and both A and B exist simultaneously, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one (item) of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one (item) of a, b, or c can represent: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, and c can be single or multiple.

[0112] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of the units described above is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. The coupling or direct coupling or communication connection between the shown or discussed units may be through some interfaces, or indirect coupling or communication connection between the apparatus or units, and may be electrical, mechanical, or other forms.

[0113] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0114] The preferred embodiments of the present application have been described above with reference to the accompanying drawings, but this does not limit the scope of the claims of the present application. Any modifications, equivalent substitutions, and improvements made by those skilled in the art without departing from the scope and substance of the embodiments of the present application shall be within the scope of the claims of the present application.

Claims

1. A data acquisition circuit, wherein, The circuit includes: GPIO acquisition interface, used to receive external current signals; An internal balancing module is electrically connected to the GPIO acquisition interface and is used to turn on the external current signal when the external current signal is high, or to release the internal current signal when the external current signal is low. The internal balancing module includes a first control MOSFET, a second control MOSFET, a signal control unit, a balancing voltage divider unit, a first conducting MOSFET, and a second conducting MOSFET; The source of the first conducting MOSFET is electrically connected to the power supply, and the drain of the first conducting MOSFET is electrically connected to the source of the second conducting MOSFET. The drain of the second conducting MOSFET is grounded and electrically connected to the source of the second control MOSFET; The signal control unit is electrically connected to the gate of the first control MOS transistor and the gate of the second control MOS transistor, and is used to release the internal balancing signal when the external current signal is low, so as to turn on the first control MOS transistor and the second control MOS transistor. The drain of the second control MOS transistor is electrically connected to the balancing voltage divider unit, and is used to conduct current to the balancing voltage divider unit after receiving the internal balancing signal; The source of the first control MOS transistor is electrically connected to the power supply, and the drain of the first control MOS transistor is electrically connected to the voltage division and balancing unit, so as to conduct current to the voltage division and balancing unit after receiving the internal balancing signal. The voltage balancing unit is used to divide the voltage and release the internal current signal; The current acquisition module is electrically connected to the internal balancing module and is used to acquire the current signal released by the internal balancing module and determine the target data based on the current signal released by the internal balancing module.

2. The circuit according to claim 1, wherein, The circuit includes at least one GPIO acquisition interface and at least one internal balancing module, and one GPIO acquisition interface is electrically connected to one internal balancing module.

3. The circuit according to claim 1, characterized in that, The voltage balancing unit includes a first balancing resistor and a second balancing resistor; The first balancing resistor is electrically connected to the first control MOSFET and the current acquisition module; The second balancing resistor is electrically connected to the second control MOS transistor and the current acquisition module.

4. The circuit according to claim 3, wherein, The current acquisition module includes a circuit protection unit and a current acquisition unit; The circuit protection unit is electrically connected to the first balancing resistor and the second balancing resistor, and is used to protect the circuit and conduct current. The current acquisition unit is electrically connected to the circuit protection unit and is used to determine the target data based on the current signal released by the internal balancing module.

5. The circuit according to claim 4, wherein, The circuit protection unit includes a first bidirectional breakdown diode and a first diode; The first bidirectional breakdown diode is electrically connected to the first balancing resistor, the second balancing resistor, and the current acquisition unit; The first diode is electrically connected to the first balancing resistor, the second balancing resistor, and the current acquisition unit.

6. The circuit according to claim 1, wherein, The circuit also includes a data acquisition module, which is electrically connected to the GPIO acquisition interface and is used to acquire target data and release the external current signal based on the target data.

7. The circuit according to claim 6, wherein, The data acquisition module includes a data acquisition unit and a data voltage divider unit; The data acquisition unit is used to acquire the target data and determine different currents based on the target data; The data voltage divider unit is electrically connected to the data acquisition unit and the GPIO acquisition interface. It is used to turn on the current and divide the voltage of the data acquisition unit, and output the external current signal representing the target data based on the current released by the data acquisition unit.

8. The circuit according to claim 7, wherein, The data acquisition unit includes a thermistor, which is electrically connected to the power supply and the data voltage divider unit. The thermistor is used to acquire temperature and determine different resistance values ​​based on the temperature.

9. The circuit according to claim 3, wherein, The first end of the first balancing resistor is electrically connected to the drain of the first control MOS transistor, and the second end of the first balancing resistor is electrically connected to the first end of the second balancing resistor.

10. The circuit according to claim 9, wherein, The second end of the first balancing resistor is also electrically connected to the current acquisition module; the second end of the second balancing resistor is electrically connected to the drain of the second control MOS transistor.

11. The circuit according to claim 4, wherein, The circuit protection unit is electrically connected to the second end of the first balancing resistor and the first end of the second balancing resistor, respectively.

12. The circuit according to claim 5, wherein, The first end of the first bidirectional breakdown diode is electrically connected to the second end of the first balancing resistor and the first end of the second balancing resistor, and the second end of the first bidirectional breakdown diode is electrically connected to the current acquisition unit.

13. The circuit according to claim 12, wherein, The anode of the first diode is electrically connected to the second end of the first balancing resistor and the first end of the second balancing resistor, and the cathode of the first diode is electrically connected to the current acquisition unit.

14. A data acquisition device, wherein, include: Data display circuitry; The data acquisition circuit as described in any one of claims 1 to 13.

15. A new energy vehicle, wherein, include: Body; Car door; Battery; A vehicle control system, the vehicle control system including the data acquisition device as described in claim 9.

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