Shift register and driving method therefor, and display panel

Abstract

The present disclosure provides a shift register and a driving method therefor, and a display panel. In the shift register, shift register circuits are used for outputting basic scanning signals by means of scanning signal output ends; first intermediate control circuits are used for controlling the output of first intermediate signal output ends; first output control circuits are used for controlling the output of first gate driving signal output ends; second intermediate control circuits are used for controlling the output of second intermediate signal output ends; and second output control circuits are used for controlling the output of second gate driving signal output ends.

Description

Shift registers and their driving methods, display panels

[0001] Cross-reference to related applications

[0002] This application claims priority to Chinese Patent Application No. 202411194911.2, filed in China on August 28, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to the field of display technology, and in particular to a shift register and its driving method, and a display panel. Background Technology

[0004] With the continuous development of display technology, the application fields of display products are becoming increasingly widespread, and people's requirements for the display quality of display products are getting higher and higher. In order to better realize narrow bezel display products, GOA (Gate On Array) technology is adopted in display products. This technology directly fabricates the gate driving circuit on the array substrate, and drives the sub-pixel rows of the display area through the shift registers of each stage included in the gate driving circuit, thereby realizing the display function of the display product. However, in order to ensure output capability, the gate driving circuit usually adopts a transistor structure with a large aspect ratio, which is not conducive to the development of narrow bezels. Summary of the Invention

[0005] The purpose of this disclosure is to provide a shift register and its driving method, as well as a display panel.

[0006] To achieve the above objectives, this disclosure provides the following technical solution:

[0007] A first aspect of this disclosure provides a shift register, comprising:

[0008] The shift register circuit includes a scan signal output terminal for outputting a basic scan signal via the scan signal output terminal;

[0009] The first intermediate control circuit is coupled to the first clock signal input terminal, the scan signal output terminal, the first level signal input terminal, the second signal input terminal, and the first intermediate signal output terminal, respectively; it is used to control the electrical connection between the first level signal input terminal and the first intermediate signal output terminal to be turned on or off, and to control the electrical connection between the second signal input terminal and the first intermediate signal output terminal to be turned on or off, under the control of the first clock signal input terminal and the basic scan signal;

[0010] A first output control circuit is coupled to a first gate drive signal output terminal, a first intermediate signal output terminal, a third level signal input terminal, and a fourth level signal input terminal, respectively; it is used to control the electrical connection between the third level signal input terminal and the first gate drive signal output terminal to be turned on or off under the control of the first intermediate signal output from the first intermediate signal output terminal; and to control the electrical connection between the fourth level signal input terminal and the first gate drive signal output terminal to be turned on or off.

[0011] The second intermediate control circuit is coupled to the second clock signal input terminal, the scan signal output terminal, the first level signal input terminal, the second signal input terminal, and the second intermediate signal output terminal, respectively; it is used to control the electrical connection between the first level signal input terminal and the second intermediate signal output terminal to be turned on or off, and to control the electrical connection between the second signal input terminal and the second intermediate signal output terminal to be turned on or off, under the control of the second clock signal input terminal and the basic scan signal;

[0012] The second output control circuit is coupled to the second gate drive signal output terminal, the second intermediate signal output terminal, the third level signal input terminal, and the fourth level signal input terminal, respectively; it is used to control the electrical connection between the third level signal input terminal and the second gate drive signal output terminal to be turned on or off under the control of the second intermediate signal output from the second intermediate signal output terminal; and to control the electrical connection between the fourth level signal input terminal and the second gate drive signal output terminal to be turned on or off.

[0013] Optionally, the second signal input terminal is a second level signal input terminal, used to input a second level signal; or, the second signal input terminal is an enable signal input terminal, used to input an enable signal.

[0014] Optionally, the first intermediate control circuit and the second intermediate control circuit include NOR gate circuits; the NOR gate circuits include a first NOR gate input terminal, a second NOR gate input terminal and a first NOR gate output terminal; the NOR gate circuits further include: a first control sub-circuit, a second control sub-circuit, a third control sub-circuit and a fourth control sub-circuit;

[0015] The first control sub-circuit is coupled to the first NOR gate input terminal, the second signal input terminal and the first control node respectively, and is used to control the electrical connection between the second signal input terminal and the first control node to be turned on or off under the control of the signal input to the first NOR gate input terminal;

[0016] The second control sub-circuit is coupled to the first control node, the second NOR gate input terminal and the first NOR gate output terminal respectively, and is used to control the electrical connection between the first control node and the first NOR gate output terminal to be turned on or off under the control of the signal input to the second NOR gate input terminal.

[0017] The third control sub-circuit is coupled to the second NOR gate input terminal, the first NOR gate output terminal and the first level signal input terminal respectively, and is used to control the conduction or disconnection of the electrical connection between the first NOR gate output terminal and the first level signal input terminal under the control of the signal input to the second NOR gate input terminal;

[0018] The fourth control sub-circuit is coupled to the first NOR gate input terminal, the first NOR gate output terminal, and the first level signal input terminal, respectively, and is used to control the electrical connection between the first NOR gate output terminal and the first level signal input terminal to be turned on or off under the control of the signal input at the second NOR gate input terminal.

[0019] In the first intermediate control circuit, one of the first NOR gate input terminal and the second NOR gate input terminal is coupled to the first clock signal input terminal, and the other is coupled to the scan signal output terminal. The first NOR gate output terminal is coupled to the first intermediate signal output terminal.

[0020] In the second intermediate control circuit, one of the first NOR gate input terminal and the second NOR gate input terminal is coupled to the second clock signal input terminal, and the other is coupled to the scan signal output terminal. The first NOR gate output terminal is coupled to the second intermediate signal output terminal.

[0021] Optionally, the first control sub-circuit includes a first control transistor, the gate of the first control transistor is coupled to the input terminal of the first NOR gate, the first terminal of the first control transistor is coupled to the second signal input terminal, and the second terminal of the first control transistor is coupled to the first control node.

[0022] The second control sub-circuit includes a second control transistor, the gate of which is coupled to the input terminal of the second NOR gate, the first terminal of which is coupled to the first control node, and the second terminal of which is coupled to the output terminal of the first NOR gate.

[0023] The third control sub-circuit includes a third control transistor, the gate of which is coupled to the input terminal of the second NOR gate, the first terminal of which is coupled to the first level signal input terminal, and the second terminal of which is coupled to the output terminal of the first NOR gate.

[0024] The fourth control sub-circuit includes a fourth control transistor, the gate of which is coupled to the input terminal of the first NOR gate, the first terminal of which is coupled to the first level signal input terminal, and the second terminal of which is coupled to the output terminal of the first NOR gate.

[0025] Optionally, the first output control circuit and the second output control circuit include NOT gate circuits; the NOT gate circuits include NOT gate input terminals and NOT gate output terminals; the NOT gate circuits include: a fifth control sub-circuit and a sixth control sub-circuit;

[0026] The fifth control sub-circuit is coupled to the NOT gate input terminal, the fourth level signal input terminal and the NOT gate output terminal respectively, and is used to control the conduction or disconnection of the electrical connection between the fourth level signal input terminal and the NOT gate output terminal under the control of the signal input at the NOT gate input terminal;

[0027] The sixth control sub-circuit is coupled to the NOT gate input terminal, the third level signal input terminal and the NOT gate output terminal respectively, and is used to control the electrical connection between the third level signal input terminal and the NOT gate output terminal to be turned on or off under the control of the signal input at the NOT gate input terminal;

[0028] In the first output control circuit, the NOT gate input terminal is coupled to the first intermediate signal output terminal, and the NOT gate output terminal is coupled to the first gate drive signal output terminal.

[0029] In the second output control circuit, the NOT gate input terminal is coupled to the second intermediate signal output terminal, and the NOT gate output terminal is coupled to the second gate drive signal output terminal.

[0030] Optionally, the fifth control sub-circuit includes a fifth control transistor, the gate of which is coupled to the input terminal of the NOT gate, the first terminal of which is coupled to the fourth level signal input terminal, and the second terminal of which is coupled to the output terminal of the NOT gate.

[0031] The sixth control sub-circuit includes a sixth control transistor, the gate of which is coupled to the input terminal of the NOT gate, the first terminal of which is coupled to the input terminal of the third level signal, and the second terminal of which is coupled to the output terminal of the NOT gate.

[0032] Optionally, the signal input at the third level signal input terminal may be the same as or different from the signal input at the first level signal input terminal; the signal input at the fourth level signal input terminal may be the same as or different from the signal input at the second level signal input terminal.

[0033] Optionally, the shift register circuit includes:

[0034] The seventh control sub-circuit is coupled to the fifth clock signal input terminal, the start signal input terminal, the second level signal input terminal, and the second control node, respectively, and is used to control the conduction or disconnection of the electrical connection between the second level signal input terminal and the second control node under the control of the fifth clock signal input terminal and the signal input terminal.

[0035] The eighth control sub-circuit is coupled to the input node, the start signal input terminal, the first level signal input terminal, and the second control node, respectively, and is used to control the conduction or disconnection of the electrical connection between the first level signal input terminal and the second control node under the control of the potential of the input node and the signal input at the start signal input terminal;

[0036] The ninth control sub-circuit is coupled to the input node, the scan signal output terminal, the second level signal input terminal, and the second control node, respectively, and is used to control the conduction or disconnection of the electrical connection between the second level signal input terminal and the second control node under the control of the potential of the input node and the basic scan signal output by the scan signal output terminal;

[0037] The tenth control sub-circuit is coupled to the fifth clock signal input terminal, the scan signal output terminal, the first level signal input terminal and the second control node respectively, and is used to control the conduction or disconnection of the electrical connection between the first level signal input terminal and the second control node under the control of the basic scan signal output by the fifth clock signal and the scan signal output terminal.

[0038] The eleventh control sub-circuit is coupled to the second control node, the first level signal input terminal, the second level signal input terminal, and the scan signal output terminal, respectively. It is used to control the electrical connection between the first level signal input terminal and the scan signal output terminal, and to control the electrical connection between the second level signal input terminal and the scan signal output terminal, under the control of the potential of the second control node.

[0039] Optionally, the shift register circuit further includes:

[0040] The twelfth control sub-circuit is coupled to the control signal input terminal, the second level signal input terminal, and the scan signal output terminal, respectively, and is used to control the electrical connection between the second level signal input terminal and the scan signal output terminal to be turned on or off under the control of the control signal input at the control signal input terminal.

[0041] Optionally, the seventh control sub-circuit includes a first transistor and a second transistor. The gate of the first transistor is coupled to the fifth clock signal input terminal, the first terminal of the first transistor is coupled to the second level signal input terminal, the second terminal of the first transistor is coupled to the first terminal of the second transistor, the gate of the second transistor is coupled to the start signal input terminal, and the second terminal of the second transistor is coupled to the second control node.

[0042] The eighth control sub-circuit includes a third transistor and a fourth transistor. The gate of the third transistor is coupled to the start signal input terminal, the first terminal of the third transistor is coupled to the second terminal of the fourth transistor, the second terminal of the third transistor is coupled to the second control node, the first terminal of the fourth transistor is coupled to the first level signal input terminal, and the gate of the fourth transistor is coupled to the input node.

[0043] The ninth control sub-circuit includes a fifth transistor and a sixth transistor. The gate of the fifth transistor is coupled to the input node, the first terminal of the fifth transistor is coupled to the second level signal input terminal, the second terminal of the fifth transistor is coupled to the first terminal of the sixth transistor, the second terminal of the sixth transistor is coupled to the second control node, and the gate of the sixth transistor is coupled to the scan signal output terminal.

[0044] The tenth control sub-circuit includes a seventh transistor and an eighth transistor. The gate of the seventh transistor is coupled to the scan signal output terminal, the first terminal of the seventh transistor is coupled to the second terminal of the eighth transistor, the second terminal of the seventh transistor is coupled to the second control node, the first terminal of the eighth transistor is coupled to the first level signal input terminal, and the gate of the eighth transistor is coupled to the fifth clock signal input terminal.

[0045] The eleventh control sub-circuit includes a ninth transistor and a tenth transistor. The gate of the ninth transistor is coupled to the second control node, the first terminal of the ninth transistor is coupled to the second level signal input terminal, and the second terminal of the ninth transistor is coupled to the scan signal output terminal. The gate of the tenth transistor is coupled to the second control node, the first terminal of the tenth transistor is coupled to the first level signal input terminal, and the second terminal of the tenth transistor is coupled to the scan signal output terminal.

[0046] The twelfth control sub-circuit includes an eleventh transistor, the gate of which is coupled to the control signal input terminal, the first terminal of which is coupled to the second level signal input terminal, and the second terminal of which is coupled to the scan signal output terminal.

[0047] Optionally, the input node is directly coupled to the sixth clock signal input terminal;

[0048] or,

[0049] The shift register circuit also includes:

[0050] The thirteenth control sub-circuit is coupled to the fifth clock signal input terminal, the first level signal input terminal, the second level signal input terminal, and the input node, respectively. It is used to control the electrical connection between the second level signal input terminal and the input node to be turned on or off under the control of the fifth clock signal input at the fifth clock signal input terminal, and to control the electrical connection between the first level signal input terminal and the input node to be turned on or off.

[0051] Optionally, the thirteenth control sub-circuit includes a twelfth transistor and a thirteenth transistor. The gate of the twelfth transistor is coupled to the fifth clock signal input terminal, the first terminal of the twelfth transistor is coupled to the second level signal input terminal, and the second terminal of the twelfth transistor is coupled to the input node. The gate of the thirteenth transistor is coupled to the fifth clock signal input terminal, the first terminal of the thirteenth transistor is coupled to the first level signal input terminal, and the second terminal of the thirteenth transistor is coupled to the input node.

[0052] Based on the above-mentioned shift register technical solution, the second aspect of this disclosure provides a display panel including multiple cascaded shift registers; the scan signal output terminal of the nth shift register is coupled to the start signal input terminal of the shift register circuit in the (n+1)th shift register, where n is an integer greater than or equal to 1;

[0053] The display panel further includes a frame start signal line, a first clock signal line, a second clock signal line, a third clock signal line, and a fourth clock signal line;

[0054] The start signal input terminal of the shift register circuit in the nth shift register is coupled to the frame start signal line;

[0055] The multiple cascaded shift registers are divided into multiple shift register groups. Each shift register group includes two adjacent shift registers. In each shift register group, the first clock signal input terminal of the preceding shift register is coupled to the first clock signal line, the second clock signal input terminal of the preceding shift register is coupled to the second clock signal line, the first clock signal input terminal of the following shift register is coupled to the third clock signal line, and the second clock signal input terminal of the following shift register is coupled to the fourth clock signal line.

[0056] Optionally, the display panel further includes: a first level signal line, a second level signal line, a third level signal line, a fourth level signal line, a fifth clock signal line, a sixth clock signal line, and a control signal line;

[0057] The frame start signal line, the control signal line, the first level signal line, the second level signal line, the sixth clock signal line, the fifth clock signal line, the fourth clock signal line, the third clock signal line, the second clock signal line, the first clock signal line, the third level signal line, and the fourth level signal line are arranged sequentially along the direction closest to the display area;

[0058] The orthographic projection of the shift register circuit on the substrate of the display panel at least partially overlaps with the orthographic projection of at least one of the following signal lines on the substrate: the frame start signal line, the control signal line, the first level signal line, the second level signal line, the sixth clock signal line, and the fifth clock signal line.

[0059] The orthographic projection of the first intermediate control circuit and / or the second intermediate control circuit on the substrate of the display panel at least partially overlaps with the orthographic projection of at least one of the fourth clock signal line, the third clock signal line, the second clock signal line and the first clock signal line on the substrate.

[0060] The orthographic projection of the first output control circuit and / or the second output control circuit on the substrate of the display panel at least partially overlaps with the orthographic projection of at least one of the third level signal lines and the fourth level signal lines on the substrate.

[0061] Based on the above-described shift register technical solution, a third aspect of this disclosure provides a shift register driving method for driving the shift register, the driving method comprising:

[0062] The shift register circuit outputs the basic scan signal through the scan signal output terminal;

[0063] Under the control of the first clock signal input at the first clock signal input terminal and the basic scan signal, the first intermediate control circuit controls the electrical connection between the first level signal input terminal and the first intermediate signal output terminal to be turned on or off, and controls the electrical connection between the second signal input terminal and the first intermediate signal output terminal to be turned on or off.

[0064] Under the control of the first intermediate signal output from the first intermediate signal output terminal, the first output control circuit controls the electrical connection between the third level signal input terminal and the first gate drive signal output terminal to be turned on or off; and controls the electrical connection between the fourth level signal input terminal and the first gate drive signal output terminal to be turned on or off.

[0065] Under the control of the second clock signal input at the second clock signal input terminal and the basic scan signal, the second intermediate control circuit controls the connection between the first level signal input terminal and the second intermediate signal output terminal to be turned on or off, and controls the connection between the second signal input terminal and the second intermediate signal output terminal to be turned on or off.

[0066] Under the control of the second intermediate signal output from the second intermediate signal output terminal, the second output control circuit controls the electrical connection between the third level signal input terminal and the second gate drive signal output terminal to be turned on or off; and controls the electrical connection between the fourth level signal input terminal and the second gate drive signal output terminal to be turned on or off. Attached Figure Description

[0067] The accompanying drawings, which are included to provide a further understanding of this disclosure and form part of this disclosure, illustrate exemplary embodiments of the present disclosure and are used to explain the disclosure, but do not constitute an undue limitation of the disclosure. In the drawings:

[0068] Figure 1 is a schematic diagram of the structure of the shift register provided in an embodiment of this disclosure;

[0069] Figure 2 is a first structural schematic diagram of the shift register circuit provided in an embodiment of this disclosure;

[0070] Figure 3 is the circuit schematic corresponding to Figure 2;

[0071] Figure 4 is a schematic diagram of the second structure of the shift register circuit provided in an embodiment of this disclosure;

[0072] Figure 5 is the circuit schematic corresponding to Figure 4;

[0073] Figure 6 is a schematic diagram of the intermediate control circuit provided in an embodiment of this disclosure;

[0074] Figure 7 is the circuit schematic corresponding to Figure 6;

[0075] Figure 8 is a schematic diagram of the output control circuit provided in an embodiment of this disclosure;

[0076] Figure 9 is the circuit schematic corresponding to Figure 8;

[0077] Figure 10 is a timing diagram of the shift register circuit provided in an embodiment of this disclosure;

[0078] Figure 11 is a timing diagram of the shift register provided in an embodiment of this disclosure;

[0079] Figure 12 is a timing diagram of the present disclosure when the gate drive signal output terminal is not output in the partial refresh mode;

[0080] Figure 13 is a schematic diagram of the layout of shift registers and signal lines in a display panel provided in an embodiment of this disclosure. Detailed Implementation

[0081] To further illustrate the shift register and its driving method, as well as the display panel provided in the embodiments of this disclosure, a detailed description is provided below with reference to the accompanying drawings.

[0082] Please refer to Figures 1 to 5. This disclosure provides a shift register, including:

[0083] The shift register circuit 10 includes a scan signal output terminal Scan_out (e.g., a first scan signal output terminal Scan_out1 and a second scan signal output terminal Scan_out2), which is used to output the basic scan signal through the scan signal output terminal Scan_out;

[0084] The first intermediate control circuit 21 is coupled to the first clock signal input terminal (connected to the first clock signal line GCK1 or the third clock signal line GCK3), the scan signal output terminal Scan_out, the first level signal input terminal V1, the second signal input terminal (e.g., the enable signal input terminal EN or the second level signal input terminal V2), and the first intermediate signal output terminal (e.g., GOUTN1, GOUTN3). It is used to control the electrical connection between the first level signal input terminal V1 and the first intermediate signal output terminal, and to control the electrical connection between the second signal input terminal and the first intermediate signal output terminal, under the control of the first clock signal input terminal and the basic scan signal.

[0085] The first output control circuit 31 is coupled to the first gate drive signal output terminal (e.g., GOUT1, GOUT3), the first intermediate signal output terminal (e.g., GOUTN1, GOUTN3), the third level signal input terminal V3, and the fourth level signal input terminal V4, respectively; it is used to control the electrical connection between the third level signal input terminal V3 and the first gate drive signal output terminal to be turned on or off under the control of the first intermediate signal output terminal; and to control the electrical connection between the fourth level signal input terminal V4 and the first gate drive signal output terminal to be turned on or off.

[0086] The second intermediate control circuit 22 is coupled to the second clock signal input terminal (connected to the second clock signal line GCK2 or the fourth clock signal line GCK4), the scan signal output terminal Scan_out, the first level signal input terminal V1, the second signal input terminal (e.g., the enable signal input terminal EN or the second level signal input terminal V2), and the second intermediate signal output terminal (e.g., GOUTN2, GOUTN4), respectively. It is used to control the connection between the first level signal input terminal V1 and the second intermediate signal output terminal, and to control the connection between the second signal input terminal and the second intermediate signal output terminal, under the control of the second clock signal input at the second clock signal input terminal and the basic scan signal.

[0087] The second output control circuit 32 is coupled to the second gate drive signal output terminal (e.g., GOUT2, GOUT4), the second intermediate signal output terminal (e.g., GOUTN2, GOUTN4), the third level signal input terminal V3, and the fourth level signal input terminal V4, respectively; it is used to control the electrical connection between the third level signal input terminal V3 and the second gate drive signal output terminal to be turned on or off under the control of the second intermediate signal output from the second intermediate signal output terminal; and to control the electrical connection between the fourth level signal input terminal V4 and the second gate drive signal output terminal to be turned on or off.

[0088] For example, under the control of the first clock signal input at the first clock signal input terminal and the basic scan signal, the first intermediate control circuit 21 controls to connect the electrical connection between the first level signal input terminal V1 and the first intermediate signal output terminal, and controls to disconnect the electrical connection between the second signal input terminal and the first intermediate signal output terminal; or, under the control of the first clock signal input at the first clock signal input terminal and the basic scan signal, the first intermediate control circuit 21 controls to disconnect the electrical connection between the first level signal input terminal V1 and the first intermediate signal output terminal, and controls to connect the electrical connection between the second signal input terminal and the first intermediate signal output terminal.

[0089] For example, under the control of the first intermediate signal output from the first intermediate signal output terminal, the first output control circuit 31 controls to connect the electrical connection between the third level signal input terminal V3 and the first gate drive signal output terminal, and controls to disconnect the electrical connection between the fourth level signal input terminal V4 and the first gate drive signal output terminal; or, under the control of the first intermediate signal output from the first intermediate signal output terminal, the first output control circuit 31 controls to disconnect the electrical connection between the third level signal input terminal V3 and the first gate drive signal output terminal, and controls to connect the electrical connection between the fourth level signal input terminal V4 and the first gate drive signal output terminal.

[0090] For example, under the control of the second clock signal input at the second clock signal input terminal and the basic scan signal, the second intermediate control circuit 22 controls the electrical connection between the first level signal input terminal V1 and the second intermediate signal output terminal to be turned on, and controls the electrical connection between the second signal input terminal and the second intermediate signal output terminal to be turned off; or, under the control of the second clock signal input at the second clock signal input terminal and the basic scan signal, the second intermediate control circuit 22 controls the electrical connection between the first level signal input terminal V1 and the second intermediate signal output terminal to be turned off, and controls the electrical connection between the second signal input terminal and the second intermediate signal output terminal to be turned on.

[0091] For example, under the control of the second intermediate signal output from the second intermediate signal output terminal, the second output control circuit 32 controls the electrical connection between the third level signal input terminal V3 and the second gate drive signal output terminal to be turned on, and controls the electrical connection between the fourth level signal input terminal V4 and the second gate drive signal output terminal to be turned off; or, under the control of the second intermediate signal output from the second intermediate signal output terminal, the second output control circuit 32 controls the electrical connection between the third level signal input terminal V3 and the second gate drive signal output terminal to be turned on, and controls the electrical connection between the fourth level signal input terminal V4 and the second gate drive signal output terminal to be turned on.

[0092] For example, the first clock signal input to the first clock signal input terminal and the second clock signal input to the second clock signal input terminal have the same pulse width and different phases.

[0093] As can be seen from the specific structure of the shift register described above, in the shift register provided in this embodiment, the shift register circuit 10, the first intermediate control circuit 21, and the first output control circuit 31 constitute a circuit structure for controlling the first gate drive signal output terminal to output a first gate drive signal; the shift register circuit 10, the second intermediate control circuit 22, and the second output control circuit 32 constitute another circuit structure for controlling the first gate drive signal output terminal to output a second gate drive signal; the two circuit structures reuse one shift register circuit 10. Therefore, in the shift register provided in this embodiment, one shift register circuit 10 can be used in conjunction with the intermediate control circuit and the output control circuit to achieve the output of two gate drive signals, namely the first gate drive signal and the second gate drive signal, thereby saving one shift register circuit 10 and effectively reducing the number of transistors used when outputting two gate drive signals. When the shift register is applied to a display product, the bezel width of the display product is further narrowed.

[0094] As shown in Figure 6, in some embodiments, the second signal input terminal is a second level signal input terminal V2, used to input a second level signal; or, the second signal input terminal is an enable signal input terminal EN, used to input an enable signal.

[0095] For example, the first level signal input at the first level signal input terminal V1 and the third level signal input at the third level signal input terminal V3 are low level signals, and the second level signal input at the second level signal input terminal V2 and the fourth level signal input at the fourth level signal input terminal V4 are high level signals.

[0096] For example, the level value of the enable signal input at the enable signal input terminal EN can switch between high level and low level.

[0097] For example, in the first display mode (e.g., without HRD partial refresh function), the second signal input terminal is set to the second level signal input terminal V2. In this case, the potential of the first intermediate signal output by the first intermediate signal output terminal is the same as the first level signal or the second level signal, and the potential of the second intermediate signal output by the second intermediate signal output terminal is the same as the first level signal or the second level signal. It should be noted that HRD stands for Hybrid Refresh Display.

[0098] For example, in the second display mode (e.g., in the case of HRD partial refresh function), the second signal input terminal is set as the enable signal input terminal EN. In this case, the potential of the first intermediate signal output by the first intermediate signal output terminal is the same as the first level signal or the enable signal, and the potential of the second intermediate signal output by the second intermediate signal output terminal is the same as the first level signal or the enable signal. The level value of the enable signal can be the same as the level value of the first level signal.

[0099] It should be noted that the second signal input terminal can be set as the enable signal input terminal EN. By controlling the enable signal input to the enable signal input terminal EN to have the same potential as the second level signal, non-HRD partial refresh can be achieved. Alternatively, the enable signal input to the enable signal input terminal EN can be controlled to have the same potential as the first level signal, thereby achieving HRD partial refresh.

[0100] When the second signal input terminal is set to the enable signal input terminal EN, the level of the first intermediate signal and the second intermediate signal can be controlled by controlling the level of the enable signal, thereby controlling whether the first gate drive signal and the second gate drive signal are at an effective level, and realizing the HRD partial refresh function.

[0101] As shown in Figures 1, 6, and 7, in some embodiments, at least one of the first intermediate control circuit 21 and the second intermediate control circuit 22 includes a NOR gate circuit; the NOR gate circuit includes a first NOR gate input terminal in1, a second NOR gate input terminal in2, and a first NOR gate output terminal out1; the NOR gate circuit further includes: a first control sub-circuit 201, a second control sub-circuit 202, a third control sub-circuit 203, and a fourth control sub-circuit 204;

[0102] The first control sub-circuit 201 is coupled to the first NOR gate input terminal in1, the second signal input terminal and the first control node N1 respectively, and is used to control the conduction or disconnection of the electrical connection between the second signal input terminal and the first control node N1 under the control of the signal input to the first NOR gate input terminal in1.

[0103] The second control sub-circuit 202 is coupled to the first control node N1, the second NOR gate input terminal in2 and the first NOR gate output terminal out1 respectively, and is used to control the electrical connection between the first control node N1 and the first NOR gate output terminal out1 under the control of the signal input to the second NOR gate input terminal in2.

[0104] The third control sub-circuit 203 is coupled to the second NOR gate input terminal in2, the first NOR gate output terminal out1 and the first level signal input terminal V1 respectively, and is used to control the electrical connection between the first NOR gate output terminal out1 and the first level signal input terminal V1 under the control of the signal input to the second NOR gate input terminal in2.

[0105] The fourth control sub-circuit 204 is coupled to the first NOR gate input terminal in1, the first NOR gate output terminal out1, and the first level signal input terminal V1, respectively, and is used to control the electrical connection between the first NOR gate output terminal out1 and the first level signal input terminal V1 under the control of the signal input at the second NOR gate input terminal in2.

[0106] In the first intermediate control circuit 21, one of the first NOR gate input terminal in1 and the second NOR gate input terminal in2 is coupled to the first clock signal input terminal, and the other is coupled to the scan signal output terminal Scan_out. The first NOR gate output terminal out1 is coupled to the first intermediate signal output terminal.

[0107] In the second intermediate control circuit 22, one of the first NOR gate input terminal in1 and the second NOR gate input terminal in2 is coupled to the second clock signal input terminal, and the other is coupled to the scan signal output terminal Scan_out. The first NOR gate output terminal out1 is coupled to the second intermediate signal output terminal.

[0108] For example, the first control sub-circuit 201 includes a first control transistor T01, the gate of the first control transistor T01 is coupled to the input terminal in1 of the first NOR gate, the first terminal of the first control transistor T01 is coupled to the second signal input terminal, and the second terminal of the first control transistor T01 is coupled to the first control node N1.

[0109] The second control sub-circuit 202 includes a second control transistor T02, the gate of the second control transistor T02 is coupled to the input terminal in2 of the second NOR gate, the first terminal of the second control transistor T02 is coupled to the first control node N1, and the second terminal of the second control transistor T02 is coupled to the output terminal out1 of the first NOR gate.

[0110] The third control sub-circuit 203 includes a third control transistor T03. The gate of the third control transistor T03 is coupled to the input terminal in2 of the second NOR gate. The first terminal of the third control transistor T03 is coupled to the first level signal input terminal V1. The second terminal of the third control transistor T03 is coupled to the output terminal out1 of the first NOR gate.

[0111] The fourth control sub-circuit 204 includes a fourth control transistor T04. The gate of the fourth control transistor T04 is coupled to the input terminal in1 of the first NOR gate, the first terminal of the fourth control transistor T04 is coupled to the input terminal V1 of the first level signal, and the second terminal of the fourth control transistor T04 is coupled to the output terminal out1 of the first NOR gate.

[0112] For example, the first control transistor T01 and the second control transistor T02 are PMOS transistors, and the third control transistor T03 and the fourth control transistor T04 are NMOS transistors. Optionally, the third control transistor T03 and the fourth control transistor T04 are dual-gate transistors, but are not limited to this.

[0113] For example, when the second signal input terminal is the second level signal input terminal V2, the NOR gate circuit satisfies the logic operation results in Table 1 below.

[0114] Table 1

[0115] For example, when the second signal input terminal is the enable signal input terminal EN, the NOR gate circuit satisfies the logic operation results shown in Table 2 below.

[0116] Table 2

[0117] As shown in Figures 8 and 9, in some embodiments, at least one of the first output control circuit 31 and the second output control circuit 32 includes a NOT gate circuit; the NOT gate circuit includes a NOT gate input terminal in3 and a NOT gate output terminal out2; the NOT gate circuit includes: a fifth control sub-circuit 305 and a sixth control sub-circuit 306;

[0118] The fifth control sub-circuit 305 is coupled to the NOT gate input terminal in3, the fourth level signal input terminal V4 and the NOT gate output terminal out2 respectively, and is used to control the conduction or disconnection of the electrical connection between the fourth level signal input terminal V4 and the NOT gate output terminal out2 under the control of the signal input to the NOT gate input terminal in3;

[0119] The sixth control sub-circuit 306 is coupled to the NOT gate input terminal in3, the third level signal input terminal V3 and the NOT gate output terminal out2 respectively, and is used to control the conduction or disconnection of the electrical connection between the third level signal input terminal V3 and the NOT gate output terminal out2 under the control of the signal input to the NOT gate input terminal in3;

[0120] In the first output control circuit 31, the NOT gate input terminal in3 is coupled to the first intermediate signal output terminal, and the NOT gate output terminal out2 is coupled to the first gate drive signal output terminal.

[0121] In the second output control circuit 32, the NOT gate input terminal in3 is coupled to the second intermediate signal output terminal, and the NOT gate output terminal out2 is coupled to the second gate drive signal output terminal.

[0122] For example, the fifth control sub-circuit 305 includes a fifth control transistor T05, the gate of the fifth control transistor T05 is coupled to the input terminal in3 of the NOT gate, the first terminal of the fifth control transistor T05 is coupled to the fourth level signal input terminal V4, and the second terminal of the fifth control transistor T05 is coupled to the output terminal out2 of the NOT gate;

[0123] The sixth control sub-circuit 306 includes a sixth control transistor T06. The gate of the sixth control transistor T06 is coupled to the input terminal in3 of the NOT gate. The first terminal of the sixth control transistor T06 is coupled to the input terminal V3 of the third level signal. The second terminal of the sixth control transistor T06 is coupled to the output terminal out2 of the NOT gate.

[0124] For example, the fifth control transistor T05 is a PMOS transistor, the sixth control transistor T06 is an NMOS transistor, and the sixth control transistor T06 is a dual-gate transistor, but it is not limited to these.

[0125] For example, the first output control circuit 31 and the second output control circuit 32 include 2n+1 NOT gate circuits, where n is an integer greater than or equal to 0. When n is greater than 0, the 2n+1 NOT gate circuits are connected in series. The NOT gate input terminal in3 of the first NOT gate circuit is coupled to the first intermediate signal output terminal or the second intermediate signal output terminal. The NOT gate output terminal out2 of the last NOT gate circuit is coupled to the first gate drive signal output terminal or the second gate drive signal output terminal.

[0126] For example, the NOT gate circuit satisfies the logic operation results shown in Table 3 below.

[0127] Table 3

[0128] In the shift register provided in the above embodiment, by setting the NOT gate circuit, the signal output from the intermediate signal output terminal can be inverted and amplified after passing through the inverter formed by the NOT gate circuit to output the final PGate signal, which is a scan signal active at low level.

[0129] The NOR gate circuits and NOT gate circuits provided in the above embodiments, when combined, satisfy the logic operation results in Tables 4 and 5 below.

[0130] In the first display mode (e.g., without HRD partial refresh functionality):

[0131] Table 4

[0132] In the second display mode (e.g., with HRD partial refresh functionality):

[0133] Table 5

[0134] In some embodiments, the signal input at the third level signal input terminal V3 may be the same as or different from the signal input at the first level signal input terminal V1; and the signal input at the fourth level signal input terminal V4 may be the same as or different from the signal input at the second level signal input terminal V2.

[0135] The above-mentioned configuration sets the signal input at the third-level signal input terminal V3 to be the same as the signal input at the first-level signal input terminal V1, allowing them to be connected to the same signal line. Similarly, the configuration sets the signal input at the fourth-level signal input terminal V4 to be the same as the signal input at the second-level signal input terminal V2, allowing them to be connected to the same signal line. This design, when applied to display products, helps reduce the number of signal lines in the display product layout, simplifying its complexity.

[0136] The above-mentioned configuration, where the signal input at the third level signal input terminal V3 is different from that input at the first level signal input terminal V1, and the signal input at the fourth level signal input terminal V4 is different from that input at the second level signal input terminal V2, is beneficial for improving output capability and reducing power consumption.

[0137] As shown in Figures 2 to 5, in some embodiments, the shift register circuit 10 includes:

[0138] The seventh control sub-circuit 107 is coupled to the fifth clock signal input terminal CK, the start signal input terminal Scan_in, the second level signal input terminal V2, and the second control node Scan_N, respectively. It is used to control the electrical connection between the second level signal input terminal V2 and the second control node Scan_N to be turned on or off under the control of the fifth clock signal input at the fifth clock signal input terminal CK and the signal input at the start signal input terminal Scan_in.

[0139] The eighth control sub-circuit 108 is coupled to the input node CKN, the start signal input terminal Scan_in, the first level signal input terminal V1, and the second control node Scan_N, respectively. It is used to control the conduction or disconnection of the electrical connection between the first level signal input terminal V1 and the second control node Scan_N under the control of the potential of the input node CKN and the signal input to the start signal input terminal Scan_in.

[0140] The ninth control sub-circuit 109 is coupled to the input node CKN, the scan signal output terminal Scan_out, the second level signal input terminal V2, and the second control node Scan_N, respectively. It is used to control the conduction or disconnection of the electrical connection between the second level signal input terminal V2 and the second control node Scan_N under the control of the potential of the input node CKN and the basic scan signal output by the scan signal output terminal Scan_out.

[0141] The tenth control sub-circuit 110 is coupled to the fifth clock signal input terminal CK, the scan signal output terminal Scan_out, the first level signal input terminal V1 and the second control node Scan_N respectively, and is used to control the electrical connection between the first level signal input terminal V1 and the second control node Scan_N to be turned on or off under the control of the basic scan signal output by the fifth clock signal and the scan signal output terminal Scan_out.

[0142] The eleventh control sub-circuit 111 is coupled to the second control node Scan_N, the first level signal input terminal V1, the second level signal input terminal V2, and the scan signal output terminal Scan_out, respectively. It is used to control the electrical connection between the first level signal input terminal V1 and the scan signal output terminal Scan_out, and to control the electrical connection between the second level signal input terminal V2 and the scan signal output terminal Scan_out, under the control of the potential of the second control node Scan_N.

[0143] For example, the seventh control sub-circuit 107 includes a first transistor T1 and a second transistor T2. The gate of the first transistor T1 is coupled to the fifth clock signal input terminal CK. The first terminal of the first transistor T1 is coupled to the second level signal input terminal V2. The second terminal of the first transistor T1 is coupled to the first terminal of the second transistor T2. The gate of the second transistor T2 is coupled to the start signal input terminal Scan_in. The second terminal of the second transistor T2 is coupled to the second control node Scan_N.

[0144] The eighth control sub-circuit 108 includes a third transistor T3 and a fourth transistor T4. The gate of the third transistor T3 is coupled to the start signal input terminal Scan_in. The first terminal of the third transistor T3 is coupled to the second terminal of the fourth transistor T4. The second terminal of the third transistor T3 is coupled to the second control node Scan_N. The first terminal of the fourth transistor T4 is coupled to the first level signal input terminal V1. The gate of the fourth transistor T4 is coupled to the input node CKN.

[0145] The ninth control sub-circuit 109 includes a fifth transistor T5 and a sixth transistor T6. The gate of the fifth transistor T5 is coupled to the input node CKN. The first terminal of the fifth transistor T5 is coupled to the second level signal input terminal V2. The second terminal of the fifth transistor T5 is coupled to the first terminal of the sixth transistor T6. The second terminal of the sixth transistor T6 is coupled to the second control node Scan_N. The gate of the sixth transistor T6 is coupled to the scan signal output terminal Scan_out.

[0146] The tenth control sub-circuit 110 includes a seventh transistor T7 and an eighth transistor T8. The gate of the seventh transistor T7 is coupled to the scan signal output terminal Scan_out. The first terminal of the seventh transistor T7 is coupled to the second terminal of the eighth transistor T8. The second terminal of the seventh transistor T7 is coupled to the second control node Scan_N. The first terminal of the eighth transistor T8 is coupled to the first level signal input terminal V1. The gate of the eighth transistor T8 is coupled to the fifth clock signal input terminal CK.

[0147] The eleventh control sub-circuit 111 includes a ninth transistor T9 and a tenth transistor T10. The gate of the ninth transistor T9 is coupled to the second control node Scan_N, the first terminal of the ninth transistor T9 is coupled to the second level signal input terminal V2, and the second terminal of the ninth transistor T9 is coupled to the scan signal output terminal Scan_out. The gate of the tenth transistor T10 is coupled to the second control node Scan_N, the first terminal of the tenth transistor T10 is coupled to the first level signal input terminal V1, and the second terminal of the tenth transistor T10 is coupled to the scan signal output terminal Scan_out.

[0148] For example, the first transistor T1, the second transistor T2, the fifth transistor T5, and the sixth transistor T6 are PMOS transistors, the third transistor T3, the fourth transistor T4, the seventh transistor T7, and the eighth transistor T8 are NMOS transistors, and the third transistor T3, the fourth transistor T4, the seventh transistor T7, and the eighth transistor T8 are dual-gate transistors, but not limited to these.

[0149] As shown in Figures 2 to 5, in some embodiments, the shift register circuit 10 further includes:

[0150] The twelfth control sub-circuit 112 is coupled to the control signal input terminal CX, the second level signal input terminal V2, and the scan signal output terminal Scan_out, respectively. It is used to control the electrical connection between the second level signal input terminal V2 and the scan signal output terminal Scan_out to be turned on or off under the control of the control signal input at the control signal input terminal CX.

[0151] For example, the twelfth control sub-circuit 112 includes an eleventh transistor T11, the gate of which is coupled to the control signal input terminal CX, the first terminal of which is coupled to the second level signal input terminal V2, and the second terminal of which is coupled to the scan signal output terminal Scan_out.

[0152] For example, the eleventh transistor T11 is a PMOS transistor, but it is not limited to this.

[0153] For example, the control signal input terminal CX is used for power-on, power-off and screen clearing. When the product is displaying normally, the control signal is kept at a high level (e.g., VGH), and when the product is powered on or off, the control signal is pulled low (e.g., VGL).

[0154] The shift register circuit 10 described above includes a twelfth control sub-circuit 112, which enables the screen to be cleared when the display product is turned on or off.

[0155] As shown in Figures 2 to 5, in some embodiments, the input node CKN is directly coupled to the sixth clock signal input terminal CB; or, the shift register circuit 10 further includes: a thirteenth control sub-circuit 113, which is coupled to the fifth clock signal input terminal CK, the first level signal input terminal V1, the second level signal input terminal V2 and the input node CKN respectively, and is used to control the conduction or disconnection of the electrical connection between the second level signal input terminal V2 and the input node CKN under the control of the fifth clock signal input at the fifth clock signal input terminal CK, and to control the conduction or disconnection of the electrical connection between the first level signal input terminal V1 and the input node CKN.

[0156] For example, the thirteenth control sub-circuit 113 includes a twelfth transistor T12 and a thirteenth transistor T13. The gate of the twelfth transistor T12 is coupled to the fifth clock signal input terminal CK, the first terminal of the twelfth transistor T12 is coupled to the second level signal input terminal V2, and the second terminal of the twelfth transistor T12 is coupled to the input node CKN. The gate of the thirteenth transistor T13 is coupled to the fifth clock signal input terminal CK, the first terminal of the thirteenth transistor T13 is coupled to the first level signal input terminal V1, and the second terminal of the thirteenth transistor T13 is coupled to the input node CKN.

[0157] For example, the twelfth transistor T12 includes a PMOS transistor, the thirteenth transistor T13 includes an NMOS transistor, and the thirteenth transistor T13 includes a dual-gate transistor, but is not limited thereto.

[0158] It should be noted that the clock signals input to the fifth clock signal input terminal CK and the sixth clock signal input terminal CB can be clock signals output independently by the driver chip, or they can be shared with clock signals used by other types of GOAs in the display, such as the ECK and ECB clock signals used by the EM GOA, or the NCK or NCB clock signals used by the NGate GOA, etc. The clock signals input to the fifth clock signal input terminal CK and the sixth clock signal input terminal CB are completely inverted.

[0159] EM GOA refers to a shift register that provides light emission control scan signals to the pixel driving circuitry in the display area. NGate GOA refers to a shift register that provides gate scan signals to the gates of the N-type transistors included in the pixel driving circuitry in the display area.

[0160] As shown in Figures 2-5 and 10, more specifically, when the level of the fifth clock signal input at the fifth clock signal input terminal CK is low, the eighth transistor T8 is off, the first transistor T1 is on, and the potential of the input node CKN or the potential of the sixth clock signal input at the sixth clock signal input terminal CB is high. At this time, the fifth transistor T5 is off, and the fourth transistor T4 is on. The shift register circuit 10 is in the transmission state. When the signal input at the start signal input terminal Scan_in is low, the second transistor T2 is on, the third transistor T3 is off, and the potential of the second control node Scan_N is high. The tenth transistor T10... When the 9th transistor T9 is turned off, the level of the basic scan signal output at Scan_out is the same as the level of the signal input at Scan_in, both being low. When the signal input at Scan_in is high, the 2nd transistor T2 is turned off, the 3rd transistor T3 is turned on, the potential of the 2nd control node Scan_N is low, the 10th transistor T10 is turned off, the 9th transistor T9 is turned on, and the level of the basic scan signal output at Scan_out is the same as the level of the signal input at Scan_in, both being high.

[0161] When the level of the fifth clock signal input at the fifth clock signal input terminal CK is high, the eighth transistor T8 turns on, the first transistor T1 turns off, and the potential of the input node CKN or the potential of the sixth clock signal input at the sixth clock signal input terminal CB is low. At this time, the fifth transistor T5 turns on, and the fourth transistor T4 turns off. The shift register circuit 10 is in the register state. The sixth transistor T6, the seventh transistor T7, the ninth transistor T9, and the tenth transistor T10 form a latch circuit. The potential of the second control node Scan_N and the level of the signal output at the scan signal output terminal Scan_out remain unchanged from the previous state.

[0162] As shown in Figure 10, during the P2 period, when the signal input at the start signal input terminal Scan_in switches from low to high, and when the level of the fifth clock signal input at the fifth clock signal input terminal CK is high, the eighth transistor T8 turns on, the first transistor T1 turns off, and the potential of the input node CKN or the potential of the sixth clock signal input at the sixth clock signal input terminal CB is low. At this time, the fifth transistor T5 turns on, and the fourth transistor T4 turns off. The shift register circuit 10 is in the register state. The sixth transistor T6, the seventh transistor T7, the ninth transistor T9, and the tenth transistor T10 form a latch circuit. The potential of the second control node Scan_N and the level of the signal output at the scan signal output terminal Scan_out remain unchanged from the previous low level state, thus completing the shift. At the next moment, when the level of the fifth clock signal input at the fifth clock signal input terminal CK is low, the eighth transistor T8 is turned off, the first transistor T1 is turned on, the potential of the input node CKN or the potential of the sixth clock signal input at the sixth clock signal input terminal CB is high, the fifth transistor T5 is turned off, and the fourth transistor T4 is turned on. At this time, the shift register circuit 10 is in the transmission state. When the signal input at the start signal input terminal Scan_in is high, the second transistor T2 is turned off, the third transistor T3 is turned on, the potential of the second control node Scan_N is low, the tenth transistor T10 is turned off, and the ninth transistor T9 is turned on. The level of the basic scan signal output at the scan signal output terminal Scan_out is the same as the level of the signal input at the start signal input terminal Scan_in, both being high, thus realizing the shift register of the signal input at the start signal input terminal Scan_in to the basic scan signal output at the scan signal output terminal Scan_out.

[0163] As shown in Figure 10, during the P1 period, when the signal input at the start signal input terminal Scan_in switches from high level to low level, and when the level of the fifth clock signal input at the fifth clock signal input terminal CK is high level, the eighth transistor T8 turns on, the first transistor T1 turns off, and the potential of the input node CKN or the potential of the sixth clock signal input at the sixth clock signal input terminal CB is low. At this time, the fifth transistor T5 turns on, and the fourth transistor T4 turns off. The shift register circuit 10 is in the register state. The sixth transistor T6, the seventh transistor T7, the ninth transistor T9, and the tenth transistor T10 form a latch circuit. The potential of the second control node Scan_N and the level of the signal output at the scan signal output terminal Scan_out remain unchanged at the previous low level, thus completing the shift. At the next moment, when the level of the fifth clock signal input at the fifth clock signal input terminal CK is low, the eighth transistor T8 is turned off, the first transistor T1 is turned on, the potential of the input node CKN or the potential of the sixth clock signal input at the sixth clock signal input terminal CB is high, the fifth transistor T5 is turned off, and the fourth transistor T4 is turned on. At this time, the shift register circuit 10 is in the transmission state. When the signal input at the start signal input terminal Scan_in is low, the second transistor T2 is turned on, the third transistor T3 is turned off, the potential of the second control node Scan_N is high, the tenth transistor T10 is turned on, and the ninth transistor T9 is turned off. The level of the basic scan signal output at the scan signal output terminal Scan_out is the same as the level of the signal input at the start signal input terminal Scan_in, both being low, thus realizing the shift register of the signal input at the start signal input terminal Scan_in to the basic scan signal output at the scan signal output terminal Scan_out.

[0164] It should be noted that Figure 10 illustrates the basic scan signal output by Scan_out(n-1) of the (n-1)th stage shift register circuit, the basic scan signal output by Scan_out(n) of the nth stage shift register circuit, the basic scan signal output by Scan_out(n) of the n+1th stage shift register circuit, the signal of the second control node Scan_N(n) of the nth stage shift register circuit, and the signal of the second control node Scan_N(n+1) of the n+1th stage shift register circuit.

[0165] Figure 11 illustrates the signal timing of the first gate drive signal output terminal GOUT1, the second gate drive signal output terminal GOUT2, the first intermediate signal output terminal GOUTN1, the second intermediate signal output terminal GOUTN2, the first gate drive signal output terminal GOUT3, the second gate drive signal output terminal GOUT4, the first intermediate signal output terminal GOUTN3, and the second intermediate signal output terminal GOUTN4 in the second-stage shift register. When the enable signal input EN is high, based on the previous working principle and logic operations, the basic scan signal and clock signal can output the PGate signal waveform through NOR gates and NOT gates.

[0166] As shown in Figure 12, under HRD partial refresh, when the enable signal input at the enable signal input terminal EN is low, based on the previous working principle and logic operations, the PGate signal output at the gate drive signal output terminal GOUT remains high. In Figure 12, the horizontal axis represents time, which is 1.54ms, 1.55ms, 1.56ms, 1.57ms, 1.58ms, 1.59ms, 1.60ms, 1.61ms, 1.62ms, 1.63ms, and 1.64ms respectively. The vertical axis represents voltage, ranging from -7V to +7V. Figure 12 illustrates -5V, 0V, and 5V.

[0167] The shift register provided in the above embodiment is built using a CMOS architecture. It uses a shift register circuit 10 in conjunction with an intermediate control circuit and an output control circuit to output two gate drive signals, thereby saving one shift register circuit 10 and effectively reducing the number of transistors used when outputting two gate drive signals. When the shift register is applied to a display product, the bezel width of the display product is further narrowed.

[0168] Compared to simple PMOS or NMOS GOA circuits, the CMOS GOA circuits provided in the above embodiments have advantages such as strong output capability, good stability, and low power consumption. They can typically achieve stronger output capability with transistors that have a smaller aspect ratio.

[0169] As shown in Figure 13, this embodiment of the present disclosure also provides a display panel, including a plurality of cascaded shift registers; the scan signal output terminal Scan_out(n) in the nth shift register is coupled to the start signal input terminal of the shift register circuit 10 in the (n+1)th shift register, where n is an integer greater than or equal to 1;

[0170] The display panel also includes a frame start signal line GSTV', a first clock signal line GCK1, a second clock signal line GCK2, a third clock signal line GCK3, and a fourth clock signal line GCK4;

[0171] The start signal input terminal Scan_in of the shift register circuit 10 in the nth shift register is coupled to the frame start signal line GSTV'.

[0172] The multiple cascaded shift registers are divided into multiple shift register groups. Each shift register group includes two adjacent shift registers. In each shift register group, the first clock signal input terminal of the preceding shift register is coupled to the first clock signal line GCK1, the second clock signal input terminal of the preceding shift register is coupled to the second clock signal line GCK2, the first clock signal input terminal of the following shift register is coupled to the third clock signal line GCK3, and the second clock signal input terminal of the following shift register is coupled to the fourth clock signal line GCK4.

[0173] For example, the first clock signal transmitted by the first clock signal line GCK1, the second clock signal transmitted by the second clock signal line GCK2, the third clock signal transmitted by the third clock signal line GCK3, and the fourth clock signal transmitted by the fourth clock signal line GCK4 have the same pulse width and different phases.

[0174] It should be noted that the two-stage shift register shown in Figure 1 is the smallest loop unit.

[0175] The shift register provided in the above embodiment can use a shift register circuit 10 in conjunction with an intermediate control circuit and an output control circuit to output two gate drive signals, namely a first gate drive signal and a second gate drive signal, thereby saving a shift register circuit 10 and effectively reducing the number of transistors used when outputting two gate drive signals. When the shift register is applied to a display product, the bezel width of the display product is further narrowed.

[0176] It should be noted that the display panel can be used in a display device, which can be any product or component with display function, such as a television, monitor, digital photo frame, mobile phone, or tablet computer. The display device also includes flexible circuit boards, printed circuit boards, and back panels.

[0177] Therefore, when the display panel provided in the embodiments of this disclosure includes the above-mentioned shift register, it can not only ensure the stability of the display area driving, but also help to further reduce the bezel width.

[0178] In some embodiments, the display panel further includes: a first level signal line V1', a second level signal line V2', a third level signal line V3', a fourth level signal line V4', a fifth clock signal line CK', a sixth clock signal line CB', and a control signal line CX';

[0179] The frame start signal line GSTV', the control signal line CX', the first level signal line V1', the second level signal line V2', the sixth clock signal line CB', the fifth clock signal line CK', the fourth clock signal line GCK4, the third clock signal line GCK3, the second clock signal line GCK2, the first clock signal line GCK1, the third level signal line V3', and the fourth level signal line V4' are arranged sequentially in the direction close to the display area. It should be noted that when the above signal lines are arranged in different layers, the orthogonal projection of the above signal lines on the substrate of the display panel can be arranged in the above order.

[0180] The orthographic projection of the shift register circuit 10 on the substrate of the display panel at least partially overlaps with the orthographic projection of at least one of the following signal lines on the substrate: the frame start signal line GSTV', the control signal line CX', the first level signal line V1', the second level signal line V2', the sixth clock signal line CB', and the fifth clock signal line CK'.

[0181] The orthographic projection of the first intermediate control circuit 21 and / or the second intermediate control circuit 22 on the substrate of the display panel at least partially overlaps with the orthographic projection of at least one of the following signal lines on the substrate: the fourth clock signal line GCK4, the third clock signal line GCK3, the second clock signal line GCK2, and the first clock signal line GCK1.

[0182] The orthographic projection of the first output control circuit 31 and / or the second output control circuit 32 on the substrate of the display panel at least partially overlaps with the orthographic projection of at least one of the third level signal line V3' and the fourth level signal line V4' on the substrate.

[0183] For example, the display panel further includes an enable signal line EN', which is coupled to the enable signal input terminal EN. The orthographic projection of the enable signal line EN' on the substrate is located between the orthographic projection of the fifth clock signal line CK' on the substrate and the orthographic projection of the fourth clock signal line GCK4 on the substrate, but is not limited thereto.

[0184] For example, the orthographic projection of the first intermediate control circuit 21 onto the substrate of the display panel may or may not overlap with the orthographic projection of the enable signal line EN' onto the substrate. The orthographic projection of the second intermediate control circuit 22 onto the substrate of the display panel may or may not overlap with the orthographic projection of the enable signal line EN' onto the substrate.

[0185] Arranging the display panel in the above manner not only helps reduce the layout difficulty between the shift register and various signal lines, but also further reduces the layout space occupied by the shift register and various signal lines, which is conducive to the development of narrow bezels in the display panel.

[0186] This disclosure also provides a method for driving a shift register, used to drive the shift register provided in the above embodiments, the method comprising:

[0187] The shift register circuit 10 outputs the basic scan signal through the scan signal output terminal Scan_out;

[0188] Under the control of the first clock signal input at the first clock signal input terminal and the basic scan signal, the first intermediate control circuit 21 controls the electrical connection between the first level signal input terminal V1 and the first intermediate signal output terminal to be turned on or off, and controls the electrical connection between the second signal input terminal and the first intermediate signal output terminal to be turned on or off.

[0189] Under the control of the first intermediate signal output from the first intermediate signal output terminal, the first output control circuit 31 controls the electrical connection between the third level signal input terminal V3 and the first gate drive signal output terminal to be turned on or off; and controls the electrical connection between the fourth level signal input terminal V4 and the first gate drive signal output terminal to be turned on or off.

[0190] Under the control of the second clock signal input at the second clock signal input terminal and the basic scan signal, the second intermediate control circuit 22 controls the electrical connection between the first level signal input terminal V1 and the second intermediate signal output terminal to be turned on or off, and controls the electrical connection between the second signal input terminal and the second intermediate signal output terminal to be turned on or off.

[0191] Under the control of the second intermediate signal output from the second intermediate signal output terminal, the second output control circuit 32 controls the electrical connection between the third level signal input terminal V3 and the second gate drive signal output terminal to be turned on or off; and controls the electrical connection between the fourth level signal input terminal V4 and the second gate drive signal output terminal to be turned on or off.

[0192] When the shift register is driven using the driving method provided in this disclosure, the shift register circuit 10, the first intermediate control circuit 21, and the first output control circuit 31 constitute a circuit structure for controlling the first gate drive signal output terminal to output the first gate drive signal; the shift register circuit 10, the second intermediate control circuit 22, and the second output control circuit 32 constitute another circuit structure for controlling the first gate drive signal output terminal to output the second gate drive signal; the two circuit structures reuse one shift register circuit 10. Therefore, by using the driving method provided in this disclosure to drive the shift register, one shift register circuit 10 can be used in conjunction with the intermediate control circuit and the output control circuit to achieve the output of two gate drive signals, namely the first gate drive signal and the second gate drive signal, thereby saving one shift register circuit 10 and effectively reducing the number of transistors used when outputting two gate drive signals. When the shift register is applied to a display product, the bezel width of the display product is further narrowed.

[0193] In the various method embodiments of this disclosure, the sequence numbers of each step are not intended to limit the order of the steps. For those skilled in the art, any changes in the order of the steps are within the scope of protection of this disclosure without any creative effort.

[0194] It should be noted that the various embodiments in this specification are described in a progressive manner, and the same or similar parts between the various embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the method embodiments are basically similar to the product embodiments, so the description is relatively simple, and the relevant parts can be referred to the description of the product embodiments.

[0195] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connection,” “coupled,” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “upper,” “lower,” “left,” and “right” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0196] It is understandable that when a component such as a layer, film, region, or substrate is referred to as being "above" or "below" another component, the component may be "directly" located "above" or "below" the other component, or there may be intermediate components present.

[0197] In the description of the above embodiments, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.

[0198] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A shift register, comprising: The shift register circuit includes a scan signal output terminal for outputting a basic scan signal via the scan signal output terminal; The first intermediate control circuit is coupled to the first clock signal input terminal, the scan signal output terminal, the first level signal input terminal, the second signal input terminal, and the first intermediate signal output terminal, respectively; it is used to control the electrical connection between the first level signal input terminal and the first intermediate signal output terminal to be turned on or off, and to control the electrical connection between the second signal input terminal and the first intermediate signal output terminal to be turned on or off, under the control of the first clock signal input terminal and the basic scan signal; The first output control circuit is coupled to the first gate drive signal output terminal, the first intermediate signal output terminal, the third level signal input terminal and the fourth level signal input terminal respectively; it is used to control the electrical connection between the third level signal input terminal and the first gate drive signal output terminal to be turned on or off under the control of the first intermediate signal output from the first intermediate signal output terminal. And control the electrical connection between the fourth level signal input terminal and the first gate drive signal output terminal to be turned on or off; The second intermediate control circuit is coupled to the second clock signal input terminal, the scan signal output terminal, the first level signal input terminal, the second signal input terminal, and the second intermediate signal output terminal, respectively; it is used to control the electrical connection between the first level signal input terminal and the second intermediate signal output terminal to be turned on or off, and to control the electrical connection between the second signal input terminal and the second intermediate signal output terminal to be turned on or off, under the control of the second clock signal input terminal and the basic scan signal; The second output control circuit is coupled to the second gate drive signal output terminal, the second intermediate signal output terminal, the third level signal input terminal and the fourth level signal input terminal respectively; it is used to control the electrical connection between the third level signal input terminal and the second gate drive signal output terminal to be turned on or off under the control of the second intermediate signal output from the second intermediate signal output terminal. And control the electrical connection between the fourth level signal input terminal and the second gate drive signal output terminal to be turned on or off.

2. The shift register according to claim 1, wherein, The second signal input terminal is a second-level signal input terminal, used to input a second-level signal; Alternatively, the second signal input terminal can be an enable signal input terminal, used to input an enable signal.

3. The shift register according to claim 2, wherein, The first intermediate control circuit and the second intermediate control circuit include NOR gate circuits; the NOR gate circuits include a first NOR gate input terminal, a second NOR gate input terminal, and a first NOR gate output terminal; The NOR gate circuit further includes: a first control sub-circuit, a second control sub-circuit, a third control sub-circuit, and a fourth control sub-circuit; The first control sub-circuit is coupled to the first NOR gate input terminal, the second signal input terminal and the first control node respectively, and is used to control the electrical connection between the second signal input terminal and the first control node to be turned on or off under the control of the signal input to the first NOR gate input terminal; The second control sub-circuit is coupled to the first control node, the second NOR gate input terminal and the first NOR gate output terminal respectively, and is used to control the electrical connection between the first control node and the first NOR gate output terminal to be turned on or off under the control of the signal input to the second NOR gate input terminal. The third control sub-circuit is coupled to the second NOR gate input terminal, the first NOR gate output terminal and the first level signal input terminal respectively, and is used to control the conduction or disconnection of the electrical connection between the first NOR gate output terminal and the first level signal input terminal under the control of the signal input to the second NOR gate input terminal; The fourth control sub-circuit is coupled to the first NOR gate input terminal, the first NOR gate output terminal, and the first level signal input terminal, respectively, and is used to control the electrical connection between the first NOR gate output terminal and the first level signal input terminal to be turned on or off under the control of the signal input at the second NOR gate input terminal. In the first intermediate control circuit, one of the first NOR gate input terminal and the second NOR gate input terminal is coupled to the first clock signal input terminal, and the other is coupled to the scan signal output terminal. The first NOR gate output terminal is coupled to the first intermediate signal output terminal. In the second intermediate control circuit, one of the first NOR gate input terminal and the second NOR gate input terminal is coupled to the second clock signal input terminal, and the other is coupled to the scan signal output terminal. The first NOR gate output terminal is coupled to the second intermediate signal output terminal.

4. The shift register according to claim 3, wherein, The first control sub-circuit includes a first control transistor, the gate of the first control transistor is coupled to the input terminal of the first NOR gate, the first terminal of the first control transistor is coupled to the second signal input terminal, and the second terminal of the first control transistor is coupled to the first control node. The second control sub-circuit includes a second control transistor, the gate of which is coupled to the input terminal of the second NOR gate, the first terminal of which is coupled to the first control node, and the second terminal of which is coupled to the output terminal of the first NOR gate. The third control sub-circuit includes a third control transistor, the gate of which is coupled to the input terminal of the second NOR gate, the first terminal of which is coupled to the first level signal input terminal, and the second terminal of which is coupled to the output terminal of the first NOR gate. The fourth control sub-circuit includes a fourth control transistor, the gate of which is coupled to the input terminal of the first NOR gate, the first terminal of which is coupled to the first level signal input terminal, and the second terminal of which is coupled to the output terminal of the first NOR gate.

5. The shift register according to claim 1, wherein, The first output control circuit and the second output control circuit include NOT gate circuits; the NOT gate circuits include NOT gate input terminals and NOT gate output terminals; The NOT gate circuit includes: a fifth control sub-circuit and a sixth control sub-circuit; The fifth control sub-circuit is coupled to the NOT gate input terminal, the fourth level signal input terminal and the NOT gate output terminal respectively, and is used to control the conduction or disconnection of the electrical connection between the fourth level signal input terminal and the NOT gate output terminal under the control of the signal input at the NOT gate input terminal; The sixth control sub-circuit is coupled to the NOT gate input terminal, the third level signal input terminal and the NOT gate output terminal respectively, and is used to control the electrical connection between the third level signal input terminal and the NOT gate output terminal to be turned on or off under the control of the signal input at the NOT gate input terminal; In the first output control circuit, the NOT gate input terminal is coupled to the first intermediate signal output terminal, and the NOT gate output terminal is coupled to the first gate drive signal output terminal. In the second output control circuit, the NOT gate input terminal is coupled to the second intermediate signal output terminal, and the NOT gate output terminal is coupled to the second gate drive signal output terminal.

6. The shift register according to claim 5, wherein, The fifth control sub-circuit includes a fifth control transistor, the gate of which is coupled to the input terminal of the NOT gate, the first terminal of which is coupled to the fourth level signal input terminal, and the second terminal of which is coupled to the output terminal of the NOT gate. The sixth control sub-circuit includes a sixth control transistor, the gate of which is coupled to the input terminal of the NOT gate, the first terminal of which is coupled to the input terminal of the third level signal, and the second terminal of which is coupled to the output terminal of the NOT gate.

7. The shift register according to claim 6, wherein, The signal input at the third level signal input terminal may be the same as or different from the signal input at the first level signal input terminal; the signal input at the fourth level signal input terminal may be the same as or different from the signal input at the second level signal input terminal.

8. The shift register according to claim 1, wherein, The shift register circuit includes: The seventh control sub-circuit is coupled to the fifth clock signal input terminal, the start signal input terminal, the second level signal input terminal, and the second control node, respectively, and is used to control the conduction or disconnection of the electrical connection between the second level signal input terminal and the second control node under the control of the fifth clock signal input terminal and the signal input terminal. The eighth control sub-circuit is coupled to the input node, the start signal input terminal, the first level signal input terminal, and the second control node, respectively, and is used to control the conduction or disconnection of the electrical connection between the first level signal input terminal and the second control node under the control of the potential of the input node and the signal input at the start signal input terminal; The ninth control sub-circuit is coupled to the input node, the scan signal output terminal, the second level signal input terminal, and the second control node, respectively, and is used to control the conduction or disconnection of the electrical connection between the second level signal input terminal and the second control node under the control of the potential of the input node and the basic scan signal output by the scan signal output terminal; The tenth control sub-circuit is coupled to the fifth clock signal input terminal, the scan signal output terminal, the first level signal input terminal and the second control node respectively, and is used to control the conduction or disconnection of the electrical connection between the first level signal input terminal and the second control node under the control of the basic scan signal output by the fifth clock signal and the scan signal output terminal. The eleventh control sub-circuit is coupled to the second control node, the first level signal input terminal, the second level signal input terminal, and the scan signal output terminal, respectively. It is used to control the electrical connection between the first level signal input terminal and the scan signal output terminal, and to control the electrical connection between the second level signal input terminal and the scan signal output terminal, under the control of the potential of the second control node.

9. The shift register according to claim 8, wherein, The shift register circuit also includes: The twelfth control sub-circuit is coupled to the control signal input terminal, the second level signal input terminal, and the scan signal output terminal, respectively, and is used to control the electrical connection between the second level signal input terminal and the scan signal output terminal to be turned on or off under the control of the control signal input at the control signal input terminal.

10. The shift register according to claim 9, wherein, The seventh control sub-circuit includes a first transistor and a second transistor. The gate of the first transistor is coupled to the fifth clock signal input terminal, the first terminal of the first transistor is coupled to the second level signal input terminal, the second terminal of the first transistor is coupled to the first terminal of the second transistor, the gate of the second transistor is coupled to the start signal input terminal, and the second terminal of the second transistor is coupled to the second control node. The eighth control sub-circuit includes a third transistor and a fourth transistor. The gate of the third transistor is coupled to the start signal input terminal, the first terminal of the third transistor is coupled to the second terminal of the fourth transistor, the second terminal of the third transistor is coupled to the second control node, the first terminal of the fourth transistor is coupled to the first level signal input terminal, and the gate of the fourth transistor is coupled to the input node. The ninth control sub-circuit includes a fifth transistor and a sixth transistor. The gate of the fifth transistor is coupled to the input node, the first terminal of the fifth transistor is coupled to the second level signal input terminal, the second terminal of the fifth transistor is coupled to the first terminal of the sixth transistor, the second terminal of the sixth transistor is coupled to the second control node, and the gate of the sixth transistor is coupled to the scan signal output terminal. The tenth control sub-circuit includes a seventh transistor and an eighth transistor. The gate of the seventh transistor is coupled to the scan signal output terminal, the first terminal of the seventh transistor is coupled to the second terminal of the eighth transistor, the second terminal of the seventh transistor is coupled to the second control node, the first terminal of the eighth transistor is coupled to the first level signal input terminal, and the gate of the eighth transistor is coupled to the fifth clock signal input terminal. The eleventh control sub-circuit includes a ninth transistor and a tenth transistor. The gate of the ninth transistor is coupled to the second control node, the first terminal of the ninth transistor is coupled to the second level signal input terminal, and the second terminal of the ninth transistor is coupled to the scan signal output terminal. The gate of the tenth transistor is coupled to the second control node, the first terminal of the tenth transistor is coupled to the first level signal input terminal, and the second terminal of the tenth transistor is coupled to the scan signal output terminal. The twelfth control sub-circuit includes an eleventh transistor, the gate of which is coupled to the control signal input terminal, the first terminal of which is coupled to the second level signal input terminal, and the second terminal of which is coupled to the scan signal output terminal.

11. The shift register according to claim 9, wherein, The input node is directly coupled to the sixth clock signal input terminal; or, The shift register circuit also includes: The thirteenth control sub-circuit is coupled to the fifth clock signal input terminal, the first level signal input terminal, the second level signal input terminal, and the input node, respectively. It is used to control the electrical connection between the second level signal input terminal and the input node to be turned on or off under the control of the fifth clock signal input at the fifth clock signal input terminal, and to control the electrical connection between the first level signal input terminal and the input node to be turned on or off.

12. The shift register according to claim 11, wherein, The thirteenth control sub-circuit includes a twelfth transistor and a thirteenth transistor. The gate of the twelfth transistor is coupled to the fifth clock signal input terminal, the first terminal of the twelfth transistor is coupled to the second level signal input terminal, and the second terminal of the twelfth transistor is coupled to the input node. The gate of the thirteenth transistor is coupled to the fifth clock signal input terminal, the first terminal of the thirteenth transistor is coupled to the first level signal input terminal, and the second terminal of the thirteenth transistor is coupled to the input node.

13. A display panel comprising a plurality of cascaded shift registers as described in any one of claims 1 to 12; the scan signal output terminal of the nth shift register is coupled to the start signal input terminal of the shift register circuit in the (n+1)th shift register, where n is an integer greater than or equal to 1; The display panel further includes a frame start signal line, a first clock signal line, a second clock signal line, a third clock signal line, and a fourth clock signal line; The start signal input terminal of the shift register circuit in the nth shift register is coupled to the frame start signal line; The multiple cascaded shift registers are divided into multiple shift register groups. Each shift register group includes two adjacent shift registers. In each shift register group, the first clock signal input terminal of the preceding shift register is coupled to the first clock signal line, the second clock signal input terminal of the preceding shift register is coupled to the second clock signal line, the first clock signal input terminal of the following shift register is coupled to the third clock signal line, and the second clock signal input terminal of the following shift register is coupled to the fourth clock signal line.

14. The display panel according to claim 13, wherein, The display panel further includes: a first level signal line, a second level signal line, a third level signal line, a fourth level signal line, a fifth clock signal line, a sixth clock signal line, and a control signal line; The frame start signal line, the control signal line, the first level signal line, the second level signal line, the sixth clock signal line, the fifth clock signal line, the fourth clock signal line, the third clock signal line, the second clock signal line, the first clock signal line, the third level signal line, and the fourth level signal line are arranged sequentially along the direction closest to the display area; The orthographic projection of the shift register circuit on the substrate of the display panel at least partially overlaps with the orthographic projection of at least one of the following signal lines on the substrate: the frame start signal line, the control signal line, the first level signal line, the second level signal line, the sixth clock signal line, and the fifth clock signal line. The orthographic projection of the first intermediate control circuit and / or the second intermediate control circuit on the substrate of the display panel at least partially overlaps with the orthographic projection of at least one of the fourth clock signal line, the third clock signal line, the second clock signal line and the first clock signal line on the substrate. The orthographic projection of the first output control circuit and / or the second output control circuit on the substrate of the display panel at least partially overlaps with the orthographic projection of at least one of the third level signal lines and the fourth level signal lines on the substrate.

15. A method for driving a shift register, used to drive a shift register as described in any one of claims 1 to 12, the method comprising: The shift register circuit outputs the basic scan signal through the scan signal output terminal; Under the control of the first clock signal input at the first clock signal input terminal and the basic scan signal, the first intermediate control circuit controls the electrical connection between the first level signal input terminal and the first intermediate signal output terminal to be turned on or off, and controls the electrical connection between the second signal input terminal and the first intermediate signal output terminal to be turned on or off. Under the control of the first intermediate signal output from the first intermediate signal output terminal, the first output control circuit controls the electrical connection between the third level signal input terminal and the first gate drive signal output terminal to be turned on or off. And control the electrical connection between the fourth level signal input terminal and the first gate drive signal output terminal to be turned on or off; Under the control of the second clock signal input at the second clock signal input terminal and the basic scan signal, the second intermediate control circuit controls the connection between the first level signal input terminal and the second intermediate signal output terminal to be turned on or off, and controls the connection between the second signal input terminal and the second intermediate signal output terminal to be turned on or off. The second output control circuit controls the electrical connection between the third level signal input terminal and the second gate drive signal output terminal to be turned on or off under the control of the second intermediate signal output terminal. And control the electrical connection between the fourth level signal input terminal and the second gate drive signal output terminal to be turned on or off.

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