Shift register and driving method therefor, and display apparatus

Abstract

The present disclosure provides a shift register and a driving method therefor, and a display apparatus. A first output sub-circuit in the shift register, under the control of a first output node, controls the electrical connection between a gate drive signal output terminal and a first clock signal input terminal to be connected or disconnected. A first output node control sub-circuit, under the control of a first level signal inputted by a first level signal input terminal, controls the electrical connection between a first node and the first output node to be connected or disconnected, and further, under the control of a second node, controls the electrical connection between the first output node and the first level signal input terminal to be connected or disconnected. A first cascade control sub-circuit, under the control of the potential of the second node, controls the electrical connection between a second clock signal input terminal and a cascade signal output terminal to be connected or disconnected.

Description

Shift registers and their driving methods, display devices

[0001] Cross-reference to related applications

[0002] This application claims priority to Chinese Patent Application No. 202411194864.1, filed in China on August 28, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to the field of display technology, and in particular to a shift register and its driving method, and a display device. Background Technology

[0004] With the continuous development of display technology, the application fields of display products are becoming increasingly widespread, and people's requirements for the display quality of display products are getting higher and higher. In order to better realize narrow bezel display products, GOA (Gate On Array) technology is adopted in display products. This technology directly fabricates the gate driving circuit on the array substrate, and drives the sub-pixel rows of the display area through the shift register units of each stage included in the gate driving circuit, thereby realizing the display function of the display product. However, the stability of the gate driving signal output by the existing shift register units is poor. How to improve the stability of the gate driving signal output by the shift register units has become an urgent technical problem to be solved. Summary of the Invention

[0005] The purpose of this disclosure is to provide a shift register and its driving method, as well as a display device.

[0006] To achieve the above objectives, this disclosure provides the following technical solution:

[0007] A first aspect of this disclosure provides a shift register, comprising:

[0008] The first output sub-circuit is coupled to the gate drive signal output terminal, the first clock signal input terminal and the first output node respectively, and is used to control the conduction or disconnection of the electrical connection between the gate drive signal output terminal and the first clock signal input terminal under the control of the potential of the first output node.

[0009] The first output node control sub-circuit is coupled to the first node, the second node, the first output node, and the first level signal input terminal, respectively. It is used to control the electrical connection between the first node and the first output node to be turned on or off under the control of the first level signal input terminal; and is also used to control the electrical connection between the first output node and the first level signal input terminal to be turned on or off under the control of the potential of the second node.

[0010] The first cascaded control sub-circuit is coupled to the cascaded signal output terminal, the second clock signal input terminal, and the second node, respectively, and is used to control the electrical connection between the second clock signal input terminal and the cascaded signal output terminal to be turned on or off under the control of the potential of the second node.

[0011] The first isolation control sub-circuit is used to control the connection between the first node and the second node to be turned on or off.

[0012] Optional, also includes:

[0013] The second output sub-circuit is coupled to the gate drive signal output terminal, the second level signal input terminal, and the second output node, respectively, and is used to control the conduction or disconnection of the electrical connection between the gate drive signal output terminal and the second level signal input terminal under the control of the potential of the second output node.

[0014] The fourth node control sub-circuit is coupled to the first node, the fourth node, the fifth node, and the third level signal input terminal, respectively. The fourth node control sub-circuit is also coupled to the fourth clock signal input terminal or the second clock signal input terminal. It is used to control the electrical connection between the fourth node and the third level signal input terminal under the control of the potential of the first node; and to control the potential of the fifth node according to the potential of the fourth node.

[0015] The fourth node control sub-circuit is also used to: control the electrical connection between the fourth node and the fourth clock signal input terminal to be turned on or off under the control of the potential of the fifth node; or, control the electrical connection between the fourth node and the second clock signal input terminal to be turned on or off under the control of the potential of the fifth node.

[0016] The second output node control sub-circuit is coupled to the second output node and the fifth node respectively, and is used to control the electrical connection between the second output node and the fifth node to be turned on or off under the control of the potential of the fifth node.

[0017] Optional, also includes:

[0018] The second isolation control sub-circuit is coupled to the first level signal input terminal, the second output node and the sixth node respectively, and is used to control the conduction or disconnection of the electrical connection between the second output node and the sixth node under the control of the first level signal input terminal.

[0019] The third isolation control sub-circuit is coupled to the first level signal input terminal, the fifth node and the seventh node respectively, and is used to control the conduction or disconnection of the electrical connection between the fifth node and the seventh node under the control of the first level signal input terminal.

[0020] The second input sub-circuit is coupled to the third clock signal input terminal, the sixth node, the seventh node, and the input node, respectively; it is used to control the electrical connection between the sixth node and the input node to be turned on or off under the control of the third clock signal input to the third clock signal input terminal, and to control the electrical connection between the seventh node and the input node to be turned on or off under the control of the third clock signal input to the third clock signal input terminal.

[0021] Optionally, the input node is directly coupled to the first level signal input terminal; the shift register further includes:

[0022] The sixth node control sub-circuit is coupled to the first node, the third clock signal input terminal and the sixth node respectively, and is used to control the conduction or disconnection of the electrical connection between the third clock signal input terminal and the sixth node under the control of the potential of the first node;

[0023] The seventh node control sub-circuit is coupled to the first node, the third clock signal input terminal and the seventh node respectively, and is used to control the electrical connection between the third clock signal input terminal and the seventh node to be turned on or off under the control of the potential of the first node.

[0024] Optional, also includes:

[0025] The first input node control sub-circuit is coupled to the start signal input terminal, the third level signal input terminal and the input node respectively, and is used to control the electrical connection between the third level signal input terminal and the input node to be turned on or off under the control of the start signal input at the start signal input terminal;

[0026] The second input node control sub-circuit is coupled to the eighth node, the first level signal input terminal and the input node respectively, and is used to control the conduction or disconnection of the electrical connection between the first level signal input terminal and the input node under the control of the potential of the eighth node;

[0027] The eighth node control sub-circuit is coupled to the third clock signal input terminal, the start signal input terminal, the eighth node, and the third level signal input terminal, respectively. It is used to control the potential of the eighth node according to the third clock signal input terminal, and also to control the electrical connection between the third level signal input terminal and the eighth node to be turned on or off under the control of the start signal input terminal.

[0028] Optionally, the input node is directly coupled to the first level signal input terminal; the shift register further includes:

[0029] The sixth node control sub-circuit is coupled to the first node, the third level signal input terminal and the sixth node respectively, and is used to control the conduction or disconnection of the electrical connection between the third level signal input terminal and the sixth node under the control of the potential of the first node;

[0030] The seventh node control sub-circuit is coupled to the first node, the third level signal input terminal and the seventh node respectively, and is used to control the conduction or disconnection of the electrical connection between the third level signal input terminal and the seventh node under the control of the potential of the first node;

[0031] A coupling sub-circuit, wherein the second input sub-circuit is coupled to the ninth node, and the ninth node is coupled to the third clock signal input terminal through the coupling sub-circuit;

[0032] The ninth node control sub-circuit is coupled to the ninth node, the start signal input terminal, and the third level signal input terminal, respectively, and is used to control the electrical connection between the third level signal input terminal and the ninth node to be turned on or off under the control of the start signal input at the start signal input terminal.

[0033] Optional, also includes

[0034] The first input sub-circuit is coupled to the start signal input terminal, the third clock signal input terminal and the first node respectively, and is used to control the electrical connection between the start signal input terminal and the first node to be turned on or off under the control of the third clock signal input at the third clock signal input terminal.

[0035] Optional, also includes:

[0036] The first node control sub-circuit is coupled to the first node, the sixth node, the third level signal input terminal, and the second clock signal input terminal, respectively. It is used to control the electrical connection between the first node and the third level signal input terminal to be turned on or off under the joint control of the potential of the sixth node and the second clock signal input terminal.

[0037] Optional, also includes:

[0038] The second cascaded control sub-circuit is coupled to the sixth node, the cascaded signal output terminal, and the third-level signal input terminal, respectively. It is used to control the electrical connection between the cascaded signal output terminal and the third-level signal input terminal under the control of the potential of the sixth node; it is also used to control the potential of the sixth node according to the third-level signal input from the third-level signal input terminal.

[0039] Optionally, the first output sub-circuit includes an eleventh transistor, the gate of which is coupled to the first output node, the first terminal of which is coupled to the first clock signal input terminal, and the second terminal of which is coupled to the gate drive signal output terminal.

[0040] The first output node control sub-circuit includes a sixteenth transistor and a nineteenth transistor. The gate of the sixteenth transistor is coupled to the first level signal input terminal, the first terminal of the sixteenth transistor is coupled to the first node, and the second terminal of the sixteenth transistor is coupled to the first output node. The gate of the nineteenth transistor is coupled to the second node, the first terminal of the nineteenth transistor is coupled to the first level signal input terminal, and the second terminal of the nineteenth transistor is coupled to the first output node.

[0041] The first cascaded control sub-circuit includes an eighth transistor and a second capacitor. The gate of the eighth transistor is coupled to the second node, the first terminal of the eighth transistor is coupled to the second clock signal input terminal, and the second terminal of the eighth transistor is coupled to the cascaded signal output terminal. The first terminal of the second capacitor is coupled to the cascaded signal output terminal, and the second terminal of the second capacitor is coupled to the second node.

[0042] The first isolation control sub-circuit includes a sixth transistor, the gate of which is coupled to the first level signal input terminal, the first terminal of which is coupled to the first node, and the second terminal of which is coupled to the second node.

[0043] Optionally, the second output sub-circuit includes a tenth transistor, the gate of which is coupled to the second output node, the first terminal of which is coupled to the second level signal input terminal, and the second terminal of which is coupled to the gate drive signal output terminal.

[0044] The fourth node control sub-circuit includes a twelfth transistor, a thirteenth transistor, and a third capacitor coupled together; the gate of the twelfth transistor is coupled to the fifth node, the first terminal of the twelfth transistor is coupled to the fourth clock signal input terminal or the second clock signal input terminal, and the second terminal of the twelfth transistor is coupled to the fourth node; the gate of the thirteenth transistor is coupled to the first node, the first terminal of the thirteenth transistor is coupled to the third level signal input terminal, and the second terminal of the thirteenth transistor is coupled to the fourth node; the first terminal of the third capacitor is coupled to the fourth node, and the second terminal of the third capacitor is coupled to the fifth node;

[0045] The second output node control sub-circuit includes a fourteenth transistor, the gate of which is coupled to the fifth node, the first terminal of which is coupled to the fifth node, and the second terminal of which is coupled to the second output node.

[0046] Optionally, the second isolation control sub-circuit includes a ninth transistor, the gate of which is coupled to the first level signal input terminal, the first terminal of which is coupled to the sixth node, and the second terminal of which is coupled to the second output node;

[0047] The third isolation control sub-circuit includes a fifteenth transistor, the gate of which is coupled to the first level signal input terminal, the first terminal of which is coupled to the seventh node, and the second terminal of which is coupled to the fifth node;

[0048] The second input sub-circuit includes a second transistor and a seventeenth transistor. The gate of the second transistor is coupled to the third clock signal input terminal, the first terminal of the second transistor is coupled to the first level signal input terminal, and the second terminal of the second transistor is coupled to the sixth node. The gate of the seventeenth transistor is coupled to the third clock signal input terminal, the first terminal of the seventeenth transistor is coupled to the first level signal input terminal, and the second terminal of the seventeenth transistor is coupled to the seventh node.

[0049] Optionally, the sixth node control sub-circuit includes a third transistor, the gate of which is coupled to the first node, the first terminal of which is coupled to the third clock signal input terminal, and the second terminal of which is coupled to the sixth node.

[0050] The seventh node control sub-circuit includes an eighteenth transistor, the gate of which is coupled to the first node, the first terminal of which is coupled to the third clock signal input terminal, and the second terminal of which is coupled to the seventh node.

[0051] Optionally, the first input node control sub-circuit includes a twentieth transistor, the gate of which is coupled to the start signal input terminal, the first terminal of which is coupled to the third level signal input terminal, and the second terminal of which is coupled to the input node.

[0052] The second input node control sub-circuit includes a twenty-first transistor, the gate of which is coupled to the eighth node, the first terminal of which is coupled to the first level signal input terminal, and the second terminal of which is coupled to the input node.

[0053] The eighth node control sub-circuit includes a twenty-second transistor and a fourth capacitor. The gate of the twenty-second transistor is coupled to the start signal input terminal, the first terminal of the twenty-second transistor is coupled to the third level signal input terminal, and the second terminal of the twenty-second transistor is coupled to the eighth node. The first terminal of the fourth capacitor is coupled to the third clock signal input terminal, and the second terminal of the fourth capacitor is coupled to the eighth node.

[0054] Optionally, the sixth node control sub-circuit includes a third transistor, the gate of which is coupled to the first node, the first terminal of which is coupled to the third level signal input terminal, and the second terminal of which is coupled to the sixth node;

[0055] The seventh node control sub-circuit includes an eighteenth transistor, the gate of which is coupled to the first node, the first terminal of which is coupled to the third level signal input terminal, and the second terminal of which is coupled to the seventh node.

[0056] The coupling sub-circuit includes a fifth capacitor, the first end of which is coupled to the third clock signal input terminal, and the second end of which is coupled to the ninth node.

[0057] The ninth node control sub-circuit includes a twenty-third transistor, the gate of which is coupled to the start signal input terminal, the first terminal of which is coupled to the third level signal input terminal, and the second terminal of which is coupled to the ninth node.

[0058] Optionally, the first input sub-circuit includes a first transistor, the gate of which is coupled to the third clock signal input terminal, the first terminal of which is coupled to the start signal input terminal, and the second terminal of which is coupled to the first node.

[0059] Optionally, the first node control sub-circuit includes a fourth transistor and a fifth transistor. The gate of the fourth transistor is coupled to the sixth node, the first terminal of the fourth transistor is coupled to the third level signal input terminal, and the second terminal of the fourth transistor is coupled to the first terminal of the fifth transistor. The gate of the fifth transistor is coupled to the second clock signal input terminal, and the second terminal of the fifth transistor is coupled to the first node.

[0060] Optionally, the second cascaded control sub-circuit includes a seventh transistor and a first capacitor. The gate of the seventh transistor is coupled to the sixth node, the first terminal of the seventh transistor is coupled to the third-level signal input terminal, and the second terminal of the seventh transistor is coupled to the cascaded signal output terminal. The first terminal of the first capacitor is coupled to the third-level signal input terminal, and the second terminal of the first capacitor is coupled to the sixth node.

[0061] Based on the above-described shift register technical solution, a second aspect of this disclosure provides a shift register driving method applied to the aforementioned shift register, the driving method comprising:

[0062] Under the control of the potential of the first output node, the first output sub-circuit controls the electrical connection between the gate drive signal output terminal and the first clock signal input terminal to be turned on or off.

[0063] The first output node control sub-circuit, under the control of the first level signal input to the first level signal input terminal, controls the electrical connection between the first node and the first output node to be turned on or off; and also, under the control of the potential of the second node, controls the electrical connection between the first output node and the first level signal input terminal to be turned on or off.

[0064] The first cascade control sub-circuit, under the control of the potential of the second node, controls the electrical connection between the second clock signal input terminal and the cascade signal output terminal to be turned on or off, and also controls the potential of the second node according to the cascade signal output by the cascade signal output terminal;

[0065] Under the control of the first level signal, the first isolation control sub-circuit controls the conduction of the electrical connection between the first node and the second node.

[0066] Optionally, the driving method further includes:

[0067] The second output sub-circuit controls the conduction or disconnection of the electrical connection between the gate drive signal output terminal and the second level signal input terminal under the control of the potential of the second output node;

[0068] The fourth node control sub-circuit, under the control of the potential of the first node, controls the electrical connection between the fourth node and the third level signal input terminal to be turned on or off; it also controls the potential of the fifth node according to the potential of the fourth node.

[0069] The fourth node control sub-circuit, under the control of the potential of the fifth node, controls the connection between the fourth node and the fourth clock signal input terminal to be turned on or off; or, under the control of the potential of the fifth node, controls the connection between the fourth node and the second clock signal input terminal to be turned on or off.

[0070] The second output node control sub-circuit, under the control of the potential of the fifth node, controls the electrical connection between the second output node and the fifth node to be turned on or off.

[0071] Based on the above-described shift register technical solution, a third aspect of this disclosure provides a display device including the aforementioned shift register. Attached Figure Description

[0072] The accompanying drawings, which are included to provide a further understanding of this disclosure and form part of this disclosure, illustrate exemplary embodiments of the present disclosure and are used to explain the disclosure, but do not constitute an undue limitation of the disclosure. In the drawings:

[0073] Figure 1 is a schematic diagram of the first structure of the shift register provided in an embodiment of this disclosure;

[0074] Figure 2 is a schematic diagram of the second structure of the shift register provided in an embodiment of this disclosure;

[0075] Figure 3 is a schematic diagram of the third structure of the shift register provided in an embodiment of this disclosure;

[0076] Figure 4 is a schematic diagram of the fourth structure of the shift register provided in the embodiments of this disclosure;

[0077] Figure 5 shows the specific circuit structure diagram corresponding to Figure 4;

[0078] Figure 6 is the driving timing diagram corresponding to Figure 5;

[0079] Figure 7 is a schematic diagram of the cascading of shift registers provided in an embodiment of this disclosure;

[0080] Figure 8 is a schematic diagram of the fifth structure of the shift register provided in the embodiments of this disclosure;

[0081] Figure 9 shows the specific circuit structure corresponding to Figure 8;

[0082] Figure 10 is the driving timing diagram corresponding to Figure 9;

[0083] Figure 11 is a schematic diagram of the sixth structure of the shift register provided in the embodiment of this disclosure;

[0084] Figure 12 is a specific circuit structure diagram corresponding to Figure 11. Detailed Implementation

[0085] To further illustrate the shift register and its driving method, as well as the display device provided in the embodiments of this disclosure, a detailed description is provided below with reference to the accompanying drawings.

[0086] Please refer to Figures 1 to 12. This disclosure provides a shift register, including:

[0087] The first output sub-circuit 10 is coupled to the gate drive signal output terminal OUT, the first clock signal input terminal GCK and the first output node Q3 respectively, and is used to control the electrical connection between the gate drive signal output terminal OUT and the first clock signal input terminal GCK to be turned on or off under the control of the potential of the first output node Q3.

[0088] The first output node control sub-circuit 11 is coupled to the first node Q1, the second node Q2, the first output node Q3, and the first level signal input terminal VGL1, respectively. It is used to control the electrical connection between the first node Q1 and the first output node Q3 to be turned on or off under the control of the first level signal input to the first level signal input terminal VGL1; it is also used to control the electrical connection between the first output node Q3 and the first level signal input terminal VGL1 to be turned on or off under the control of the potential of the second node Q2.

[0089] The first cascaded control sub-circuit 12 is coupled to the cascaded signal output terminal CR, the second clock signal input terminal CKB and the second node Q2 respectively, and is used to control the electrical connection between the second clock signal input terminal CKB and the cascaded signal output terminal CR under the control of the potential of the second node Q2.

[0090] The first isolation control sub-circuit 13 is used to control the connection between the first node Q1 and the second node Q2 to be turned on or off.

[0091] For example, the first cascade control sub-circuit 12 is also used to control the potential of the second node Q2 according to the cascade signal output by the cascade signal output terminal CR.

[0092] For example, the first isolation control sub-circuit 13 is coupled to the first level signal input terminal VGL1, the first node Q1 and the second node Q2 respectively, and is used to control the conduction or disconnection of the electrical connection between the first node Q1 and the second node Q2 under the control of the first level signal.

[0093] For example, the first output sub-circuit 10 includes an eleventh transistor T11. The gate of the eleventh transistor T11 is coupled to the first output node Q3, the first terminal of the eleventh transistor T11 is coupled to the first clock signal input terminal GCK, and the second terminal of the eleventh transistor T11 is coupled to the gate drive signal output terminal OUT. The eleventh transistor T11 is used to control the electrical connection between the gate drive signal output terminal OUT and the first clock signal input terminal GCK under the control of the potential of the first output node Q3.

[0094] For example, the first output node control sub-circuit 11 includes a sixteenth transistor T16 and a nineteenth transistor T19. The gate of the sixteenth transistor T16 is coupled to the first level signal input terminal VGL1, the first terminal of the sixteenth transistor T16 is coupled to the first node Q1, and the second terminal of the sixteenth transistor T16 is coupled to the first output node Q3. The gate of the nineteenth transistor T19 is coupled to the second node Q2, the first terminal of the nineteenth transistor T19 is coupled to the first level signal input terminal VGL1, and the second terminal of the nineteenth transistor T19 is coupled to the first output node Q3. The sixteenth transistor T16 is used to control the electrical connection between the first node Q1 and the first output node Q3 to be turned on or off under the control of the first level signal input to the first level signal input terminal VGL1. The nineteenth transistor T19 is used to control the electrical connection between the first output node Q3 and the first level signal input terminal VGL1 to be turned on or off under the control of the potential of the second node Q2.

[0095] For example, the first cascade control sub-circuit 12 includes an eighth transistor T8 and a second capacitor C2. The gate of the eighth transistor T8 is coupled to the second node Q2, the first terminal of the eighth transistor T8 is coupled to the second clock signal input terminal CKB, and the second terminal of the eighth transistor T8 is coupled to the cascade signal output terminal CR. The first terminal of the second capacitor C2 is coupled to the cascade signal output terminal CR, and the second terminal of the second capacitor C2 is coupled to the second node Q2. The eighth transistor T8 is used to control the electrical connection between the second clock signal input terminal CKB and the cascade signal output terminal CR under the control of the potential of the second node Q2. The second capacitor C2 is used to control the potential of the second node Q2 according to the cascade signal output by the cascade signal output terminal CR.

[0096] For example, the first isolation control sub-circuit 13 includes a sixth transistor T6. The gate of the sixth transistor T6 is coupled to the first level signal input terminal VGL1, the first terminal of the sixth transistor T6 is coupled to the first node Q1, and the second terminal of the sixth transistor T6 is coupled to the second node Q2. Under the control of the first level signal, the sixth transistor T6 controls the conduction or disconnection of the electrical connection between the first node Q1 and the second node Q2.

[0097] For example, in the shift register provided in the embodiments of this disclosure, the transistors included in each sub-circuit may be P-type transistors, but are not limited thereto.

[0098] As can be seen from the specific structure of the shift register described above, in the shift register provided in this embodiment, when the potential control of the second node Q2 turns on the cascaded signal output terminal CR and the second clock signal input terminal CKB, the second clock signal input to the second clock signal input terminal CKB will be transmitted to the cascaded signal output terminal CR, thereby affecting the potential of the second node Q2.

[0099] Since the potential of the second node Q2 can control the electrical connection between the first output node Q3 and the first level signal input terminal VGL1 to be turned on or off, when the potential of the second node Q2 is affected and becomes lower, it can better control the electrical connection between the first output node Q3 and the first level signal input terminal VGL1 to be turned on, keeping the potential of the first output node Q3 at an effective potential. This effective potential can turn on the electrical connection between the gate drive signal output terminal OUT and the first clock signal input terminal GCK, so that the signal of the gate drive signal output terminal OUT is consistent with the signal input to the first clock signal input terminal GCK, ensuring the stability of the signal output by the gate drive signal output terminal OUT.

[0100] When the potential of the second node Q2 becomes higher due to the influence of the first isolation control sub-circuit 13, the potential of the first node Q1 is affected. Since the first output node control sub-circuit 11 can control the disconnection of the electrical connection between the first node Q1 and the first output node Q3 under the control of the first level signal input at the first level signal input terminal VGL1, the potential of the first output node Q3 can avoid being affected by the potential of the first node Q1. The first output node Q3 can continue to maintain its original state and maintain the control state of the first output node Q3 on the first output sub-circuit 10, thereby better maintaining the stability of the signal output at the gate drive signal output terminal OUT.

[0101] As shown in Figures 2 to 12, in some embodiments, the shift register further includes:

[0102] The second output sub-circuit 14 is coupled to the gate drive signal output terminal OUT, the second level signal input terminal VGL2, and the second output node QB2, respectively, and is used to control the conduction or disconnection of the electrical connection between the gate drive signal output terminal OUT and the second level signal input terminal VGL2 under the control of the potential of the second output node QB2.

[0103] The fourth node control sub-circuit 15 is coupled to the first node Q1, the fourth node GD, the fifth node QB3, and the third level signal input terminal VGH, respectively. The fourth node control sub-circuit 15 is also coupled to the fourth clock signal input terminal CKA2 or the second clock signal input terminal CKB. It is used to control the electrical connection between the fourth node GD and the third level signal input terminal VGH under the control of the potential of the first node Q1; and to control the potential of the fifth node QB3 according to the potential of the fourth node GD.

[0104] The fourth node control sub-circuit 15 is also used to: control the electrical connection between the fourth node GD and the fourth clock signal input terminal CKA2 to be turned on or off under the control of the potential of the fifth node QB3; or, control the electrical connection between the fourth node GD and the second clock signal input terminal CKB to be turned on or off under the control of the potential of the fifth node QB3.

[0105] The second output node control sub-circuit 16 is coupled to the second output node QB2 and the fifth node QB3 respectively, and is used to control the electrical connection between the second output node QB2 and the fifth node QB3 to be turned on or off under the control of the potential of the fifth node QB3.

[0106] For example, the second output sub-circuit 14 includes a tenth transistor T10, the gate of which is coupled to the second output node QB2, the first terminal of which is coupled to the second level signal input terminal VGL2, and the second terminal of which is coupled to the gate drive signal output terminal OUT. The tenth transistor T10 is used to control the electrical connection between the gate drive signal output terminal OUT and the second level signal input terminal VGL2 under the control of the potential of the second output node QB2.

[0107] For example, the fourth node control sub-circuit 15 includes a twelfth transistor T12, a thirteenth transistor T13, and a third capacitor C3 coupled together; the gate of the twelfth transistor T12 is coupled to the fifth node QB3, the first terminal of the twelfth transistor T12 is coupled to the fourth clock signal input terminal CKA2 or the second clock signal input terminal CKB, and the second terminal of the twelfth transistor T12 is coupled to the fourth node GD; the gate of the thirteenth transistor T13 is coupled to the first node Q1, the first terminal of the thirteenth transistor T13 is coupled to the third level signal input terminal VGH, and the second terminal of the thirteenth transistor T13 is coupled to the fourth node GD; the first terminal of the third capacitor C3 is coupled to the fourth node GD, and the second terminal of the third capacitor C3 is coupled to the fifth node QB3.

[0108] The thirteenth transistor T13 is used to control the electrical connection between the fourth node GD and the third level signal input terminal VGH under the control of the potential of the first node Q1; the third capacitor C3 is used to control the potential of the fifth node QB3 according to the potential of the fourth node GD; the twelfth transistor T12 is used to control the electrical connection between the fourth node GD and the fourth clock signal input terminal CKA2 under the control of the potential of the fifth node QB3; or, the twelfth transistor T12 is used to control the electrical connection between the fourth node GD and the second clock signal input terminal CKB under the control of the potential of the fifth node QB3.

[0109] For example, the second output node control sub-circuit 16 includes a fourteenth transistor T14, the gate of which is coupled to the fifth node QB3, the first terminal of which is coupled to the fifth node QB3, and the second terminal of which is coupled to the second output node QB2. The fourteenth transistor T14 is used to control the electrical connection between the second output node QB2 and the fifth node QB3 to be turned on or off under the control of the potential of the fifth node QB3.

[0110] Optionally, when the fourth node control sub-circuit 15 is coupled to the second clock signal input terminal CKB, the time at which the potential of the second output node QB2 is pulled down to a lower level is delayed by 1H compared to the case of the fourth clock signal input terminal CKA2.

[0111] In the shift register provided in the above embodiment, when the electrical connection between the fourth node GD and the third level signal input terminal VGH is disconnected under the control of the potential of the first node Q1; and when the electrical connection between the fourth node GD and the second clock signal input terminal CKB or the fourth clock signal input terminal CKA2 is connected under the control of the potential of the fifth node QB3: the fourth clock signal input at the fourth clock signal input terminal CKA2 is transmitted to the fourth node GD, and the potential of the fourth node GD then controls the potential of the fifth node QB3.

[0112] When the potential of the fifth node QB3 becomes lower due to the influence, the second output node control sub-circuit 16 can better control the conduction of the electrical connection between the second output node QB2 and the fifth node QB3, and control the potential of the second output node QB2 at an effective potential. This effective potential can conduct the electrical connection between the gate drive signal output terminal OUT and the second level signal input terminal VGL2, so that the signal of the gate drive signal output terminal OUT is consistent with the signal input to the second level signal input terminal VGL2, and ensure the stability of the signal output by the gate drive signal output terminal OUT.

[0113] As shown in Figures 3 to 12, in some embodiments, the shift register further includes:

[0114] The second isolation control sub-circuit 17 is coupled to the first level signal input terminal VGL1, the second output node QB2 and the sixth node QB1 respectively, and is used to control the conduction or disconnection of the electrical connection between the second output node QB2 and the sixth node QB1 under the control of the first level signal input terminal VGL1.

[0115] The third isolation control sub-circuit 18 is coupled to the first level signal input terminal VGL1, the fifth node QB3 and the seventh node QB4 respectively, and is used to control the conduction or disconnection of the electrical connection between the fifth node QB3 and the seventh node QB4 under the control of the first level signal input terminal VGL1.

[0116] The second input sub-circuit 19 is coupled to the third clock signal input terminal CKA, the sixth node QB1, the seventh node QB4, and the input node QB5, respectively. It is used to control the electrical connection between the sixth node QB1 and the input node QB5 under the control of the third clock signal input to the third clock signal input terminal CKA, and to control the electrical connection between the seventh node QB4 and the input node QB5 under the control of the third clock signal input to the third clock signal input terminal CKA.

[0117] For example, the second isolation control sub-circuit 17 includes a ninth transistor T9, the gate of which is coupled to the first level signal input terminal VGL1, the first terminal of which is coupled to the sixth node QB1, and the second terminal of which is coupled to the second output node QB2. The ninth transistor T9 is used to control the electrical connection between the second output node QB2 and the sixth node QB1 to be turned on or off under the control of the first level signal input to the first level signal input terminal VGL1.

[0118] For example, the third isolation control sub-circuit 18 includes a fifteenth transistor T15, the gate of which is coupled to the first level signal input terminal VGL1, the first terminal of which is coupled to the seventh node QB4, and the second terminal of which is coupled to the fifth node QB3; the fifteenth transistor T15 is used to control the conduction or disconnection of the electrical connection between the fifth node QB3 and the seventh node QB4 under the control of the first level signal input to the first level signal input terminal VGL1.

[0119] For example, the second input sub-circuit 19 includes a second transistor T2 and a seventeenth transistor T17. The gate of the second transistor T2 is coupled to the third clock signal input terminal CKA, the first terminal of the second transistor T2 is coupled to the first level signal input terminal VGL1, and the second terminal of the second transistor T2 is coupled to the sixth node QB1. The gate of the seventeenth transistor T17 is coupled to the third clock signal input terminal CKA, the first terminal of the seventeenth transistor T17 is coupled to the first level signal input terminal VGL1, and the second terminal of the seventeenth transistor T17 is coupled to the seventh node QB4. The second transistor T2 is used to control the conduction or disconnection of the electrical connection between the sixth node QB1 and the input node QB5 under the control of the third clock signal input at the third clock signal input terminal CKA. The seventeenth transistor T17 is used to control the conduction or disconnection of the electrical connection between the seventh node QB4 and the input node QB5 under the control of the third clock signal input at the third clock signal input terminal CKA.

[0120] In the shift register provided in the above embodiment, by setting the second input sub-circuit 19, the second isolation control sub-circuit 17, and the third isolation control sub-circuit 18, the second input sub-circuit 19 and the second isolation control sub-circuit 17 form a first transmission path, and the second input sub-circuit 19 and the third isolation control sub-circuit 18 form a second transmission path. The potential of the input node QB5 can be transmitted to the second output node QB2 through the two transmission paths, thereby controlling the second output sub-circuit 14 to achieve a stable output function.

[0121] Moreover, the above configuration ensures that when the fifth node QB3 is controlled by the fourth node GD, the potential of the fifth node QB3 will not directly affect the sixth node QB1, thus guaranteeing the stability of the transmitted signal on the first transmission path. This further ensures that the second output node QB2 has better stability when controlled by the transmitted signal on the first transmission path, thereby controlling the second output sub-circuit 14 to achieve a stable output function.

[0122] As shown in Figures 4 and 5, in some embodiments, the input node QB5 is directly coupled to the first level signal input terminal VGL1; the shift register further includes:

[0123] The sixth node control sub-circuit 21 is coupled to the first node Q1, the third clock signal input terminal CKA and the sixth node QB1 respectively, and is used to control the electrical connection between the third clock signal input terminal CKA and the sixth node QB1 to be turned on or off under the control of the potential of the first node Q1.

[0124] The seventh node control sub-circuit 22 is coupled to the first node Q1, the third clock signal input terminal CKA and the seventh node QB4 respectively, and is used to control the electrical connection between the third clock signal input terminal CKA and the seventh node QB4 under the control of the potential of the first node Q1.

[0125] For example, the sixth node control sub-circuit 21 includes a third transistor T3, the gate of which is coupled to the first node Q1, the first terminal of which is coupled to the third clock signal input terminal CKA, and the second terminal of which is coupled to the sixth node QB1; the third transistor T3 is used to control the electrical connection between the third clock signal input terminal CKA and the sixth node QB1 under the control of the potential of the first node Q1.

[0126] For example, the seventh node control sub-circuit 22 includes an eighteenth transistor T18, the gate of which is coupled to the first node Q1, the first terminal of which is coupled to the third clock signal input terminal CKA, and the second terminal of which is coupled to the seventh node QB4; the eighteenth transistor T18 is used to control the electrical connection between the third clock signal input terminal CKA and the seventh node QB4 under the control of the potential of the first node Q1.

[0127] The shift register described above also includes a sixth node control sub-circuit 21 and a seventh node control sub-circuit 22, so that under the control of the potential of the first node Q1, the potential of the sixth node QB1 can be controlled by the sixth node control sub-circuit 21, and the potential of the seventh node QB4 can be controlled by the seventh node control sub-circuit 22, thereby realizing independent control of the potentials of the sixth node QB1 and the seventh node QB4 by the potential of the first node Q1.

[0128] As shown in Figures 8 and 9, in some embodiments, the shift register further includes:

[0129] The first input node control sub-circuit 25 is coupled to the start signal input terminal STV, the third level signal input terminal VGH and the input node QB5 respectively, and is used to control the electrical connection between the third level signal input terminal VGH and the input node QB5 to be turned on or off under the control of the start signal input at the start signal input terminal STV.

[0130] The second input node control sub-circuit 26 is coupled to the eighth node QB6, the first level signal input terminal VGL1 and the input node QB5 respectively, and is used to control the conduction or disconnection of the electrical connection between the first level signal input terminal VGL1 and the input node QB5 under the control of the potential of the eighth node QB6.

[0131] The eighth node control sub-circuit 27 is coupled to the third clock signal input terminal CKA, the start signal input terminal STV, the eighth node QB6, and the third level signal input terminal VGH, respectively. It is used to control the potential of the eighth node QB6 according to the third clock signal input terminal CKA, and also to control the electrical connection between the third level signal input terminal VGH and the eighth node QB6 under the control of the start signal input terminal STV.

[0132] For example, the first input node control sub-circuit 25 includes a twentieth transistor T20. The gate of the twentieth transistor T20 is coupled to the start signal input terminal STV, the first terminal of the twentieth transistor T20 is coupled to the third level signal input terminal VGH, and the second terminal of the twentieth transistor T20 is coupled to the input node QB5. The twentieth transistor T20 is used to control the conduction or disconnection of the electrical connection between the third level signal input terminal VGH and the input node QB5 under the control of the start signal input at the start signal input terminal STV.

[0133] For example, the second input node control sub-circuit 26 includes a twenty-first transistor T21, the gate of which is coupled to the eighth node QB6, the first terminal of which is coupled to the first level signal input terminal VGL1, and the second terminal of which is coupled to the input node QB5; the second transistor T21 is used to control the electrical connection between the first level signal input terminal VGL1 and the input node QB5 under the control of the potential of the eighth node QB6.

[0134] The eighth node control sub-circuit 27 includes a twenty-second transistor T22 and a fourth capacitor C4. The gate of the twenty-second transistor T22 is coupled to the start signal input terminal STV, the first terminal of the twenty-second transistor T22 is coupled to the third level signal input terminal VGH, and the second terminal of the twenty-second transistor T22 is coupled to the eighth node QB6. The first terminal of the fourth capacitor C4 is coupled to the third clock signal input terminal CKA, and the second terminal of the fourth capacitor C4 is coupled to the eighth node QB6. The fourth capacitor C4 is used to control the potential of the eighth node QB6 according to the third clock signal input terminal CKA. The twenty-second transistor T22 is used to control the electrical connection between the third level signal input terminal VGH and the eighth node QB6 under the control of the start signal input terminal STV.

[0135] The shift register described above also includes a first input node control sub-circuit 25, a second input node control sub-circuit 26, and an eighth node control sub-circuit 27. The first input node control sub-circuit 25 can control the potential of the input node QB5, and the eighth node control sub-circuit 27 and the second input node control sub-circuit 26 can also control the potential of the input node QB5, thus achieving better control over the potential of the input node QB5.

[0136] As shown in Figures 11 and 12, in some embodiments, the input node QB5 is directly coupled to the first level signal input terminal VGL1; the shift register further includes:

[0137] The sixth node control sub-circuit 21 is coupled to the first node Q1, the third level signal input terminal VGH and the sixth node QB1 respectively, and is used to control the conduction or disconnection of the electrical connection between the third level signal input terminal VGH and the sixth node QB1 under the control of the potential of the first node Q1.

[0138] The seventh node control sub-circuit 22 is coupled to the first node Q1, the third level signal input terminal VGH and the seventh node QB4 respectively, and is used to control the conduction or disconnection of the electrical connection between the third level signal input terminal VGH and the seventh node QB4 under the control of the potential of the first node Q1.

[0139] Coupler sub-circuit 28, the second input sub-circuit 19 is coupled to the ninth node QB7, and the ninth node QB7 is coupled to the third clock signal input terminal CKA through the coupler sub-circuit 28;

[0140] The ninth node control sub-circuit 29 is coupled to the ninth node QB7, the start signal input terminal STV, and the third level signal input terminal VGH, respectively. It is used to control the electrical connection between the third level signal input terminal VGH and the ninth node QB7 under the control of the start signal input at the start signal input terminal STV.

[0141] For example, the sixth node control sub-circuit 21 includes a third transistor T3, the gate of which is coupled to the first node Q1, the first terminal of which is coupled to the third level signal input terminal VGH, and the second terminal of which is coupled to the sixth node QB1; the third transistor T3 is used to control the conduction or disconnection of the electrical connection between the third level signal input terminal VGH and the sixth node QB1 under the control of the potential of the first node Q1.

[0142] The seventh node control sub-circuit 22 includes an eighteenth transistor T18. The gate of the eighteenth transistor T18 is coupled to the first node Q1, the first terminal of the eighteenth transistor T18 is coupled to the third level signal input terminal VGH, and the second terminal of the eighteenth transistor T18 is coupled to the seventh node QB4. The eighteenth transistor T18 is used to control the conduction or disconnection of the electrical connection between the third level signal input terminal VGH and the seventh node QB4 under the control of the potential of the first node Q1.

[0143] The coupling sub-circuit 28 includes a fifth capacitor C5, the first end of which is coupled to the third clock signal input terminal CKA, and the second end of which is coupled to the ninth node QB7.

[0144] The ninth node control sub-circuit 29 includes a twenty-third transistor T23. The gate of the twenty-third transistor T23 is coupled to the start signal input terminal STV, the first terminal of the twenty-third transistor T23 is coupled to the third level signal input terminal VGH, and the second terminal of the twenty-third transistor T23 is coupled to the ninth node QB7. The twenty-third transistor T23 is used to control the electrical connection between the third level signal input terminal VGH and the ninth node QB7 under the control of the start signal input at the start signal input terminal STV.

[0145] The shift register described above also includes a sixth node control sub-circuit 21 and a seventh node control sub-circuit 22, so that under the control of the potential of the first node Q1, the potential of the sixth node QB1 can be controlled by the sixth node control sub-circuit 21, and the potential of the seventh node QB4 can be controlled by the seventh node control sub-circuit 22, thereby realizing independent control of the potentials of the sixth node QB1 and the seventh node QB4 by the potential of the first node Q1.

[0146] The shift register described above also includes a coupling sub-circuit 28 and a ninth node control sub-circuit 29, which can control the potential of the input node QB5, thereby achieving better control over the potential of the input node QB5.

[0147] As shown in Figures 4 to 12, in some embodiments, the shift register further includes

[0148] The first input sub-circuit 20 is coupled to the start signal input terminal STV, the third clock signal input terminal CKA, and the first node Q1, respectively, and is used to control the electrical connection between the start signal input terminal STV and the first node Q1 to be turned on or off under the control of the third clock signal input at the third clock signal input terminal CKA.

[0149] For example, the first input sub-circuit 20 includes a first transistor T1, the gate of which is coupled to the third clock signal input terminal CKA, the first terminal of which is coupled to the start signal input terminal STV, and the second terminal of which is coupled to the first node Q1. The first transistor T1 is used to control the conduction or disconnection of the electrical connection between the start signal input terminal STV and the first node Q1 under the control of the third clock signal input at the third clock signal input terminal CKA.

[0150] As shown in Figures 4 and 5, in some embodiments, the shift register further includes:

[0151] The first node control sub-circuit 23 is coupled to the first node Q1, the sixth node QB1, the third level signal input terminal VGH, and the second clock signal input terminal CKB, respectively. It is used to control the electrical connection between the first node Q1 and the third level signal input terminal VGH to be turned on or off under the joint control of the potential of the sixth node QB1 and the second clock signal input terminal CKB.

[0152] For example, the first node control sub-circuit 23 includes a fourth transistor T4 and a fifth transistor T5. The gate of the fourth transistor T4 is coupled to the sixth node QB1, the first terminal of the fourth transistor T4 is coupled to the third-level signal input terminal VGH, and the second terminal of the fourth transistor T4 is coupled to the first terminal of the fifth transistor T5. The gate of the fifth transistor T5 is coupled to the second clock signal input terminal CKB, and the second terminal of the fifth transistor T5 is coupled to the first node Q1. The fourth transistor T4 is used to control the conduction or disconnection of the electrical connection between the third-level signal input terminal VGH and the first terminal of the fifth transistor T5 under the control of the potential of the sixth node QB1. The fifth transistor T5 is used to control the conduction or disconnection of the electrical connection between the first terminal of the fifth transistor T5 and the first node Q1 under the control of the second clock signal input at the second clock signal input terminal CKB.

[0153] As shown in Figures 4 to 12, in some embodiments, the shift register further includes:

[0154] The second cascaded control sub-circuit 24 is coupled to the sixth node QB1, the cascaded signal output terminal CR, and the third-level signal input terminal VGH, respectively. It is used to control the electrical connection between the cascaded signal output terminal CR and the third-level signal input terminal VGH under the control of the potential of the sixth node QB1; it is also used to control the potential of the sixth node QB1 according to the third-level signal input at the third-level signal input terminal VGH.

[0155] The second cascaded control sub-circuit 24 includes a seventh transistor T7 and a first capacitor C1. The gate of the seventh transistor T7 is coupled to the sixth node QB1, the first terminal of the seventh transistor T7 is coupled to the third-level signal input terminal VGH, and the second terminal of the seventh transistor T7 is coupled to the cascaded signal output terminal CR. The first terminal of the first capacitor C1 is coupled to the third-level signal input terminal VGH, and the second terminal of the first capacitor C1 is coupled to the sixth node QB1. The seventh transistor T7 is used to control the electrical connection between the cascaded signal output terminal CR and the third-level signal input terminal VGH under the control of the potential of the sixth node QB1. The first capacitor C1 is used to control the potential of the sixth node QB1 according to the third-level signal input at the third-level signal input terminal VGH.

[0156] More specifically, when the shift register adopts the structure shown in Figures 4 and 5, the driving timing of the shift register is shown in Figure 6, and the specific working process is as follows:

[0157] During the P1 period, when the start signal input at the start signal input terminal STV is high voltage and the third clock signal input at the third clock signal input terminal CKA changes from high voltage to low voltage, the first node Q1, the second node Q2, and the first output node Q3 maintain high voltage, the fourth node GD is high voltage, the fifth node QB3 maintains low voltage, the sixth node QB1 maintains low voltage, the second output node QB2 maintains an even lower voltage, the cascade signal output at the cascade signal output terminal CR maintains high voltage, and the gate drive signal output at the gate drive signal output terminal OUT maintains low voltage.

[0158] During the P2 period, when the third clock signal input at the third clock signal input terminal CKA is high and the fourth clock signal input at the fourth clock signal input terminal CKA2 changes from high to low, the first node Q1, the second node Q2, and the first output node Q3 remain at high voltage. The fourth node GD is pulled low by the fourth clock signal input at the fourth clock signal input terminal CKA2. The fifth node QB3 is pulled low from low voltage to an even lower voltage. The second output node QB2 maintains a very low voltage. The cascade signal output at the cascade signal output terminal CR remains at high voltage, and the gate drive signal output at the gate drive signal output terminal OUT remains at low voltage.

[0159] During the P3 period, when the start signal input at the start signal input terminal STV changes from high voltage to low voltage, and the third clock signal input at the third clock signal input terminal CKA changes from high voltage to low voltage, the first node Q1 and the second node Q2 change from high voltage to low voltage, the eighth transistor T8 remains on, the first output node Q3 changes from high voltage to low voltage, and the sixth node QB1, the second output node QB2, the fifth node QB3, and the seventh node QB4 maintain the low voltage of the previous state. Since the second clock signal input at the second clock signal input terminal CKB is high voltage at this time, the cascade signal output at the cascade signal output terminal CR is high voltage, the first clock signal input at the first clock signal input terminal GCK is low voltage, and the gate drive signal output at the gate drive signal output terminal OUT maintains a low voltage.

[0160] During period P4, when the start signal input at the start signal input terminal STV goes low, and the third clock signal input at the third clock signal input terminal CKA goes high, due to the voltage stabilization effect of the first capacitor C1 and the second capacitor C2, the first node Q1, the second node Q2, and the first output node Q3 maintain low voltage. At this time, the third transistor T3 and the eighteenth transistor T18 remain in the open state, and the sixth node QB1, the second output node QB2, the fifth node QB3, and the seventh node QB4 go high. Since the second clock signal input at the second clock signal input terminal CKB is high, the cascade signal output at the cascade signal output terminal CR is high, the first clock signal input at the first clock signal input terminal GCK is low, and the gate drive signal output at the gate drive signal output terminal OUT maintains low voltage.

[0161] During period P5, when the third clock signal input at the third clock signal input terminal CKA is high, and the second clock signal input at the second clock signal input terminal CKB changes from high to low, since the eighth transistor T8 remains on, the voltage change of the cascaded signal output at the cascaded signal output terminal CR from high to low is coupled to the second node Q2 through the second capacitor C2. The second node Q2 is pulled down to an even lower voltage. Due to the voltage limiting effect of the sixth transistor T6, the first node Q1 is slightly pulled down to near the first level signal input at the first level signal input terminal VGL1. At this time, the nineteenth transistor T19 turns on, and the first output node Q3 is pulled down to around the voltage value of the first level signal. At this time, the first clock signal input at the first clock signal input terminal GCK is low, and the gate drive signal output at the gate drive signal output terminal OUT remains low. At this time, the sixth node QB1, the second output node QB2, the fifth node QB3, and the seventh node QB4 remain high.

[0162] During period P6, when the third clock signal input at the third clock signal input terminal CKA is high, and the first clock signal input at the first clock signal input terminal GCK changes from low to high (the change from low to high voltage of the first clock signal input at the first clock signal input terminal GCK occurs when the second clock signal input at the second clock signal input terminal CKB is low), the nineteenth transistor T19 remains on. The first output node Q3 maintains a potential around the current first level signal voltage value, and the gate drive signal output at the gate drive signal output terminal OUT changes from low to high voltage. The voltages of other nodes remain unchanged.

[0163] During period P7, when the third clock signal input at the third clock signal input terminal CKA is high, and the second clock signal input at the second clock signal input terminal CKB changes from low to high, due to the coupling effect of the second capacitor C2, the second node Q2 and the first node Q1 are affected by the process of the cascaded signal output from the cascaded signal output terminal CR changing from low to high voltage. This causes the voltage to return to the potential at the end of the change in the third clock signal input at the third clock signal input terminal CKA. At this time, the voltage of the first output node Q3 remains essentially unchanged due to the isolation effect of the sixteenth transistor T16. The cascaded signal output from the cascaded signal output terminal CR changes from low to high voltage, while the voltages of other nodes remain unchanged. It should be noted that at this time, the sixteenth transistor T16 is in the off state due to the influence of the gate voltage and the source voltage.

[0164] During the P8 period, when the third clock signal input at the third clock signal input terminal CKA is a high voltage, since the eleventh transistor T11 is a buffer transistor with a relatively large parasitic capacitance, the voltage of the first output node Q3 is pulled down to a very low level, ensuring that the eleventh transistor T11 outputs a complete falling edge, and the voltages of other nodes do not change.

[0165] During the P9 period, when the start signal input at the start signal input terminal STV is high voltage and the third clock signal input at the third clock signal input terminal CKA changes from high voltage to low voltage, the first node Q1, the second node Q2, and the first output node Q3 change from low voltage to high voltage. The fourth node GD maintains a high voltage at this time, while the sixth node QB1, the second output node QB2, the fifth node QB3, and the seventh node QB4 change from high voltage to low voltage. The cascade signal output at the cascade signal output terminal CR maintains a high voltage, and the gate drive signal output at the gate drive signal output terminal OUT maintains a low voltage.

[0166] During period P10, when the third clock signal input at the third clock signal input terminal CKA is high and the fourth clock signal input at the fourth clock signal input terminal CKA2 changes from high to low, the first node Q1, the second node Q2, and the first output node Q3 remain at high voltage. The fourth node GD is pulled low by the fourth clock signal input at the fourth clock signal input terminal CKA2. The fifth node QB3 is pulled low to an even lower voltage, and the second output node QB2 is pulled low to an even lower voltage. The cascade signal output at the cascade signal output terminal CR remains at high voltage, and the gate drive signal output at the gate drive signal output terminal OUT remains at low voltage.

[0167] During the P11 period, when the third clock signal input at the third clock signal input terminal CKA is at a high voltage and the second clock signal input at the second clock signal input terminal CKB changes from a high voltage to a low voltage, the fourth transistor T4 and the fifth transistor T5 turn on. The first node Q1, the second node Q2, and the first output node Q3 are input to the third level signal input at the third level signal input terminal VGH, making them less susceptible to interference from other clock signals.

[0168] It is worth noting that the start signal input at the STV terminal only needs to maintain a low voltage signal during the period when the third clock signal input at the CKA terminal is low. Depending on the actual pixel driving requirements, the pulse width can be set to be greater than 4H or less than 1H.

[0169] When the shift register adopts the structure shown in Figures 8 and 9, the driving timing of the shift register is shown in Figure 10, and the specific working process is as follows:

[0170] During period n1, when the start signal input at the start signal input terminal STV is high and the third clock signal input at the third clock signal input terminal CKA changes from high to low, the voltage of the eighth node QB6 is pulled low, the voltage of the input node QB5 is pulled low, the first node Q1, the second node Q2, and the first output node Q3 remain high, the fourth node GD is high, the fifth node QB3 remains low, the input node QB5 and the fifth node QB3 are low, the sixth node QB1 and the second output node QB2 are affected by the potential of the input node QB5 and the fifth node QB3, and are pulled high but still remain low, the cascade signal output at the cascade signal output terminal CR remains high, and the gate drive signal output at the gate drive signal output terminal OUT remains low.

[0171] During the n2 period, when the third clock signal input at the third clock signal input terminal CKA is high and the fourth clock signal input at the fourth clock signal input terminal CKA2 changes from high to low, the eighth node QB6, the first node Q1, and the second node Q2 remain at high voltage. The fourth node GD is pulled low by the fourth clock signal input at the fourth clock signal input terminal CKA2. The fifth node QB3 is pulled low from low voltage to an even lower voltage. The sixth node QB1 is pulled low again. The cascade signal output at the cascade signal output terminal CR remains at high voltage, and the gate drive signal output at the gate drive signal output terminal OUT remains at low voltage.

[0172] During period n3, when the start signal input at the start signal input terminal STV changes from high voltage to low voltage, the eighth node QB6 and input node QB5 maintain high voltage. When the third clock signal input at the third clock signal input terminal CKA changes from high voltage to low voltage, the first node Q1 and the second node Q2 change from high voltage to low voltage, the eighth transistor T8 remains on, the first output node Q3 changes from high voltage to low voltage, input node QB5 maintains high voltage, and the voltages at the sixth node QB1, the fifth node QB3, and the seventh node QB4 change from low to high. Since the second clock signal input at the second clock signal input terminal CKB is high voltage at this time, the cascade signal output at the cascade signal output terminal CR is high voltage, the first clock signal input at the first clock signal input terminal GCK is low voltage, and the gate drive signal output at the gate drive signal output terminal OUT maintains low voltage.

[0173] During the n4 period, when the start signal input at the start signal input terminal STV goes low, and the third clock signal input at the third clock signal input terminal CKA goes from low to high, due to the voltage stabilization effect of the first capacitor C1 and the second capacitor C2, the first node Q1, the second node Q2, and the first output node Q3 maintain low voltage, while the sixth node QB1, the fifth node QB3, the seventh node QB4, and the second output node QB2 maintain high voltage. Since the second clock signal input at the second clock signal input terminal CKB is high at this time, the cascade signal output at the cascade signal output terminal CR is high, the first clock signal input at the first clock signal input terminal GCK is low, and the gate drive signal output at the gate drive signal output terminal OUT maintains low voltage.

[0174] During period n5, when the third clock signal input at the third clock signal input terminal CKA is high and the second clock signal input at the second clock signal input terminal CKB changes from high to low, since the eighth transistor T8 remains on, the voltage change of the cascaded signal output at the cascaded signal output terminal CR from high to low is coupled to the second node Q2 through the second capacitor C2. The second node Q2 is pulled down to an even lower voltage. Due to the voltage limiting effect of the sixth transistor T6, the first node Q1 is slightly pulled down to a voltage close to the first level signal input at the first level signal input terminal VGL1. At this time, the nineteenth transistor T19 turns on, and the first output node Q3 is pulled down to approximately the voltage value of the first level signal input at the first level signal input terminal VGL1. At this time, the first clock signal input at the first clock signal input terminal GCK is low, and the gate drive signal output at the gate drive signal output terminal OUT remains low. At this time, the input node QB5, the sixth node QB1, the fifth node QB3, the seventh node QB4, and the second output node QB2 remain high.

[0175] During period n6, when the third clock signal input at the third clock signal input terminal CKA is high, and the first clock signal input at the first clock signal input terminal GCK changes from low to high (the change from low to high voltage of the first clock signal input at the first clock signal input terminal GCK occurs when the second clock signal input at the second clock signal input terminal CKB is low), the nineteenth transistor T19 remains on. The first output node Q3 maintains a potential around the current first level signal voltage value input at the first level signal input terminal VGL1. The gate drive signal output at the gate drive signal output terminal OUT changes from low to high voltage, while the voltages of other nodes remain unchanged.

[0176] During the n7 period, when the third clock signal input at the third clock signal input terminal CKA is high and the second clock signal input at the second clock signal input terminal CKB changes from low to high, due to the coupling effect of the second capacitor C2, the first node Q1 and the second node Q2 are affected by the process of the cascaded signal output at the cascaded signal output terminal CR changing from low voltage to high voltage. This causes the voltage to return to the potential at the end of the change from low voltage to high voltage of the third clock signal input at the third clock signal input terminal CKA. At this time, the voltage of the first output node Q3 remains basically unchanged due to the isolation effect of the sixteenth transistor T16. The cascaded signal output at the cascaded signal output terminal CR changes from low voltage to high voltage, while the voltages of other nodes remain unchanged.

[0177] During the n8 period, when the third clock signal input at the third clock signal input terminal CKA is at a high voltage and the first clock signal input at the first clock signal input terminal GCK changes from a high voltage to a low voltage, since the eleventh transistor T11 is a buffer transistor with a relatively large parasitic capacitance, the voltage of the first output node Q3 is pulled down to a very low level, ensuring that the eleventh transistor T11 outputs a complete falling edge, and the voltages of other nodes remain unchanged.

[0178] During the n9 period, when the start signal input at the start signal input terminal STV is high voltage and the third clock signal input at the third clock signal input terminal CKA changes from high voltage to low voltage, the eighth node QB6 changes from high voltage to low voltage, the input node QB5 changes from high voltage to low voltage, the first node Q1, the second node Q2, and the first output node Q3 change from low voltage to high voltage, the fourth node GD maintains a high voltage at this time, the sixth node QB1, the fifth node QB3, the seventh node QB4, and the second output node QB2 change from high voltage to low voltage, the cascade signal output at the cascade signal output terminal CR maintains a high voltage, and the gate drive signal output at the gate drive signal output terminal OUT maintains a low voltage.

[0179] During the n10 period, when the third clock signal input at the third clock signal input terminal CKA is high and the fourth clock signal input at the fourth clock signal input terminal CKA2 changes from high to low, the eighth node QB6, the first node Q1, the second node Q2, and the first output node Q3 remain at high voltage. The fourth node GD is pulled low by the fourth clock signal input at the fourth clock signal input terminal CKA2. The fifth node QB3 is pulled low to an even lower voltage. The first output node Q3 is pulled low to an even lower voltage. The cascade signal output at the cascade signal output terminal CR remains at high voltage, and the gate drive signal output at the gate drive signal output terminal OUT remains at low voltage.

[0180] Figure 7 illustrates the cascaded connection of six shift registers (GOA-1, GOA-2, GOA-3, GOA-4, GOA-5, GOA-6). It shows the first clock signal line GCK1, the second clock signal line GCK2, the third clock signal line GCK3, the fourth clock signal line GCK4, the start signal line STV', the fifth clock signal line CKA', the sixth clock signal line CKA2', the seventh clock signal line CKB', and the eighth clock signal line CKB2'.

[0181] The clock signals transmitted by the first clock signal line GCK1, the second clock signal line GCK2, the third clock signal line GCK3, and the fourth clock signal line GCK4 are a set of clock signals with the same pulse width but different phases. The voltage variation range is from the level value of the second level signal input at the second level signal input terminal to the level value of the fifth level signal transmitted at the fifth level signal input terminal.

[0182] The clock signals transmitted by the fifth clock signal line CKA', the sixth clock signal line CKA2', the seventh clock signal line CKB', and the eighth clock signal line CKB2' are a set of clock signals with the same pulse width but different phases. The voltage variation range is from the level value of the first level signal input at the first level signal input terminal to the level value of the fourth level signal transmitted at the fourth level signal input terminal.

[0183] The following relationships must be met: the level value of the first level signal is less than or equal to the level value of the second level signal; the level value of the fourth level signal is greater than or equal to the level value of the fifth level signal. The above relationship applies when the level values ​​have a positive or negative sign.

[0184] It should be noted that in the shift registers of the above embodiments, the third-level signals input to each of the connected third-level signal input terminals VGH can be different. For example, some of the third-level signal input terminals VGH can be the same as the fourth-level signal, and another part of the third-level signal input terminals VGH can be the same as the fifth-level signal, but it is not limited to this.

[0185] The cascaded signal output terminal CR of the x-th shift register is coupled to the start signal input terminal STV of the (x+2)-th shift register, where x is an integer greater than 2. The start signal input terminals STV of the 1st and 2nd shift registers are directly coupled to the start signal line STV'.

[0186] In the case of multiple cascaded shift registers, the third clock signal input terminal CKA of the (4N+1)th shift register is coupled to the fifth clock signal line CKA'; the fourth clock signal input terminal CKA2 of the (4N+1)th shift register is coupled to the sixth clock signal line CKA2'; the second clock signal input terminal CKB of the (4N+1)th shift register is coupled to the seventh clock signal line CKB'; and the first clock signal input terminal GCK of the (4N+1)th shift register is coupled to the first clock signal line GCK1. N is an integer greater than or equal to 0.

[0187] The third clock signal input terminal CKA in the 4N+2 shift register is coupled to the sixth clock signal line CKA2'; the fourth clock signal input terminal CKA2 in the 4N+2 shift register is coupled to the seventh clock signal line CKB'; the second clock signal input terminal CKB in the 4N+2 shift register is coupled to the eighth clock signal line CKB2'; and the first clock signal input terminal GCK in the 4N+2 shift register is coupled to the second clock signal line GCK2.

[0188] The third clock signal input terminal CKA in the 4N+3 shift register is coupled to the seventh clock signal line CKB'; the fourth clock signal input terminal CKA2 in the 4N+3 shift register is coupled to the eighth clock signal line CKB2'; the second clock signal input terminal CKB in the 4N+3 shift register is coupled to the fifth clock signal line CKA'; and the first clock signal input terminal GCK in the 4N+3 shift register is coupled to the third clock signal line GCK3.

[0189] The third clock signal input terminal CKA in the 4N+4th shift register is coupled to the eighth clock signal line CKB2'; the fourth clock signal input terminal CKA2 in the 4N+4th shift register is coupled to the fifth clock signal line CKA'; the second clock signal input terminal CKB in the 4N+4th shift register is coupled to the sixth clock signal line CKA2'; and the first clock signal input terminal GCK in the 4N+4th shift register is coupled to the fourth clock signal line GCK4.

[0190] Figures 6 and 10 also illustrate the cascaded signal output terminal CR of the Nth shift register unit. <n>The cascaded signal output terminal CR of the (N+1)th shift register unit<N+1> The timing of the cascaded output signals; and the gate drive signal output terminal OUT of the Nth shift register unit. <n>and the gate drive signal output terminal OUT of the (N+1)th shift register unit<N+1> Timing of the output gate drive signal.

[0191] The shift register provided in the above embodiments can be applied to LTPO or LTPS OLED display products. For example, the shift register provided in the above embodiments can be applied to LTPO. In this type of display product, the transistor that controls the gate of the driving transistor to write data signals in the pixel circuit is an oxide transistor. It needs to be a gate drive signal with a high voltage pulse with a pulse width of less than 1H or about 1.5H as the control signal for the oxide transistor. The shift register that outputs this signal can be called NGate GOA.

[0192] The shift register provided in the above embodiments can use a P-type transistor to output a gate drive signal with a high voltage pulse that has shifted, and the waveform of the signal can maintain low potential stability.

[0193] This disclosure also provides a method for driving a shift register, applied to the shift register provided in the above embodiments, the method comprising:

[0194] Under the control of the potential of the first output node Q3, the first output sub-circuit 10 controls the electrical connection between the gate drive signal output terminal OUT and the first clock signal input terminal GCK to be turned on or off.

[0195] The first output node control sub-circuit 11 controls the electrical connection between the first node Q1 and the first output node Q3 to be turned on or off under the control of the first level signal input to the first level signal input terminal VGL1; and also controls the electrical connection between the first output node Q3 and the first level signal input terminal VGL1 to be turned on or off under the control of the potential of the second node Q2.

[0196] Under the control of the potential of the second node Q2, the first cascade control sub-circuit 12 controls the electrical connection between the second clock signal input terminal CKB and the cascade signal output terminal CR to be turned on or off, and also controls the potential of the second node Q2 according to the cascade signal output by the cascade signal output terminal CR.

[0197] Under the control of the first level signal, the first isolation control sub-circuit 13 controls the conduction of the electrical connection between the first node Q1 and the second node Q2.

[0198] When the shift register is driven using the driving method provided in this embodiment, if the potential of the second node Q2 controls the conduction of the cascaded signal output terminal CR and the second clock signal input terminal CKB, the second clock signal input at the second clock signal input terminal CKB will be transmitted to the cascaded signal output terminal CR, thereby affecting the potential of the second node Q2. Since the potential of the second node Q2 can control the conduction or disconnection of the electrical connection between the first output node Q3 and the first level signal input terminal VGL1, when the potential of the second node Q2 is affected and becomes lower, it can better control the conduction of the electrical connection between the first output node Q3 and the first level signal input terminal VGL1, keeping the potential of the first output node Q3 at an effective potential. This effective potential can conduct the electrical connection between the gate drive signal output terminal OUT and the first clock signal input terminal GCK, ensuring that the signal of the gate drive signal output terminal OUT is consistent with the signal input at the first clock signal input terminal GCK, thus guaranteeing the stability of the signal output by the gate drive signal output terminal OUT.

[0199] When the potential of the second node Q2 becomes higher due to the influence of the first isolation control sub-circuit 13, the potential of the first node Q1 is affected. Since the first output node control sub-circuit 11 can control the disconnection of the electrical connection between the first node Q1 and the first output node Q3 under the control of the first level signal input at the first level signal input terminal VGL1, the potential of the first output node Q3 can avoid being affected by the potential of the first node Q1. The first output node Q3 can continue to maintain its original state and maintain the control state of the first output node Q3 on the first output sub-circuit 10, thereby better maintaining the stability of the signal output at the gate drive signal output terminal OUT.

[0200] In some embodiments, the driving method further includes:

[0201] Under the control of the potential of the second output node QB2, the second output sub-circuit 14 controls the electrical connection between the gate drive signal output terminal OUT and the second level signal input terminal VGL2 to be turned on or off.

[0202] The fourth node control sub-circuit 15, under the control of the potential of the first node Q1, controls the electrical connection between the fourth node GD and the third level signal input terminal VGH to be turned on or off; it also controls the potential of the fifth node QB3 according to the potential of the fourth node GD.

[0203] The fourth node control sub-circuit 15, under the control of the potential of the fifth node QB3, controls the connection between the fourth node GD and the fourth clock signal input terminal CKA2 to be turned on or off; or, under the control of the potential of the fifth node QB3, controls the connection between the fourth node GD and the second clock signal input terminal CKB to be turned on or off.

[0204] The second output node control sub-circuit 16 controls the electrical connection between the second output node QB2 and the fifth node QB3 to be turned on or off under the control of the potential of the fifth node QB3.

[0205] When driving the shift register using the driving method provided in the above embodiments, when the electrical connection between the fourth node GD and the third level signal input terminal VGH is disconnected under the control of the potential of the first node Q1, and the electrical connection between the fourth node GD and the second clock signal input terminal CKB or the fourth clock signal input terminal CKA2 is connected under the control of the potential of the fifth node QB3: the fourth clock signal input at the fourth clock signal input terminal CKA2 is transmitted to the fourth node GD, and the potential of the fourth node GD then controls the potential of the fifth node QB3. When the potential of the fifth node QB3 becomes lower due to the influence, the second output node control sub-circuit 16 can better control the connection between the second output node QB2 and the fifth node QB3, keeping the potential of the second output node QB2 at an effective potential. This effective potential can connect the electrical connection between the gate drive signal output terminal OUT and the second level signal input terminal VGL2, ensuring that the signal of the gate drive signal output terminal OUT is consistent with the signal input at the second level signal input terminal VGL2, thus guaranteeing the stability of the signal output by the gate drive signal output terminal OUT.

[0206] This disclosure also provides a display device, including the shift register provided in the above embodiments.

[0207] For example, the display device includes a gate driving circuit, which includes a plurality of cascaded shift registers.

[0208] It should be noted that the display device can be any product or component with display function, such as a television, monitor, digital photo frame, mobile phone, or tablet computer. The display device also includes flexible circuit boards, printed circuit boards, and backplanes.

[0209] In the shift register provided in the above embodiment, when the potential of the second node Q2 controls the conduction of the cascaded signal output terminal CR and the second clock signal input terminal CKB, the second clock signal input at the second clock signal input terminal CKB will be transmitted to the cascaded signal output terminal CR, thereby affecting the potential of the second node Q2. Since the potential of the second node Q2 can control the conduction or disconnection of the electrical connection between the first output node Q3 and the first level signal input terminal VGL1, when the potential of the second node Q2 is affected and becomes lower, it can better control the conduction of the electrical connection between the first output node Q3 and the first level signal input terminal VGL1, keeping the potential of the first output node Q3 at an effective potential. This effective potential can conduct the electrical connection between the gate drive signal output terminal OUT and the first clock signal input terminal GCK, ensuring that the signal of the gate drive signal output terminal OUT is consistent with the signal input at the first clock signal input terminal GCK, thus guaranteeing the stability of the signal output by the gate drive signal output terminal OUT. When the potential of the second node Q2 becomes higher due to the influence of the first isolation control sub-circuit 13, the potential of the first node Q1 is affected. Since the first output node control sub-circuit 11 can control the disconnection of the electrical connection between the first node Q1 and the first output node Q3 under the control of the first level signal input at the first level signal input terminal VGL1, the potential of the first output node Q3 can avoid being affected by the potential of the first node Q1. The first output node Q3 can continue to maintain its original state and maintain the control state of the first output node Q3 on the first output sub-circuit 10, thereby better maintaining the stability of the signal output at the gate drive signal output terminal OUT.

[0210] Therefore, the display device provided in this disclosure, when including the shift register provided in the above embodiments, also has the above-mentioned beneficial effects and can achieve better display effects.

[0211] In all embodiments of this disclosure, the transistors used can be thin-film transistors, field-effect transistors, or other devices with similar characteristics. In the embodiments of this disclosure, to distinguish the two terminals of the transistor other than the gate, one terminal is referred to as the first terminal and the other as the second terminal.

[0212] In actual operation, when the transistor is a thin-film transistor or a field-effect transistor, the first electrode can be the drain and the second electrode can be the source; or, the first electrode can be the source and the second electrode can be the drain.

[0213] It should be noted that, in the embodiments of this disclosure, "same layer" can refer to film layers located on the same structural layer. Alternatively, for example, film layers located on the same layer can be layer structures formed by using the same film deposition process to form a specific pattern, and then patterning the film layer using the same photomask through a single patterning process. Depending on the specific pattern, the single patterning process may include multiple exposure, development, or etching processes, and the specific pattern in the formed layer structure can be continuous or discontinuous. These specific patterns may also be at different heights or have different thicknesses.

[0214] In the various method embodiments of this disclosure, the sequence numbers of each step are not intended to limit the order of the steps. For those skilled in the art, any changes in the order of the steps are within the scope of protection of this disclosure without any creative effort.

[0215] It should be noted that the various embodiments in this specification are described in a progressive manner, and the same or similar parts between the various embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the method embodiments are basically similar to the product embodiments, so the description is relatively simple, and the relevant parts can be referred to the description of the product embodiments.

[0216] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms "first," "second," and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as "comprising" or "including" mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as "connection," "coupled," or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as "upper," "lower," "left," and "right" are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0217] It is understandable that when a component such as a layer, film, region, or substrate is referred to as being "above" or "below" another component, the component may be "directly" located "above" or "below" the other component, or there may be intermediate components present.

[0218] In the description of the above embodiments, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples. The above descriptions are merely specific embodiments of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.< / n> < / n>

Claims

1. A shift register, comprising: The first output sub-circuit is coupled to the gate drive signal output terminal, the first clock signal input terminal and the first output node respectively, and is used to control the conduction or disconnection of the electrical connection between the gate drive signal output terminal and the first clock signal input terminal under the control of the potential of the first output node. The first output node control sub-circuit is coupled to the first node, the second node, the first output node and the first level signal input terminal respectively, and is used to control the electrical connection between the first node and the first output node to be turned on or off under the control of the first level signal input at the first level signal input terminal. It is also used to control the electrical connection between the first output node and the first level signal input terminal to be turned on or off under the control of the potential of the second node; The first cascaded control sub-circuit is coupled to the cascaded signal output terminal, the second clock signal input terminal, and the second node, respectively, and is used to control the electrical connection between the second clock signal input terminal and the cascaded signal output terminal to be turned on or off under the control of the potential of the second node. The first isolation control sub-circuit is used to control the connection between the first node and the second node to be turned on or off.

2. The shift register according to claim 1, wherein, Also includes: The second output sub-circuit is coupled to the gate drive signal output terminal, the second level signal input terminal, and the second output node, respectively, and is used to control the conduction or disconnection of the electrical connection between the gate drive signal output terminal and the second level signal input terminal under the control of the potential of the second output node. The fourth node control sub-circuit is coupled to the first node, the fourth node, the fifth node, and the third level signal input terminal, respectively. The fourth node control sub-circuit is also coupled to the fourth clock signal input terminal or the second clock signal input terminal. It is used to control the electrical connection between the fourth node and the third level signal input terminal under the control of the potential of the first node; and to control the potential of the fifth node according to the potential of the fourth node. The fourth node control sub-circuit is also used to: control the electrical connection between the fourth node and the fourth clock signal input terminal to be turned on or off under the control of the potential of the fifth node; or, control the electrical connection between the fourth node and the second clock signal input terminal to be turned on or off under the control of the potential of the fifth node. The second output node control sub-circuit is coupled to the second output node and the fifth node respectively, and is used to control the electrical connection between the second output node and the fifth node to be turned on or off under the control of the potential of the fifth node.

3. The shift register according to claim 2, wherein, Also includes: The second isolation control sub-circuit is coupled to the first level signal input terminal, the second output node and the sixth node respectively, and is used to control the conduction or disconnection of the electrical connection between the second output node and the sixth node under the control of the first level signal input terminal. The third isolation control sub-circuit is coupled to the first level signal input terminal, the fifth node and the seventh node respectively, and is used to control the conduction or disconnection of the electrical connection between the fifth node and the seventh node under the control of the first level signal input terminal. The second input sub-circuit is coupled to the third clock signal input terminal, the sixth node, the seventh node, and the input node, respectively; it is used to control the electrical connection between the sixth node and the input node to be turned on or off under the control of the third clock signal input to the third clock signal input terminal, and to control the electrical connection between the seventh node and the input node to be turned on or off under the control of the third clock signal input to the third clock signal input terminal.

4. The shift register according to claim 3, wherein, The input node is directly coupled to the first level signal input terminal; the shift register further includes: The sixth node control sub-circuit is coupled to the first node, the third clock signal input terminal and the sixth node respectively, and is used to control the conduction or disconnection of the electrical connection between the third clock signal input terminal and the sixth node under the control of the potential of the first node; The seventh node control sub-circuit is coupled to the first node, the third clock signal input terminal and the seventh node respectively, and is used to control the electrical connection between the third clock signal input terminal and the seventh node to be turned on or off under the control of the potential of the first node.

5. The shift register according to claim 3, wherein, Also includes: The first input node control sub-circuit is coupled to the start signal input terminal, the third level signal input terminal and the input node respectively, and is used to control the electrical connection between the third level signal input terminal and the input node to be turned on or off under the control of the start signal input at the start signal input terminal; The second input node control sub-circuit is coupled to the eighth node, the first level signal input terminal and the input node respectively, and is used to control the conduction or disconnection of the electrical connection between the first level signal input terminal and the input node under the control of the potential of the eighth node; The eighth node control sub-circuit is coupled to the third clock signal input terminal, the start signal input terminal, the eighth node, and the third level signal input terminal, respectively. It is used to control the potential of the eighth node according to the third clock signal input terminal, and also to control the electrical connection between the third level signal input terminal and the eighth node to be turned on or off under the control of the start signal input terminal.

6. The shift register according to claim 3, wherein, The input node is directly coupled to the first level signal input terminal; the shift register further includes: The sixth node control sub-circuit is coupled to the first node, the third level signal input terminal and the sixth node respectively, and is used to control the conduction or disconnection of the electrical connection between the third level signal input terminal and the sixth node under the control of the potential of the first node; The seventh node control sub-circuit is coupled to the first node, the third level signal input terminal and the seventh node respectively, and is used to control the conduction or disconnection of the electrical connection between the third level signal input terminal and the seventh node under the control of the potential of the first node; A coupling sub-circuit, wherein the second input sub-circuit is coupled to the ninth node, and the ninth node is coupled to the third clock signal input terminal through the coupling sub-circuit; The ninth node control sub-circuit is coupled to the ninth node, the start signal input terminal, and the third level signal input terminal, respectively, and is used to control the electrical connection between the third level signal input terminal and the ninth node to be turned on or off under the control of the start signal input at the start signal input terminal.

7. The shift register according to any one of claims 4 to 6, wherein, Also includes The first input sub-circuit is coupled to the start signal input terminal, the third clock signal input terminal and the first node respectively, and is used to control the electrical connection between the start signal input terminal and the first node to be turned on or off under the control of the third clock signal input at the third clock signal input terminal.

8. The shift register according to any one of claims 4 to 6, wherein, Also includes: The first node control sub-circuit is coupled to the first node, the sixth node, the third level signal input terminal, and the second clock signal input terminal, respectively. It is used to control the electrical connection between the first node and the third level signal input terminal to be turned on or off under the joint control of the potential of the sixth node and the second clock signal input terminal.

9. The shift register according to any one of claims 4 to 6, wherein, Also includes: The second cascaded control sub-circuit is coupled to the sixth node, the cascaded signal output terminal, and the third-level signal input terminal, respectively. It is used to control the electrical connection between the cascaded signal output terminal and the third-level signal input terminal under the control of the potential of the sixth node; it is also used to control the potential of the sixth node according to the third-level signal input from the third-level signal input terminal.

10. The shift register according to claim 1, wherein, The first output sub-circuit includes an eleventh transistor, the gate of which is coupled to the first output node, the first terminal of which is coupled to the first clock signal input terminal, and the second terminal of which is coupled to the gate drive signal output terminal. The first output node control sub-circuit includes a sixteenth transistor and a nineteenth transistor. The gate of the sixteenth transistor is coupled to the first level signal input terminal, the first terminal of the sixteenth transistor is coupled to the first node, and the second terminal of the sixteenth transistor is coupled to the first output node. The gate of the nineteenth transistor is coupled to the second node, the first terminal of the nineteenth transistor is coupled to the first level signal input terminal, and the second terminal of the nineteenth transistor is coupled to the first output node. The first cascaded control sub-circuit includes an eighth transistor and a second capacitor. The gate of the eighth transistor is coupled to the second node, the first terminal of the eighth transistor is coupled to the second clock signal input terminal, and the second terminal of the eighth transistor is coupled to the cascaded signal output terminal. The first terminal of the second capacitor is coupled to the cascaded signal output terminal, and the second terminal of the second capacitor is coupled to the second node. The first isolation control sub-circuit includes a sixth transistor, the gate of which is coupled to the first level signal input terminal, the first terminal of which is coupled to the first node, and the second terminal of which is coupled to the second node.

11. The shift register according to claim 2, wherein, The second output sub-circuit includes a tenth transistor, the gate of which is coupled to the second output node, the first terminal of which is coupled to the second level signal input terminal, and the second terminal of which is coupled to the gate drive signal output terminal. The fourth node control sub-circuit includes a twelfth transistor, a thirteenth transistor, and a third capacitor coupled together; the gate of the twelfth transistor is coupled to the fifth node, the first terminal of the twelfth transistor is coupled to the fourth clock signal input terminal or the second clock signal input terminal, and the second terminal of the twelfth transistor is coupled to the fourth node; the gate of the thirteenth transistor is coupled to the first node, the first terminal of the thirteenth transistor is coupled to the third level signal input terminal, and the second terminal of the thirteenth transistor is coupled to the fourth node; the first terminal of the third capacitor is coupled to the fourth node, and the second terminal of the third capacitor is coupled to the fifth node; The second output node control sub-circuit includes a fourteenth transistor, the gate of which is coupled to the fifth node, the first terminal of which is coupled to the fifth node, and the second terminal of which is coupled to the second output node.

12. The shift register according to claim 3, wherein, The second isolation control sub-circuit includes a ninth transistor, the gate of which is coupled to the first level signal input terminal, the first terminal of which is coupled to the sixth node, and the second terminal of which is coupled to the second output node; The third isolation control sub-circuit includes a fifteenth transistor, the gate of which is coupled to the first level signal input terminal, the first terminal of which is coupled to the seventh node, and the second terminal of which is coupled to the fifth node; The second input sub-circuit includes a second transistor and a seventeenth transistor. The gate of the second transistor is coupled to the third clock signal input terminal, the first terminal of the second transistor is coupled to the first level signal input terminal, and the second terminal of the second transistor is coupled to the sixth node. The gate of the seventeenth transistor is coupled to the third clock signal input terminal, the first terminal of the seventeenth transistor is coupled to the first level signal input terminal, and the second terminal of the seventeenth transistor is coupled to the seventh node.

13. The shift register according to claim 4, wherein, The sixth node control sub-circuit includes a third transistor, the gate of which is coupled to the first node, the first terminal of which is coupled to the third clock signal input terminal, and the second terminal of which is coupled to the sixth node. The seventh node control sub-circuit includes an eighteenth transistor, the gate of which is coupled to the first node, the first terminal of which is coupled to the third clock signal input terminal, and the second terminal of which is coupled to the seventh node.

14. The shift register according to claim 5, wherein, The first input node control sub-circuit includes a twentieth transistor, the gate of which is coupled to the start signal input terminal, the first terminal of which is coupled to the third level signal input terminal, and the second terminal of which is coupled to the input node. The second input node control sub-circuit includes a twenty-first transistor, the gate of which is coupled to the eighth node, the first terminal of which is coupled to the first level signal input terminal, and the second terminal of which is coupled to the input node. The eighth node control sub-circuit includes a twenty-second transistor and a fourth capacitor. The gate of the twenty-second transistor is coupled to the start signal input terminal, the first terminal of the twenty-second transistor is coupled to the third level signal input terminal, and the second terminal of the twenty-second transistor is coupled to the eighth node. The first terminal of the fourth capacitor is coupled to the third clock signal input terminal, and the second terminal of the fourth capacitor is coupled to the eighth node.

15. The shift register according to claim 6, wherein, The sixth node control sub-circuit includes a third transistor, the gate of which is coupled to the first node, the first terminal of which is coupled to the third level signal input terminal, and the second terminal of which is coupled to the sixth node. The seventh node control sub-circuit includes an eighteenth transistor, the gate of which is coupled to the first node, the first terminal of which is coupled to the third level signal input terminal, and the second terminal of which is coupled to the seventh node. The coupling sub-circuit includes a fifth capacitor, the first end of which is coupled to the third clock signal input terminal, and the second end of which is coupled to the ninth node. The ninth node control sub-circuit includes a twenty-third transistor, the gate of which is coupled to the start signal input terminal, the first terminal of which is coupled to the third level signal input terminal, and the second terminal of which is coupled to the ninth node.

16. The shift register according to claim 7, wherein, The first input sub-circuit includes a first transistor, the gate of which is coupled to the third clock signal input terminal, the first terminal of which is coupled to the start signal input terminal, and the second terminal of which is coupled to the first node.

17. The shift register according to claim 8, wherein, The first node control sub-circuit includes a fourth transistor and a fifth transistor. The gate of the fourth transistor is coupled to the sixth node, the first terminal of the fourth transistor is coupled to the third level signal input terminal, and the second terminal of the fourth transistor is coupled to the first terminal of the fifth transistor. The gate of the fifth transistor is coupled to the second clock signal input terminal, and the second terminal of the fifth transistor is coupled to the first node.

18. The shift register according to claim 9, wherein, The second cascaded control sub-circuit includes a seventh transistor and a first capacitor. The gate of the seventh transistor is coupled to the sixth node, the first terminal of the seventh transistor is coupled to the third-level signal input terminal, and the second terminal of the seventh transistor is coupled to the cascaded signal output terminal. The first terminal of the first capacitor is coupled to the third-level signal input terminal, and the second terminal of the first capacitor is coupled to the sixth node.

19. A method for driving a shift register, applied to a shift register as described in any one of claims 1 to 18, the method comprising: Under the control of the potential of the first output node, the first output sub-circuit controls the electrical connection between the gate drive signal output terminal and the first clock signal input terminal to be turned on or off. The first output node control sub-circuit controls the electrical connection between the first node and the first output node to be turned on or off under the control of the first level signal input at the first level signal input terminal. Under the control of the potential of the second node, the electrical connection between the first output node and the first level signal input terminal is controlled to be turned on or off. The first cascade control sub-circuit, under the control of the potential of the second node, controls the electrical connection between the second clock signal input terminal and the cascade signal output terminal to be turned on or off, and also controls the potential of the second node according to the cascade signal output by the cascade signal output terminal; Under the control of the first level signal, the first isolation control sub-circuit controls the conduction of the electrical connection between the first node and the second node.

20. The method for driving a shift register according to claim 19, wherein, The driving method further includes: The second output sub-circuit, under the control of the potential of the second output node, controls the electrical connection between the gate drive signal output terminal and the second level signal input terminal to be turned on or off. The fourth node control sub-circuit, under the control of the potential of the first node, controls the electrical connection between the fourth node and the third level signal input terminal to be turned on or off; it also controls the potential of the fifth node according to the potential of the fourth node. The fourth node control sub-circuit, under the control of the potential of the fifth node, controls the connection between the fourth node and the fourth clock signal input terminal to be turned on or off; or, under the control of the potential of the fifth node, controls the connection between the fourth node and the second clock signal input terminal to be turned on or off. The second output node control sub-circuit, under the control of the potential of the fifth node, controls the electrical connection between the second output node and the fifth node to be turned on or off.

21. A display device comprising a shift register as claimed in any one of claims 1 to 18.

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