Display adjustment method, display adjustment module and display apparatus

Abstract

Provided in the present disclosure are a display adjustment method, a display adjustment module and a display apparatus. The display adjustment method comprises: when pixel circuits in a first predetermined display area are in a hold phase and pixel circuits in a second predetermined display area are in a refresh phase, controlling, during at least two frames of display time among adjacent M frames of display time and at the boundary of the adjacent display areas, the positions of pixel circuits that start to work to be different; and / or, when the pixel circuits in the first predetermined display area are in a refresh phase and the pixel circuits in the second predetermined display area are in a hold phase, controlling, during at least two frames of display time among the adjacent M frames of display time and at the boundary of the adjacent display areas, the positions of pixel circuits that start to stop working to be different, wherein M is a positive integer, and M is greater than 1 and less than or equal to 5. The present disclosure can ameliorate defects in display performance.

Description

Display adjustment method, display adjustment module, and display device

[0001] Cross-references to related applications

[0002] This application claims priority to Chinese Patent Application No. 202411178472.6, filed in China on August 26, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to the field of display technology, and in particular to a display adjustment method, a display adjustment module, and a display device. Background Technology

[0004] In related AMOLED (Active Matrix Organic Light Emitting Diode) module applications, to achieve the ultimate and superior intelligent display, the overall fixed-frequency display of the module is no longer sufficient. Consequently, multi-zone displays with different frequencies have emerged. In related technologies, when the same display module uses different refresh rates in different display areas, each display frequency corresponds to the same set of Gamma data. For example, using 120Hz Gamma data as a baseline, other display refresh rates (60Hz / 30Hz) will share this set of Gamma data. Currently, the various frequencies of split-screen displays are also implemented based on 120Hz using frame skipping. That is, at 120Hz, refreshing one frame and holding it for one frame is 60Hz; refreshing one frame and holding it for three frames is 30Hz; and so on. During refresh frames, the brightness of each display refresh rate is basically the same, and all are emitting light normally. However, during hold frames, the brightness changes as the number of hold frames increases; generally, the more hold frames, the lower the brightness. Therefore, the greater the difference in display refresh rates between two adjacent display areas, the greater the difference in brightness. In related technologies, voltage compensation settings are applied to the data voltage of the low refresh rate area to adjust the brightness of two adjacent display areas to be more consistent. This solves the overall area brightness problem, but there will still be obvious dividing lines between adjacent display areas, which is a display issue (module display malfunction (no display, abnormal screen distortion, etc.)). Summary of the Invention

[0005] The main objective of this disclosure is to provide a display adjustment method, a display adjustment module, and a display device, which solves the problem in related technologies that when the display refresh rates of adjacent display areas are different, there will be obvious dividing lines between adjacent display areas.

[0006] In one aspect, embodiments of this disclosure provide a display adjustment method applied to a display panel, the display panel including a plurality of display areas, wherein pixel circuits are disposed within the display areas; the display adjustment method includes:

[0007] When the pixel circuit in the first predetermined display area is in the holding phase and the pixel circuit in the second predetermined display area is in the refresh phase, and the pixel circuit in the first predetermined display area is scanned to the pixel circuit in the second predetermined display area, during at least two display periods within the adjacent M-frame display time, the positions of the pixel circuit controlling the start of operation are different at the boundary between the first and second predetermined display areas; and / or,

[0008] When the pixel circuit in the first predetermined display area is in the refresh phase and the pixel circuit in the second predetermined display area is in the hold phase, and the pixel circuit in the first predetermined display area is scanned to the pixel circuit in the second predetermined display area, the pixel circuit controlling the start and stop of operation is in different positions at the boundary between the first and second predetermined display areas during at least two display periods included in the adjacent M frame display time.

[0009] M is a positive integer, greater than 1 and less than or equal to 5; the first predetermined display area and the second predetermined display area are adjacent.

[0010] In at least one embodiment of this disclosure, the display panel includes a scan signal generation module and a multi-row, multi-column pixel circuit. The scan signal generation module includes a multi-level scan signal generation circuit. The scan signal generation circuit is electrically connected to a corresponding row pixel circuit and is used to provide a corresponding scan signal to the corresponding row pixel circuit. The plurality of display areas are arranged sequentially along the column direction. The display adjustment method includes:

[0011] When the pixel circuit in the first predetermined display area is in the holding phase and the pixel circuit in the second predetermined display area is in the refresh phase, and the pixel circuit in the first predetermined display area is scanned to the pixel circuit in the second predetermined display area, during at least two display periods within the adjacent M-frame display time, the row numbers of the pixel circuits controlling the start of operation are different when scanning to the boundary between the first and second predetermined display areas; and / or,

[0012] When the pixel circuit in the first predetermined display area is in the refresh phase and the pixel circuit in the second predetermined display area is in the hold phase, and the pixel circuit in the first predetermined display area is scanned to the pixel circuit in the second predetermined display area, the number of rows of the pixel circuit that controls the start of stopping operation is different when the pixel circuit is scanned to the boundary between the first and second predetermined display areas during at least two display periods of adjacent M frame display time.

[0013] The display adjustment method described in at least one embodiment of this disclosure includes:

[0014] When the pixel circuit in the first predetermined display area is in the holding phase and the pixel circuit in the second predetermined display area is in the refresh phase, and the pixel circuit in the first predetermined display area is scanned to the pixel circuit in the second predetermined display area, during at least two adjacent M-frame display times, when the pixel circuit controlling the start of operation reaches the boundary between the first and second predetermined display areas, the difference in the row number of the pixel circuit is less than or equal to p rows; and / or,

[0015] When the pixel circuit in the first predetermined display area is in the refresh phase and the pixel circuit in the second predetermined display area is in the hold phase, and the pixel circuit in the first predetermined display area is scanned to the pixel circuit in the second predetermined display area, during at least two display periods included in the adjacent M frame display time, when the pixel circuit that controls the start of stopping operation is located at the boundary between the first and second predetermined display areas, the difference in the number of rows of the pixel circuit is less than or equal to p rows.

[0016] p is less than or equal to 24, and p is a positive integer.

[0017] In at least one embodiment of this disclosure, the display panel further includes an enable signal line electrically connected to the multi-level scan signal generation circuit. When the enable signal line provides a valid enable signal, the scan signal generation circuit can provide a valid scan signal to the corresponding row pixel circuit within a corresponding time period; when the enable signal line provides an invalid enable signal, the scan signal generation circuit provides an invalid scan signal to the corresponding row pixel circuit; the boundary line between the first predetermined display area and the second predetermined display area is the r-th row; r is a positive integer.

[0018] In at least one embodiment of this disclosure, the display refresh rate of the first predetermined display area is less than the display refresh rate of the second predetermined display area;

[0019] When the pixel circuit in the first predetermined display area is in the holding phase and the pixel circuit in the second predetermined display area is in the refresh phase, and the pixel circuit in the first predetermined display area is scanned to the pixel circuit in the second predetermined display area, each adjacent N frames constitute a time group; the display adjustment method includes:

[0020] Within a set of time periods, at least in two adjacent frame times, at different line scan times, the enable signal line begins to provide a valid enable signal.

[0021] In at least one embodiment of this disclosure, the display refresh rate of the first predetermined display area is less than the display refresh rate of the second predetermined display area;

[0022] When the pixel circuit in the first predetermined display area is in the holding phase and the pixel circuit in the second predetermined display area is in the refresh phase, and the pixel circuit in the first predetermined display area is scanned to the pixel circuit in the second predetermined display area, each adjacent N frames constitute a time group; the display adjustment method includes:

[0023] Within a set of time periods, in two adjacent frame times, at different line scan times, the enable signal line begins to provide a valid enable signal.

[0024] In at least one embodiment of this disclosure, the display adjustment method includes: at the x×n-(n-1)th frame time, during the rth line scan time, the enable signal line begins to provide a valid enable signal; at the x×nmth frame time, during the ry(m)th line scan time, the enable signal line begins to provide a valid enable signal, wherein n, r, and x are positive integers, m is a positive integer less than n-1, and y(m) is a positive integer corresponding to m; or,

[0025] The display adjustment method includes: at the x×n-(n-1) frame time, during the r-th line scan time, the enable signal line begins to provide a valid enable signal; at the x×n-(2p-1) frame time, during the ry(2p-1)-th line scan time, the enable signal line begins to provide a valid enable signal; at the x×n-2p frame time, during the r+y(2p)-th line scan time, the enable signal line begins to provide a valid enable signal; wherein, n, r, p, and x are positive integers, 2p is less than n-1, y(2p-1) is a positive integer corresponding to 2p-1, and y(2p) is a positive integer corresponding to 2p; or...

[0026] The display adjustment method includes: at the x×n-(n-1) frame time, during the r-th row scan time, the enable signal line begins to provide a valid enable signal; at the x×n-(2p-1) frame time, during the r+y(2p-1)-th row scan time, the enable signal line begins to provide a valid enable signal; at the x×n-2p frame time, during the ry(2p)-th row scan time, the enable signal line begins to provide a valid enable signal; wherein, n, r, p, and x are positive integers, 2p is less than n-1, y(2p-1) is a positive integer corresponding to 2p-1, and y(2p) is a positive integer corresponding to 2p.

[0027] In at least one embodiment of this disclosure, the display refresh rate of the first predetermined display area is greater than the display refresh rate of the second predetermined display area; when the pixel circuit in the first predetermined display area is in the refresh phase and the pixel circuit in the second predetermined display area is in the hold phase, and the pixel circuit in the first predetermined display area is scanned to the pixel circuit in the second predetermined display area, each adjacent N frames constitute a set of time; the display adjustment method includes:

[0028] Within a set of time periods, at least in two partially adjacent frame times, at different line scan times, the enable signal line begins to provide an invalid enable signal.

[0029] In at least one embodiment of this disclosure, when the pixel circuit in the first predetermined display area is in the refresh phase and the pixel circuit in the second predetermined display area is in the hold phase, each adjacent N frames constitute a set of time; the display adjustment method includes:

[0030] Within a set of time intervals, in two adjacent frame intervals, at different line scan intervals, the enable signal line begins to provide an invalid enable signal.

[0031] In at least one embodiment of this disclosure, the display adjustment method includes: at the x×n-(n-1)th frame time, during the rth line scan time, the enable signal line begins to provide an invalid enable signal; at the x×nmth frame time, during the ry(m)th line scan time, the enable signal line begins to provide an invalid enable signal, wherein n, r, and x are positive integers, m is a positive integer less than n-1, and y(m) is a positive integer corresponding to m; or,

[0032] The display adjustment method includes: at the x×n-(n-1) frame time, during the r-th line scan time, the enable signal line begins to provide an invalid enable signal; at the x×n-(2p-1) frame time, during the ry(2p-1)-th line scan time, the enable signal line begins to provide an invalid enable signal; at the x×n-2p frame time, during the r+y(2p)-th line scan time, the enable signal line begins to provide an invalid enable signal; where n, r, p, and x are positive integers, 2p is less than n-1, y(2p-1) is a positive integer corresponding to 2p-1, and y(2p) is a positive integer corresponding to 2p; or,

[0033] The display adjustment method includes: at the x×n-(n-1) frame time, during the r-th row scan time, the enable signal line begins to provide an invalid enable signal; at the x×n-(2p-1) frame time, during the r+y(2p-1)-th row scan time, the enable signal line begins to provide an invalid enable signal; at the x×n-2p frame time, during the ry(2p)-th row scan time, the enable signal line begins to provide an invalid enable signal; wherein, n, r, p, and x are positive integers, 2p is less than n-1, y(2p-1) is a positive integer corresponding to 2p-1, and y(2p) is a positive integer corresponding to 2p.

[0034] In at least one embodiment of this disclosure, the display panel includes a scan signal generation module and a multi-row, multi-column pixel circuit. The scan signal generation module includes a multi-level scan signal generation circuit. The scan signal generation circuit is electrically connected to a corresponding column pixel circuit and is used to provide a corresponding scan signal to the corresponding column pixel circuit. The plurality of display areas are arranged sequentially along the row direction. The display adjustment method includes:

[0035] When the pixel circuit in the first predetermined display area is in the holding phase and the pixel circuit in the second predetermined display area is in the refresh phase, and the pixel circuit in the first predetermined display area is scanned to the pixel circuit in the second predetermined display area, during at least two adjacent M-frame display times, when the pixel circuit controlling the start of operation is located at the boundary between the first and second predetermined display areas, the column numbers of the pixel circuits are different; and / or,

[0036] When the pixel circuit in the first predetermined display area is in the refresh phase and the pixel circuit in the second predetermined display area is in the hold phase, and the pixel circuit in the first predetermined display area is scanned to the pixel circuit in the second predetermined display area, the number of columns of the pixel circuit that controls the start of stopping operation is different when the pixel circuit is scanned to the boundary between the first and second predetermined display areas during at least two display periods included in the adjacent M frame display time.

[0037] The display adjustment method described in at least one embodiment of this disclosure includes:

[0038] When a pixel circuit in a predetermined display area is in a holding phase and a pixel circuit in a second predetermined display area is in a refresh phase, and the pixel circuit in the first predetermined display area is scanned to the pixel circuit in the second predetermined display area, during at least two adjacent M-frame display times, when the pixel circuit scanning reaches the boundary between the first and second predetermined display areas, the difference in column numbers between the pixel circuits that control the start of operation is less than or equal to p columns; and / or,

[0039] When the pixel circuit in a predetermined display area is in the refresh phase and the pixel circuit in the second predetermined display area is in the hold phase, and the pixel circuit in the first predetermined display area is scanned to the pixel circuit in the second predetermined display area, during at least two display periods included in the adjacent M frame display time, when the pixel circuit that controls the start of stopping operation is located at the boundary between the first and second predetermined display areas, the difference in the number of columns is less than or equal to p columns.

[0040] p is less than or equal to 24, and p is a positive integer.

[0041] In at least one embodiment of this disclosure, the display panel further includes an enable signal line electrically connected to the multi-level scan signal generation circuit. When the enable signal line provides a valid enable signal, the scan signal generation circuit can provide a valid scan signal to the corresponding column pixel circuit within a corresponding time period. When the enable signal line provides an invalid enable signal, the scan signal generation circuit provides an invalid scan signal to the corresponding column pixel circuit. The boundary column between the first predetermined display area and the second predetermined display area is the h-th column, where h is a positive integer.

[0042] In at least one embodiment of this disclosure, the display refresh rate of the first predetermined display area is less than the display refresh rate of the second predetermined display area; when the pixel circuit in the first predetermined display area is in a holding phase and the pixel circuit in the second predetermined display area is in a refresh phase, and the pixel circuit in the first predetermined display area is scanned to the pixel circuit in the second predetermined display area, each adjacent N frames constitute a set of time; the display adjustment method includes:

[0043] Within a set of time periods, at least in two adjacent frames, during different column scan times, the enable signal line begins to provide a valid enable signal.

[0044] In at least one embodiment of this disclosure, the display refresh rate of the first predetermined display area is less than the display refresh rate of the second predetermined display area; when the pixel circuit in the first predetermined display area is in a holding phase and the pixel circuit in the second predetermined display area is in a refresh phase, and the pixel circuit in the first predetermined display area is scanned to the pixel circuit in the second predetermined display area, each adjacent N frames constitute a set of time; the display adjustment method includes:

[0045] Within a set of time periods, in two adjacent frame times, at different column scan times, the enable signal line begins to provide a valid enable signal.

[0046] In at least one embodiment of this disclosure, the display adjustment method includes: at the x×n-(n-1)th frame time, during the h-th column scan time, the enable signal line begins to provide a valid enable signal; at the x×nmth frame time, during the hy(m)-th column scan time, the enable signal line begins to provide a valid enable signal, wherein n, h, and x are positive integers, m is a positive integer less than n-1, and y(m) is a positive integer corresponding to m; or,

[0047] The display adjustment method includes: at the x×n-(n-1) frame time, during the h-th column scan time, the enable signal line begins to provide a valid enable signal; at the x×n-(2p-1) frame time, during the hy(2p-1)-th column scan time, the enable signal line begins to provide a valid enable signal; at the x×n-2p frame time, during the h+y(2p)-th column scan time, the enable signal line begins to provide a valid enable signal; wherein, n, h, p, and x are positive integers, 2p is less than n-1, y(2p-1) is a positive integer corresponding to 2p-1, and y(2p) is a positive integer corresponding to 2p; or...

[0048] The display adjustment method includes: at the x×n-(n-1) frame time, during the h-th column scan time, the enable signal line begins to provide a valid enable signal; at the x×n-(2p-1) frame time, during the h+y(2p-1)-th column scan time, the enable signal line begins to provide a valid enable signal; at the x×n-2p frame time, during the hy(2p)-th column scan time, the enable signal line begins to provide a valid enable signal; wherein, n, h, p, and x are positive integers, 2p is less than n-1, y(2p-1) is a positive integer corresponding to 2p-1, and y(2p) is a positive integer corresponding to 2p.

[0049] In at least one embodiment of this disclosure, the display refresh rate of the first predetermined display area is greater than the display refresh rate of the second predetermined display area; when the pixel circuit in the first predetermined display area is in the refresh phase and the pixel circuit in the second predetermined display area is in the hold phase, and the pixel circuit in the first predetermined display area is scanned to the pixel circuit in the second predetermined display area, each adjacent N frames constitute a set of time; the display adjustment method includes:

[0050] Within a set of time periods, at least in two adjacent frames, during different column scan times, the enable signal line begins to provide an invalid enable signal.

[0051] In at least one embodiment of this disclosure, when the pixel circuit in the first predetermined display area is in the refresh phase and the pixel circuit in the second predetermined display area is in the hold phase, and the pixel circuit in the first predetermined display area is scanned to the pixel circuit in the second predetermined display area, each adjacent N frames constitute a set of time; the display adjustment method includes:

[0052] Within a set of time periods, in two adjacent frame times, at different column scan times, the enable signal line begins to provide an invalid enable signal.

[0053] In at least one embodiment of this disclosure, the display adjustment method includes: at the x×n-(n-1)th frame time, during the h-th column scan time, the enable signal line begins to provide an invalid enable signal; at the x×nmth frame time, during the hy(m)-th column scan time, the enable signal line begins to provide an invalid enable signal, wherein n, h, and x are positive integers, m is a positive integer less than n-1, and y(m) is a positive integer corresponding to m; or,

[0054] The display adjustment method includes: at the x×n-(n-1) frame time, during the h-th column scan time, the enable signal line begins to provide an invalid enable signal; at the x×n-(2p-1) frame time, during the hy(2p-1)-th column scan time, the enable signal line begins to provide an invalid enable signal; at the x×n-2p frame time, during the h+y(2p)-th column scan time, the enable signal line begins to provide an invalid enable signal; wherein n, h, p, and x are positive integers, 2p is less than n-1, y(2p-1) is a positive integer corresponding to 2p-1, and y(2p) is a positive integer corresponding to 2p; or,

[0055] The display adjustment method includes: at the x×n-(n-1) frame time, during the h-th column scan time, the enable signal line begins to provide an invalid enable signal; at the x×n-(2p-1) frame time, during the h+y(2p-1)-th column scan time, the enable signal line begins to provide an invalid enable signal; at the x×n-2p frame time, during the hy(2p)-th column scan time, the enable signal line begins to provide an invalid enable signal; wherein, n, h, p, and x are positive integers, 2p is less than n-1, y(2p-1) is a positive integer corresponding to 2p-1, and y(2p) is a positive integer corresponding to 2p.

[0056] In a second aspect, embodiments of this disclosure provide a display adjustment module applied to a display panel, the display panel including multiple display areas, adjacent display areas having different display refresh rates, and pixel circuits disposed within the display areas; the display adjustment module includes a control circuit;

[0057] The control circuit is configured to, when the pixel circuit in the first predetermined display area is in the holding phase and the pixel circuit in the second predetermined display area is in the refresh phase, and when the pixel circuit in the first predetermined display area scans to the pixel circuit in the second predetermined display area, control the position of the pixel circuit that starts working to be different at the boundary between the first predetermined display area and the second predetermined display area within at least two display frames included in the adjacent M frame display time, and / or, the control circuit is configured to, when the pixel circuit in the first predetermined display area is in the refresh phase and the pixel circuit in the second predetermined display area is in the holding phase, and when the pixel circuit in the first predetermined display area scans to the pixel circuit in the second predetermined display area, control the position of the pixel circuit that starts stopping working to be different at the boundary between the first predetermined display area and the second predetermined display area within at least two display frames included in the adjacent M frame display time;

[0058] M is a positive integer, greater than 1 and less than or equal to 5; the first predetermined display area and the second predetermined display area are adjacent.

[0059] In at least one embodiment of this disclosure, the display panel includes a scan signal generation module and a multi-row, multi-column pixel circuit. The scan signal generation module includes a multi-level scan signal generation circuit. The scan signal generation circuit is electrically connected to a corresponding row pixel circuit and is used to provide a corresponding scan signal to the corresponding row pixel circuit. The plurality of display areas are arranged sequentially along the column direction.

[0060] The control circuit is configured to, when a pixel circuit in a first predetermined display area is in a holding phase and a pixel circuit in a second predetermined display area is in a refresh phase, and when the pixel circuit in the first predetermined display area scans to the pixel circuit in the second predetermined display area, control the row number of the pixel circuit that starts working to be different within at least two display frames included in the adjacent M-frame display time, when scanning to the boundary between the first and second predetermined display areas; and / or, the control circuit is configured to, when a pixel circuit in the first predetermined display area is in a refresh phase and a pixel circuit in the second predetermined display area is in a holding phase, and when the pixel circuit in the first predetermined display area scans to the pixel circuit in the second predetermined display area, control the row number of the pixel circuit that starts working to be different within at least two display frames included in the adjacent M-frame display time, when scanning to the boundary between the first and second predetermined display areas.

[0061] In at least one embodiment of this disclosure, the control circuit is configured to, when a pixel circuit in a first predetermined display area is in a holding phase and a pixel circuit in a second predetermined display area is in a refresh phase, and when the pixel circuit in the first predetermined display area scans to the pixel circuit in the second predetermined display area, control the pixel circuit that starts working to have a row number difference of less than or equal to p rows when scanning to the boundary between the first and second predetermined display areas within at least two adjacent M-frame display times; and / or the control circuit is configured to, when a pixel circuit in the first predetermined display area is in a refresh phase and a pixel circuit in the second predetermined display area is in a holding phase, and when the pixel circuit in the first predetermined display area scans to the pixel circuit in the second predetermined display area, control the pixel circuit that starts stopping working to have a row number difference of less than or equal to p rows when scanning to the boundary between the first and second predetermined display areas within at least two adjacent M-frame display times;

[0062] p is less than or equal to 24, and p is a positive integer.

[0063] In at least one embodiment of this disclosure, the display panel includes a scan signal generation module and a multi-row, multi-column pixel circuit. The scan signal generation module includes a multi-level scan signal generation circuit. The scan signal generation circuit is electrically connected to a corresponding column pixel circuit and is used to provide a corresponding scan signal to the corresponding column pixel circuit. The plurality of display areas are arranged sequentially along the row direction.

[0064] The control circuit is configured to, when a pixel circuit in a first predetermined display area is in a holding phase and a pixel circuit in a second predetermined display area is in a refresh phase, and when the pixel circuit in the first predetermined display area scans to the pixel circuit in the second predetermined display area, control the number of columns of the pixel circuits that start working to be different within at least two display frames included in the adjacent M-frame display time, when scanning to the boundary between the first and second predetermined display areas; and / or, the control circuit is configured to, when a pixel circuit in the first predetermined display area is in a refresh phase and a pixel circuit in the second predetermined display area is in a holding phase, and when the pixel circuit in the first predetermined display area scans to the pixel circuit in the second predetermined display area, control the number of columns of the pixel circuits that start working to be different within at least two display frames included in the adjacent M-frame display time, when scanning to the boundary between the first and second predetermined display areas.

[0065] In at least one embodiment of this disclosure, the control circuit is configured to, when a pixel circuit in a predetermined display area is in a holding phase and a pixel circuit in a second predetermined display area is in a refresh phase, and when the pixel circuit in the first predetermined display area scans to the pixel circuit in the second predetermined display area, control the difference in column number of the pixel circuit that starts working to be less than or equal to p columns during at least two display periods included in adjacent M frame display periods, when scanning to the boundary between the first and second predetermined display areas; and / or, the control circuit is configured to, when a pixel circuit in a predetermined display area is in a refresh phase and a pixel circuit in a second predetermined display area is in a holding phase, and when the pixel circuit in the first predetermined display area scans to the pixel circuit in the second predetermined display area, control the difference in column number of the pixel circuit that starts to stop working to be less than or equal to p columns during at least two display periods included in adjacent M frame display periods, when scanning to the boundary between the first and second predetermined display areas;

[0066] p is less than or equal to 24, and p is a positive integer.

[0067] In a third aspect, embodiments of this disclosure provide a display device including the display adjustment module described above.

[0068] In this embodiment, when the pixel circuit in the first predetermined display area is in the holding phase and the pixel circuit in the second predetermined display area is in the refresh phase, the positions of the pixel circuits that start to access the data voltage signal are different at the boundary between the first and second predetermined display areas during at least two display frames included in the adjacent M-frame display time. When the pixel circuit in the first predetermined display area is in the refresh phase and the pixel circuit in the second predetermined display area is in the holding phase, the positions of the pixel circuits that start to stop accessing the data voltage signal are different at the boundary between the first and second predetermined display areas during at least two display frames included in the adjacent M-frame display time. This allows for dynamic adjustment of the boundary positions of the high refresh rate area and the low refresh rate area, thereby achieving a blurred boundary effect. This can be well applied to AMOLED local frequency conversion modules to improve poor display performance. Attached Figure Description

[0069] Figure 1A is a schematic diagram of the connection relationship between the first driving module and the control transistor electrically connected thereto in at least one embodiment of the present disclosure.

[0070] Figure 1B is a schematic diagram of the display area division of the display panel in at least one embodiment of the present disclosure;

[0071] Figure 2 is a waveform diagram of the enable signal provided by the enable signal line EN at different frame times during operation of at least one embodiment of the display panel shown in Figure 1B.

[0072] Figure 3 is a schematic diagram of the display area division of the display panel in at least one embodiment of this disclosure;

[0073] Figure 4 is a waveform diagram of the enable signal provided by the enable signal line EN at different frame times during operation of at least one embodiment of the display panel shown in Figure 2.

[0074] Figure 5 is a schematic diagram of the connection relationship between the scan signal generation module and the pixel circuit in at least one embodiment of this disclosure;

[0075] Figure 6 is a schematic diagram of the display area division of the display panel in at least one embodiment of the present disclosure;

[0076] Figure 7 is a waveform diagram of the enable signal provided by the enable signal line EN at different frame times during operation of at least one embodiment of the display panel shown in Figure 6.

[0077] Figure 8 is a schematic diagram of the connection relationship between the scan signal generation module and the pixel circuit in at least one embodiment of this disclosure. Detailed Implementation

[0078] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this disclosure.

[0079] The display adjustment method described in this embodiment is applied to a display panel, the display panel including multiple display areas, and pixel circuits are disposed in the display areas; the display adjustment method includes:

[0080] When the pixel circuit in the first predetermined display area is in the holding phase and the pixel circuit in the second predetermined display area is in the refresh phase, and the pixel circuit in the first predetermined display area is scanned to the pixel circuit in the second predetermined display area, during at least two display periods within the adjacent M-frame display time, the positions of the pixel circuit controlling the start of operation are different at the boundary between the first and second predetermined display areas; and / or,

[0081] When the pixel circuit in the first predetermined display area is in the refresh phase and the pixel circuit in the second predetermined display area is in the hold phase, and the pixel circuit in the first predetermined display area is scanned to the pixel circuit in the second predetermined display area, the pixel circuit controlling the start and stop of operation is in different positions at the boundary between the first and second predetermined display areas during at least two display periods included in the adjacent M frame display time.

[0082] M is a positive integer, greater than 1 and less than or equal to 5; the first predetermined display area and the second predetermined display area are adjacent.

[0083] In at least one embodiment of this disclosure, the display refresh rates of two adjacent display areas in the display panel are different.

[0084] In related AMOLED (Active Matrix Organic Light Emitting Diode) module applications, to achieve the ultimate and superior intelligent display, the overall fixed-frequency display of the module is no longer sufficient. Consequently, multi-zone displays with different frequencies have emerged. In related technologies, when the same display module uses different refresh rates in different display areas, each display frequency corresponds to the same set of Gamma data. For example, using 120Hz Gamma data as a baseline, other display refresh rates (60Hz / 30Hz) will share this set of Gamma data. Currently, the various frequencies of split-screen displays are also implemented based on 120Hz using frame skipping. That is, at 120Hz, refreshing one frame and holding it for one frame is 60Hz; refreshing one frame and holding it for three frames is 30Hz; and so on. During refresh frames, the brightness of each display refresh rate is basically consistent, with all displaying normal illumination. However, during hold frames, the brightness changes as the number of hold frames increases; generally, the more hold frames, the lower the brightness. Therefore, the greater the difference in refresh rates between two adjacent display areas, the greater the brightness difference. Related technologies use voltage compensation settings on the data voltage of the low refresh rate area to adjust the brightness of two adjacent display areas to be more consistent. This solves the overall area brightness problem, but a noticeable dividing line still exists between adjacent display areas, which is considered a display issue.

[0085] Based on the above problems, in the display adjustment method described in the embodiments of this disclosure, when the pixel circuit in the first predetermined display area is in the holding phase and the pixel circuit in the second predetermined display area is in the refresh phase, the positions of the pixel circuits that start working are different at the boundary between the first and second predetermined display areas during at least two display times included in the adjacent M frame display times; when the pixel circuit in the first predetermined display area is in the refresh phase and the pixel circuit in the second predetermined display area is in the holding phase, the positions of the pixel circuits that start and stop working are different at the boundary between the first and second predetermined display areas during at least two display times included in the adjacent M frame display times; so as to dynamically adjust the boundary positions of the high refresh area and the low refresh area, thereby achieving the effect of blurring the boundary, which can be well applied to AMOLED local frequency conversion modules to improve the poor display effect.

[0086] In at least one embodiment of this disclosure, pixel circuit operation can refer to the pixel circuit writing the data voltage it receives into the gate of the driving transistor in the pixel circuit.

[0087] The pixel circuit stopping operation can refer to the pixel circuit ceasing to write the data voltage it receives into the gate of the driving transistor.

[0088] In at least one embodiment of this disclosure, the pixel circuit may include a driving transistor, a data writing transistor, and a compensation control transistor;

[0089] The data writing transistor can be electrically connected to the write control terminal, the data line and the first pole of the driving transistor respectively, and is used to connect the data voltage provided by the data line to the first pole of the driving transistor under the control of the write control signal provided by the write control terminal;

[0090] The compensation control transistor can be electrically connected to the scanning terminal, the gate of the driving transistor, and the second electrode of the driving transistor, respectively. Under the control of the scanning signal provided by the scanning terminal, it controls the connection between the gate of the driving transistor and the second electrode of the driving transistor, so as to control whether the data voltage can be written to the gate of the driving transistor under the control of the scanning signal, thereby controlling whether to perform display refresh.

[0091] In the display adjustment method described in this embodiment, when the pixel circuit in the first predetermined display area is in a holding phase and the pixel circuit in the second predetermined display area is in a refresh phase, and the data voltage accessed by the pixel circuit in the first predetermined display area is not written to the gate of the driving transistor in the pixel circuit, so as to maintain the display; when the data voltage accessed by the pixel circuit in the first predetermined display area is scanned to the pixel circuit in the second predetermined display area, the pixel circuit in the second predetermined display area begins to write the accessed data voltage to the gate of the driving transistor, so as to refresh the display; and / or,

[0092] When the pixel circuit in the first predetermined display area is in the holding phase and the pixel circuit in the second predetermined display area is in the refresh phase, and the pixel circuit in the first predetermined display area scans to the pixel circuit in the second predetermined display area, the pixel circuit in the first predetermined display area writes the incoming data voltage to the gate of the driving transistor to perform display refresh; when the pixel circuit in the first predetermined display area scans to the pixel circuit in the second predetermined display area, the pixel circuit in the second predetermined display area stops writing the incoming data voltage to the gate of the driving transistor to perform display holding.

[0093] In at least one embodiment of this disclosure, the display panel includes a scan signal generation module and a multi-row, multi-column pixel circuit. The scan signal generation module includes a multi-level scan signal generation circuit. The scan signal generation circuit is electrically connected to a corresponding row pixel circuit and is used to provide a corresponding scan signal to the corresponding row pixel circuit. The plurality of display areas are arranged sequentially along the column direction. The display adjustment method includes:

[0094] When the pixel circuit in the first predetermined display area is in the holding phase and the pixel circuit in the second predetermined display area is in the refresh phase, and the pixel circuit in the first predetermined display area is scanned to the pixel circuit in the second predetermined display area, during at least two display periods within the adjacent M-frame display time, the row numbers of the pixel circuits controlling the start of operation are different when scanning to the boundary between the first and second predetermined display areas; and / or,

[0095] When the pixel circuit in the first predetermined display area is in the refresh phase and the pixel circuit in the second predetermined display area is in the hold phase, and the pixel circuit in the first predetermined display area is scanned to the pixel circuit in the second predetermined display area, the number of rows of the pixel circuit that controls the start of stopping operation is different when the pixel circuit is scanned to the boundary between the first and second predetermined display areas during at least two display periods of adjacent M frame display time.

[0096] In specific implementation, when the multiple display areas are arranged sequentially along the column direction, when the pixel circuit in the first predetermined display area is in the holding phase and the pixel circuit in the second predetermined display area is in the refresh phase, during at least two display periods included in the adjacent M frame display time, when scanning to the boundary between the first and second predetermined display areas, the row number of the pixel circuit that starts working is controlled to be different, so as to dynamically adjust the boundary position of the high refresh area and the low refresh area, thereby achieving the effect of blurring the boundary.

[0097] When the pixel circuit in the first predetermined display area is in the refresh phase and the pixel circuit in the second predetermined display area is in the hold phase, and the pixel circuit in the first predetermined display area is scanned to the pixel circuit in the second predetermined display area, during at least two display periods in the adjacent M-frame display time, when the pixel circuit that starts to stop working is located at the boundary between the first and second predetermined display areas, the number of rows of the pixel circuit is different, so as to dynamically adjust the boundary position of the high refresh area and the low refresh area, thereby achieving the effect of blurring the boundary.

[0098] The display adjustment method described in at least one embodiment of this disclosure includes:

[0099] When the pixel circuit in the first predetermined display area is in the holding phase and the pixel circuit in the second predetermined display area is in the refresh phase, and the pixel circuit in the first predetermined display area is scanned to the pixel circuit in the second predetermined display area, during at least two adjacent M-frame display times, when the pixel circuit controlling the start of operation reaches the boundary between the first and second predetermined display areas, the difference in the row number of the pixel circuit is less than or equal to p rows; and / or,

[0100] When the pixel circuit in the first predetermined display area is in the refresh phase and the pixel circuit in the second predetermined display area is in the hold phase, and the pixel circuit in the first predetermined display area is scanned to the pixel circuit in the second predetermined display area, during at least two display periods included in the adjacent M frame display time, when the pixel circuit that controls the start of stopping operation is located at the boundary between the first and second predetermined display areas, the difference in the number of rows of the pixel circuit is less than or equal to p rows.

[0101] p is less than or equal to 24, and p is a positive integer.

[0102] In specific implementation, when the pixel circuit in the first predetermined display area is in the holding phase and the pixel circuit in the second predetermined display area is in the refresh phase, during at least two display periods included in the adjacent M frame display time, when scanning to the boundary between the first and second predetermined display areas, the row number difference of the pixel circuit that starts working is less than or equal to p rows, so as to avoid the boundary rows between adjacent display areas being too far apart during the adjacent M frame display time, which would affect the display effect;

[0103] When the pixel circuit in the first predetermined display area is in the refresh phase and the pixel circuit in the second predetermined display area is in the hold phase, during at least two display periods within the adjacent M-frame display time, when scanning to the boundary between the first and second predetermined display areas, the number of rows where the pixel circuit that starts to stop working is located differs by less than or equal to p rows, so as to prevent the boundary rows between adjacent display areas from being too far apart during the adjacent M-frame display time, thus affecting the display effect.

[0104] In at least one embodiment of this disclosure, the display panel further includes an enable signal line electrically connected to the multi-level scan signal generation circuit. When the enable signal line provides a valid enable signal, the scan signal generation circuit can provide a valid scan signal to the corresponding row pixel circuit within a corresponding time period; when the enable signal line provides an invalid enable signal, the scan signal generation circuit provides an invalid scan signal to the corresponding row pixel circuit; the boundary line between the first predetermined display area and the second predetermined display area is the r-th row; r is a positive integer.

[0105] In a specific implementation, the display panel may include an enable signal line. The enable signal provided by the enable signal line can control whether the scan signal generation circuit can provide a valid enable signal. When the enable signal line provides a valid enable signal, the scan signal generation circuit can provide a valid scan signal to the corresponding row pixel circuit within a corresponding time period, so that the corresponding row pixel circuit can write the input data voltage into the gate of the driving transistor in the pixel circuit for data voltage refresh. When the enable signal line provides an invalid enable signal, the scan signal generation circuit provides an invalid scan signal to the corresponding row pixel circuit, so that the corresponding row pixel circuit stops writing the input data voltage into the gate of the driving transistor, does not perform data voltage refresh, and maintains the data voltage. Optionally, the valid enable signal can be a high voltage signal, and the invalid enable signal can be a low voltage signal; or, the valid enable signal can be a low voltage signal, and the invalid enable signal can be a high voltage signal.

[0106] As shown in Figure 1A, the first drive module includes a multi-stage drive circuit;

[0107] The circuit labeled GA1 is the first-stage drive circuit, GA2 is the second-stage drive circuit, GA3 is the third-stage drive circuit, and GA4 is the fourth-stage drive circuit; the circuit labeled GAN-1 is the (N-1)th-stage drive circuit, and the circuit labeled GAN is the Nth-stage drive circuit; N is an integer greater than 6.

[0108] The output of GA1 is electrically connected to the first row pixel circuit P1 through the first control transistor T1;

[0109] The output of GA2 is electrically connected to the second row pixel circuit P2 through the second control transistor T2;

[0110] The output of GA3 is electrically connected to the third row pixel circuit P3 through the third control transistor T3;

[0111] The output of GA4 is electrically connected to the fourth row pixel circuit P4 through the fourth control transistor T4;

[0112] The output of GAN-1 is electrically connected to the pixel circuit PN-1 of the (N-1)th row through the (N-1)th control transistor TN-1.

[0113] The output of GAN is electrically connected to the Nth row pixel circuit PN through the Nth control transistor TN.

[0114] The gates of T1, T2, T3, T4, TN-1, and TN are all electrically connected to the enable signal line EN.

[0115] T1, T2, T3, T4, TN-1, and TN are all n-type transistors;

[0116] When EN provides a high voltage signal, T1, T2, T3, T4, TN-1, and TN are turned on. The first row scan signal provided by GA1 is transmitted to P1 through T1, the second row scan signal provided by GA2 is transmitted to P2 through T2, the third row scan signal provided by GA3 is transmitted to P3 through T3, the fourth row scan signal provided by GA4 is transmitted to P4 through T4, the (N-1)th row scan signal provided by GAN-1 is transmitted to PN-1 through TN-1, and the Nth row scan signal provided by GAN is transmitted to PN through TN.

[0117] When EN provides a low voltage signal, T1, T2, T3, T4, TN-1 and TN are turned off, and the scan signals provided by each stage of the drive circuit cannot be transmitted to the corresponding row pixel circuit through the corresponding control transistor.

[0118] In at least one embodiment of this disclosure, the display refresh rate of the first predetermined display area is less than the display refresh rate of the second predetermined display area; when the pixel circuit in the first predetermined display area is in a holding phase and the pixel circuit in the second predetermined display area is in a refresh phase, and the pixel circuit in the first predetermined display area is scanned to the pixel circuit in the second predetermined display area, each adjacent N frames constitute a set of time; the display adjustment method includes:

[0119] Within a set of time periods, at least in two adjacent frame times, at different line scan times, the enable signal line is controlled to begin providing a valid enable signal.

[0120] In specific implementation, the display refresh frequency of the first predetermined display area can be lower than that of the second predetermined display area. When the pixel circuit in the first predetermined display area is in the holding phase and the pixel circuit in the second predetermined display area is in the refresh phase, and the pixel circuit in the first predetermined display area is scanned to the pixel circuit in the second predetermined display area, within a set of time (each adjacent N frame time can be a set of time), within at least two adjacent frame times, at different line scan times, the enable signal line begins to provide an effective enable signal to blur the boundary, improve the strength and size of the dividing line under different brightness, until the effect of weakening the dividing line is achieved.

[0121] In at least one embodiment of this disclosure, the display refresh rate of the first predetermined display area is less than the display refresh rate of the second predetermined display area;

[0122] When the pixel circuit in the first predetermined display area is in the holding phase and the pixel circuit in the second predetermined display area is in the refresh phase, and the pixel circuit in the first predetermined display area is scanned to the pixel circuit in the second predetermined display area, each adjacent N frames constitute a time group; the display adjustment method includes:

[0123] Within a set of time periods, in two adjacent frame times, at different line scan times, the enable signal line begins to provide a valid enable signal.

[0124] In specific implementation, the display refresh rate of the first predetermined display area can be lower than the display refresh rate of the second predetermined display area. When the pixel circuit in the first predetermined display area is in the holding phase and the pixel circuit in the second predetermined display area is in the refresh phase, and the pixel circuit in the first predetermined display area is scanned to the pixel circuit in the second predetermined display area, within a set of time (each adjacent N frame time can be a set of time), in two adjacent frame times, at different line scan times, the enable signal line begins to provide an effective enable signal to blur the boundary, improve the strength and size of the dividing line under different brightness, until the effect of weakening the dividing line is achieved.

[0125] In at least one embodiment of this disclosure, the display adjustment method includes: at the x×n-(n-1)th frame time, during the rth line scan time, the enable signal line begins to provide a valid enable signal; at the x×nmth frame time, during the ry(m)th line scan time, the enable signal line begins to provide a valid enable signal, wherein n, r, and x are positive integers, m is a positive integer less than n-1, and y(m) is a positive integer corresponding to m; or,

[0126] The display adjustment method includes: at the x×n-(n-1) frame time, during the r-th line scan time, the enable signal line begins to provide a valid enable signal; at the x×n-(2p-1) frame time, during the ry(2p-1)-th line scan time, the enable signal line begins to provide a valid enable signal; at the x×n-2p frame time, during the r+y(2p)-th line scan time, the enable signal line begins to provide a valid enable signal; wherein, n, r, p, and x are positive integers, 2p is less than n-1, y(2p-1) is a positive integer corresponding to 2p-1, and y(2p) is a positive integer corresponding to 2p; or...

[0127] The display adjustment method includes: at the x×n-(n-1) frame time, during the r-th row scan time, the enable signal line begins to provide a valid enable signal; at the x×n-(2p-1) frame time, during the r+y(2p-1)-th row scan time, the enable signal line begins to provide a valid enable signal; at the x×n-2p frame time, during the ry(2p)-th row scan time, the enable signal line begins to provide a valid enable signal; wherein, n, r, p, and x are positive integers, 2p is less than or equal to n-1, y(2p-1) is a positive integer corresponding to 2p-1, and y(2p) is a positive integer corresponding to 2p.

[0128] When 2p-1 equals 1, y(1) is the positive integer corresponding to 1; when 2p equals 2, y(2) is the positive integer corresponding to 2; when 2p-1 equals 3, y(3) is the positive integer corresponding to 3; and when 2p equals 4, y(4) is the positive integer corresponding to 4.

[0129] Optionally, x can be equal to 8, 16, 5, 10, or other positive integers. In at least one embodiment of this disclosure, x equal to 5 is used as an example for specific illustration. In practical applications, the value of x can be adjusted according to the display product.

[0130] In at least one embodiment of this disclosure, the display adjustment method includes: at frame 5n-4, during the scan time of line r, the enable signal line begins to provide a valid enable signal; at frame 5n-3, during the scan time of line ra, the enable signal line begins to provide a valid enable signal; at frame 5n-2, during the scan time of line rb, the enable signal line begins to provide a valid enable signal; at frame 5n-1, during the scan time of line rc, the enable signal line begins to provide a valid enable signal; and at frame 5n, during the scan time of line r, the enable signal line begins to provide a valid enable signal; n, r, a, b, and c are all positive integers; or...

[0131] The display adjustment method includes: at frame 5n-4, during the scan time of line r, the enable signal line begins to provide a valid enable signal; at frame 5n-3, during the scan time of line r+a, the enable signal line begins to provide a valid enable signal; at frame 5n-2, during the scan time of line rb, the enable signal line begins to provide a valid enable signal; at frame 5n-1, during the scan time of line r+c, the enable signal line begins to provide a valid enable signal; and at frame 5n, during the scan time of line rd, the enable signal line begins to provide a valid enable signal; n, r, a, b, c, and d are all positive integers; or...

[0132] The display adjustment method includes: at frame 5n-4, during the scan time of line r, the enable signal line begins to provide a valid enable signal; at frame 5n-3, during the scan time of line ra, the enable signal line begins to provide a valid enable signal; at frame 5n-2, during the scan time of line r+b, the enable signal line begins to provide a valid enable signal; at frame 5n-1, during the scan time of line rc, the enable signal line begins to provide a valid enable signal; and at frame 5n, during the scan time of line r+d, the enable signal line begins to provide a valid enable signal; where n, r, a, b, c, and d are all positive integers.

[0133] In at least one embodiment of this disclosure, the display refresh rate of the first predetermined display area is greater than the display refresh rate of the second predetermined display area; when the pixel circuit in the first predetermined display area is in the refresh phase and the pixel circuit in the second predetermined display area is in the hold phase, and the pixel circuit in the first predetermined display area is scanned to the pixel circuit in the second predetermined display area, each adjacent N frames constitute a set of time; the display adjustment method includes:

[0134] Within a set of time periods, at least in two partially adjacent frame times, at different line scan times, the enable signal line begins to provide an invalid enable signal.

[0135] In specific implementation, when the display refresh frequency of the first predetermined display area is greater than that of the second predetermined display area, when the pixel circuit in the first predetermined display area is in the refresh phase and the pixel circuit in the second predetermined display area is in the hold phase, and the pixel circuit in the first predetermined display area is scanned to the pixel circuit in the second predetermined display area, within a set of time (each adjacent N frames is one frame time), in at least two adjacent frames, at different line scan times, the enable signal line begins to provide an invalid enable signal to blur the boundary, improve the strength and size of the dividing line under different brightness, until the effect of weakening the dividing line is achieved.

[0136] Optionally, the display refresh rate of the first predetermined display area is greater than the display refresh rate of the second predetermined display area; when the pixel circuit in the first predetermined display area is in the refresh phase and the pixel circuit in the second predetermined display area is in the hold phase, and the pixel circuit in the first predetermined display area is scanned to the pixel circuit in the second predetermined display area, each adjacent N frames constitute a set of time; the display adjustment method includes:

[0137] Within a set of time intervals, in two adjacent frame intervals, at different line scan intervals, the enable signal line begins to provide an invalid enable signal.

[0138] In specific implementation, when the display refresh frequency of the first predetermined display area is greater than that of the second predetermined display area, when the pixel circuit in the first predetermined display area is in the refresh phase and the pixel circuit in the second predetermined display area is in the hold phase, and the pixel circuit in the first predetermined display area scans to the pixel circuit in the second predetermined display area, within a set of time (each adjacent N frames is one frame time), in two adjacent frame times, at different line scan times, the enable signal line begins to provide an invalid enable signal to blur the boundary, improve the strength and size of the dividing line under different brightness, until the effect of weakening the dividing line is achieved.

[0139] In at least one embodiment of this disclosure, the display adjustment method includes: at the x×n-(n-1)th frame time, during the rth line scan time, the enable signal line begins to provide an invalid enable signal; at the x×nmth frame time, during the ry(m)th line scan time, the enable signal line begins to provide an invalid enable signal, wherein n, r, and x are positive integers, m is a positive integer less than n-1, and y(m) is a positive integer corresponding to m; or,

[0140] The display adjustment method includes: at the x×n-(n-1) frame time, during the r-th line scan time, the enable signal line begins to provide an invalid enable signal; at the x×n-(2p-1) frame time, during the ry(2p-1)-th line scan time, the enable signal line begins to provide an invalid enable signal; at the x×n-2p frame time, during the r+y(2p)-th line scan time, the enable signal line begins to provide an invalid enable signal; where n, r, p, and x are positive integers, 2p is less than n-1, y(2p-1) is a positive integer corresponding to 2p-1, and y(2p) is a positive integer corresponding to 2p; or,

[0141] The display adjustment method includes: at the x×n-(n-1) frame time, during the r-th row scan time, the enable signal line begins to provide an invalid enable signal; at the x×n-(2p-1) frame time, during the r+y(2p-1)-th row scan time, the enable signal line begins to provide an invalid enable signal; at the x×n-2p frame time, during the ry(2p)-th row scan time, the enable signal line begins to provide an invalid enable signal; wherein, n, r, p, and x are positive integers, 2p is less than n-1, y(2p-1) is a positive integer corresponding to 2p-1, and y(2p) is a positive integer corresponding to 2p.

[0142] In at least one embodiment of this disclosure, the display adjustment method includes: at frame 5n-4, during the scan time of line r, the enable signal line begins to provide an invalid enable signal; at frame 5n-3, during the scan time of line ra, the enable signal line begins to provide an invalid enable signal; at frame 5n-2, during the scan time of line rb, the enable signal line begins to provide an invalid enable signal; at frame 5n-1, during the scan time of line rc, the enable signal line begins to provide an invalid enable signal; at frame 5n, during the scan time of line r, the enable signal line begins to provide an invalid enable signal; n, r, a, b, and c are all positive integers; or...

[0143] The display adjustment method includes: at frame 5n-4, during the scan time of line r, the enable signal line begins to provide an invalid enable signal; at frame 5n-3, during the scan time of line r+a, the enable signal line begins to provide an invalid enable signal; at frame 5n-2, during the scan time of line rb, the enable signal line begins to provide an invalid enable signal; at frame 5n-1, during the scan time of line r+c, the enable signal line begins to provide an invalid enable signal; and at frame 5n, during the scan time of line rd, the enable signal line begins to provide an invalid enable signal; where n, r, a, b, c, and d are all positive integers; or...

[0144] The display adjustment method includes: at frame 5n-4, during the scan time of line r, the enable signal line begins to provide an invalid enable signal; at frame 5n-3, during the scan time of line ra, the enable signal line begins to provide an invalid enable signal; at frame 5n-2, during the scan time of line r+b, the enable signal line begins to provide an invalid enable signal; at frame 5n-1, during the scan time of line rc, the enable signal line begins to provide an invalid enable signal; at frame 5n, during the scan time of line r+d, the enable signal line begins to provide an invalid enable signal; n, r, a, b, c, and d are all positive integers.

[0145] As shown in Figure 1B, the display panel includes a first display area A1, a second display area A2, and a third display area A3 arranged sequentially along the column direction;

[0146] The display refresh rate of the first display area A1 is 10Hz, the display refresh rate of the second display area A2 is 120Hz, and the display refresh rate of the third display area A3 is 10Hz.

[0147] Figure 2 is a waveform diagram of the enable signal provided by the enable signal line EN at different frame times during operation of at least one embodiment of the display panel shown in Figure 1B.

[0148] The dividing line between the first display area A1 and the second display area A2 is the r-th row; r is a positive integer; as shown in Figure 2.

[0149] At frame time F1, during the scan time of line r, the enable signal line EN begins to provide a high voltage signal; at frame time F2, during the scan time of line ra, the enable signal line EN begins to provide a high voltage signal; at frame time F3, during the scan time of line rb, the enable signal line EN begins to provide a high voltage signal; at frame time F4, during the scan time of line rc, the enable signal line EN begins to provide a high voltage signal; at frame time F5, during the scan time of line r, the enable signal line EN begins to provide a high voltage signal; a, b, and c are positive integers;

[0150] At frame time F1, from the first line scan time to the (r-1)th line scan time, EN provides a low voltage signal; at frame time F2, from the first line scan time to the (ra-1)th line scan time, EN provides a low voltage signal; at frame time F3, from the first line scan time to the (rb-1)th line scan time, EN provides a low voltage signal; at frame time F4, from the first line scan time to the (rc-1)th line scan time, EN provides a low voltage signal; at frame time F5, from the first line scan time to the (r-1)th line scan time, EN provides a low voltage signal.

[0151] At frame time F5N-4 (5N-4), during the scan time of line r, the enable signal line EN begins to provide a high voltage signal; at frame time F5N-3 (5N-3), during the scan time of line ra, the enable signal line EN begins to provide a high voltage signal; at frame time F5N-2 (5N-2), during the scan time of line rb, the enable signal line EN begins to provide a high voltage signal; at frame time F5N-1 (5N-1), during the scan time of line rc, the enable signal line EN begins to provide a high voltage signal; at frame time F5N (5N), during the scan time of line r, the enable signal line EN begins to provide a high voltage signal.

[0152] At frame time F5N-4 (5N-4), from the first line scan time to the (r-1)th line scan time, EN provides a low voltage signal. At frame time F5N-3 (5N-3), from the first line scan time to the (ra-1)th line scan time, EN provides a low voltage signal. At frame time F5N-2 (5N-2), from the first line scan time to the (rb-1)th line scan time, EN provides a low voltage signal. At frame time F5N-1 (5N-1), from the first line scan time to the (rc-1)th line scan time, EN provides a low voltage signal. At frame time F5N (5N), from the first line scan time to the (r-1)th line scan time, EN provides a low voltage signal. Wherein, N is an integer greater than 1.

[0153] In at least one embodiment shown in Figure 2, the valid voltage signal is a high voltage signal, and the invalid voltage signal is a low voltage signal.

[0154] In at least one embodiment shown in Figure 2, a frame can last for 8.33 ms.

[0155] In at least one embodiment shown in Figure 2, a can be equal to 8, b can be equal to 16, and c can be equal to 8, but is not limited thereto. In actual operation, the values ​​of a, b, and c can be flexibly selected. For example, a can be equal to 8, b can be equal to 6, and c can be equal to 10. At least two of a, b, and c can be different from each other, or a, b, and c can be different from each other. Furthermore, the difference between two of a, b, and c is not significant. For example, the difference between two of a, b, and c does not exceed 24, but is not limited thereto.

[0156] In at least one embodiment of this disclosure, the relationship between a, b, and c can be adjusted arbitrarily, and the number of frames per cycle can also be adjusted. It can be a cycle of 5 frames, 10 frames, or 20 frames. The ratio of a, b, and c is different in different display scenarios, which can improve the strength and size of the boundary line under different brightness, until the effect of weakening the boundary line is achieved.

[0157] As shown in Figure 2, the dividing row between the second display area A2 and the third display area A3 can be the s-th row, where s is a positive integer;

[0158] At frame time F1, during the s-th row scan time, the enable signal line EN begins to provide a low voltage signal; at frame time F2, during the s+a-th row scan time, the enable signal line EN begins to provide a low voltage signal; at frame time F3, during the s+b-th row scan time, the enable signal line EN begins to provide a low voltage signal; at frame time F4, during the s+c-th row scan time, the enable signal line EN begins to provide a low voltage signal; at frame time F5, during the s-th row scan time, the enable signal line EN begins to provide a low voltage signal.

[0159] At frame time F1, from the scan time of line s to the scan time of line s-1, EN provides a high voltage signal; at frame time F2, from the scan time of line sa to the scan time of line s+a-1, EN provides a high voltage signal; at frame time F3, from the scan time of line sb to the scan time of line s+b-1, EN provides a high voltage signal; at frame time F4, from the scan time of line sc to the scan time of line s+c-1, EN provides a high voltage signal; at frame time F5, from the scan time of line s to the scan time of line s-1, EN provides a high voltage signal.

[0160] At frame time F5N-4 (5N-4), during the s-th row scan time, the enable signal line EN begins to provide a low voltage signal. At frame time F5N-3 (5N-3), during the s+a-th row scan time, the enable signal line EN begins to provide a low voltage signal. At frame time F5N-2 (5N-2), during the s+b-th row scan time, the enable signal line EN begins to provide a low voltage signal. At frame time F5N-1 (5N-1), during the s+c-th row scan time, the enable signal line EN begins to provide a low voltage signal. At frame time F5N (5N), during the s-th row scan time, the enable signal line EN begins to provide a low voltage signal.

[0161] At frame time F5N-4 (5N-4), during the scan time from line s to line s-1, EN provides a high voltage signal. At frame time F5N-3 (5N-3), during the scan time from line sa to line s+a-1, EN provides a high voltage signal. At frame time F5N-2 (5N-2), during the scan time from line sb to line s+b-1, EN provides a high voltage signal. At frame time F5N-1 (5N-1), during the scan time from line sc to line s+c-1, EN provides a high voltage signal. At frame time F5N (5N), during the scan time from line s to line s-1, EN provides a high voltage signal; where N is an integer greater than 1.

[0162] As shown in Figure 3, the display panel includes a first display area A1 and a second display area A2 arranged sequentially along the column direction;

[0163] The refresh rate of the first display area A1 is 120Hz, and the refresh rate of the second display area A2 is 10Hz.

[0164] Figure 4 is a waveform diagram of the enable signal provided by the enable signal line EN at different frame times during operation of at least one embodiment of the display panel shown in Figure 2.

[0165] In practical implementation, in a common application scenario, namely, a two-part display, the embodiments of this disclosure can greatly improve the optimization of existing dividing lines.

[0166] As shown in Figure 4, the dividing line between the first display area A1 and the second display area A2 is the r-th row, where r is a positive integer;

[0167] At frame time F1, during the scan time of line r, the enable signal line EN begins to provide a low voltage signal; at frame time F2, during the scan time of line ra, the enable signal line EN begins to provide a low voltage signal; at frame time F3, during the scan time of line r+b, the enable signal line EN begins to provide a low voltage signal; at frame time F4, during the scan time of line rc, the enable signal line EN begins to provide a low voltage signal; at frame time F5, during the scan time of line r+d, the enable signal line EN begins to provide a low voltage signal; a, b, c, and d are positive integers;

[0168] In the first frame time F1, from the first row scan time to the (r-1)th row scan time, the enable signal line EN provides a high voltage signal; in the second frame time F2, from the first row scan time to the (ra-1)th row scan time, the enable signal line EN provides a high voltage signal; in the third frame time F3, from the first row scan time to the (r+b-1)th row scan time, the enable signal line EN provides a high voltage signal; in the fourth frame time F4, from the first row scan time to the (rc-1)th row scan time, the enable signal line EN provides a high voltage signal; in the fifth frame time F5, from the first row scan time to the (r+d-1)th row scan time, the enable signal line EN provides a high voltage signal; N is an integer greater than 1;

[0169] At frame time F5N-4 (5N-4), during the scan time of line r, the enable signal line EN begins to provide a low voltage signal; at frame time F5N-3 (5N-3), during the scan time of line ra, the enable signal line EN begins to provide a low voltage signal; at frame time F5N-2 (5N-2), during the scan time of line r+b, the enable signal line EN begins to provide a low voltage signal; at frame time F5N-1 (5N-1), during the scan time of line rc, the enable signal line EN begins to provide a low voltage signal; at frame time F5N (5N), during the scan time of line r+d, the enable signal line EN begins to provide a low voltage signal; N is an integer greater than 1;

[0170] At frame time F5N-4 (5N-4), from the first line scan time to the (r-1)th line scan time, the enable signal line EN provides a high voltage signal; at frame time F5N-3 (5N-3), from the first line scan time to the (ra-1)th line scan time, the enable signal line EN provides a high voltage signal; at frame time F5N-2 (5N-2), from the first line scan time to the (r+b-1)th line scan time, the enable signal line EN provides a high voltage signal; at frame time F5N-1 (5N-1), from the first line scan time to the (rc-1)th line scan time, the enable signal line EN provides a high voltage signal; at frame time F5N (5N), from the first line scan time to the (r+d-1)th line scan time, the enable signal line EN provides a high voltage signal.

[0171] In at least one embodiment shown in Figure 4, a and c can be equal to 4, and b and d can be equal to 8, but are not limited thereto.

[0172] In at least one embodiment shown in Figure 4, a, b, c, and d may be equal; or, at least two of a, b, c, and d may be unequal; or, a, b, c, and d may be unequal.

[0173] In at least one embodiment of this disclosure, a, b, c, and d can be adjusted for visual effects, and the cycle period can be 5, 10, 15, or 20.

[0174] In at least one embodiment of this disclosure, the display panel includes a scan signal generation module and a multi-row, multi-column pixel circuit. The scan signal generation module includes a multi-level scan signal generation circuit. The scan signal generation circuit is electrically connected to a corresponding row pixel circuit and is used to provide a corresponding scan signal to the corresponding row pixel circuit. The plurality of display areas are arranged sequentially along the column direction.

[0175] As shown in Figure 5, GA1 is the first-stage scanning signal generation circuit included in the scanning signal generation module, GA2 is the second-stage scanning signal generation circuit included in the scanning signal generation module, GAM-1 is the (M-1)th stage scanning signal generation circuit included in the scanning signal generation module, and GAM is the Mth stage scanning signal generation circuit included in the scanning signal generation module, where M is an integer greater than 1.

[0176] GA1 is electrically connected to the first row pixel circuit H1 and is used to provide the first row scanning signal to the first row pixel circuit H1.

[0177] GA2 is electrically connected to the second row pixel circuit H2 and is used to provide the second row scanning signal to the second row pixel circuit H2.

[0178] GAM-1 is electrically connected to the (M-1)th row pixel circuit HM-1 and is used to provide the (M-1)th row scanning signal to the (M-1)th row pixel circuit HM-1.

[0179] GAM is electrically connected to the M-row pixel circuit HM and is used to provide the M-row scanning signal to the M-row pixel circuit HM.

[0180] In at least one embodiment of this disclosure, the display panel includes a scan signal generation module and a multi-row, multi-column pixel circuit. The scan signal generation module includes a multi-level scan signal generation circuit. The scan signal generation circuit is electrically connected to a corresponding column pixel circuit and is used to provide a corresponding scan signal to the corresponding column pixel circuit. The plurality of display areas are arranged sequentially along the row direction. The display adjustment method includes:

[0181] When the pixel circuit in the first predetermined display area is in the holding phase and the pixel circuit in the second predetermined display area is in the refresh phase, and the pixel circuit in the first predetermined display area is scanned to the pixel circuit in the second predetermined display area, during at least two adjacent M-frame display times, when the pixel circuit controlling the start of operation is located at the boundary between the first and second predetermined display areas, the column numbers of the pixel circuits are different; and / or,

[0182] When the pixel circuit in the first predetermined display area is in the refresh phase and the pixel circuit in the second predetermined display area is in the hold phase, and the pixel circuit in the first predetermined display area is scanned to the pixel circuit in the second predetermined display area, the number of columns of the pixel circuit that controls the start of stopping operation is different when the pixel circuit is scanned to the boundary between the first and second predetermined display areas during at least two display periods included in the adjacent M frame display time.

[0183] In a practical implementation, multiple display areas can be arranged sequentially along the row direction in the display panel;

[0184] When the pixel circuit in the first predetermined display area is in the holding phase and the pixel circuit in the second predetermined display area is in the refresh phase, during at least two display periods including the adjacent M frame display time, when scanning to the boundary between the first and second predetermined display areas, the number of columns of the pixel circuit that starts working is controlled to be different, so as to achieve the purpose of blurring the boundary, improve the strength and size of the boundary line under different brightness, and until the effect of weakening the boundary line is achieved.

[0185] When the pixel circuit in the first predetermined display area is in the refresh phase and the pixel circuit in the second predetermined display area is in the hold phase, during at least two display periods including the adjacent M frames, when scanning to the boundary between the first and second predetermined display areas, the number of columns of the pixel circuit that starts to stop working is different, so as to achieve the purpose of blurring the boundary, improving the strength and size of the boundary line under different brightness, until the effect of weakening the boundary line is achieved.

[0186] In at least one embodiment of this disclosure, when a pixel circuit in a predetermined display area is in a holding phase and a pixel circuit in a second predetermined display area is in a refresh phase, and the pixel circuit in the first predetermined display area is scanned to the pixel circuit in the second predetermined display area, during at least two adjacent M-frame display times, when the pixel circuit scans to the boundary between the first and second predetermined display areas, the difference in column numbers between the pixel circuits that control the start of operation is less than or equal to p columns; and / or,

[0187] When the pixel circuit in a predetermined display area is in the refresh phase and the pixel circuit in the second predetermined display area is in the hold phase, and the pixel circuit in the first predetermined display area is scanned to the pixel circuit in the second predetermined display area, during at least two display periods included in the adjacent M frame display time, when the pixel circuit that controls the start of stopping operation is located at the boundary between the first and second predetermined display areas, the difference in the number of columns is less than or equal to p columns.

[0188] p is less than or equal to 24, and p is a positive integer.

[0189] In specific implementation, when the pixel circuit in a predetermined display area is in the holding phase and the pixel circuit in a second predetermined display area is in the refresh phase, during at least two display periods included in the adjacent M frame display time, when scanning to the boundary between the first and second predetermined display areas, the difference in the number of columns of the pixel circuit that starts working is less than or equal to p rows, so as to prevent the boundary columns between adjacent display areas from being too far apart during the adjacent M frame display time, which would affect the display effect;

[0190] When the pixel circuit in a predetermined display area is in the refresh phase and the pixel circuit in a second predetermined display area is in the hold phase, during at least two display periods within the adjacent M-frame display time, when scanning to the boundary between the first and second predetermined display areas, the difference in the number of columns of the pixel circuit that controls the start of stopping operation is less than or equal to p columns, so as to prevent the boundary columns between adjacent display areas from being too far apart during the adjacent M-frame display time, which would affect the display effect.

[0191] In at least one embodiment of this disclosure, the display panel further includes an enable signal line electrically connected to the multi-level scan signal generation circuit. When the enable signal line provides a valid enable signal, the scan signal generation circuit can provide a valid scan signal to the corresponding column pixel circuit within a corresponding time period. When the enable signal line provides an invalid enable signal, the scan signal generation circuit provides an invalid scan signal to the corresponding column pixel circuit. The boundary column between the first predetermined display area and the second predetermined display area is the h-th column, where h is a positive integer.

[0192] In a specific implementation, the display panel may further include an enable signal line. The enable signal provided by the enable signal line can control whether the scan signal generation circuit can provide a valid enable signal. When the enable signal line provides a valid enable signal, the scan signal generation circuit can provide a valid scan signal to the corresponding column pixel circuit during a corresponding time period, so that the corresponding column pixel circuit can write the incoming data voltage into the gate of the driving transistor in the pixel circuit for display refresh. When the enable signal line provides an invalid enable signal, the scan signal generation circuit provides an invalid scan signal to the corresponding column pixel circuit, so that the corresponding column pixel circuit stops writing the incoming data voltage into the gate of the driving transistor for display maintenance.

[0193] In at least one embodiment of this disclosure, the display refresh rate of the first predetermined display area is less than the display refresh rate of the second predetermined display area; when the pixel circuit in the first predetermined display area is in a holding phase and the pixel circuit in the second predetermined display area is in a refresh phase, and the pixel circuit in the first predetermined display area is scanned to the pixel circuit in the second predetermined display area, each adjacent N frames constitute a set of time; the display adjustment method includes:

[0194] Within a set of time periods, at least in two adjacent frames, during different column scan times, the enable signal line begins to provide a valid enable signal.

[0195] In specific implementation, the display refresh rate of the first predetermined display area can be lower than the display refresh rate of the second predetermined display area. When the pixel circuit in the first predetermined display area is in the holding phase and the pixel circuit in the second predetermined display area is in the refresh phase, and the pixel circuit in the first predetermined display area is scanned to the pixel circuit in the second predetermined display area, within a set of time (each adjacent N frames is a set of time), within at least two adjacent frames, during different column scan times, the enable signal line begins to provide an effective enable signal to blur the boundary, improve the strength and size of the dividing line under different brightness, until the effect of weakening the dividing line is achieved.

[0196] Optionally, when the pixel circuit in the first predetermined display area is in the holding phase and the pixel circuit in the second predetermined display area is in the refresh phase, and the pixel circuit in the first predetermined display area is scanned to the pixel circuit in the second predetermined display area, each adjacent N frames constitute a time group; the display adjustment method includes:

[0197] Within a set of time periods, in two adjacent frame times, at different column scan times, the enable signal line begins to provide a valid enable signal.

[0198] In specific implementation, the display refresh rate of the first predetermined display area can be lower than the display refresh rate of the second predetermined display area. When the pixel circuit in the first predetermined display area is in the holding phase and the pixel circuit in the second predetermined display area is in the refresh phase, and the pixel circuit in the first predetermined display area is scanned to the pixel circuit in the second predetermined display area, within a set of time (each adjacent N frames is a set of time), in two adjacent frames, during different column scan times, the enable signal line begins to provide an effective enable signal to blur the boundary, improve the strength and size of the dividing line under different brightness, until the effect of weakening the dividing line is achieved.

[0199] In at least one embodiment of this disclosure, the display adjustment method includes: at the x×n-(n-1)th frame time, during the h-th column scan time, the enable signal line begins to provide a valid enable signal; at the x×nmth frame time, during the hy(m)-th column scan time, the enable signal line begins to provide a valid enable signal, wherein n, h, and x are positive integers, m is a positive integer less than n-1, and y(m) is a positive integer corresponding to m; or,

[0200] The display adjustment method includes: at the x×n-(n-1) frame time, during the h-th column scan time, the enable signal line begins to provide a valid enable signal; at the x×n-(2p-1) frame time, during the hy(2p-1)-th column scan time, the enable signal line begins to provide a valid enable signal; at the x×n-2p frame time, during the h+y(2p)-th column scan time, the enable signal line begins to provide a valid enable signal; wherein, n, h, p, and x are positive integers, 2p is less than n-1, y(2p-1) is a positive integer corresponding to 2p-1, and y(2p) is a positive integer corresponding to 2p; or...

[0201] The display adjustment method includes: at the x×n-(n-1) frame time, during the h-th column scan time, the enable signal line begins to provide a valid enable signal; at the x×n-(2p-1) frame time, during the h+y(2p-1)-th column scan time, the enable signal line begins to provide a valid enable signal; at the x×n-2p frame time, during the hy(2p)-th column scan time, the enable signal line begins to provide a valid enable signal; wherein, n, h, p, and x are positive integers, 2p is less than n-1, y(2p-1) is a positive integer corresponding to 2p-1, and y(2p) is a positive integer corresponding to 2p.

[0202] In at least one embodiment of this disclosure, the display adjustment method includes: at frame 5n-4, during the scan time of column h, the enable signal line begins to provide a valid enable signal; at frame 5n-3, during the scan time of column ha, the enable signal line begins to provide a valid enable signal; at frame 5n-2, during the scan time of column hb, the enable signal line begins to provide a valid enable signal; at frame 5n-1, during the scan time of column hc, the enable signal line begins to provide a valid enable signal; and at frame 5n, during the scan time of column h, the enable signal line begins to provide a valid enable signal; n, h, a, b, and c are all positive integers; or...

[0203] The display adjustment method includes: at frame 5n-4, during the scan time of column h, the enable signal line begins to provide a valid enable signal; at frame 5n-3, during the scan time of column h+a, the enable signal line begins to provide a valid enable signal; at frame 5n-2, during the scan time of column hb, the enable signal line begins to provide a valid enable signal; at frame 5n-1, during the scan time of column h+c, the enable signal line begins to provide a valid enable signal; and at frame 5n, during the scan time of column hd, the enable signal line begins to provide a valid enable signal; where n, h, a, b, c, and d are all positive integers; or...

[0204] The display adjustment method includes: at frame 5n-4, during the scan time of column h, the enable signal line begins to provide a valid enable signal; at frame 5n-3, during the scan time of column ha, the enable signal line begins to provide a valid enable signal; at frame 5n-2, during the scan time of column h+b, the enable signal line begins to provide a valid enable signal; at frame 5n-1, during the scan time of column hc, the enable signal line begins to provide a valid enable signal; and at frame 5n, during the scan time of column h+d, the enable signal line begins to provide a valid enable signal; n, h, a, b, c, and d are all positive integers.

[0205] In at least one embodiment of this disclosure, the display refresh rate of the first predetermined display area is greater than the display refresh rate of the second predetermined display area; when the pixel circuit in the first predetermined display area is in the refresh phase and the pixel circuit in the second predetermined display area is in the hold phase, and the pixel circuit in the first predetermined display area is scanned to the pixel circuit in the second predetermined display area, each adjacent N frames constitute a set of time; the display adjustment method includes:

[0206] Within a set of time periods, at least in two adjacent frames, during different column scan times, the enable signal line begins to provide an invalid enable signal.

[0207] In specific implementation, the display refresh rate of the first predetermined display area can be greater than the display refresh rate of the second predetermined display area. When the pixel circuit in the first predetermined display area is in the refresh phase and the pixel circuit in the second predetermined display area is in the hold phase, and the pixel circuit in the first predetermined display area is scanned to the pixel circuit in the second predetermined display area, within a set of time (each adjacent N frames is a set of time), within at least two adjacent frames, during different column scan times, the enable signal line begins to provide an invalid enable signal, so as to blur the boundary, improve the strength and size of the dividing line under different brightness, until the effect of weakening the dividing line is achieved.

[0208] Optionally, when the pixel circuit in the first predetermined display area is in the refresh phase and the pixel circuit in the second predetermined display area is in the hold phase, and the pixel circuit in the first predetermined display area is scanned to the pixel circuit in the second predetermined display area, each adjacent N frames constitute a time group; the display adjustment method includes:

[0209] Within a set of time periods, in two adjacent frame times, at different column scan times, the enable signal line begins to provide an invalid enable signal.

[0210] In specific implementation, the display refresh rate of the first predetermined display area can be greater than the display refresh rate of the second predetermined display area. When the pixel circuit in the first predetermined display area is in the refresh phase and the pixel circuit in the second predetermined display area is in the hold phase, and the pixel circuit in the first predetermined display area is scanned to the pixel circuit in the second predetermined display area, within a set of time (each adjacent N frames is a set of time), in two adjacent frames, during different column scan times, the enable signal line begins to provide an invalid enable signal, so as to blur the boundary, improve the strength and size of the dividing line under different brightness, until the effect of weakening the dividing line is achieved.

[0211] In at least one embodiment of this disclosure, the display adjustment method includes: at the x×n-(n-1)th frame time, during the h-th column scan time, the enable signal line begins to provide an invalid enable signal; at the x×nmth frame time, during the hy(m)-th column scan time, the enable signal line begins to provide an invalid enable signal, wherein n, h, and x are positive integers, m is a positive integer less than n-1, and y(m) is a positive integer corresponding to m; or,

[0212] The display adjustment method includes: at the x×n-(n-1) frame time, during the h-th column scan time, the enable signal line begins to provide an invalid enable signal; at the x×n-(2p-1) frame time, during the hy(2p-1)-th column scan time, the enable signal line begins to provide an invalid enable signal; at the x×n-2p frame time, during the h+y(2p)-th column scan time, the enable signal line begins to provide an invalid enable signal; wherein n, h, p, and x are positive integers, 2p is less than n-1, y(2p-1) is a positive integer corresponding to 2p-1, and y(2p) is a positive integer corresponding to 2p; or,

[0213] The display adjustment method includes: at the x×n-(n-1) frame time, during the h-th column scan time, the enable signal line begins to provide an invalid enable signal; at the x×n-(2p-1) frame time, during the h+y(2p-1)-th column scan time, the enable signal line begins to provide an invalid enable signal; at the x×n-2p frame time, during the hy(2p)-th column scan time, the enable signal line begins to provide an invalid enable signal; wherein, n, h, p, and x are positive integers, 2p is less than n-1, y(2p-1) is a positive integer corresponding to 2p-1, and y(2p) is a positive integer corresponding to 2p.

[0214] In at least one embodiment of this disclosure, the display adjustment method includes: at frame 5n-4, during the scan time of column h, the enable signal line begins to provide an invalid enable signal; at frame 5n-3, during the scan time of column ha, the enable signal line begins to provide an invalid enable signal; at frame 5n-2, during the scan time of column hb, the enable signal line begins to provide an invalid enable signal; at frame 5n-1, during the scan time of column hc, the enable signal line begins to provide an invalid enable signal; at frame 5n, during the scan time of column h, the enable signal line begins to provide an invalid enable signal; n, h, a, b, and c are all positive integers; or...

[0215] The display adjustment method includes: at frame 5n-4, during the scan time of column h, the enable signal line begins to provide an invalid enable signal; at frame 5n-3, during the scan time of column h+a, the enable signal line begins to provide an invalid enable signal; at frame 5n-2, during the scan time of column hb, the enable signal line begins to provide an invalid enable signal; at frame 5n-1, during the scan time of column h+c, the enable signal line begins to provide an invalid enable signal; and at frame 5n, during the scan time of column h, the enable signal line begins to provide an invalid enable signal; where n, h, a, b, c, and d are all positive integers; or...

[0216] The display adjustment method includes: at frame 5n-4, during the scan time of column h, the enable signal line begins to provide an invalid enable signal; at frame 5n-3, during the scan time of column ha, the enable signal line begins to provide an invalid enable signal; at frame 5n-2, during the scan time of column h+b, the enable signal line begins to provide an invalid enable signal; at frame 5n-1, during the scan time of column hc, the enable signal line begins to provide an invalid enable signal; at frame 5n, during the scan time of column h+d, the enable signal line begins to provide an invalid enable signal; n, h, a, b, c, and d are all positive integers.

[0217] As shown in Figure 6, the display panel includes a first display area A1 and a second display area A2 arranged along the row direction;

[0218] The refresh rate of the first display area A1 is 10Hz, and the refresh rate of the second display area A2 is 120Hz.

[0219] As shown in Figure 7, the dividing line between the first display area A1 and the second display area A2 is the h-th column, where h is a positive integer;

[0220] In the first frame time F1, during the scan time of column h, the enable signal line EN begins to provide a high voltage signal; in the second frame time F2, during the scan time of column ha, the enable signal line EN begins to provide a high voltage signal; in the third frame time F3, during the scan time of column h+b, the enable signal line EN begins to provide a high voltage signal; in the fourth frame time F4, during the scan time of column hc, the enable signal line EN begins to provide a high voltage signal; in the fifth frame time F5, during the scan time of column h+d, the enable signal line EN begins to provide a high voltage signal; a, b, c, and d are positive integers;

[0221] In the first frame time F1, from the first column scan time to the (h-1)th column scan time, the enable signal line EN provides a low voltage signal; in the second frame time F2, from the first column scan time to the (ha-1)th column scan time, the enable signal line EN provides a low voltage signal; in the third frame time F3, from the first column scan time to the (h+b-1)th column scan time, the enable signal line EN provides a low voltage signal; in the fourth frame time F4, from the first column scan time to the (hc-1)th column scan time, the enable signal line EN provides a low voltage signal; in the fifth frame time F5, from the first column scan time to the (h+d-1)th column scan time, the enable signal line EN provides a low voltage signal; N is an integer greater than 1;

[0222] At frame time F5N-4 (5N-4), during the scan time of column h, the enable signal line EN begins to provide a high voltage signal; at frame time F5N-3 (5N-3), during the scan time of column ha, the enable signal line EN begins to provide a high voltage signal; at frame time F5N-2 (5N-2), during the scan time of column h+b, the enable signal line EN begins to provide a high voltage signal; at frame time F5N-1 (5N-1), during the scan time of column hc, the enable signal line EN begins to provide a high voltage signal; at frame time F5N (5N), during the scan time of column h+d, the enable signal line EN begins to provide a high voltage signal; N is an integer greater than 1;

[0223] At frame time F5N-4 (5N-4), from the first column scan time to the h-1th column scan time, the enable signal line EN provides a low voltage signal; at frame time F5N-3 (5N-3), from the first column scan time to the ha-1th column scan time, the enable signal line provides a low voltage signal; at frame time F5N-2 (5N-2), from the first column scan time to the h+b-1th column scan time, the enable signal line EN provides a low voltage signal; at frame time F5N-1 (5N-1), from the first column scan time to the hc-1th column scan time, the enable signal line EN provides a low voltage signal; at frame time F5N (5N), from the first column scan time to the h+d-1th column scan time, the enable signal line EN provides a low voltage signal.

[0224] In at least one embodiment shown in Figure 7, a and c can be equal to 4, and b and d can be equal to 8, but are not limited thereto.

[0225] In at least one embodiment shown in Figure 7, a, b, c, and d may be equal; or, at least two of a, b, c, and d may be unequal; or, a, b, c, and d may be unequal.

[0226] In at least one embodiment of this disclosure, a, b, c, and d can be adjusted for visual effects, and the cycle period can be 5, 10, 15, or 20.

[0227] In another type of column-direction refresh display mode with partial refresh, the display panel can be divided into two or more display areas in the horizontal direction and displayed at different frequencies. At least one embodiment of this disclosure can blur the partition boundaries, thereby weakening the boundaries to meet the visual effect specifications.

[0228] As shown in Figure 8, GA1 is the first-stage scanning signal generation circuit included in the scanning signal generation module, GA2 is the second-stage scanning signal generation circuit included in the scanning signal generation module, GAM-1 is the (M-1)th stage scanning signal generation circuit included in the scanning signal generation module, and GAM is the Mth stage scanning signal generation circuit included in the scanning signal generation module, where M is an integer greater than 1.

[0229] GA1 is electrically connected to the first column pixel circuit L1 and is used to provide the first column scanning signal to the first column pixel circuit L1.

[0230] GA2 is electrically connected to the second column pixel circuit L2 and is used to provide the second column scanning signal to the second column pixel circuit L2.

[0231] GAM-1 is electrically connected to the (M-1)th column pixel circuit LM-1 and is used to provide the (M-1)th column scanning signal to the (M-1)th column pixel circuit LM-1.

[0232] GAM is electrically connected to the M-th column pixel circuit LM and is used to provide the M-th column scan signal to the M-th column pixel circuit LM.

[0233] The display adjustment module described in this embodiment is applied to a display panel, which includes multiple display areas with different refresh rates for adjacent display areas. Pixel circuits are provided within the display areas. The display adjustment module includes a control circuit.

[0234] The control circuit is configured to, when a pixel circuit in a first predetermined display area is in a holding phase and a pixel circuit in a second predetermined display area is in a refresh phase, and the pixel circuit in the first predetermined display area is scanned to the pixel circuit in the second predetermined display area, control the position of the pixel circuit that starts working to be different within at least two display frames included in the adjacent M-frame display time, at the boundary between the first and second predetermined display areas; and / or, the control circuit is configured to, when a pixel circuit in the first predetermined display area is in a refresh phase and a pixel circuit in the second predetermined display area is in a holding phase, and the pixel circuit in the first predetermined display area is scanned to the pixel circuit in the second predetermined display area, control the position of the pixel circuit that starts stopping working to be different within at least two display frames included in the adjacent M-frame display time, at the boundary between the first and second predetermined display areas;

[0235] M is a positive integer, greater than 1 and less than or equal to 5; the first predetermined display area and the second predetermined display area are adjacent.

[0236] In the display adjustment module described in this embodiment, when the pixel circuit in the first predetermined display area is in the holding phase and the pixel circuit in the second predetermined display area is in the refresh phase, the positions of the pixel circuits that start working are different at the boundary between the first and second predetermined display areas during at least two display frames included in the adjacent M-frame display time; when the pixel circuit in the first predetermined display area is in the refresh phase and the pixel circuit in the second predetermined display area is in the holding phase, the positions of the pixel circuits that start and stop working are different at the boundary between the first and second predetermined display areas during at least two display frames included in the adjacent M-frame display time; this allows for dynamic adjustment of the boundary positions of the high refresh rate area and the low refresh rate area, thereby achieving a blurred boundary effect. This can be well applied to AMOLED local frequency conversion modules to improve poor display effects.

[0237] In at least one embodiment of this disclosure, the display panel includes a scan signal generation module and a multi-row, multi-column pixel circuit. The scan signal generation module includes a multi-level scan signal generation circuit. The scan signal generation circuit is electrically connected to a corresponding row pixel circuit and is used to provide a corresponding scan signal to the corresponding row pixel circuit. The plurality of display areas are arranged sequentially along the column direction.

[0238] The control circuit is configured to, when a pixel circuit in a first predetermined display area is in a holding phase and a pixel circuit in a second predetermined display area is in a refresh phase, and when the pixel circuit in the first predetermined display area scans to the pixel circuit in the second predetermined display area, control the row number of the pixel circuit that starts working to be different within at least two display frames included in the adjacent M-frame display time, when scanning to the boundary between the first and second predetermined display areas; and / or, the control circuit is configured to, when a pixel circuit in the first predetermined display area is in a refresh phase and a pixel circuit in the second predetermined display area is in a holding phase, and when the pixel circuit in the first predetermined display area scans to the pixel circuit in the second predetermined display area, control the row number of the pixel circuit that starts working to be different within at least two display frames included in the adjacent M-frame display time, when scanning to the boundary between the first and second predetermined display areas.

[0239] In at least one embodiment of this disclosure, the control circuit is configured to, when a pixel circuit in a first predetermined display area is in a holding phase and a pixel circuit in a second predetermined display area is in a refresh phase, and when the pixel circuit in the first predetermined display area scans to the pixel circuit in the second predetermined display area, control the pixel circuit that starts working to have a row number difference of less than or equal to p rows when scanning to the boundary between the first and second predetermined display areas within at least two display frames included in the adjacent M frame display time; and / or, the control circuit is configured to, when a pixel circuit in the first predetermined display area is in a refresh phase and a pixel circuit in the second predetermined display area is in a holding phase, and when the pixel circuit in the first predetermined display area scans to the pixel circuit in the second predetermined display area, control the pixel circuit that starts stopping working to have a row number difference of less than or equal to p rows when scanning to the boundary between the first and second predetermined display areas within at least two display frames included in the adjacent M frame display time;

[0240] p is less than or equal to 24, and p is a positive integer.

[0241] In at least one embodiment of this disclosure, the display panel includes a scan signal generation module and a multi-row, multi-column pixel circuit. The scan signal generation module includes a multi-level scan signal generation circuit. The scan signal generation circuit is electrically connected to a corresponding column pixel circuit and is used to provide a corresponding scan signal to the corresponding column pixel circuit. The plurality of display areas are arranged sequentially along the row direction.

[0242] The control circuit is configured to, when a pixel circuit in a first predetermined display area is in a holding phase and a pixel circuit in a second predetermined display area is in a refresh phase, and when the pixel circuit in the first predetermined display area scans to the pixel circuit in the second predetermined display area, control the number of columns of the pixel circuits that start working to be different within at least two display frames included in the adjacent M-frame display time, when scanning to the boundary between the first and second predetermined display areas; and / or, the control circuit is configured to, when a pixel circuit in the first predetermined display area is in a refresh phase and a pixel circuit in the second predetermined display area is in a holding phase, and when the pixel circuit in the first predetermined display area scans to the pixel circuit in the second predetermined display area, control the number of columns of the pixel circuits that start working to be different within at least two display frames included in the adjacent M-frame display time, when scanning to the boundary between the first and second predetermined display areas.

[0243] In at least one embodiment of this disclosure, the control circuit is configured to, when a pixel circuit in a predetermined display area is in a holding phase and a pixel circuit in a second predetermined display area is in a refresh phase, and when the pixel circuit in the first predetermined display area scans to the pixel circuit in the second predetermined display area, control the difference in column number of the pixel circuit that starts working to be less than or equal to p columns during at least two display periods included in adjacent M frame display periods, when scanning to the boundary between the first and second predetermined display areas; and / or, the control circuit is configured to, when a pixel circuit in a predetermined display area is in a refresh phase and a pixel circuit in a second predetermined display area is in a holding phase, and when the pixel circuit in the first predetermined display area scans to the pixel circuit in the second predetermined display area, control the difference in column number of the pixel circuit that starts to stop working to be less than or equal to p columns during at least two display periods included in adjacent M frame display periods, when scanning to the boundary between the first and second predetermined display areas;

[0244] p is less than or equal to 24, and p is a positive integer.

[0245] The display device described in this embodiment includes the display adjustment module described above.

[0246] The above description represents the preferred embodiments of this disclosure. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles described herein, and these improvements and modifications should also be considered within the scope of protection of this disclosure.

Claims

1. A display adjustment method applied to a display panel, the display panel including multiple display areas, wherein pixel circuits are disposed within the display areas; the display adjustment method includes: When the pixel circuit in the first predetermined display area is in the holding phase and the pixel circuit in the second predetermined display area is in the refresh phase, and the pixel circuit in the first predetermined display area is scanned to the pixel circuit in the second predetermined display area, during at least two display periods within the adjacent M-frame display time, the positions of the pixel circuit controlling the start of operation are different at the boundary between the first and second predetermined display areas; and / or, When the pixel circuit in the first predetermined display area is in the refresh phase and the pixel circuit in the second predetermined display area is in the hold phase, and the pixel circuit in the first predetermined display area is scanned to the pixel circuit in the second predetermined display area, the pixel circuit controlling the start and stop of operation is in different positions at the boundary between the first and second predetermined display areas during at least two display periods included in the adjacent M frame display time. M is a positive integer, greater than 1 and less than or equal to 5; the first predetermined display area and the second predetermined display area are adjacent.

2. The display adjustment method as described in claim 1, wherein, The display panel includes a scan signal generation module and a multi-row, multi-column pixel circuit. The scan signal generation module includes a multi-level scan signal generation circuit. The scan signal generation circuit is electrically connected to the corresponding row pixel circuit and is used to provide the corresponding row pixel circuit with a corresponding scan signal. The multiple display areas are arranged sequentially along the column direction. The display adjustment method includes: When the pixel circuit in the first predetermined display area is in the holding phase and the pixel circuit in the second predetermined display area is in the refresh phase, and the pixel circuit in the first predetermined display area is scanned to the pixel circuit in the second predetermined display area, during at least two display periods within the adjacent M-frame display time, the row numbers of the pixel circuits controlling the start of operation are different when scanning to the boundary between the first and second predetermined display areas; and / or, When the pixel circuit in the first predetermined display area is in the refresh phase and the pixel circuit in the second predetermined display area is in the hold phase, and the pixel circuit in the first predetermined display area is scanned to the pixel circuit in the second predetermined display area, the number of rows of the pixel circuit that controls the start of stopping operation is different when the pixel circuit is scanned to the boundary between the first and second predetermined display areas during at least two display periods of adjacent M frame display time.

3. The display adjustment method as described in claim 2, wherein, include: When the pixel circuit in the first predetermined display area is in the holding phase and the pixel circuit in the second predetermined display area is in the refresh phase, and the pixel circuit in the first predetermined display area is scanned to the pixel circuit in the second predetermined display area, during at least two adjacent M-frame display times, when the pixel circuit controlling the start of operation reaches the boundary between the first and second predetermined display areas, the difference in the row number of the pixel circuit is less than or equal to p rows; and / or, When the pixel circuit in the first predetermined display area is in the refresh phase and the pixel circuit in the second predetermined display area is in the hold phase, and the pixel circuit in the first predetermined display area is scanned to the pixel circuit in the second predetermined display area, during at least two display periods in the adjacent M frame display time, when the pixel circuit that controls the start of stopping operation is located at the boundary between the first and second predetermined display areas, the difference in the number of rows of the pixel circuit is less than or equal to p rows. p is less than or equal to 24, and p is a positive integer.

4. The display adjustment method as described in claim 3, wherein, The display panel also includes an enable signal line, which is electrically connected to the multi-level scan signal generation circuit. When the enable signal line provides a valid enable signal, the scan signal generation circuit can provide a valid scan signal to the corresponding row pixel circuit within a corresponding time period. When the enable signal line provides an invalid enable signal, the scan signal generation circuit provides an invalid scan signal to the corresponding row pixel circuit; the boundary line between the first predetermined display area and the second predetermined display area is the r-th row; r is a positive integer.

5. The display adjustment method as described in claim 4, wherein, The display refresh rate of the first predetermined display area is less than the display refresh rate of the second predetermined display area; When the pixel circuit in the first predetermined display area is in the holding phase and the pixel circuit in the second predetermined display area is in the refresh phase, and the pixel circuit in the first predetermined display area is scanned to the pixel circuit in the second predetermined display area, each adjacent N frames is a set of time. The display adjustment method includes: Within a set of time periods, at least in two adjacent frame times, at different line scan times, the enable signal line begins to provide a valid enable signal.

6. The display adjustment method as described in claim 4, wherein, The display refresh rate of the first predetermined display area is less than the display refresh rate of the second predetermined display area; When the pixel circuit in the first predetermined display area is in the holding phase and the pixel circuit in the second predetermined display area is in the refresh phase, and the pixel circuit in the first predetermined display area is scanned to the pixel circuit in the second predetermined display area, each adjacent N frames is a set of time. The display adjustment method includes: Within a set of time periods, in two adjacent frame times, at different line scan times, the enable signal line begins to provide a valid enable signal.

7. The display adjustment method as described in claim 6, wherein, The display adjustment method includes: at the x×n-(n-1)th frame time, during the rth line scan time, the enable signal line begins to provide a valid enable signal; at the x×nmth frame time, during the ry(m)th line scan time, the enable signal line begins to provide a valid enable signal, where n, r, and x are positive integers, m is a positive integer less than n-1, and y(m) is a positive integer corresponding to m; or, The display adjustment method includes: at the x×n-(n-1) frame time, during the r-th line scan time, the enable signal line begins to provide a valid enable signal; at the x×n-(2p-1) frame time, during the ry(2p-1)-th line scan time, the enable signal line begins to provide a valid enable signal; at the x×n-2p frame time, during the r+y(2p)-th line scan time, the enable signal line begins to provide a valid enable signal; wherein, n, r, p, and x are positive integers, 2p is less than n-1, y(2p-1) is a positive integer corresponding to 2p-1, and y(2p) is a positive integer corresponding to 2p; or... The display adjustment method includes: at the x×n-(n-1) frame time, during the r-th row scan time, the enable signal line begins to provide a valid enable signal; at the x×n-(2p-1) frame time, during the r+y(2p-1)-th row scan time, the enable signal line begins to provide a valid enable signal; at the x×n-2p frame time, during the ry(2p)-th row scan time, the enable signal line begins to provide a valid enable signal; wherein, n, r, p, and x are positive integers, 2p is less than n-1, y(2p-1) is a positive integer corresponding to 2p-1, and y(2p) is a positive integer corresponding to 2p.

8. The display adjustment method as described in claim 4, wherein, The display refresh rate of the first predetermined display area is greater than the display refresh rate of the second predetermined display area; when the pixel circuit in the first predetermined display area is in the refresh phase and the pixel circuit in the second predetermined display area is in the hold phase, and the pixel circuit in the first predetermined display area is scanned to the pixel circuit in the second predetermined display area, each adjacent N frames is a set of time; The display adjustment method includes: Within a set of time periods, at least in two partially adjacent frame times, at different line scan times, the enable signal line begins to provide an invalid enable signal.

9. The display adjustment method as described in claim 8, wherein, When the pixel circuit in the first predetermined display area is in the refresh phase and the pixel circuit in the second predetermined display area is in the hold phase, each adjacent N frames constitute a set of time. The display adjustment method includes: Within a set of time intervals, in two adjacent frame intervals, at different line scan intervals, the enable signal line begins to provide an invalid enable signal.

10. The display adjustment method as described in claim 9, wherein, The display adjustment method includes: at the x×n-(n-1)th frame time, during the rth line scan time, the enable signal line begins to provide an invalid enable signal; at the x×nmth frame time, during the ry(m)th line scan time, the enable signal line begins to provide an invalid enable signal, where n, r, and x are positive integers, m is a positive integer less than n-1, and y(m) is a positive integer corresponding to m; or, The display adjustment method includes: at the x×n-(n-1) frame time, during the r-th line scan time, the enable signal line begins to provide an invalid enable signal; at the x×n-(2p-1) frame time, during the ry(2p-1)-th line scan time, the enable signal line begins to provide an invalid enable signal; at the x×n-2p frame time, during the r+y(2p)-th line scan time, the enable signal line begins to provide an invalid enable signal; where n, r, p, and x are positive integers, 2p is less than n-1, y(2p-1) is a positive integer corresponding to 2p-1, and y(2p) is a positive integer corresponding to 2p; or, The display adjustment method includes: at the x×n-(n-1) frame time, during the r-th row scan time, the enable signal line begins to provide an invalid enable signal; at the x×n-(2p-1) frame time, during the r+y(2p-1)-th row scan time, the enable signal line begins to provide an invalid enable signal; at the x×n-2p frame time, during the ry(2p)-th row scan time, the enable signal line begins to provide an invalid enable signal; wherein, n, r, p, and x are positive integers, 2p is less than n-1, y(2p-1) is a positive integer corresponding to 2p-1, and y(2p) is a positive integer corresponding to 2p.

11. The display adjustment method as described in claim 1, wherein, The display panel includes a scan signal generation module and a multi-row, multi-column pixel circuit. The scan signal generation module includes a multi-level scan signal generation circuit. The scan signal generation circuit is electrically connected to a corresponding column pixel circuit and is used to provide a corresponding scan signal to the corresponding column pixel circuit. The multiple display areas are arranged sequentially along the row direction. The display adjustment method includes: When the pixel circuit in the first predetermined display area is in the holding phase and the pixel circuit in the second predetermined display area is in the refresh phase, and the pixel circuit in the first predetermined display area is scanned to the pixel circuit in the second predetermined display area, during at least two adjacent M-frame display times, when the pixel circuit controlling the start of operation is located at the boundary between the first and second predetermined display areas, the column numbers of the pixel circuits are different; and / or, When the pixel circuit in the first predetermined display area is in the refresh phase and the pixel circuit in the second predetermined display area is in the hold phase, and the pixel circuit in the first predetermined display area is scanned to the pixel circuit in the second predetermined display area, the number of columns of the pixel circuit that controls the start of stopping operation is different when the pixel circuit is scanned to the boundary between the first and second predetermined display areas during at least two display periods included in the adjacent M frame display time.

12. The display adjustment method as described in claim 11, wherein, include: When a pixel circuit in a predetermined display area is in a holding phase and a pixel circuit in a second predetermined display area is in a refresh phase, and the pixel circuit in the first predetermined display area is scanned to the pixel circuit in the second predetermined display area, during at least two adjacent M-frame display times, when the pixel circuit scanning reaches the boundary between the first and second predetermined display areas, the difference in column numbers between the pixel circuits that control the start of operation is less than or equal to p columns; and / or, When the pixel circuit in a predetermined display area is in the refresh phase and the pixel circuit in the second predetermined display area is in the hold phase, and the pixel circuit in the first predetermined display area is scanned to the pixel circuit in the second predetermined display area, during at least two display periods included in the adjacent M frame display time, when the pixel circuit that controls the start of stopping operation is located at the boundary between the first and second predetermined display areas, the difference in the number of columns is less than or equal to p columns. p is less than or equal to 24, and p is a positive integer.

13. The display adjustment method as described in claim 11, wherein, The display panel also includes an enable signal line, which is electrically connected to the multi-level scan signal generation circuit. When the enable signal line provides a valid enable signal, the scan signal generation circuit can provide a valid scan signal to the corresponding column pixel circuit within a corresponding time period. When the enable signal line provides an invalid enable signal, the scan signal generation circuit provides an invalid scan signal to the corresponding column pixel circuit. The boundary column between the first predetermined display area and the second predetermined display area is the h-th column, where h is a positive integer.

14. The display adjustment method as described in claim 13, wherein, The display refresh rate of the first predetermined display area is less than the display refresh rate of the second predetermined display area; when the pixel circuit in the first predetermined display area is in the holding phase and the pixel circuit in the second predetermined display area is in the refresh phase, and the pixel circuit in the first predetermined display area is scanned to the pixel circuit in the second predetermined display area, each adjacent N frames is a set of time; The display adjustment method includes: Within a set of time periods, at least in two adjacent frames, during different column scan times, the enable signal line begins to provide a valid enable signal.

15. The display adjustment method as described in claim 13, wherein, The display refresh rate of the first predetermined display area is less than the display refresh rate of the second predetermined display area; when the pixel circuit in the first predetermined display area is in the holding phase and the pixel circuit in the second predetermined display area is in the refresh phase, and the pixel circuit in the first predetermined display area is scanned to the pixel circuit in the second predetermined display area, each adjacent N frames is a set of time; The display adjustment method includes: Within a set of time periods, in two adjacent frame times, at different column scan times, the enable signal line begins to provide a valid enable signal.

16. The display adjustment method as described in claim 15, wherein, The display adjustment method includes: at the x×n-(n-1)th frame time, during the h-th column scan time, the enable signal line begins to provide a valid enable signal; at the x×nmth frame time, during the hy(m)-th column scan time, the enable signal line begins to provide a valid enable signal, where n, h, and x are positive integers, m is a positive integer less than n-1, and y(m) is a positive integer corresponding to m; or, The display adjustment method includes: at the x×n-(n-1) frame time, during the h-th column scan time, the enable signal line begins to provide a valid enable signal; at the x×n-(2p-1) frame time, during the hy(2p-1)-th column scan time, the enable signal line begins to provide a valid enable signal; at the x×n-2p frame time, during the h+y(2p)-th column scan time, the enable signal line begins to provide a valid enable signal; wherein, n, h, p, and x are positive integers, 2p is less than n-1, y(2p-1) is a positive integer corresponding to 2p-1, and y(2p) is a positive integer corresponding to 2p; or... The display adjustment method includes: at the x×n-(n-1) frame time, during the h-th column scan time, the enable signal line begins to provide a valid enable signal; at the x×n-(2p-1) frame time, during the h+y(2p-1)-th column scan time, the enable signal line begins to provide a valid enable signal; at the x×n-2p frame time, during the hy(2p)-th column scan time, the enable signal line begins to provide a valid enable signal; wherein, n, h, p, and x are positive integers, 2p is less than n-1, y(2p-1) is a positive integer corresponding to 2p-1, and y(2p) is a positive integer corresponding to 2p.

17. The display adjustment method as described in claim 13, wherein, The display refresh rate of the first predetermined display area is greater than the display refresh rate of the second predetermined display area; when the pixel circuit in the first predetermined display area is in the refresh phase and the pixel circuit in the second predetermined display area is in the hold phase, and the pixel circuit in the first predetermined display area is scanned to the pixel circuit in the second predetermined display area, each adjacent N frames is a set of time; The display adjustment method includes: Within a set of time periods, at least in two adjacent frames, during different column scan times, the enable signal line begins to provide an invalid enable signal.

18. The display adjustment method as described in claim 17, wherein, When the pixel circuit in the first predetermined display area is in the refresh phase and the pixel circuit in the second predetermined display area is in the hold phase, and the pixel circuit in the first predetermined display area is scanned to the pixel circuit in the second predetermined display area, each adjacent N frames is a set of time. The display adjustment method includes: Within a set of time periods, in two adjacent frame times, at different column scan times, the enable signal line begins to provide an invalid enable signal.

19. The display adjustment method as described in claim 18, wherein, The display adjustment method includes: at the x×n-(n-1)th frame time, during the h-th column scan time, the enable signal line begins to provide an invalid enable signal; at the x×nmth frame time, during the hy(m)-th column scan time, the enable signal line begins to provide an invalid enable signal, where n, h, and x are positive integers, m is a positive integer less than n-1, and y(m) is a positive integer corresponding to m; or, The display adjustment method includes: at the x×n-(n-1) frame time, during the h-th column scan time, the enable signal line begins to provide an invalid enable signal; at the x×n-(2p-1) frame time, during the hy(2p-1)-th column scan time, the enable signal line begins to provide an invalid enable signal; at the x×n-2p frame time, during the h+y(2p)-th column scan time, the enable signal line begins to provide an invalid enable signal; wherein n, h, p, and x are positive integers, 2p is less than n-1, y(2p-1) is a positive integer corresponding to 2p-1, and y(2p) is a positive integer corresponding to 2p; or, The display adjustment method includes: at the x×n-(n-1) frame time, during the h-th column scan time, the enable signal line begins to provide an invalid enable signal; at the x×n-(2p-1) frame time, during the h+y(2p-1)-th column scan time, the enable signal line begins to provide an invalid enable signal; at the x×n-2p frame time, during the hy(2p)-th column scan time, the enable signal line begins to provide an invalid enable signal; wherein, n, h, p, and x are positive integers, 2p is less than n-1, y(2p-1) is a positive integer corresponding to 2p-1, and y(2p) is a positive integer corresponding to 2p.

20. A display adjustment module applied to a display panel, the display panel including multiple display areas, adjacent display areas having different display refresh rates, and pixel circuits disposed within the display areas; the display adjustment module including a control circuit; The control circuit is configured to, when the pixel circuit in the first predetermined display area is in the holding phase and the pixel circuit in the second predetermined display area is in the refresh phase, and when the pixel circuit in the first predetermined display area scans to the pixel circuit in the second predetermined display area, control the position of the pixel circuit that starts working to be different at the boundary between the first predetermined display area and the second predetermined display area within at least two display frames included in the adjacent M frame display time, and / or, the control circuit is configured to, when the pixel circuit in the first predetermined display area is in the refresh phase and the pixel circuit in the second predetermined display area is in the holding phase, and when the pixel circuit in the first predetermined display area scans to the pixel circuit in the second predetermined display area, control the position of the pixel circuit that starts stopping working to be different at the boundary between the first predetermined display area and the second predetermined display area within at least two display frames included in the adjacent M frame display time; M is a positive integer, greater than 1 and less than or equal to 5; the first predetermined display area and the second predetermined display area are adjacent.

21. The display adjustment module as described in claim 20, wherein, The display panel includes a scan signal generation module and a multi-row, multi-column pixel circuit. The scan signal generation module includes a multi-level scan signal generation circuit. The scan signal generation circuit is electrically connected to the corresponding row pixel circuit and is used to provide the corresponding row pixel circuit with a corresponding scan signal. The multiple display areas are arranged sequentially along the column direction. The control circuit is configured to, when a pixel circuit in a first predetermined display area is in a holding phase and a pixel circuit in a second predetermined display area is in a refresh phase, and when the pixel circuit in the first predetermined display area scans to the pixel circuit in the second predetermined display area, control the row number of the pixel circuit that starts working to be different within at least two display frames included in the adjacent M-frame display time, when scanning to the boundary between the first and second predetermined display areas; and / or, the control circuit is configured to, when a pixel circuit in the first predetermined display area is in a refresh phase and a pixel circuit in the second predetermined display area is in a holding phase, and when the pixel circuit in the first predetermined display area scans to the pixel circuit in the second predetermined display area, control the row number of the pixel circuit that starts working to be different within at least two display frames included in the adjacent M-frame display time, when scanning to the boundary between the first and second predetermined display areas.

22. The display adjustment module as described in claim 21, wherein, The control circuit is configured to, when the pixel circuit in the first predetermined display area is in the holding phase and the pixel circuit in the second predetermined display area is in the refresh phase, and when the pixel circuit in the first predetermined display area scans to the pixel circuit in the second predetermined display area, within at least two display frames included in the adjacent M frame display time, when scanning to the boundary between the first and second predetermined display areas, control the row number difference of the pixel circuit that starts working to be less than or equal to p rows; and / or the control circuit is configured to, when the pixel circuit in the first predetermined display area is in the refresh phase and the pixel circuit in the second predetermined display area is in the holding phase, and when the pixel circuit in the first predetermined display area scans to the pixel circuit in the second predetermined display area, within at least two display frames included in the adjacent M frame display time, when scanning to the boundary between the first and second predetermined display areas, control the row number difference of the pixel circuit that starts working to be less than or equal to p rows; p is less than or equal to 24, and p is a positive integer.

23. The display adjustment module as described in claim 20, wherein, The display panel includes a scan signal generation module and a multi-row, multi-column pixel circuit. The scan signal generation module includes a multi-level scan signal generation circuit. The scan signal generation circuit is electrically connected to the corresponding column pixel circuit and is used to provide the corresponding column pixel circuit with a corresponding scan signal. The multiple display areas are arranged sequentially along the row direction. The control circuit is configured to, when a pixel circuit in a first predetermined display area is in a holding phase and a pixel circuit in a second predetermined display area is in a refresh phase, and when the pixel circuit in the first predetermined display area scans to the pixel circuit in the second predetermined display area, control the number of columns of the pixel circuits that start working to be different within at least two display frames included in the adjacent M-frame display time, when scanning to the boundary between the first and second predetermined display areas; and / or, the control circuit is configured to, when a pixel circuit in the first predetermined display area is in a refresh phase and a pixel circuit in the second predetermined display area is in a holding phase, and when the pixel circuit in the first predetermined display area scans to the pixel circuit in the second predetermined display area, control the number of columns of the pixel circuits that start working to be different within at least two display frames included in the adjacent M-frame display time, when scanning to the boundary between the first and second predetermined display areas.

24. The display adjustment module as described in claim 23, wherein, The control circuit is configured to, when a pixel circuit in a predetermined display area is in a holding phase and a pixel circuit in a second predetermined display area is in a refresh phase, and when the pixel circuit in the first predetermined display area scans to the pixel circuit in the second predetermined display area, within at least two display frames included in the adjacent M frame display time, when scanning to the boundary between the first and second predetermined display areas, control the difference in column number of the pixel circuit that starts working to be less than or equal to p columns; and / or, the control circuit is configured to, when a pixel circuit in a predetermined display area is in a refresh phase and a pixel circuit in a second predetermined display area is in a holding phase, and when the pixel circuit in the first predetermined display area scans to the pixel circuit in the second predetermined display area, within at least two display frames included in the adjacent M frame display time, when scanning to the boundary between the first and second predetermined display areas, control the difference in column number of the pixel circuit that starts working to be less than or equal to p columns; p is less than or equal to 24, and p is a positive integer.

25. A display device comprising a display adjustment module as described in any one of claims 20 to 24.

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