Pixel circuit, pixel driving method, and display device

Abstract

The present disclosure provides a pixel circuit, a pixel driving method, and a display device. The pixel circuit comprises a driving circuit, a data writing circuit, and a setting circuit; a driving transistor comprises a first gate, a second gate, a first electrode, and a second electrode; the first gate of the driving transistor is electrically connected to a first node, and the second gate of the driving transistor is electrically connected to a fourth node; the data writing circuit writes a data voltage into the first node under the control of a scanning signal; and the setting circuit writes a first voltage signal into the fourth node under the control of a setting control signal. In the present disclosure, by designing data voltage writing and threshold voltage compensation to be separate, the required scanning time for one row is reduced, such that, during high-frequency display, data voltage writing time can be ensured, and the pixel circuit can be fully charged by the data voltage while ensuring display uniformity, thereby ensuring the display effect.

Description

Pixel circuits, pixel driving methods, and display devices

[0001] Cross-reference to related applications

[0002] This application claims priority to Chinese Patent Application No. 202411186517.4, filed in China on August 27, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to the field of display technology, and in particular to a pixel circuit, a pixel driving method, and a display device. Background Technology

[0004] With the rapid development of AMOLED (Active-matrix organic light-emitting diode), medium and large-sized tablet computers and laptops have become important future development directions. Customers have increasingly strong demands for high-frequency displays. Existing pixel circuits perform threshold voltage compensation and data voltage writing simultaneously. High-frequency technology leads to line time compression, which cannot effectively compensate for the threshold voltage of the driving transistor in the driving circuit, and thus cannot achieve high-frequency driving. Summary of the Invention

[0005] The main objective of this disclosure is to provide a pixel circuit, a pixel driving method, and a display device to solve the problem that the pixel circuit cannot effectively compensate for the threshold voltage of the driving transistor in the driving circuit due to the compression of one line time caused by high-frequency technology, thus failing to achieve high-frequency driving.

[0006] In one aspect, embodiments of this disclosure provide a pixel circuit, including a driving circuit, a data writing circuit, and a setting circuit; the driving circuit includes a driving transistor; the driving transistor includes a first gate, a second gate, a first electrode, and a second electrode;

[0007] The first gate of the driving transistor is electrically connected to the first node, the first electrode of the driving transistor is electrically connected to the second node, the second electrode of the driving transistor is electrically connected to the third node, and the second gate of the driving transistor is electrically connected to the fourth node.

[0008] The data writing circuit is electrically connected to the scanning end, the data line and the first node respectively, and is used to write the data voltage provided by the data line into the first node under the control of the scanning signal provided by the scanning end;

[0009] The set circuit is electrically connected to the set control terminal, the first voltage terminal and the fourth node respectively, and is used to write the first voltage signal provided by the first voltage terminal into the fourth node under the control of the set control signal provided by the set control terminal.

[0010] The pixel circuit described in at least one embodiment of this disclosure further includes a first initialization circuit and a second initialization circuit;

[0011] The first initialization circuit is electrically connected to the first reset control terminal, the first initial voltage terminal and the first node respectively, and is used to write the first initial voltage provided by the first initial voltage terminal into the first node under the control of the first reset control signal provided by the first reset control terminal.

[0012] The second initialization circuit is electrically connected to the second reset control terminal, the first initial voltage terminal and the third node, respectively, and is used to write the first initial voltage into the third node under the control of the second reset control signal provided by the second reset control terminal.

[0013] The pixel circuit described in at least one embodiment of this disclosure further includes a first energy storage circuit;

[0014] The first end of the first energy storage circuit is electrically connected to the fourth node, and the second end of the first energy storage circuit is electrically connected to the third node.

[0015] In at least one embodiment of this disclosure, the first gate is a top gate and the second gate is a bottom gate.

[0016] In at least one embodiment of this disclosure, the driving transistor is an n-type transistor, and the voltage value of the first voltage signal provided by the first voltage terminal is greater than 0; or, the driving transistor is a p-type transistor, and the voltage value of the first voltage signal is less than 0.

[0017] In at least one embodiment of this disclosure, the setting circuit includes an on / off control circuit and a first light-emitting control circuit, and the setting control terminal includes a first reset control terminal and a first light-emitting control terminal;

[0018] The on / off control circuit is electrically connected to the first reset control terminal, the second node, and the fourth node, respectively, and is used to control the connection between the second node and the fourth node under the control of the first reset control signal provided by the first reset control terminal;

[0019] The first light-emitting control circuit is electrically connected to the first light-emitting control terminal, the first voltage terminal, and the second node, respectively, and is used to control the connection between the first voltage terminal and the second node under the control of the first light-emitting control signal provided by the first light-emitting control terminal.

[0020] The pixel circuit described in at least one embodiment of this disclosure further includes a second energy storage circuit;

[0021] The first end of the second energy storage circuit is electrically connected to the first node, and the second end of the second energy storage circuit is electrically connected to the third node.

[0022] The pixel circuit described in at least one embodiment of this disclosure further includes a light-emitting element, a second light-emitting control circuit, and a third initialization circuit;

[0023] The second light-emitting control circuit is electrically connected to the second light-emitting control terminal, the third node, and the first electrode of the light-emitting element, respectively, and is used to control the connection between the third node and the first electrode of the light-emitting element under the control of the second light-emitting control signal provided by the second light-emitting control terminal;

[0024] The third initialization circuit is electrically connected to the third reset control terminal, the second initial voltage terminal, and the first electrode of the light-emitting element, respectively, and is used to write the second initial voltage provided by the second initial voltage terminal into the first electrode of the light-emitting element under the control of the third reset control signal provided by the third reset control terminal.

[0025] The second electrode of the light-emitting element is electrically connected to the second voltage terminal.

[0026] In at least one embodiment of this disclosure, the transistors included in the first light-emitting control circuit and the transistors included in the second light-emitting control circuit are both n-type transistors or both are p-type transistors. The first light-emitting control terminal is the nth-level light-emitting control terminal, and the second light-emitting control terminal is the (n+a)th-level light-emitting control circuit, where n and a are both positive integers.

[0027] In at least one embodiment of this disclosure, the pixel circuit further includes a first initialization circuit and a second initialization circuit;

[0028] The second reset control terminal is the same as the third reset control terminal.

[0029] In at least one embodiment of this disclosure, the data writing circuit includes a first transistor; the first energy storage circuit includes a first capacitor;

[0030] The gate of the first transistor is electrically connected to the scan terminal, the first electrode of the first transistor is electrically connected to the data line, and the second electrode of the first transistor is electrically connected to the first node.

[0031] The first terminal of the first capacitor is electrically connected to the fourth node, and the second terminal of the first capacitor is electrically connected to the third node.

[0032] In at least one embodiment of this disclosure, the first transistor is a low-temperature polycrystalline silicon transistor.

[0033] In at least one embodiment of this disclosure, the on / off control circuit includes a second transistor, and the first light-emitting control circuit includes a third transistor;

[0034] The gate of the second transistor is electrically connected to the first reset control terminal, the first terminal of the second transistor is electrically connected to the second node, and the second terminal of the second transistor is electrically connected to the fourth node.

[0035] The gate of the third transistor is electrically connected to the first light-emitting control terminal, the first electrode of the third transistor is electrically connected to the first voltage terminal, and the second electrode of the third transistor is electrically connected to the second node.

[0036] In at least one embodiment of this disclosure, the third transistor is a low-temperature polycrystalline silicon transistor.

[0037] In at least one embodiment of this disclosure, the first initialization circuit includes a fourth transistor, and the second initialization circuit includes a fifth transistor;

[0038] The gate of the fourth transistor is electrically connected to the first reset control terminal, the first terminal of the fourth transistor is electrically connected to the first initial voltage terminal, and the second terminal of the fourth transistor is electrically connected to the first node.

[0039] The gate of the fifth transistor is electrically connected to the second reset control terminal, the first terminal of the fifth transistor is electrically connected to the first initial voltage terminal, and the second terminal of the fifth transistor is electrically connected to the third node.

[0040] In at least one embodiment of this disclosure, the second energy storage circuit includes a second capacitor;

[0041] The first end of the second capacitor is electrically connected to the first node, and the second end of the second capacitor is electrically connected to the third node.

[0042] In at least one embodiment of this disclosure, the second light-emitting control circuit includes a sixth transistor, and the third initialization circuit includes a seventh transistor;

[0043] The gate of the sixth transistor is electrically connected to the second light-emitting control terminal, the first terminal of the sixth transistor is electrically connected to the third node, and the second terminal of the sixth transistor is electrically connected to the first terminal of the light-emitting element.

[0044] The gate of the seventh transistor is electrically connected to the third reset control terminal, the first terminal of the seventh transistor is electrically connected to the second initial voltage terminal, and the second terminal of the seventh transistor is electrically connected to the first terminal of the light-emitting element.

[0045] In at least one embodiment of this disclosure, the sixth transistor is a low-temperature polycrystalline silicon transistor.

[0046] In a second aspect, embodiments of this disclosure provide a pixel driving method applied to the aforementioned pixel circuit, wherein the display cycle includes a reset phase and a data writing phase;

[0047] During the reset phase, the set circuit, under the control of the set control signal, writes the first voltage signal into the fourth node;

[0048] During the data writing phase, the data writing circuit writes the data voltage to the first node under the control of the scanning signal.

[0049] In at least one embodiment of this disclosure, the pixel circuit further includes a first initialization circuit and a second initialization circuit; the pixel driving method further includes:

[0050] During the reset phase, the first initialization circuit, under the control of the first reset control signal, writes the first initial voltage into the first node, and the second initialization circuit, under the control of the second reset control signal, writes the first initial voltage into the third node.

[0051] In a third aspect, embodiments of this disclosure provide a display device including the pixel circuit described above.

[0052] The pixel circuit described in this embodiment separates the data voltage writing and threshold voltage compensation during operation, requiring less scanning time per line. This ensures sufficient data voltage writing time during high-frequency display, allowing the pixel circuit to be fully charged by the data voltage while maintaining display uniformity, thus guaranteeing display performance. Attached Figure Description

[0053] Figure 1 is a structural diagram of the pixel circuit according to at least one embodiment of this disclosure;

[0054] Figure 2 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0055] Figure 3 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0056] Figure 4 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0057] Figure 5 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0058] Figure 6 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0059] Figure 7 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0060] Figure 8 is a timing diagram of at least one embodiment of the driving circuit shown in Figure 7;

[0061] Figure 9 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0062] Figure 10 is a timing diagram of at least one embodiment of the driving circuit shown in Figure 9;

[0063] Figure 11 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0064] Figure 12 is a timing diagram of at least one embodiment of the driving circuit shown in Figure 11;

[0065] Figure 13 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0066] Figure 14 is a timing diagram of at least one embodiment of the driving circuit shown in Figure 13;

[0067] Figure 15 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0068] Figure 16 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0069] Figure 17 is a timing diagram of at least one embodiment of the driving circuit shown in Figure 16. Detailed Implementation

[0070] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this disclosure.

[0071] In all embodiments of this disclosure, the transistors used can be thin-film transistors, field-effect transistors, or other devices with similar characteristics. In the embodiments of this disclosure, to distinguish the two terminals of the transistor other than the gate, one terminal is referred to as the first terminal and the other as the second terminal.

[0072] In actual operation, when the transistor is a thin-film transistor or a field-effect transistor, the first electrode can be the drain and the second electrode can be the source; or, the first electrode can be the source and the second electrode can be the drain.

[0073] As shown in Figure 1, the pixel circuit of this embodiment includes a driving circuit 10, a data writing circuit 11, and a setting circuit 12; the driving circuit 10 includes a driving transistor DT; the driving transistor DT includes a first gate, a second gate, a first electrode, and a second electrode;

[0074] The first gate of the driving transistor DT is electrically connected to the first node N1, the first terminal of the driving transistor DT is electrically connected to the second node N2, the second terminal of the driving transistor DT is electrically connected to the third node N3, and the second gate of the driving transistor DT is electrically connected to the fourth node N4.

[0075] The data writing circuit 11 is electrically connected to the scanning end GT, the data line DL and the first node N1 respectively, and is used to write the data voltage provided by the data line DL into the first node N1 under the control of the scanning signal provided by the scanning end GT.

[0076] The set circuit 12 is electrically connected to the set control terminal RST, the first voltage terminal V1 and the fourth node N4 respectively, and is used to write the first voltage signal provided by the first voltage terminal V1 into the fourth node N4 under the control of the set control signal provided by the set control terminal RST.

[0077] In the pixel circuit described in the embodiments of this disclosure, the driving circuit 10 includes a driving transistor DT, which is a dual-gate transistor, and the first voltage terminal can be a DC voltage terminal, for example, the first voltage terminal can be a power supply voltage terminal.

[0078] When the pixel circuit described in this embodiment is working, the display cycle may include a reset phase and a data writing phase;

[0079] During the reset phase, the set circuit 12, under the control of the set control signal, writes the first voltage signal into the fourth node N4, that is, writes the first voltage signal into the second gate of the driving transistor DT, so that by biasing the potential of the second gate of the driving transistor DT, the same voltage signal is provided to the second gate of the driving transistors in the multi-row and multi-column pixel circuits included in the display panel during the reset phase, so as to control and ensure the uniformity of the threshold voltage of the driving transistors in the multiple pixel circuits included in the display panel.

[0080] During the data writing phase, the data writing circuit, under the control of the scanning signal, writes the data voltage to the first node.

[0081] The pixel circuit described in this embodiment separates the data voltage writing and threshold voltage compensation during operation, requiring less scanning time per line. This ensures sufficient data voltage writing time during high-frequency display, allowing the pixel circuit to be fully charged by the data voltage while maintaining display uniformity, thus guaranteeing display performance.

[0082] The embodiments disclosed herein can reduce compensation loss while increasing compensation time, thereby improving the process compensation capability of pixel circuits.

[0083] The pixel circuit described in at least one embodiment of this disclosure further includes a first initialization circuit and a second initialization circuit;

[0084] The first initialization circuit is electrically connected to the first reset control terminal, the first initial voltage terminal and the first node respectively, and is used to write the first initial voltage provided by the first initial voltage terminal into the first node under the control of the first reset control signal provided by the first reset control terminal.

[0085] The second initialization circuit is electrically connected to the second reset control terminal, the first initial voltage terminal and the third node, respectively, and is used to write the first initial voltage into the third node under the control of the second reset control signal provided by the second reset control terminal.

[0086] In a specific implementation, the pixel circuit may further include a first initialization circuit and a second initialization circuit. During the reset phase, the first initialization circuit, under the control of the first reset control signal, writes the first initial voltage into the first node, and the second initialization circuit, under the control of the second reset control signal, writes the first initial voltage into the third node, so that the gate-source voltage of the driving transistor is equal to 0. Under the premise that the gate-source voltage of the driving transistor is equal to 0, the second gate of the driving transistor is set by the first voltage signal, which can set the threshold voltage of the driving transistor, so as to control and ensure the uniformity of the threshold voltage of the driving transistors in the multiple pixel circuits included in the display panel.

[0087] As shown in Figure 2, based on at least one embodiment of the pixel circuit shown in Figure 1, the pixel circuit of at least one embodiment of this disclosure further includes a first initialization circuit 21 and a second initialization circuit 22.

[0088] The first initialization circuit 21 is electrically connected to the first reset control terminal R1, the first initial voltage terminal I1 and the first node N1 respectively, and is used to write the first initial voltage Vinit1 provided by the first initial voltage terminal I1 into the first node N1 under the control of the first reset control signal provided by the first reset control terminal R1.

[0089] The second initialization circuit 22 is electrically connected to the second reset control terminal R2, the first initial voltage terminal I1 and the third node N3 respectively, and is used to write the first initial voltage Vinit1 into the third node N3 under the control of the second reset control signal provided by the second reset control terminal R2.

[0090] The pixel circuit described in at least one embodiment of this disclosure further includes a first energy storage circuit;

[0091] The first end of the first energy storage circuit is electrically connected to the fourth node, and the second end of the first energy storage circuit is electrically connected to the third node.

[0092] In a specific implementation, the pixel circuit may further include a first energy storage circuit, which is electrically connected to the fourth node and the third node respectively, and is used to store electrical energy.

[0093] As shown in Figure 3, based on at least one embodiment of the pixel circuit shown in Figure 2, the pixel circuit described in at least one embodiment of this disclosure may further include a first energy storage circuit 31;

[0094] The first terminal of the first energy storage circuit 31 is electrically connected to the fourth node N4, and the second terminal of the first energy storage circuit 31 is electrically connected to the third node N3.

[0095] Optionally, the first gate is a top gate and the second gate is a bottom gate.

[0096] In a specific implementation, the driving transistor can be a dual-gate transistor, which can write data voltage into the top gate of the driving transistor and control the threshold voltage of the driving transistor by controlling the potential of the bottom gate of the driving transistor.

[0097] In at least one embodiment of this disclosure, the driving transistor is an n-type transistor, and the voltage value of the first voltage signal provided by the first voltage terminal is greater than 0; or, the driving transistor is a p-type transistor, and the voltage value of the first voltage signal is less than 0.

[0098] In specific implementation, when the driving transistor is an n-type transistor, the voltage value of the first voltage signal can be greater than 0, and when the driving transistor is a p-type transistor, the voltage value of the first voltage signal can be less than 0.

[0099] In at least one embodiment of this disclosure, the setting circuit includes an on / off control circuit and a first light-emitting control circuit, and the setting control terminal includes a first reset control terminal and a first light-emitting control terminal;

[0100] The on / off control circuit is electrically connected to the first reset control terminal, the second node, and the fourth node, respectively, and is used to control the connection between the second node and the fourth node under the control of the first reset control signal provided by the first reset control terminal;

[0101] The first light-emitting control circuit is electrically connected to the first light-emitting control terminal, the first voltage terminal, and the second node, respectively, and is used to control the connection between the first voltage terminal and the second node under the control of the first light-emitting control signal provided by the first light-emitting control terminal.

[0102] In a specific implementation, the setting circuit may include an on / off control circuit and a first light-emitting control circuit. The on / off control circuit controls the connection between the second node and the fourth node under the control of the first reset control signal. The first light-emitting control circuit writes the first voltage signal into the second node under the control of the first light-emitting control signal.

[0103] Optionally, the structure of the set circuit is not limited to including an on / off control circuit and a first light emission control signal. For example, the set circuit may include a set transistor, the gate of which is electrically connected to a set control terminal, the first terminal of which is electrically connected to a first voltage terminal, and the second terminal of which is electrically connected to the second gate of the driving transistor.

[0104] As shown in Figure 4, based on at least one embodiment of the pixel circuit shown in Figure 3, the setting circuit includes an on / off control circuit 40 and a first light emission control circuit 41, and the setting control terminal includes a first reset control terminal R1 and a first light emission control terminal EM1.

[0105] The on / off control circuit 40 is electrically connected to the first reset control terminal R1, the second node N2 and the fourth node N4 respectively, and is used to control the connection between the second node N2 and the fourth node N4 under the control of the first reset control signal provided by the first reset control terminal R1.

[0106] The first light-emitting control circuit 41 is electrically connected to the first light-emitting control terminal EM1, the first voltage terminal V1 and the second node N2 respectively, and is used to control the connection between the first voltage terminal V1 and the second node N2 under the control of the first light-emitting control signal provided by the first light-emitting control terminal EM1.

[0107] In at least one embodiment of the pixel circuit shown in Figure 4 of this disclosure, during the reset phase, the first light-emitting control circuit 41, under the control of the first light-emitting control signal, writes the first voltage signal provided by the first voltage terminal V1 into the second node N2. The on / off control circuit 40, under the control of the first reset control signal, controls the connection between the second node N2 and the fourth node N4 to write the first voltage signal into the fourth node N4, sets the potential of the fourth node N4, so that the driving transistor DT is in a biased state, and adjusts the threshold voltage of the driving transistor DT.

[0108] The pixel circuit described in at least one embodiment of this disclosure further includes a second energy storage circuit;

[0109] The first end of the second energy storage circuit is electrically connected to the first node, and the second end of the second energy storage circuit is electrically connected to the third node.

[0110] In a specific implementation, the pixel circuit may further include a second energy storage circuit, which is electrically connected to the first node and the third node respectively, and is used to store electrical energy.

[0111] As shown in Figure 5, based on at least one embodiment of the pixel circuit shown in Figure 4, the pixel circuit of at least one embodiment of this disclosure further includes a second energy storage circuit 32;

[0112] The first end of the second energy storage circuit 32 is electrically connected to the first node N1, and the second end of the second energy storage circuit 32 is electrically connected to the third node N3. The second energy storage circuit 32 can control the potential of the third node N3 according to the potential of the first node N1.

[0113] The pixel circuit described in at least one embodiment of this disclosure further includes a light-emitting element, a second light-emitting control circuit, and a third initialization circuit;

[0114] The second light-emitting control circuit is electrically connected to the second light-emitting control terminal, the third node, and the first electrode of the light-emitting element, respectively, and is used to control the connection between the third node and the first electrode of the light-emitting element under the control of the second light-emitting control signal provided by the second light-emitting control terminal;

[0115] The third initialization circuit is electrically connected to the third reset control terminal, the second initial voltage terminal, and the first electrode of the light-emitting element, respectively, and is used to write the second initial voltage provided by the second initial voltage terminal into the first electrode of the light-emitting element under the control of the third reset control signal provided by the third reset control terminal.

[0116] The second electrode of the light-emitting element is electrically connected to the second voltage terminal.

[0117] In a specific implementation, the pixel circuit may further include a light-emitting element, a second light-emitting control circuit, and a third initialization circuit; the second light-emitting control circuit, under the control of a second light-emitting control signal, controls the connection between the third node and the first electrode of the light-emitting element to perform light-emitting control; the third initialization circuit, under the control of a third reset control signal, writes a second initial voltage into the first electrode of the light-emitting element to clear the residual charge on the first electrode of the light-emitting element.

[0118] Optionally, the second voltage terminal can be a low voltage terminal or a ground terminal.

[0119] Optionally, the light-emitting element can be an OLED (organic light-emitting diode), a Micro LED (micro light-emitting diode), or a mini LED (mini light-emitting diode).

[0120] As shown in Figure 6, based on at least one embodiment of the pixel circuit shown in Figure 5, the pixel circuit of at least one embodiment of this disclosure further includes a light-emitting element E1, a second light-emitting control circuit 42, and a third initialization circuit 23.

[0121] The second light-emitting control circuit 42 is electrically connected to the second light-emitting control terminal EM2, the third node N3, and the first pole of the light-emitting element E1, respectively, and is used to control the connection between the third node N3 and the first pole of the light-emitting element E1 under the control of the second light-emitting control signal provided by the second light-emitting control terminal EM2.

[0122] The third initialization circuit 23 is electrically connected to the third reset control terminal R3, the second initial voltage terminal I2 and the first pole of the light-emitting element E1, respectively, and is used to write the second initial voltage Vinit2 provided by the second initial voltage terminal I2 into the first pole of the light-emitting element E1 under the control of the third reset control signal provided by the third reset control terminal R3.

[0123] The second electrode of the light-emitting element E1 is electrically connected to the second voltage terminal V2.

[0124] In at least one embodiment of this disclosure, the transistors included in the first light-emitting control circuit and the transistors included in the second light-emitting control circuit are both n-type transistors or both are p-type transistors. The first light-emitting control terminal is the nth-level light-emitting control terminal, and the second light-emitting control terminal is the (n+a)th-level light-emitting control circuit, where n and a are both positive integers.

[0125] In practical implementation, the first light emission control signal and the second light emission control signal can be provided by the same GOA (Gate On Array, gate drive circuit set on array substrate) module, so as to reduce the number of GOA modules used, which is beneficial to achieve narrow bezel and save costs.

[0126] In at least one embodiment of this disclosure, the pixel circuit further includes a first initialization circuit and a second initialization circuit;

[0127] The second reset control terminal is the same as the third reset control terminal.

[0128] In practical implementation, the second reset control terminal and the third control terminal can be the same reset control terminal to reduce the number of control terminals and GOA modules used, which is beneficial to achieving high PPI (pixel density) and narrow bezels.

[0129] Optionally, the data writing circuit includes a first transistor; the first energy storage circuit includes a first capacitor;

[0130] The gate of the first transistor is electrically connected to the scan terminal, the first electrode of the first transistor is electrically connected to the data line, and the second electrode of the first transistor is electrically connected to the first node.

[0131] The first terminal of the first capacitor is electrically connected to the fourth node, and the second terminal of the first capacitor is electrically connected to the third node.

[0132] In at least one embodiment of this disclosure, the first transistor is a low-temperature polycrystalline silicon transistor.

[0133] In practical implementation, the first transistor can be set as an LTPS (Low Temperature Polycrystalline Silicon) transistor, which can improve the data voltage write current and improve the data voltage write efficiency at high frequencies.

[0134] Optionally, the on / off control circuit includes a second transistor, and the first light-emitting control circuit includes a third transistor;

[0135] The gate of the second transistor is electrically connected to the first reset control terminal, the first terminal of the second transistor is electrically connected to the second node, and the second terminal of the second transistor is electrically connected to the fourth node.

[0136] The gate of the third transistor is electrically connected to the first light-emitting control terminal, the first electrode of the third transistor is electrically connected to the first voltage terminal, and the second electrode of the third transistor is electrically connected to the second node.

[0137] In at least one embodiment of this disclosure, the third transistor is a low-temperature polycrystalline silicon transistor.

[0138] In practical implementation, the third transistor can be set as an LTPS (Low Temperature Polycrystalline Silicon) transistor, which is beneficial for high PPI layout and space node optimization. At the same time, LTPS transistors have high mobility and can light up quickly, reducing the brightness difference caused by the mobility or threshold voltage fluctuation of oxide transistors.

[0139] Optionally, the first initialization circuit includes a fourth transistor, and the second initialization circuit includes a fifth transistor;

[0140] The gate of the fourth transistor is electrically connected to the first reset control terminal, the first terminal of the fourth transistor is electrically connected to the first initial voltage terminal, and the second terminal of the fourth transistor is electrically connected to the first node.

[0141] The gate of the fifth transistor is electrically connected to the second reset control terminal, the first terminal of the fifth transistor is electrically connected to the first initial voltage terminal, and the second terminal of the fifth transistor is electrically connected to the third node.

[0142] Optionally, the second energy storage circuit includes a second capacitor;

[0143] The first end of the second capacitor is electrically connected to the first node, and the second end of the second capacitor is electrically connected to the third node.

[0144] Optionally, the second light-emitting control circuit includes a sixth transistor, and the third initialization circuit includes a seventh transistor;

[0145] The gate of the sixth transistor is electrically connected to the second light-emitting control terminal, the first terminal of the sixth transistor is electrically connected to the third node, and the second terminal of the sixth transistor is electrically connected to the first terminal of the light-emitting element.

[0146] The gate of the seventh transistor is electrically connected to the third reset control terminal, the first terminal of the seventh transistor is electrically connected to the second initial voltage terminal, and the second terminal of the seventh transistor is electrically connected to the first terminal of the light-emitting element.

[0147] In at least one embodiment of this disclosure, the sixth transistor is a low-temperature polycrystalline silicon transistor.

[0148] In practical implementation, the sixth transistor can be set as an LTPS (Low Temperature Polycrystalline Silicon) transistor, which is beneficial for high PPI layout and space node optimization. At the same time, LTPS transistors have high mobility and can light up quickly, reducing the brightness difference caused by the mobility or threshold voltage fluctuation of oxide transistors.

[0149] As shown in Figure 7, based on at least one embodiment of the pixel circuit shown in Figure 6, the light-emitting element is an organic light-emitting diode O1;

[0150] The top gate of the driving transistor DT is electrically connected to the first node N1, the bottom gate of the driving transistor DT is electrically connected to the fourth node N4, the drain of the driving transistor DT is electrically connected to the second node N2, and the source of the driving transistor DT is electrically connected to the third node N3.

[0151] The data writing circuit includes a first transistor T1; the first energy storage circuit includes a first capacitor C1.

[0152] The gate of the first transistor T1 is electrically connected to the scan terminal GT, the drain of the first transistor T1 is electrically connected to the data line DL, and the source of the first transistor T1 is electrically connected to the first node N1.

[0153] The first terminal of the first capacitor C1 is electrically connected to the fourth node N4, and the second terminal of the first capacitor C1 is electrically connected to the third node N3;

[0154] The on / off control circuit includes a second transistor T2, and the first light-emitting control circuit includes a third transistor T3;

[0155] The gate of the second transistor T2 is electrically connected to the first reset control terminal R1, the drain of the second transistor T2 is electrically connected to the second node N2, and the source of the second transistor T2 is electrically connected to the fourth node N4.

[0156] The gate of the third transistor T3 is electrically connected to the first light-emitting control terminal EM1, the drain of the third transistor T3 is electrically connected to the power supply voltage terminal VDD, and the source of the third transistor T3 is electrically connected to the second node N2.

[0157] The first initialization circuit includes a fourth transistor T4, and the second initialization circuit includes a fifth transistor T5;

[0158] The gate of the fourth transistor T4 is electrically connected to the first reset control terminal R1, the drain of the fourth transistor T4 is electrically connected to the first initial voltage terminal I1, and the source of the fourth transistor T4 is electrically connected to the first node N1.

[0159] The gate of the fifth transistor T5 is electrically connected to the second reset control terminal R2, the drain of the fifth transistor T5 is electrically connected to the first initial voltage terminal I1, and the source of the fifth transistor T5 is electrically connected to the third node N3.

[0160] The second energy storage circuit includes a second capacitor C2;

[0161] The first terminal of the second capacitor C2 is electrically connected to the first node N1, and the second terminal of the second capacitor C2 is electrically connected to the third node N3;

[0162] The second light-emitting control circuit includes a sixth transistor T6, and the third initialization circuit includes a seventh transistor T7;

[0163] The gate of the sixth transistor T6 is electrically connected to the second light-emitting control terminal EM2, the drain of the sixth transistor T6 is electrically connected to the third node N3, and the source of the sixth transistor T6 is electrically connected to the anode of O1.

[0164] The gate of the seventh transistor T7 is electrically connected to the third reset control terminal R3, the drain of the seventh transistor T7 is electrically connected to the second initial voltage terminal I2, and the source of the seventh transistor T7 is electrically connected to the anode of O1.

[0165] The cathode of O1 is electrically connected to the low-voltage terminal VSS.

[0166] In at least one embodiment of the pixel circuit shown in Figure 7, all transistors are n-type transistors and all transistors are oxide transistors.

[0167] In at least one embodiment of the pixel circuit shown in Figure 7, the voltage value of the first initial voltage Vinit1 provided by I1 is positive, and can fluctuate according to the debugging; the voltage value of the second initial voltage Vinit2 provided by I2 is positive or negative, or 0V, and can fluctuate according to the actual debugging. It can be set to be consistent with VSS, or have a certain difference; the voltage value of the low voltage signal provided by VSS is positive or negative, or 0V, and can fluctuate according to the actual debugging.

[0168] As shown in FIG8, when at least one embodiment of the pixel circuit shown in FIG7 of this disclosure is in operation, the display cycle may include a reset stage S1, a bias voltage storage stage S2, a data writing stage S3 and a light emission stage S4 arranged sequentially.

[0169] During the reset phase S1, EM1 provides a high voltage signal, EM2 provides a low voltage signal, R1 provides a high voltage signal, R2 provides a high voltage signal, GT provides a low voltage signal, and R3 provides a high voltage signal. T4, T5, T3, T7, and T2 are turned on. The potential of N1 is the first initial voltage Vinit1 provided by I1, and the potential of N3 is the first initial voltage Vinit1, making the gate-source voltage Vgs of DT equal to 0. VDD provides a power supply voltage signal to N4 to set the potential of the bottom gate of DT, bias DT, and adjust the threshold voltage of DT. The anode potential of O1 is the second initial voltage Vinit2 provided by I2.

[0170] During the bias voltage storage phase S2, EM1 and EM2 both provide low voltage signals, R1 provides a high voltage signal, R2 provides a high voltage signal, GT provides a low voltage signal, and R3 provides a high voltage signal. T2 is turned on, and the potentials of N2 and N4 are maintained at the voltage value of the power supply voltage signal. T4 and T5 are turned on, and the potentials of N1 and N3 are both Vinit1. The gate-source voltage of DT is maintained at 0. At this time, N4 is still controlled to be connected to the power supply voltage signal to store the bias voltage of DT. T7 is turned on, and the anode of O1 is connected to Vinit2 to clear the residual charge on the anode of O1.

[0171] During the data writing phase S3, EM1 and EM2 both provide low voltage signals, R1 provides a low voltage signal, GT provides a high voltage signal, R2 and R3 both provide high voltage signals, T1 is turned on, DL provides the data voltage Vdata to N1, T5 is turned on, T7 is turned on, I1 provides the first initial voltage Vinit1 to the third node, and I2 provides the second initial voltage Vinit2 to the anode of O1 to clear the residual charge on the anode of O1.

[0172] During the light-emitting stage S4, EM1 and EM2 provide high voltage signals, R1, R2, GT and R3 provide low voltage signals, T3 and T6 are both turned on, and DT drives O1 to emit light.

[0173] In at least one embodiment of this disclosure, the display panel includes multiple pixel circuits. During the reset phase and the bias voltage storage phase, the potentials of the first node and the third node in the pixel circuit are set to be equal, and the bottom gate of the driving transistor is set by the first voltage signal provided by the first voltage terminal, so as to adjust the threshold voltage of the driving transistor in the multiple pixel circuits to the same threshold voltage value, thereby improving the display uniformity.

[0174] The difference between at least one embodiment of the pixel circuit shown in Figure 9 and at least one embodiment of the pixel circuit shown in Figure 7 is that the gate of T6 is electrically connected to the first light-emitting control terminal EM1(n+3) of the (n+3)th row.

[0175] In at least one embodiment shown in Figure 9, the first light-emitting control terminal EM1 is the first light-emitting control terminal in the nth row, where n is a positive integer.

[0176] Figure 10 is a timing diagram of at least one embodiment shown in Figure 9.

[0177] In at least one embodiment of the pixel circuit shown in Figure 9, through timing optimization, the first and second light-emitting control signals are provided through the same GOA module. T6 is controlled by staggered row transmission, saving the number of GOA signals in the pixel circuit. The number of GOA module groups used in the display panel is reduced from six to five, achieving a narrow bezel effect. The number of rows the light-emitting control signals are staggered is not limited and can be changed according to simulation or functional requirements.

[0178] The difference between at least one embodiment of the pixel circuit shown in Figure 11 and at least one embodiment of the pixel circuit shown in Figure 7 is that the gate of T7 is electrically connected to the second reset control terminal R2.

[0179] The second reset control terminal R2 and the third reset control terminal are the same control terminal.

[0180] Figure 12 is a timing diagram of at least one embodiment of the pixel circuit shown in Figure 11.

[0181] At least one embodiment of the pixel circuit shown in Figure 11 of this disclosure, during operation, optimizes timing by controlling the gates of T5 and T7 through the same GOA module, controlling T5 and T7 to be turned on simultaneously, resetting the potential of N3 through Vinit1, and resetting the potential of the anode of O1 through Vinit2. At least one embodiment of this disclosure can reduce the number of GOA signals in the pixel circuit, reducing the number of GOA module groups used in the display panel from six to five, thus achieving a narrow bezel effect.

[0182] The differences between at least one embodiment of the pixel circuit shown in FIG13 of this disclosure and at least one embodiment of the pixel circuit shown in FIG7 of this disclosure are as follows:

[0183] T3 and T6 are p-type transistors, and T3 and T6 are LTPS transistors.

[0184] Figure 14 is a timing diagram of at least one embodiment of the pixel circuit shown in Figure 13 of this disclosure.

[0185] In at least one embodiment of the pixel circuit shown in FIG13 of this disclosure, T3 and T6 are set as LTPS transistors, which is beneficial for high PPI layout and space node optimization. At the same time, LTPS has a high mobility, which can quickly turn on and reduce the brightness difference caused by the mobility or threshold voltage fluctuation of oxide transistors.

[0186] The difference between at least one embodiment of the pixel circuit shown in FIG15 of this disclosure and at least one embodiment of the pixel circuit shown in FIG7 of this disclosure is as follows: T1 is an LTPS transistor.

[0187] In at least one embodiment of the pixel circuit shown in FIG15 of this disclosure, replacing T1 with an LTPS transistor can increase the data voltage write current and improve the data voltage write efficiency at high frequencies.

[0188] The differences between at least one embodiment of the pixel circuit shown in Figure 16 of this disclosure and at least one embodiment of the pixel circuit shown in Figure 7 of this disclosure are as follows:

[0189] The gate of T6 is electrically connected to the first light-emitting control terminal EM1(n+3) in the (n+3)th row;

[0190] The gate of T7 is electrically connected to the second reset control terminal R2;

[0191] T3 and T6 are p-type transistors, and T3 and T6 are LTPS transistors; T1 is a p-type transistor.

[0192] In at least one embodiment of the pixel circuit shown in Figure 16, the first light-emitting control terminal EM1 is the first light-emitting control terminal of the nth row, where n is a positive integer;

[0193] In at least one embodiment of the pixel circuit shown in Figure 16, the first and second light-emitting control signals are provided through the same GOA module, and the second and third reset control signals are provided through the same GOA module, thereby reducing the number of GOA modules used. In at least one embodiment of the pixel circuit shown in Figure 17 of this disclosure, the number of GOA modules used is reduced from six to four, which is beneficial for achieving a narrow bezel. Simultaneously, in at least one embodiment of the pixel circuit shown in Figure 16 of this disclosure, T1 is set as an LTPS transistor, which can increase the data voltage write current and improve the data voltage write efficiency at high frequencies. In at least one embodiment of the pixel circuit shown in Figure 16 of this disclosure, T3 and T6 are set as LTPS transistors, which is beneficial for high PPI layout and space node optimization. At the same time, LTPS transistors have high mobility, allowing for rapid start-up and reducing brightness differences caused by fluctuations in the mobility or threshold voltage of oxide transistors.

[0194] At least one embodiment of this disclosure replaces the transistor used for light emission control with an LTPS transistor, which can increase the turn-on current Ion, improve the transistor mobility, enhance signal writing capability, and reduce power consumption.

[0195] Figure 17 is a timing diagram of at least one embodiment of the pixel circuit shown in Figure 16.

[0196] The above-mentioned solutions for replacing oxide transistors with LTPS transistors can be combined in various ways to meet different functional requirements and for replacement purposes, and are not limited to the above embodiments.

[0197] The pixel driving method described in this disclosure is applied to the pixel circuit described above, and the display cycle includes a reset phase and a data writing phase.

[0198] During the reset phase, the set circuit, under the control of the set control signal, writes the first voltage signal into the fourth node so that it can bias the potential of the second gate of the driving transistor. By providing the same voltage signal to the second gate of the driving transistor in the multi-row and multi-column pixel circuit of the display panel during the reset phase, the threshold voltage uniformity of the driving transistor in the multiple pixel circuits of the display panel is controlled and guaranteed.

[0199] During the data writing phase, the data writing circuit writes the data voltage to the first node under the control of the scanning signal.

[0200] In the pixel driving method described in this embodiment, the data voltage writing and threshold voltage compensation are designed separately, requiring less scanning time per line. This ensures that the data voltage writing time is guaranteed during high-frequency display, and that the pixel circuit is fully charged by the data voltage while ensuring display uniformity, thus guaranteeing the display effect.

[0201] In at least one embodiment of this disclosure, the pixel circuit further includes a first initialization circuit and a second initialization circuit; the pixel driving method further includes:

[0202] During the reset phase, the first initialization circuit, under the control of the first reset control signal, writes the first initial voltage into the first node, and the second initialization circuit, under the control of the second reset control signal, writes the first initial voltage into the third node.

[0203] In specific implementation, during the reset phase, the first initialization circuit, under the control of the first reset control signal, writes the first initial voltage into the first node, and the second initialization circuit, under the control of the second reset control signal, writes the first initial voltage into the third node, so that the gate-source voltage of the driving transistor is equal to 0. Under the premise that the gate-source voltage of the driving transistor is equal to 0, the second gate of the driving transistor is set by the first voltage signal, which can set the threshold voltage of the driving transistor, so as to control and ensure the uniformity of the threshold voltage of the driving transistors in the multiple pixel circuits included in the display panel.

[0204] The display device described in this disclosure includes the pixel circuit described above.

[0205] The above description represents the preferred embodiments of this disclosure. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles described herein, and these improvements and modifications should also be considered within the scope of protection of this disclosure.

Claims

1. A pixel circuit, comprising a driving circuit, a data writing circuit, and a setting circuit; the driving circuit includes a driving transistor; the driving transistor includes a first gate, a second gate, a first electrode, and a second electrode; The first gate of the driving transistor is electrically connected to the first node, the first electrode of the driving transistor is electrically connected to the second node, the second electrode of the driving transistor is electrically connected to the third node, and the second gate of the driving transistor is electrically connected to the fourth node. The data writing circuit is electrically connected to the scanning end, the data line and the first node respectively, and is used to write the data voltage provided by the data line into the first node under the control of the scanning signal provided by the scanning end; The set circuit is electrically connected to the set control terminal, the first voltage terminal and the fourth node respectively, and is used to write the first voltage signal provided by the first voltage terminal into the fourth node under the control of the set control signal provided by the set control terminal.

2. The pixel circuit as described in claim 1, wherein, It also includes a first initialization circuit and a second initialization circuit; The first initialization circuit is electrically connected to the first reset control terminal, the first initial voltage terminal and the first node respectively, and is used to write the first initial voltage provided by the first initial voltage terminal into the first node under the control of the first reset control signal provided by the first reset control terminal. The second initialization circuit is electrically connected to the second reset control terminal, the first initial voltage terminal and the third node, respectively, and is used to write the first initial voltage into the third node under the control of the second reset control signal provided by the second reset control terminal.

3. The pixel circuit as described in claim 1, wherein, It also includes a first energy storage circuit; The first end of the first energy storage circuit is electrically connected to the fourth node, and the second end of the first energy storage circuit is electrically connected to the third node.

4. The pixel circuit as described in claim 1, wherein, The first gate is a top gate, and the second gate is a bottom gate.

5. The pixel circuit as described in claim 1, wherein, The driving transistor is an n-type transistor, and the voltage value of the first voltage signal provided by the first voltage terminal is greater than 0; or, the driving transistor is a p-type transistor, and the voltage value of the first voltage signal is less than 0.

6. The pixel circuit according to any one of claims 1 to 5, wherein, The setting circuit includes an on / off control circuit and a first light-emitting control circuit, and the setting control terminal includes a first reset control terminal and a first light-emitting control terminal. The on / off control circuit is electrically connected to the first reset control terminal, the second node, and the fourth node, respectively, and is used to control the connection between the second node and the fourth node under the control of the first reset control signal provided by the first reset control terminal; The first light-emitting control circuit is electrically connected to the first light-emitting control terminal, the first voltage terminal, and the second node, respectively, and is used to control the connection between the first voltage terminal and the second node under the control of the first light-emitting control signal provided by the first light-emitting control terminal.

7. The pixel circuit according to any one of claims 1 to 5, wherein, It also includes a second energy storage circuit; The first end of the second energy storage circuit is electrically connected to the first node, and the second end of the second energy storage circuit is electrically connected to the third node.

8. The pixel circuit as described in claim 6, wherein, It also includes a light-emitting element, a second light-emitting control circuit, and a third initialization circuit; The second light-emitting control circuit is electrically connected to the second light-emitting control terminal, the third node, and the first electrode of the light-emitting element, respectively, and is used to control the connection between the third node and the first electrode of the light-emitting element under the control of the second light-emitting control signal provided by the second light-emitting control terminal; The third initialization circuit is electrically connected to the third reset control terminal, the second initial voltage terminal, and the first electrode of the light-emitting element, respectively, and is used to write the second initial voltage provided by the second initial voltage terminal into the first electrode of the light-emitting element under the control of the third reset control signal provided by the third reset control terminal. The second electrode of the light-emitting element is electrically connected to the second voltage terminal.

9. The pixel circuit as described in claim 8, wherein, The transistors included in the first light-emitting control circuit and the transistors included in the second light-emitting control circuit are both n-type transistors or both p-type transistors. The first light-emitting control terminal is the nth-level light-emitting control terminal, and the second light-emitting control terminal is the (n+a)th-level light-emitting control circuit, where n and a are both positive integers.

10. The pixel circuit as claimed in claim 8, wherein, The pixel circuit further includes a first initialization circuit and a second initialization circuit. The second reset control terminal is the same as the third reset control terminal.

11. The pixel circuit as claimed in claim 3, wherein, The data writing circuit includes a first transistor; the first energy storage circuit includes a first capacitor. The gate of the first transistor is electrically connected to the scan terminal, the first electrode of the first transistor is electrically connected to the data line, and the second electrode of the first transistor is electrically connected to the first node. The first terminal of the first capacitor is electrically connected to the fourth node, and the second terminal of the first capacitor is electrically connected to the third node.

12. The pixel circuit as claimed in claim 11, wherein, The first transistor is a low-temperature polycrystalline silicon transistor.

13. The pixel circuit as claimed in claim 6, wherein, The on / off control circuit includes a second transistor, and the first light-emitting control circuit includes a third transistor; The gate of the second transistor is electrically connected to the first reset control terminal, the first terminal of the second transistor is electrically connected to the second node, and the second terminal of the second transistor is electrically connected to the fourth node. The gate of the third transistor is electrically connected to the first light-emitting control terminal, the first electrode of the third transistor is electrically connected to the first voltage terminal, and the second electrode of the third transistor is electrically connected to the second node.

14. The pixel circuit as claimed in claim 13, wherein, The third transistor is a low-temperature polycrystalline silicon transistor.

15. The pixel circuit as claimed in claim 2, wherein, The first initialization circuit includes a fourth transistor, and the second initialization circuit includes a fifth transistor; The gate of the fourth transistor is electrically connected to the first reset control terminal, the first terminal of the fourth transistor is electrically connected to the first initial voltage terminal, and the second terminal of the fourth transistor is electrically connected to the first node. The gate of the fifth transistor is electrically connected to the second reset control terminal, the first terminal of the fifth transistor is electrically connected to the first initial voltage terminal, and the second terminal of the fifth transistor is electrically connected to the third node.

16. The pixel circuit as claimed in claim 7, wherein, The second energy storage circuit includes a second capacitor; The first end of the second capacitor is electrically connected to the first node, and the second end of the second capacitor is electrically connected to the third node.

17. The pixel circuit as claimed in claim 8, wherein, The second light-emitting control circuit includes a sixth transistor, and the third initialization circuit includes a seventh transistor; The gate of the sixth transistor is electrically connected to the second light-emitting control terminal, the first terminal of the sixth transistor is electrically connected to the third node, and the second terminal of the sixth transistor is electrically connected to the first terminal of the light-emitting element. The gate of the seventh transistor is electrically connected to the third reset control terminal, the first terminal of the seventh transistor is electrically connected to the second initial voltage terminal, and the second terminal of the seventh transistor is electrically connected to the first terminal of the light-emitting element.

18. The pixel circuit of claim 17, wherein, The sixth transistor is a low-temperature polycrystalline silicon transistor.

19. A pixel driving method, applied to a pixel circuit as described in any one of claims 1 to 18, wherein the display cycle includes a reset phase and a data writing phase; During the reset phase, the set circuit, under the control of the set control signal, writes the first voltage signal into the fourth node; During the data writing phase, the data writing circuit writes the data voltage to the first node under the control of the scanning signal.

20. The pixel driving method as described in claim 19, wherein, The pixel circuit further includes a first initialization circuit and a second initialization circuit. The pixel driving method further includes: During the reset phase, the first initialization circuit, under the control of the first reset control signal, writes the first initial voltage into the first node, and the second initialization circuit, under the control of the second reset control signal, writes the first initial voltage into the third node.

21. A display device comprising a pixel circuit as described in any one of claims 1 to 18.

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