Display panel and display apparatus

Abstract

A display panel and a display apparatus. The display panel comprises: a plurality of pixel driving circuits (R, G, B), a plurality of data lines (Da), a source driving circuit, a plurality of data connection lines (DL), a plurality of gate lines (Gs) and a gate driving circuit; one end of each data connection line (DL) is connected to the source driving circuit, and the other end of each data connection line (DL) is connected to a plurality of data lines (Da), the source driving circuit being used for providing data signals to the plurality of data lines (Da) by means of the data connection lines (DL); the gate driving circuit provides gate driving signals to the pixel driving circuits (R, G, B) by means of the gate lines (Gs); the plurality of data lines (Da) form a plurality of data line groups (Daz1, Daz2), each data line group (Daz1, Daz2) comprising a plurality of data lines (Da), and a plurality of data lines (Da) connected to a same data connection line (DL) being in different data line groups (Daz1, Daz2); the gate driving circuit is used for controlling the pixel driving circuits (R, G, B) connected to the different data line groups (Daz1, Daz2) to perform time-division scanning, the scanning of the pixel driving circuits (R, G, B) comprising writing data signals into the pixel driving circuits (R, G, B). The configuration of the display panel can improve the display effect of the display panel.

Description

Display panel and display device

[0001] Cross-reference to related applications

[0002] This application claims priority to Chinese Patent Application No. 202411196102.5, filed on August 28, 2024, entitled “Display Panel and Display Device”, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] This disclosure relates to the field of display technology, and more particularly to a display panel and a display device. Background Technology

[0004] In related technologies, a single data connection line connects multiple data lines through multiple switching transistors. This configuration can cause leakage current in the data lines through the switching transistors, thereby affecting the display effect.

[0005] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0006] According to one aspect of this disclosure, a display panel is provided, wherein the display panel includes:

[0007] Multiple pixel driving circuits are arranged in an array along a first direction and a second direction, the first direction and the second direction intersecting;

[0008] Multiple data lines, the data lines being connected to multiple pixel driving circuits distributed in the second direction;

[0009] Source drive circuit;

[0010] Multiple data connection lines are provided, one end of which is connected to the source drive circuit, and the other end of which is connected to multiple data lines. The source drive circuit is used to provide data signals to the multiple data lines through the data connection lines.

[0011] Multiple gate lines, the gate lines being connected to multiple pixel driving circuits distributed in the first direction;

[0012] A gate driving circuit provides a gate driving signal to the pixel driving circuit through the gate line;

[0013] The multiple data lines form multiple data line groups, and each data line group includes multiple data lines, with the multiple data lines connected to the same data connection line located in different data line groups.

[0014] The gate driving circuit is used to control the pixel driving circuits connected to different data line groups to perform time-division scanning, and the scanning of the pixel driving circuit includes writing the data signal to the pixel driving circuit.

[0015] In one exemplary embodiment of this disclosure, the plurality of gate lines include a plurality of scan gate lines, and the same scan gate line connects at least a portion of the pixel driving circuits connected to different data line groups.

[0016] In one exemplary embodiment of this disclosure, the pixel driving circuit includes:

[0017] One or more switching circuits are connected between two nodes and are also connected to the scan grid line. The switching circuits are used to turn on the two nodes in response to a signal from the scan grid line.

[0018] One or more control circuits are provided, corresponding to the switching circuit. The control circuit and the corresponding switching circuit are connected in series between the two nodes. The control circuit is connected to a control signal terminal and is used to respond to the signal of the control signal terminal to turn on the two nodes.

[0019] The pixel driving circuits connected to different data line groups are connected to different control signal terminals.

[0020] In one exemplary embodiment of this disclosure, pixel driving circuits connected to the same data line group form a pixel driving circuit group. The control signal terminal is used to output an on level when the pixel driving circuit connected to it is in a scanning period, and the control signal terminal is used to output an off level when the pixel driving circuit group to which the pixel driving circuit connected to it is in a non-scanning period.

[0021] In one exemplary embodiment of this disclosure, the plurality of scanning gate lines includes a first gate line, and one or more switching circuits include:

[0022] A data writing circuit is connected to a data writing node, a data line, and a first gate line. The data writing circuit is used to respond to a signal from the first gate line to connect the data writing node and the data line.

[0023] One or more control circuits include:

[0024] A first control circuit is connected in series with the data writing circuit between the data writing node and the data line. The first control circuit is also connected to a control signal terminal. The first control circuit is used to respond to the signal of the control signal terminal to connect the data writing node and the data line.

[0025] The gate driving circuit is used to control the pixel driving circuits connected to different data line groups to write the data signal in a time-division manner through the first gate line.

[0026] In one exemplary embodiment of this disclosure, the display panel further includes a light-emitting unit, and the pixel driving circuit further includes:

[0027] A driving transistor that provides a driving current to the light-emitting unit according to its gate voltage;

[0028] The multiple scan gate lines include a reset signal line, and one or more switching circuits include:

[0029] A first reset circuit is connected to the reset signal line, the gate of the driving transistor, and the initial signal line. The first reset circuit is used to respond to the signal of the reset signal line to turn on the gate of the driving transistor and the initial signal line.

[0030] The second reset circuit is connected to the reset signal line, the first electrode of the light-emitting unit, and the initial signal line. The second reset circuit is used to respond to the signal of the reset signal line to turn on the first electrode of the light-emitting unit and the initial signal line.

[0031] A compensation circuit is connected to the first gate line, the gate of the driving transistor, and the second terminal of the driving transistor. The compensation circuit is used to respond to the signal of the first gate line to connect the gate of the driving transistor and the second terminal of the driving transistor.

[0032] One or more control circuits include:

[0033] The second control circuit and the first reset circuit are connected in series between the gate of the driving transistor and the initial signal line, and the second control circuit and the compensation circuit are connected in series between the gate of the driving transistor and the second terminal of the driving transistor. The second control circuit is also connected to the control signal terminal. The second control circuit is used to respond to the signal of the control signal terminal to turn on the gate of the driving transistor and the second terminal of the driving transistor, and to turn on the gate of the driving transistor and the initial signal line.

[0034] The third control circuit and the second reset circuit are connected in series between the first electrode of the light-emitting unit and the initial signal line. The third control circuit is also connected to the control signal terminal. The third control circuit is used to respond to the signal of the control signal terminal to turn on the first electrode of the light-emitting unit and the initial signal line.

[0035] The scanning of the pixel driving circuit includes inputting the signal of the initial signal line to the first electrode of the light-emitting unit and the gate of the driving transistor. The gate driving circuit is used to control the pixel driving circuits connected to different data line groups to write the initial signal of the initial signal line to the first electrode of the light-emitting unit and the gate of the driving transistor in a time-division manner through the reset signal line.

[0036] In one exemplary embodiment of this disclosure, the first electrode of the driving transistor forms the data writing node, and the data writing circuit includes:

[0037] A fourth transistor, wherein the first terminal of the fourth transistor is connected to the data line, and the gate is connected to the first gate line;

[0038] The first control circuit includes:

[0039] The eighth transistor has its first terminal connected to the second terminal of the fourth transistor, the second terminal connected to the data writing node, and its gate connected to the control signal terminal.

[0040] The first reset circuit includes:

[0041] A first transistor, wherein the first terminal of the first transistor is connected to the initial signal line and the gate is connected to the reset signal line;

[0042] The compensation circuit includes:

[0043] The second transistor has its second terminal connected to the second terminal of the driving transistor, and its gate connected to the first gate line;

[0044] The second control circuit includes:

[0045] The ninth transistor has its first terminal connected to the second terminal of the first transistor and the first terminal of the second transistor, its second terminal connected to the gate of the driving transistor, and its gate connected to the control signal terminal.

[0046] The second reset circuit includes:

[0047] The seventh transistor has its first terminal connected to the initial signal line and its gate connected to the reset signal line.

[0048] The third control circuit includes:

[0049] The tenth transistor has its first electrode connected to the second electrode of the seventh transistor, the second electrode connected to the first electrode of the light-emitting unit, and its gate connected to the control signal terminal.

[0050] In one exemplary embodiment of this disclosure, the initial signal line is multiplexed as the control signal terminal in the same pixel driving circuit.

[0051] In one exemplary embodiment of this disclosure, the pixel driving circuit includes:

[0052] One or more switching circuits, wherein the control terminal of the switching circuit is connected to the scan grid line;

[0053] One or more gating circuits are provided, and the gating circuits and the switching circuits are correspondingly provided. The switching circuits are connected to the scanning grid lines through the gating circuits they correspond to. The gating circuits are also connected to gating signal terminals. The gating circuits are used to respond to the signals of the gating signal terminals to turn on the control terminals of the switching circuits and the scanning grid lines.

[0054] The pixel driving circuits connected to different data line groups are connected to different gating signal terminals.

[0055] In one exemplary embodiment of this disclosure, the plurality of scanning gate lines includes a first gate line, and one or more switching circuits include:

[0056] A data writing circuit is connected to a data writing node, the data line, and a first gate line. The data writing circuit is used to respond to a signal from the first gate line to connect the data writing node and the data line.

[0057] One or more gating circuits include:

[0058] A first gating circuit, wherein the data writing circuit is connected to the first gate line through the first gating circuit, and the first gating circuit is used to respond to the signal of the gating signal terminal to connect the data writing circuit and the first gate line;

[0059] The gate driving circuit is used to control the pixel driving circuits connected to different data line groups to write the data signal in a time-division manner through the first gate line.

[0060] In one exemplary embodiment of this disclosure, the display panel further includes a light-emitting unit, and the pixel driving circuit further includes:

[0061] A driving transistor that provides a driving current to the light-emitting unit according to its gate voltage;

[0062] The multiple scan gate lines include a reset signal line, and one or more switching circuits include:

[0063] A first reset circuit is connected to the reset signal line, the gate of the driving transistor, and the initial signal line. The first reset circuit is used to respond to the signal of the reset signal line to turn on the gate of the driving transistor and the initial signal line.

[0064] The second reset circuit is connected to the reset signal line, the first electrode of the light-emitting unit, and the initial signal line. The second reset circuit is used to respond to the signal of the reset signal line to turn on the first electrode of the light-emitting unit and the initial signal line.

[0065] A compensation circuit is connected between the gate of the driving transistor and the second terminal of the driving transistor. The compensation circuit is connected to the first gate line through the first gating circuit. The compensation circuit is used to respond to the signal of the first gate line to conduct the gate of the driving transistor and the second terminal of the driving transistor.

[0066] One or more gating circuits include:

[0067] The second gating circuit connects the first reset circuit and the second reset circuit to the reset signal line. The second gating circuit is used to respond to the signal at the gating signal terminal to connect the reset signal line and the first reset circuit and the second reset circuit.

[0068] The scanning of the pixel driving circuit includes inputting an initial signal of the initial signal line to the first electrode of the light-emitting unit and the gate of the driving transistor;

[0069] The gate driving circuit is used to control the pixel driving circuits connected to different data line groups to write the initial signal of the initial signal line to the first electrode of the light-emitting unit and the gate of the driving transistor in a time-division manner through the reset signal line.

[0070] In one exemplary embodiment of this disclosure, the first electrode of the driving transistor forms the data writing node, and the data writing circuit includes:

[0071] The fourth transistor has its first terminal connected to the data line and its second terminal connected to the first terminal of the driving transistor.

[0072] The compensation circuit includes:

[0073] The second transistor has a first terminal connected to the gate of the driving transistor and a second terminal connected to the second terminal of the driving transistor.

[0074] The first gating circuit includes:

[0075] The eighth transistor has its first terminal connected to the first gate line, its second terminal connected to the gate of the fourth transistor and the gate of the second transistor, and its gate connected to the strobe signal terminal.

[0076] The first reset circuit includes:

[0077] A first transistor, wherein a first terminal of the first transistor is connected to the initial signal line and a second terminal is connected to the gate of the driving transistor;

[0078] The second reset circuit includes:

[0079] The seventh transistor has its first electrode connected to the initial signal line and its second electrode connected to the first electrode of the light-emitting unit.

[0080] The second gating circuit includes:

[0081] The tenth transistor has its first terminal connected to the reset signal line, and its second terminal connected to the gate of the first transistor and the gate of the seventh transistor. The gate of the transistor is connected to the strobe signal terminal.

[0082] In one exemplary embodiment of this disclosure, the plurality of gate lines include a plurality of scan gate lines, the first direction is the row direction, and a row of pixel driving circuits is provided with a plurality of the same type of scan gate lines. In the plurality of the same type of scan gate lines corresponding to a row of pixel driving circuits, the scan gate lines are connected to the pixel driving circuits connected to the same data line group, and the pixel driving circuits connected to different data line groups are connected to different scan gate lines.

[0083] In one exemplary embodiment of this disclosure, the display panel further includes:

[0084] Multiple selection circuits are provided, and multiple selection circuits are provided for each row of pixel driving circuits. Multiple selection circuits and multiple scan gate lines of the same type are provided in a one-to-one correspondence with the multiple selection circuits corresponding to the same row of pixel driving circuits. Multiple scan gate lines of the same type corresponding to a row of pixel driving circuits are respectively connected to the same signal output terminal of the gate driving circuit through their corresponding selection circuits.

[0085] The gating circuit is connected to the gating signal terminal, and the gating circuit is used to respond to the signal of the gating signal terminal to conduct the output terminal of the scan gate line and the gate driving circuit.

[0086] Among them, the gating circuits corresponding to the pixel driving circuits that connect different data line groups are connected to different gating signal terminals.

[0087] In one exemplary embodiment of this disclosure, pixel driving circuits connected to the same data line group form a pixel driving circuit group. The strobe signal terminal is used to output a conduction level when the pixel driving circuit connected to it is in a scanning period, and the strobe signal terminal is used to output a shutdown level when the pixel driving circuit group to which the pixel driving circuit connected to it is in a non-scanning period.

[0088] In one exemplary embodiment of this disclosure, the gate driving circuit includes a plurality of sub-gate driving circuits. Multiple identical scanning gate lines corresponding to the same row of pixel driving circuits are respectively configured to correspond to the plurality of sub-gate driving circuits. The plurality of sub-gate driving circuits are respectively used to scan the pixel driving circuits connected to them at different time periods.

[0089] In one exemplary embodiment of this disclosure, the second direction is a column direction, and the display panel includes a plurality of pixel units, the pixel units including a plurality of pixel driving circuits adjacent to each other in the first direction;

[0090] The data line group connects multiple columns of the pixel units.

[0091] In one exemplary embodiment of this disclosure, multiple data lines form two data line groups, one data line group connecting the pixel units in odd-numbered columns and the other data line group connecting the pixel units in even-numbered columns.

[0092] In one exemplary embodiment of this disclosure, the data connection line and the data cable are directly connected.

[0093] According to one aspect of this disclosure, a display device is provided, wherein the display device includes the display panel described above.

[0094] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0095] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0096] Figure 1 is a schematic diagram of the pixel driving circuit in an exemplary embodiment of the display panel of this disclosure;

[0097] Figure 2 is a timing diagram of each node in a driving method of the pixel driving circuit shown in Figure 1;

[0098] Figure 3 is a schematic diagram of the structure of an exemplary embodiment of the display panel of this disclosure;

[0099] Figure 4 is a schematic diagram of the connection structure of the source drive circuit and data line in a display panel.

[0100] Figure 5 is a timing diagram of each node in one driving method of the display panel shown in Figure 4;

[0101] Figure 6 is a schematic diagram of the structure of an exemplary embodiment of the display panel of this disclosure;

[0102] Figure 7 is a schematic diagram of the pixel driving circuit in the display panel shown in Figure 6;

[0103] Figure 8 is a timing diagram of each node in one driving method of the display panel shown in Figure 6;

[0104] Figure 9 is a schematic diagram of the pixel driving circuit in another exemplary embodiment of the display panel shown in Figure 6;

[0105] Figure 10 is a timing diagram of each node in a driving method for the display panel shown in Figure 6;

[0106] Figure 11 is a schematic diagram of another exemplary embodiment of the display panel of this disclosure;

[0107] Figure 12 is a timing diagram of each node in a driving method for the display panel shown in Figure 11;

[0108] Figure 13 is a schematic diagram of the gate driving circuit in an exemplary embodiment of the display panel of this disclosure;

[0109] Figure 14 is a schematic diagram of another exemplary embodiment of the display panel of this disclosure;

[0110] Figure 15 is a schematic diagram of the gate driving circuit in an exemplary embodiment of the display panel shown in Figure 14;

[0111] Figure 16 is a schematic diagram of the gate drive circuit in another exemplary embodiment of the display panel shown in Figure 14. Detailed Implementation

[0112] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, they are provided so that this disclosure will be more comprehensive and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore their detailed description will be omitted.

[0113] The terms “a,” “one,” and “the” are used to indicate the existence of one or more elements / components / etc.; the terms “including” and “having” are used to indicate an open-ended meaning of inclusion and that there may be other elements / components / etc. in addition to the listed elements / components / etc.

[0114] In the description of this disclosure, unless otherwise expressly specified and limited, the terms “first” and “second” are used for descriptive purposes only and should not be construed as indicating or implying relative importance; the term “multiple” refers to two or more; and the term “and / or” includes any and all combinations of one or more associated listed items. In particular, references to “the / described” object or “a” object are also intended to indicate one of a possible plurality of such objects.

[0115] Unless otherwise specified or stated, the terms "connection," "fixed," etc., should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, an integral connection, an electrical connection, or a signal connection; "connection" can be a direct connection or an indirect connection through an intermediate medium. Those skilled in the art can understand the specific meaning of the above terms in this disclosure according to the specific circumstances.

[0116] Furthermore, it should be understood that the directional terms such as "upper," "lower," "inner," and "outer" described in the exemplary embodiments of this disclosure are used to describe the angles shown in the accompanying drawings and should not be construed as limiting the exemplary embodiments of this disclosure. It should also be understood that, in the context of an element or feature being connected to one or more "upper," "lower," "inner," or "outer" elements, it can be directly connected to one or more "upper," "lower," "inner," or "outer" elements, or indirectly connected to one or more "upper," "lower," "inner," or "outer" elements through intermediate elements.

[0117] Figure 1 shows a schematic diagram of the pixel driving circuit in an exemplary embodiment of the display panel of this disclosure. The pixel driving circuit may include: a driving transistor T3, a first transistor T1, a second transistor T2, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a capacitor C. In this circuit, the first electrode of the fourth transistor T4 is connected to the data line Da, the second electrode is connected to the first electrode of the driving transistor T3, and the gate is connected to the first gate line G1; the first electrode of the fifth transistor T5 is connected to the first power supply line VDD, the second electrode is connected to the first electrode of the driving transistor T3, and the gate is connected to the enable signal line EM; the gate of the driving transistor T3 is connected to node N; the first electrode of the second transistor T2 is connected to node N, the second electrode is connected to the second electrode of the driving transistor T3, and the gate is connected to the first gate line G1; the first electrode of the sixth transistor T6 is connected to the second electrode of the driving transistor T3, the second electrode is connected to the second electrode of the seventh transistor T7, and the gate is connected to the enable signal line EM; the first electrode of the seventh transistor T7 is connected to the initial signal line Vinit, and the gate is connected to the reset signal line Re; the second electrode of the first transistor T1 is connected to node N, the first electrode is connected to the initial signal line Vinit, and the gate is connected to the reset signal line Re; the first electrode of the capacitor C is connected to node N, and the second electrode is connected to the first power supply line VDD. This pixel driving circuit can be connected to a light-emitting unit L, which is used to drive the light-emitting unit L to emit light. The first electrode of the light-emitting unit L can be connected to the second electrode of the sixth transistor T6, and the second electrode of the light-emitting unit L is connected to the second power supply terminal VSS. Among them, the first transistor T1, the second transistor T2, the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 can be P-type transistors.

[0118] Figure 2 shows the timing diagram of each node in one driving method of the pixel driving circuit shown in Figure 1. Here, EM represents the timing diagram of the enable signal line, Re represents the timing diagram of the reset signal line, and G1 represents the timing diagram of the first gate line.

[0119] The pixel driving circuit driving method may include a reset phase t1, a data writing phase t2, and a light-emitting phase t3. In the reset phase, the reset signal line Re outputs a low-level signal, the first transistor T1 and the seventh transistor T7 are turned on, and the initial signal line Vinit inputs an initial signal to the gate of the driving transistor T3 and the first electrode of the light-emitting unit. In the data writing phase, the first gate line G1 outputs a low-level signal, the second transistor T2 and the fourth transistor T4 are turned on, and simultaneously the data line Da outputs a data signal to write a compensation voltage Vdata+Vth to node N, where Vdata is the voltage of the data signal and Vth is the threshold voltage of the driving transistor T3. In the light-emitting phase: the enable signal line EM outputs a low-level signal, the sixth transistor T6 and the fifth transistor T5 are turned on, and the driving transistor T3 drives the light-emitting unit to emit light under the action of the compensation voltage Vdata+Vth stored in capacitor C. In this pixel driving circuit, the output current of the driving transistor I = (μWCox / 2L)(Vdata+Vth-Vdd-Vth) 2 This pixel driving circuit can avoid the influence of the driving transistor threshold on its output current. Where I is the driving transistor output current; μ is the carrier mobility; Cox is the gate capacitance per unit area; W is the width of the driving transistor channel; L is the length of the driving transistor channel; Vgs is the gate-source voltage difference of the driving transistor; and Vth is the driving transistor threshold voltage.

[0120] Figure 3 shows a schematic diagram of an exemplary embodiment of the display panel of this disclosure. The display panel may include a timing controller, a source driving circuit, a gate driving circuit, and a pixel array. The timing controller is connected to both the source driving circuit and the gate driving circuit. The source driving circuit is connected to multiple data lines (Da1 to Dan). The gate driving circuit includes a scan driving circuit and a light-emitting driving circuit. The scan driving circuit is connected to multiple scan gate lines (S1 to Sm), and the light-emitting driving circuit is connected to multiple enable signal lines (E1 to Eo). The scan gate lines and enable signal lines form gate lines. The pixel array may include multiple sub-pixels Pxij, where i and j can be natural numbers. At least one sub-pixel Pxij may include a pixel driving circuit and a light-emitting unit connected to the pixel driving circuit. The pixel driving circuit may be connected to the scan gate lines, enable signal lines, and data lines, respectively. In an exemplary embodiment, the timing controller can provide grayscale values ​​and control signals of specifications suitable for the source driver circuit to the source driver circuit, clock signals, scan start signals, etc. of specifications suitable for the scan driver circuit to the scan driver circuit, and clock signals, transmit stop signals, etc. of specifications suitable for the light-emitting driver circuit to the light-emitting driver circuit. The source driver circuit can use the grayscale values ​​and control signals received from the timing controller to generate data voltages to be provided to data lines Da1, Da2, Da3, ..., Dan. For example, the source driver circuit can sample the grayscale values ​​using a clock signal and apply the data voltage corresponding to the grayscale values ​​to data lines Da1 to Dan on a pixel-by-pixel basis, where n can be a natural number. The scan driver circuit can generate scan signals to be provided to scan gate lines S1, S2, S3, ..., Sm by receiving clock signals, scan start signals, etc. from the timing controller. For example, the scan driver circuit can sequentially provide scan signals with conduction level pulses to scan gate lines S1 to Sm. For example, the scan driver circuit can be configured as a shift register and can generate scan signals by sequentially transmitting scan start signals, provided in the form of on-level pulses, to the next stage circuit under the control of a clock signal, where m can be a natural number. The light-emitting driver circuit can generate transmit signals to be provided to enable signal lines E1, E2, E3, ..., Eo by receiving clock signals, transmit stop signals, etc., from a timing controller. For example, the light-emitting driver circuit can sequentially provide transmit signals with cutoff level pulses to enable signal lines E1 to Eo. For example, the light-emitting driver circuit can be configured as a shift register and can generate transmit signals by sequentially transmitting transmit stop signals, provided in the form of cutoff level pulses, to the next stage circuit under the control of a clock signal, where o can be a natural number.

[0121] In related technologies, as shown in Figure 4, a schematic diagram of the connection structure of the source driving circuit and data lines in a display panel is presented. One data output terminal of the source driving circuit can be connected to two data lines Da through a data connection line DL. The data connection line DL is connected to different data lines Da through switching transistors Tx1 and Tx2 respectively. The gate of switching transistor Tx1 is connected to the first gating signal terminal MUX1, and the gate of switching transistor Tx2 is connected to the second gating signal terminal MUX2. Figure 5 shows the timing diagram of each node in a driving method for the display panel shown in Figure 4. Here, EM represents the timing diagram of the enable signal line in the pixel driving circuit, Re represents the timing diagram of the reset signal line in the pixel driving circuit, G1 represents the timing diagram of the first gate line in the pixel driving circuit, MUX1 represents the timing diagram of the first gating signal terminal, and MUX2 represents the timing diagram of the second gating signal terminal. In the pixel driving circuit, after the reset phase t1 and before the data writing phase t2, the first strobe signal terminal MUX1 and the second strobe signal terminal MUX2 sequentially turn on the switching transistors Tx1 and Tx2. The source driving circuit inputs a data signal to the data line Da connected to the switching transistor Tx1 during the first time period ta, and then inputs a data signal to the data line Da connected to the switching transistor Tx2 during the second time period tb, thereby realizing data writing to all data lines. This setup saves on the number of source driving circuits and also facilitates the configuration of the data connection lines DL.

[0122] However, as shown in Figure 5, the data writing stage t2 of the pixel driving circuit needs to be performed after the first time period ta and the second time period tb. Due to the turn-off leakage current of the switching transistor, the data signal on the data line Da will leak through the switching transistor Tx1 in the second time period tb, which will cause display abnormalities such as vertical lines on the display panel.

[0123] Based on this, this exemplary embodiment provides a display panel, wherein the display panel includes: a plurality of pixel driving circuits, a plurality of data lines, a source driving circuit, a plurality of data connection lines, a plurality of gate lines, and a gate driving circuit. The plurality of pixel driving circuits are arrayed along a first direction and a second direction, the first direction and the second direction intersecting; the data lines connect to the plurality of pixel driving circuits distributed along the second direction; one end of each data connection line is connected to the source driving circuit, and the other end of each data connection line is connected to the plurality of data lines, the source driving circuit providing data signals to the plurality of data lines through the data connection lines; the gate lines connect to the plurality of pixel driving circuits distributed along the first direction; the gate driving circuit provides gate driving signals to the pixel driving circuits through the gate lines; wherein the plurality of data lines form a plurality of data line groups, each data line group including a plurality of data lines, and the plurality of data lines connected to the same data connection line are located in different data line groups; the gate driving circuit controls the pixel driving circuits connected to different data line groups to perform time-division scanning, the scanning of the pixel driving circuit including writing the data signals to the pixel driving circuit.

[0124] This exemplary embodiment uses a gate driving circuit to perform time-division scanning of pixel driving circuits connected to different data line groups. That is, after scanning one group of data line groups, the gate driving circuit scans the pixel driving circuits connected to another group of data line groups. This configuration allows the source driving circuit to provide data signals to the data lines and the pixel driving circuit to write data synchronously, thereby improving the aforementioned data line leakage problem.

[0125] Figure 6 shows a schematic diagram of an exemplary embodiment of the display panel of this disclosure. R represents a pixel driving circuit for driving red light-emitting units, G represents a pixel driving circuit for driving green light-emitting units, and B represents a pixel driving circuit for driving blue light-emitting units. The first direction X can be a row direction, and the second direction Y can be a column direction. Adjacent pixel driving circuits R, G, and B in the first direction X form a pixel unit Pix. As shown in Figure 6, multiple data lines Da form two data line groups: a first data line group Daz1 and a second data line group Daz2. Pixel units Pix in odd-numbered columns are connected to the first data line group Daz1, and pixel units in even-numbered columns are connected to the second data line group Daz2.

[0126] As shown in Figure 6, the multiple gate lines include multiple scan gate lines Gs. The same scan gate line Gs connects at least some of the pixel driving circuits connected to different data line groups. For example, the scan gate line Gs connects all pixel driving circuits located in the same row.

[0127] Figure 7 shows a schematic diagram of the pixel driving circuit in the display panel shown in Figure 6. The pixel driving circuit is used to drive the light-emitting unit L in the display panel. The pixel driving circuit includes: a driving transistor T3, a capacitor C, multiple switching circuits CT, and a light-emitting control circuit 5. The light-emitting control circuit 5 is connected to the first power line VDD, the first electrode of the driving transistor T3, the enable signal line EM, the first electrode of the light-emitting unit, and the second electrode of the driving transistor T3. The light-emitting control circuit 5 is used to respond to the signal of the enable signal line EM to connect the first power line VDD and the first electrode of the driving transistor, and to connect the second electrode of the driving transistor and the first electrode of the light-emitting unit. The capacitor C is connected between the first power line VDD and the gate of the driving transistor T3. The switching circuit CT is connected between two nodes, and the switching circuit CT is also connected to the scan gate line Gs. The switching circuit CT is used to respond to the signal of the scan gate line Gs to turn on the two nodes. As shown in Figure 7, the pixel driving circuit further includes: multiple control circuits KT, with each control circuit KT corresponding to a switch circuit CT. The control circuit KT and its corresponding switch circuit CT are connected in series between the two nodes. The control circuit KT is connected to the control signal terminal CK and is used to respond to the signal of the control signal terminal CK to turn on the two nodes. The pixel driving circuits connected to different data line groups are respectively connected to different control signal terminals.

[0128] As shown in Figure 7, the multiple switching circuits CT include: a data writing circuit 1, a first reset circuit 2, a second reset circuit 3, and a compensation circuit 4. The multiple scanning gate lines Gs include a reset signal line and a first gate line G1. The data writing circuit 1 connects the data line Da, the first electrode of the driving transistor T3, and the first gate line G1. The data writing circuit 1 responds to the signal from the first gate line G1 to conduct the data line Da and the first electrode of the driving transistor T3. The first reset circuit 2 connects the reset signal line Re, the gate of the driving transistor T3, and the initial signal line Vinit. The first reset circuit 2 responds to the signal from the reset signal line Re to connect the initial signal line Vinit and the gate of the driving transistor T3. The second reset circuit 3 connects the first electrode of the light-emitting unit, the initial signal line Vinit, and the reset signal line Re. The second reset circuit 3 responds to the signal from the reset signal line Re to connect the initial signal line Vinit and the first electrode of the light-emitting unit. The compensation circuit 4 connects the gate of the driving transistor T3, the second electrode of the driving transistor, and the first gate line G1. The compensation circuit 4 responds to the signal from the first gate line G1 to connect the gate and the second electrode of the driving transistor.

[0129] As shown in Figure 7, the multiple control circuits KT include: a first control circuit KT1, a second control circuit KT2, and a third control circuit KT3. The first control circuit KT1 and the data writing circuit 1 are connected in series between the first terminal of the driving transistor T3 and the data line Da. The first control circuit KT1 is also connected to a control signal terminal CK, and is used to respond to the signal from the control signal terminal CK to connect the first terminal of the driving transistor T3 and the data line Da. The second control circuit KT2 and the first reset circuit 2 are connected in series between the gate of the driving transistor T3 and the initial signal line Vinit. The second control circuit KT2 and the compensation circuit 4 are connected in series between the gate of the driving transistor and the second terminal of the driving transistor. The second control circuit KT2 is also connected to the control signal terminal CK, and is used to respond to the signal from the control signal terminal CK to conduct the gate of the driving transistor T3 and the second terminal of the driving transistor, and to conduct the gate of the driving transistor and the initial signal line Vinit. The third control circuit KT3 and the second reset circuit 3 are connected in series between the first electrode of the light-emitting unit L and the initial signal line Vinit. The third control circuit KT3 is also connected to the control signal terminal CK. The third control circuit KT3 is used to respond to the signal of the control signal terminal CK to turn on the first electrode of the light-emitting unit L and the initial signal line Vinit.

[0130] As shown in Figure 7, the data writing circuit 1 includes: a fourth transistor T4, the first terminal of which is connected to the data line, and the gate of which is connected to the first gate line; the first control circuit KT1 includes: an eighth transistor T8, the first terminal of which is connected to the second terminal of the fourth transistor, the second terminal of which is connected to the data writing node, and the gate of which is connected to the control signal terminal; the first reset circuit 2 includes: a first transistor T1, the first terminal of which is connected to the initial signal line, and the gate of which is connected to the reset signal line; the compensation circuit 4 includes: a second transistor T2, the second terminal of which is connected to the second terminal of the driving transistor, and the gate of which is connected to the first gate line. The second control circuit KT2 includes: a ninth transistor T9, the first terminal of which is connected to the second terminal of the first transistor T1 and the first terminal of the second transistor T2, the second terminal of which is connected to the gate of the driving transistor T3, and the gate of which is connected to the control signal terminal CK; the second reset circuit 3 includes: a seventh transistor T7, the first terminal of which is connected to the initial signal line Vinit, and the gate of which is connected to the reset signal line Re; the third control circuit KT3 includes: a tenth transistor T10, the first terminal of which is connected to the second terminal of the seventh transistor T7, the second terminal of which is connected to the first electrode of the light-emitting unit L, and the gate of which is connected to the control signal terminal CK. The light-emitting control circuit 5 includes: a fifth transistor T5 and a sixth transistor T6, the first terminal of which is connected to the first power supply line VDD, the second terminal of which is connected to the first terminal of the driving transistor T3, and the gate of which is connected to the enable signal line EM; the first terminal of which is connected to the second terminal of the driving transistor T3, the second terminal of which is connected to the first electrode of the light-emitting unit L, and the gate of which is connected to the enable signal line EM. In this exemplary embodiment, the first transistor T1, the second transistor T2, the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9, and the tenth transistor T10 can be P-type transistors.

[0131] It should be understood that, in other exemplary embodiments, one or more of the first transistor T1, the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9, and the tenth transistor T10 may also be N-type transistors.

[0132] In this exemplary embodiment, pixel driving circuits connected to the same data line group form a pixel driving circuit group. The control signal terminal CK is used to output a conduction level when the pixel driving circuit connected to it is in a scanning period. For example, the control signal terminal CK is used to output a conduction level when the pixel driving circuit group containing the pixel driving circuit connected to it is in a scanning period, and the control signal terminal is used to output a shutdown level when the pixel driving circuit group containing the pixel driving circuit connected to it is in a non-scanning period. It should be noted that the scanning of the pixel driving circuit includes the reset phase and the data writing phase shown in FIG2. The shutdown level represents the level of the target circuit being turned off, and the conduction level represents the level of the target circuit being turned on. Correspondingly, the gate driving circuit can be used to control the pixel driving circuits connected to different data line groups to write the initial signal of the initial signal line to the first electrode of the light-emitting unit and the gate of the driving transistor in a time-division manner through the reset signal line, and the gate driving circuit can be used to control the pixel driving circuits connected to different data line groups to write the data signal in a time-division manner through the first gate line.

[0133] For example, Figure 8 shows the timing diagram of each node in a driving method for the display panel shown in Figure 6. CK1 represents the timing diagram of the control signal terminal connected to the pixel driving circuit of the first data line group Daz1, and CK2 represents the timing diagram of the control signal terminal connected to the pixel driving circuit of the second data line group Daz2.

[0134] In the first half of frame T, the control signal terminal connected to the odd-numbered pixel units of the first data line group Daz1 outputs a low level. The eighth transistor T8, the ninth transistor T9, and the tenth transistor T10 in the odd-numbered pixel units are turned on. The data connection line DL outputs a data signal through the data signal line in the first data line group Daz1. The gate drive circuit drives the odd-numbered pixel units row by row through the reset signal line Re and the first gate line G1. At the same time, the control signal terminal connected to the even-numbered pixel units of the second data line group Daz2 outputs a high level. The eighth transistor T8, the ninth transistor T9, and the tenth transistor T10 in the even-numbered pixel units are turned off. The even-numbered pixel units are not scanned, thus maintaining the state of the previous frame.

[0135] In the latter half of frame T, the control signal terminal connected to the even-numbered pixel units of the second data line group Daz2 outputs a low level. The eighth transistor T8, ninth transistor T9, and tenth transistor T10 in the even-numbered pixel units are turned on. The data connection line DL outputs a data signal through the data signal line in the second data line group Daz2. The gate drive circuit drives the even-numbered pixel units row by row through the reset signal line Re and the first gate line G1. Simultaneously, the control signal terminal connected to the odd-numbered pixel units of the first data line group Daz1 outputs a high level. The eighth transistor T8, ninth transistor T9, and tenth transistor T10 in the odd-numbered pixel units are turned off, and the odd-numbered pixel units do not perform scanning, thus maintaining the state of the previous frame.

[0136] As shown in Figure 7, the initial signal used to reset the gate of the driving transistor T3 and the first electrode of the light-emitting unit L is a low-level signal. Correspondingly, in the same pixel driving circuit, the initial signal line Vinit can be multiplexed as the control signal terminal CK.

[0137] In this exemplary embodiment, the signal lines used to connect the control signal terminals can extend along the column direction, thereby enabling odd-numbered column pixel units and even-numbered column pixel units to connect to different control signal terminals. Furthermore, the signal lines used to connect the control signal terminals can also extend along the row direction. Accordingly, each row of pixel driving circuits can be provided with two signal lines for connecting the control signal terminals, with the two signal lines respectively connecting to the control signal terminals of the odd-numbered column pixel units and the even-numbered column pixel units.

[0138] Figure 9 shows a schematic diagram of the pixel driving circuit in another exemplary embodiment of the display panel shown in Figure 6. The pixel driving circuit is used to drive the light-emitting unit L in the display panel. The pixel driving circuit includes: a driving transistor T3, a capacitor C, multiple switching circuits CT, and a light-emitting control circuit 5. The light-emitting control circuit 5 is connected to a first power supply line VDD, a first electrode of the driving transistor T3, an enable signal line EM, a first electrode of the light-emitting unit, and a second electrode of the driving transistor T3. The light-emitting control circuit 5 is used to respond to the signal of the enable signal line EM to connect the first power supply line VDD and the first electrode of the driving transistor, and to connect the second electrode of the driving transistor and the first electrode of the light-emitting unit. The capacitor C is connected between the first power supply line VDD and the gate of the driving transistor T3. The control terminal of the switching circuit CT is connected to the scanning grid line. As shown in Figure 9, the pixel driving circuit also includes multiple gating circuits XT, which are correspondingly configured with the switching circuit CT. The switching circuit CT is connected to the scanning grid line through its corresponding gating circuit XT. The gating circuit XT is also connected to a gating signal terminal MUX. The gating circuit XT is used to respond to the signal of the gating signal terminal MUX to turn on the control terminal of the switching circuit CT and the scanning grid line. The pixel driving circuits connected to different data line groups are respectively connected to different gating signal terminals.

[0139] As shown in Figure 9, the multiple scanning gate lines Gs include a reset signal line and a first gate line G1. The multiple switching circuits CT include: a data writing circuit 1, a first reset circuit 2, a second reset circuit 3, and a compensation circuit 4. The data writing circuit 1 connects the data line Da, the first electrode of the driving transistor T3, and the first gate line G1. The data writing circuit 1 responds to the signal of the first gate line G1 to conduct the data line Da and the first electrode of the driving transistor T3. The first reset circuit 2 connects the reset signal line Re, the gate of the driving transistor T3, and the initial signal line Vinit. The first reset circuit 2 responds to the signal of the reset signal line Re to connect the initial signal line Vinit and the gate of the driving transistor T3. The second reset circuit 3 connects the first electrode of the light-emitting unit, the initial signal line Vinit, and the reset signal line Re. The second reset circuit 3 responds to the signal of the reset signal line Re to connect the initial signal line Vinit and the first electrode of the light-emitting unit. The compensation circuit 4 connects the gate of the driving transistor T3, the second electrode of the driving transistor, and the first gate line G1. The compensation circuit 4 responds to the signal of the first gate line G1 to connect the gate and the second electrode of the driving transistor.

[0140] As shown in Figure 9, the multiple gating circuits include a first gating circuit XT1 and a second gating circuit XT2. The data writing circuit 1 and the compensation circuit 4 are connected to the first gate line G1 through the first gating circuit XT1. The first gating circuit XT1 is used to respond to the signal of the gating signal terminal MUX to connect the first gate line G1 and the data writing circuit 1 and the compensation circuit 4. The first reset circuit 2 and the second reset circuit 3 are connected to the reset signal line Re through the second gating circuit XT2. The second gating circuit XT2 is used to respond to the signal of the gating signal terminal MUX to connect the reset signal line Re and the first reset circuit 2 and the second reset circuit 3.

[0141] As shown in Figure 9, the data writing circuit 1 includes: a fourth transistor T4, the first terminal of which is connected to the data line; the compensation circuit 4 includes: a second transistor T2, the first terminal of which is connected to the gate of the driving transistor T3, and the second terminal of which is connected to the second terminal of the driving transistor T3; the first gating circuit includes: an eighth transistor T8, the first terminal of which is connected to the first gate line G1, and the second terminal of which is connected to the gate of the fourth transistor T4 and the gate of the second transistor T2, and the gate is connected to the gating signal terminal MUX; the first reset circuit 2 includes: a first transistor T1, the first terminal of which is connected to the initial signal line Vinit, and the second terminal of which is connected to the gate of the driving transistor T3; the second reset circuit includes: a seventh transistor T7, the first terminal of which is connected to the initial signal line Vinit, and the second terminal of which is connected to the first electrode of the light-emitting unit L; the second gating circuit includes: a tenth transistor T10, the first terminal of which is connected to the reset signal line Re, and the second terminal of which is connected to the gate of the first transistor T1 and the gate of the seventh transistor T7, and the gate is connected to the gating signal terminal MUX. In this exemplary embodiment, the first transistor T1, the second transistor T2, the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, and the tenth transistor T10 can be P-type transistors.

[0142] It should be understood that, in other exemplary embodiments, one or more of the first transistor T1, the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, and the tenth transistor T10 may also be N-type transistors.

[0143] In this exemplary embodiment, pixel driving circuits connected to the same data line group form a pixel driving circuit group. The strobe signal terminal MUX is used to output a conduction level when the pixel driving circuit connected to it is in a scanning period. For example, the strobe signal terminal MUX is used to output a conduction level when the pixel driving circuit group containing the pixel driving circuit connected to it is in a scanning period, and the strobe signal terminal MUX is used to output a cut-off level when the pixel driving circuit group containing the pixel driving circuit connected to it is in a non-scanning period. The scanning of the pixel driving circuit includes a reset phase and a data writing phase as shown in FIG2. Accordingly, the gate driving circuit can be used to control the pixel driving circuits connected to different data line groups to write the initial signal of the initial signal line to the first electrode of the light-emitting unit and the gate of the driving transistor in a time-division manner through the reset signal line, and the gate driving circuit can be used to control the pixel driving circuits connected to different data line groups to write the data signal in a time-division manner through the first gate line.

[0144] For example, Figure 10 shows the timing diagram of each node in a driving method for the display panel shown in Figure 6. MUX1 represents the timing diagram of the gating signal terminal connected to the pixel driving circuit of the first data line group Daz1, and MUX2 represents the timing diagram of the gating signal terminal connected to the pixel driving circuit of the second data line group Daz2.

[0145] In the first half of frame T, the gating signal terminal connected to the odd-numbered pixel units of the first data line group Daz1 outputs a low level. The eighth transistor T8 and the tenth transistor T10 in the odd-numbered pixel units are turned on. The data connection line DL outputs a data signal through the data signal line in the first data line group Daz1. The gate drive circuit drives the odd-numbered pixel units row by row through the reset signal line Re and the first gate line G1. At the same time, the gating signal terminal connected to the even-numbered pixel units of the second data line group Daz2 outputs a high level. The eighth transistor T8 and the tenth transistor T10 in the even-numbered pixel units are turned off. The even-numbered pixel units are not scanned, thus maintaining the state of the previous frame.

[0146] In the latter half of frame T, the strobe signal terminal connected to the even-numbered column pixel units via the second data line group Daz2 outputs a low level. The eighth transistor T8 and the tenth transistor T10 in the even-numbered column pixel units are turned on. The data connection line DL outputs a data signal through the data signal line in the second data line group Daz2. The gate drive circuit drives the even-numbered column pixel units row by row through the reset signal line Re and the first gate line G1. Simultaneously, the strobe signal terminal connected to the odd-numbered column pixel units via the first data line group Daz1 outputs a high level. The eighth transistor T8 and the tenth transistor T10 in the odd-numbered column pixel units are turned off, and the odd-numbered column pixel units do not perform scanning, thus maintaining the state of the previous frame.

[0147] In this exemplary embodiment, the signal lines used to connect the gating signal terminals can extend along the column direction, thereby enabling odd-numbered column pixel units and even-numbered column pixel units to connect to different gating signal terminals. Furthermore, the signal lines used to connect the gating signal terminals can also extend along the row direction. Accordingly, each row pixel driving circuit can be provided with two signal lines for connecting the gating signal terminals, with the two signal lines respectively connecting to the gating signal terminals of the odd-numbered column pixel units and the even-numbered column pixel units.

[0148] As shown in Figures 7 and 9, the data writing node of the data writing circuit 1, which writes the data signal, is the first terminal of the driving transistor. It should be understood that in other exemplary embodiments, the pixel driving circuit can have other structures, and correspondingly, the data writing node of the data writing circuit 1 can be located in other positions. Furthermore, in other pixel driving circuit structures, the switching circuit CT in the pixel driving circuit can also have other connection relationships with the driving transistor. In the same pixel driving circuit, the number of control circuits can be set according to the number of switching circuits, and the number of selection circuits can be set according to the number of scan gate lines.

[0149] Figure 11 shows a schematic diagram of another exemplary embodiment of the display panel of this disclosure. Adjacent pixel driving circuits R, G, and B in the first direction X form pixel units Pix. Multiple data lines Da form two data line groups: a first data line group Daz1 and a second data line group Daz2. Pixel units Pix in odd-numbered columns are connected to the first data line group Daz1, and pixel units in even-numbered columns are connected to the second data line group Daz2. Each row of pixel driving circuits is provided with two identical scanning gate lines Gs. One gate line connects to the pixel driving circuit connected to the first data line group Daz1, and the other gate line connects to the pixel driving circuit connected to the second data line group Daz2.

[0150] It should be noted that the same type of scan gate line refers to the scan gate line that provides the gate drive signal to the same type of transistor in each pixel driving circuit. For example, the first gate line G1 is a scan gate line and the reset signal line Re is a scan gate line. In this exemplary embodiment, each row of pixel driving circuits can be provided with two reset signal lines Re and two first gate lines G1.

[0151] As shown in Figure 11, the display panel further includes: multiple gating circuits XT, with two gating circuits corresponding to each row of pixel driving circuits: a first gating circuit XT1 and a second gating circuit XT2. Each row of pixel driving circuits has two gating circuits and two identical scan gate lines corresponding to the same row of pixel driving circuits. The two identical scan gate lines Gs corresponding to a row of pixel driving circuits are respectively connected to the same signal output terminal of the gate driving circuit through their corresponding two gating circuits. The gating circuit XT is connected to a gating signal terminal MUX, and the gating circuit XT is used to respond to the signal of the gating signal terminal MUX to conduct the scan gate line Gs and the output terminal of the gate driving circuit. Specifically, the gating circuits XT corresponding to pixel driving circuits connected to different data line groups are connected to different gating signal terminals MUX. For example, the first gating circuit XT1 corresponding to the pixel driving circuit connected to the first data line group Daz1 is connected to the first gating signal terminal MUX1, and the second gating circuit XT2 corresponding to the pixel driving circuit connected to the second data line group Daz2 is connected to the second gating signal terminal MUX2.

[0152] In this exemplary embodiment, the gating circuit XT can be integrated into the bezel area of ​​the display panel.

[0153] In this exemplary embodiment, the first gating circuit XT1 may include an eighth transistor T8. The gate of the eighth transistor T8 is connected to the first gating signal terminal MUX1, its first terminal is connected to the output terminal of the gate driving circuit, and its second terminal is connected to the corresponding scan gate line Gs. The second gating circuit XT2 includes a ninth transistor T9. The gate of the ninth transistor T9 is connected to the second gating signal terminal MUX2, its first terminal is connected to the output terminal of the gate driving circuit, and its second terminal is connected to the corresponding scan gate line Gs. The eighth transistor T8 and the ninth transistor T9 may be P-type transistors.

[0154] Figure 12 shows the timing diagram of each node in a driving method for the display panel shown in Figure 11. MUX1 represents the timing diagram of the first strobe signal terminal, and MUX2 represents the timing diagram of the second strobe signal terminal.

[0155] In the first half of frame T, the first strobe signal terminal MUX1 outputs a low level, the first strobe circuit XT1 connected to the odd-numbered pixel units is turned on, the data connection line DL outputs a data signal through the data signal line in the first data line group Daz1, and the gate drive circuit drives the odd-numbered pixel units row by row through the reset signal line Re and the first gate line G1 connected to the first strobe circuit XT1. At the same time, the second strobe signal terminal MUX2 outputs a high level, the second strobe circuit XT2 connected to the even-numbered pixel units is turned off, and the even-numbered pixel units do not perform scanning, thus maintaining the state of the previous frame.

[0156] In the latter half of frame T, the second strobe signal terminal MUX2 outputs a low level, the second strobe circuit XT2 connected to the even-numbered column pixel units is turned on, the data connection line DL outputs a data signal through the data signal line in the second data line group Daz2, and the gate drive circuit drives the even-numbered column pixel units row by row through the reset signal line Re and the first gate line G1 connected to the second strobe circuit XT2. At the same time, the first strobe signal terminal MUX1 outputs a high level, the first strobe circuit XT1 connected to the odd-numbered column pixel units is turned off, and the odd-numbered column pixel units do not perform scanning, thus maintaining the state of the previous frame.

[0157] It should be understood that in other exemplary embodiments, the display panel may include other numbers of data line groups. For example, the display panel may include n data line groups. Correspondingly, each row of pixel driving circuits is provided with n identical scan gate lines Gs. Among the n identical scan gate lines Gs corresponding to each row of pixel driving circuits, the scan gate lines Gs are connected to the pixel driving circuits connected to the same data line group, and the pixel driving circuits connected to different data line groups are connected to different scan gate lines. n is a positive integer greater than or equal to 2. Accordingly, the display panel also includes: a plurality of gating circuits XT. Each row of pixel driving circuits is provided with n gating circuits, and the n gating circuits and n identical scan gate lines corresponding to the same row of pixel driving circuits are arranged one-to-one. The n identical scan gate lines Gs corresponding to each row of pixel driving circuits are respectively connected to the same signal output terminal of the gate driving circuit through their corresponding n gating circuits XT; wherein the gating circuits corresponding to pixel driving circuits connected to different data line groups are connected to different gating signal terminals. The pixel driving circuits connected to the same data line group form a pixel driving circuit group. The strobe signal terminal can be used to output a conduction level when the connected pixel driving circuit is in a scanning period, and the strobe signal terminal can be used to output a cut-off level when the pixel driving circuit group containing the connected pixel driving circuit is in a non-scanning period. This setting can also realize time-division scanning of the display panel.

[0158] Figure 13 shows a schematic diagram of the gate driving circuit in an exemplary embodiment of the display panel of this disclosure. In the display panels shown in Figures 6-12, the gate driving circuit may include multiple cascaded shift register units GOA. The output terminal OUT of the previous stage shift register unit is connected to the input terminal of the adjacent next stage shift register unit, so that the output signal of the previous stage shift register unit is used as the input signal of the next stage shift register unit. It should be understood that in other exemplary embodiments, the output terminal of the previous stage shift register unit may also be connected to the input terminals of spaced-apart next stage shift register units.

[0159] In this exemplary embodiment, the reset signal line Re and the first gate line G1 can be connected to the same set of cascaded shift register units. Among the reset signal line Re and the first gate line G1 connected to the same row of pixel driving circuits, the reset signal line Re can be connected to the output of the upper-level shift register unit, and the first gate line G1 can be connected to the output of the lower-level shift register unit. It should be understood that in other exemplary embodiments, the gate driving circuit may also include two sets of cascaded shift register units, with the two sets of shift register units respectively connected to the reset signal line Re and the first gate line G1.

[0160] In this exemplary embodiment, as shown in FIG13, the input terminal of the first-stage shift register unit GOA is connected to the initialization signal terminal STV. The initialization signal terminal STV inputs an initial signal to the first-stage shift register unit GOA, and the gate driving circuit begins to output shift signals stage by stage. In the display panel shown in FIG6-FIG12, multiple initial signals can be output by the initialization signal terminal STV in a time-division manner to realize the gate driving circuit scanning the pixel driving circuits connected to different data line groups in a time-division manner. For example, in the first half of a frame, the initialization signal terminal STV outputs an initial signal, and the gate driving circuit scans the pixel units in odd-numbered columns; in the second half of a frame, the initialization signal terminal STV outputs an initial signal again, and the gate driving circuit scans the pixel units in even-numbered columns. In addition, there can be a gap period between the scanning periods of the pixel driving circuits connected to different data line groups. The gap period can be the scanning duration of one or more pixel driving circuit rows. The gap period can be implemented by the timing of the initial signals. The gap period can be used to avoid the gate driving circuit output disorder.

[0161] It should be understood that in other exemplary embodiments, the shift register unit can also be configured internally to allow the odd-numbered and even-numbered pixel units to scan in opposite directions. For example, the odd-numbered pixel units scan from the first row to the last row, while the even-numbered pixel units scan in reverse from the last row to the first row. The input signal of the shift register unit corresponding to the last row of even-numbered pixel units can be provided by the output signal of the shift register unit corresponding to the last row of odd-numbered pixel units. Furthermore, there can be a gap between the scanning periods of the pixel driving circuits connected to different data line groups. This gap can be the scanning duration of one or more rows of pixel driving circuits, and the gap can be implemented by the timing of the clock signal in the shift register unit.

[0162] Figure 14 shows a schematic diagram of another exemplary embodiment of the display panel of this disclosure. Each row of pixel driving circuits is provided with two identical scanning gate lines Gs. The gate driving circuit includes two sub-gate driving circuits. The two identical scanning gate lines Gs corresponding to the same row of pixel driving circuits are respectively provided with the two sub-gate driving circuits. The multiple sub-gate driving circuits are used to scan the pixel driving circuits connected to them at different time periods. For example, one sub-gate driving circuit scans odd-numbered columns of pixel units in the first half of a frame, and the other sub-gate driving circuit scans even-numbered columns of pixel units in the second half of a frame.

[0163] Figure 15 shows a schematic diagram of the gate driving circuit in an exemplary embodiment of the display panel shown in Figure 14. The two sub-gate driving circuits include a first sub-gate driving circuit Gd1 and a second sub-gate driving circuit Gd2. The first sub-gate driving circuit Gd1 and the second sub-gate driving circuit Gd2 are cascaded. The output terminal OUT of the a-th stage shift register unit GOA is connected to the input terminal of the (a+b)-th stage shift register unit. a and b are positive integers greater than or equal to 1. The output terminal of the shift register unit is connected to the scan gate line Gs. The first sub-gate driving circuit Gd1's first-stage shift register unit GOA receives the first initial signal STV1. The first sub-gate driving circuit Gd1 can be used to scan odd-numbered column pixel units. For example, the first sub-gate driving circuit Gd1 can provide a gate driving signal to the first gate line connected to the odd-numbered column pixel units. The second sub-gate driving circuit Gd2's first-stage shift register unit GOA receives the second initial signal STV2. The second sub-gate driving circuit Gd2 can be used to scan even-numbered column pixel units. For example, the second sub-gate driving circuit Gd2 can provide a gate driving signal to the first gate line connected to the even-numbered column pixel units.

[0164] Figure 16 shows a schematic diagram of the gate driving circuit in another exemplary embodiment of the display panel shown in Figure 14. The two sub-gate driving circuits include a first sub-gate driving circuit Gd1 and a second sub-gate driving circuit Gd2. The output of the last stage shift register unit GOA in the first sub-gate driving circuit Gd1 is connected to the input of the first stage shift register unit in the second sub-gate driving circuit Gd2. The output of the shift register unit is connected to the scan gate line Gs. The first sub-gate driving circuit Gd1 can be used to scan odd-numbered column pixel units; for example, the first sub-gate driving circuit Gd1 can provide a gate driving signal to the first gate line connected to the odd-numbered column pixel units. The second sub-gate driving circuit Gd2 can be used to scan even-numbered column pixel units; for example, the second sub-gate driving circuit Gd2 can provide a gate driving signal to the first gate line connected to the even-numbered column pixel units.

[0165] It should be noted that Figures 13, 15, and 16 only illustrate a portion of the shift register units, and this exemplary embodiment does not limit the number of shift register units in the gate drive circuit. Figures 6, 11, and 14 only illustrate a portion of the pixel drive circuit, and this exemplary embodiment does not limit the number of pixel drive circuits.

[0166] In this exemplary embodiment, as shown in Figures 6, 11, and 14, the display panel includes multiple pixel units, each pixel unit including three adjacent pixel driving circuits R, G, and B in the first direction; the data line group connects multiple columns of the pixel units. This arrangement allows the pixel driving circuits within a pixel unit to scan synchronously, thereby avoiding color shift issues in the display panel. In this exemplary embodiment, the pixel units in the display panel are distributed in a RealRGB manner. It should be understood that in other exemplary embodiments, the pixel units in the display panel may be distributed in other ways, and correspondingly, the pixel units may include other numbers of pixel unit circuits. For example, the pixel units in the display panel may be distributed in an RGBG manner, and correspondingly, the pixel unit includes four adjacent pixel driving circuits R, G, B, and G in the first direction. Furthermore, it should be understood that in other exemplary embodiments, the pixel driving circuits located in the same pixel unit may also be connected to different data line groups.

[0167] In this exemplary embodiment, as shown in Figures 6, 11, and 14, the multiple data lines form two data line groups: a first data line group Daz1 and a second data line group Daz2. The first data line group Daz1 connects the pixel units in the odd-numbered columns, and the second data line group Daz2 connects the pixel units in the even-numbered columns. This arrangement allows the odd-numbered and even-numbered pixel units to be driven in a time-sharing manner, thereby avoiding screen splitting on the display panel.

[0168] In this exemplary embodiment, as shown in Figures 6, 11, and 14, the pixel driving circuit connected to different data line groups is controlled by the gate driving circuit for time-division scanning. Accordingly, the data connection line DL and the data line Da are directly connected, that is, no transistor is placed between the data connection line DL and the data line Da.

[0169] In this exemplary embodiment, the gate driving circuit includes a light-emitting driving circuit for providing gate driving signals to the enable signal line EM. The light-emitting driving circuit can also control the time-division scanning of pixel driving circuits connected to different data line groups. For example, in the embodiments shown in Figures 6, 11, and 14, the light-emitting driving circuit drives odd-numbered column pixel units to scan line by line in the first half of a frame, and drives even-numbered column pixel units to scan line by line in the second half of a frame. In the second half of a frame, even if the light-emitting driving circuit provides gate driving signals to even-numbered column pixel units, odd-numbered column pixel units will only experience a brief blackout, thus not affecting the overall display of the display panel. Of course, the light-emitting driving circuit can also be configured similarly to the embodiments shown in Figures 6, 11, and 14, by connecting a control circuit in series with the light-emitting control circuit in the pixel driving circuit, or by setting a gating circuit between the light-emitting control circuit and the enable signal line, or by setting a gating circuit between the light-emitting driving circuit and the enable signal line, or by setting two sub-light-emitting driving circuits, thereby ensuring that the gate driving signals provided by the light-emitting driving circuit to the pixel driving circuit group do not affect other pixel driving circuit groups.

[0170] In this exemplary embodiment, the display panel can be packaged using COF (Chip On Film) technology, and the source drive circuit can be connected to the data line via a data connection line integrated on the chip-on-film.

[0171] This exemplary embodiment also provides a display device, which includes the display panel described above. The display device can be a mobile phone, tablet computer, television, or other display device.

[0172] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the disclosure herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the claims.

[0173] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this disclosure is defined only by the appended claims.

Claims

1. A display panel, wherein, The display panel includes: Multiple pixel driving circuits are arranged in an array along a first direction and a second direction, the first direction and the second direction intersecting; Multiple data lines, the data lines being connected to multiple pixel driving circuits distributed in the second direction; Source drive circuit; Multiple data connection lines are provided, one end of which is connected to the source drive circuit, and the other end of which is connected to multiple data lines. The source drive circuit is used to provide data signals to the multiple data lines through the data connection lines. Multiple gate lines, the gate lines being connected to multiple pixel driving circuits distributed in the first direction; A gate driving circuit provides a gate driving signal to the pixel driving circuit through the gate line; The multiple data lines form multiple data line groups, and each data line group includes multiple data lines, with the multiple data lines connected to the same data connection line located in different data line groups. The gate driving circuit is used to control the pixel driving circuits connected to different data line groups to perform time-division scanning, and the scanning of the pixel driving circuit includes writing the data signal to the pixel driving circuit.

2. The display panel according to claim 1, wherein, The multiple gate lines include multiple scan gate lines, and the same scan gate line connects at least some of the pixel driving circuits connected to different data line groups.

3. The display panel according to claim 2, wherein, The pixel driving circuit includes: One or more switching circuits are connected between two nodes and are also connected to the scan grid line. The switching circuits are used to turn on the two nodes in response to a signal from the scan grid line. One or more control circuits are provided, corresponding to the switching circuit. The control circuit and the corresponding switching circuit are connected in series between the two nodes. The control circuit is connected to a control signal terminal and is used to respond to the signal of the control signal terminal to turn on the two nodes. The pixel driving circuits connected to different data line groups are connected to different control signal terminals.

4. The display panel according to claim 3, wherein, The pixel driving circuits connected to the same data line group form a pixel driving circuit group. The control signal terminal is used to output a conduction level when the pixel driving circuit connected to it is in the scanning period, and the control signal terminal is used to output a shutdown level when the pixel driving circuit group to which the pixel driving circuit connected to it is in the non-scanning period.

5. The display panel according to claim 3, wherein, The plurality of said scanning gate lines includes a first gate line, and one or more switching circuits include: A data writing circuit is connected to a data writing node, a data line, and a first gate line. The data writing circuit is used to respond to a signal from the first gate line to connect the data writing node and the data line. One or more control circuits include: A first control circuit is connected in series with the data writing circuit between the data writing node and the data line. The first control circuit is also connected to a control signal terminal. The first control circuit is used to respond to the signal of the control signal terminal to connect the data writing node and the data line. The gate driving circuit is used to control the pixel driving circuits connected to different data line groups to write the data signal in a time-division manner through the first gate line.

6. The display panel according to claim 5, wherein, The display panel further includes a light-emitting unit, and the pixel driving circuit further includes: A driving transistor that provides a driving current to the light-emitting unit according to its gate voltage; The multiple scan gate lines include a reset signal line, and one or more switching circuits include: A first reset circuit is connected to the reset signal line, the gate of the driving transistor, and the initial signal line. The first reset circuit is used to respond to the signal of the reset signal line to turn on the gate of the driving transistor and the initial signal line. The second reset circuit is connected to the reset signal line, the first electrode of the light-emitting unit, and the initial signal line. The second reset circuit is used to respond to the signal of the reset signal line to turn on the first electrode of the light-emitting unit and the initial signal line. A compensation circuit is connected to the first gate line, the gate of the driving transistor, and the second terminal of the driving transistor. The compensation circuit is used to respond to the signal of the first gate line to connect the gate of the driving transistor and the second terminal of the driving transistor. One or more control circuits include: The second control circuit and the first reset circuit are connected in series between the gate of the driving transistor and the initial signal line, and the second control circuit and the compensation circuit are connected in series between the gate of the driving transistor and the second terminal of the driving transistor. The second control circuit is also connected to the control signal terminal. The second control circuit is used to respond to the signal of the control signal terminal to turn on the gate of the driving transistor and the second terminal of the driving transistor, and to turn on the gate of the driving transistor and the initial signal line. The third control circuit and the second reset circuit are connected in series between the first electrode of the light-emitting unit and the initial signal line. The third control circuit is also connected to the control signal terminal. The third control circuit is used to respond to the signal of the control signal terminal to turn on the first electrode of the light-emitting unit and the initial signal line. The scanning of the pixel driving circuit includes inputting the signal of the initial signal line to the first electrode of the light-emitting unit and the gate of the driving transistor. The gate driving circuit is used to control the pixel driving circuits connected to different data line groups to write the initial signal of the initial signal line to the first electrode of the light-emitting unit and the gate of the driving transistor in a time-division manner through the reset signal line.

7. The display panel according to claim 6, wherein, The first electrode of the driving transistor forms the data writing node, and the data writing circuit includes: A fourth transistor, wherein the first terminal of the fourth transistor is connected to the data line, and the gate is connected to the first gate line; The first control circuit includes: The eighth transistor has its first terminal connected to the second terminal of the fourth transistor, the second terminal connected to the data writing node, and its gate connected to the control signal terminal. The first reset circuit includes: A first transistor, wherein the first terminal of the first transistor is connected to the initial signal line and the gate is connected to the reset signal line; The compensation circuit includes: The second transistor has its second terminal connected to the second terminal of the driving transistor, and its gate connected to the first gate line; The second control circuit includes: The ninth transistor has its first terminal connected to the second terminal of the first transistor and the first terminal of the second transistor, its second terminal connected to the gate of the driving transistor, and its gate connected to the control signal terminal. The second reset circuit includes: The seventh transistor has its first terminal connected to the initial signal line and its gate connected to the reset signal line. The third control circuit includes: The tenth transistor has its first electrode connected to the second electrode of the seventh transistor, the second electrode connected to the first electrode of the light-emitting unit, and its gate connected to the control signal terminal.

8. The display panel according to claim 6, wherein, In the same pixel driving circuit, the initial signal line is multiplexed as the control signal terminal.

9. The display panel according to claim 2, wherein, The pixel driving circuit includes: One or more switching circuits, wherein the control terminal of the switching circuit is connected to the scan grid line; One or more gating circuits are provided, and the gating circuits and the switching circuits are correspondingly provided. The switching circuits are connected to the scanning grid lines through the gating circuits they correspond to. The gating circuits are also connected to gating signal terminals. The gating circuits are used to respond to the signals of the gating signal terminals to turn on the control terminals of the switching circuits and the scanning grid lines. The pixel driving circuits connected to different data line groups are connected to different gating signal terminals.

10. The display panel according to claim 9, wherein, The plurality of said scanning gate lines includes a first gate line, and one or more switching circuits include: A data writing circuit is connected to a data writing node, the data line, and a first gate line. The data writing circuit is used to respond to a signal from the first gate line to connect the data writing node and the data line. One or more gating circuits include: A first gating circuit, wherein the data writing circuit is connected to the first gate line through the first gating circuit, and the first gating circuit is used to respond to the signal of the gating signal terminal to connect the data writing circuit and the first gate line; The gate driving circuit is used to control the pixel driving circuits connected to different data line groups to write the data signal in a time-division manner through the first gate line.

11. The display panel according to claim 10, wherein, The display panel further includes a light-emitting unit, and the pixel driving circuit further includes: A driving transistor that provides a driving current to the light-emitting unit according to its gate voltage; The multiple scan gate lines include a reset signal line, and one or more switching circuits include: A first reset circuit is connected to the reset signal line, the gate of the driving transistor, and the initial signal line. The first reset circuit is used to respond to the signal of the reset signal line to turn on the gate of the driving transistor and the initial signal line. The second reset circuit is connected to the reset signal line, the first electrode of the light-emitting unit, and the initial signal line. The second reset circuit is used to respond to the signal of the reset signal line to turn on the first electrode of the light-emitting unit and the initial signal line. A compensation circuit is connected between the gate of the driving transistor and the second terminal of the driving transistor. The compensation circuit is connected to the first gate line through the first gating circuit. The compensation circuit is used to respond to the signal of the first gate line to conduct the gate of the driving transistor and the second terminal of the driving transistor. One or more gating circuits include: The second gating circuit connects the first reset circuit and the second reset circuit to the reset signal line. The second gating circuit is used to respond to the signal at the gating signal terminal to connect the reset signal line and the first reset circuit and the second reset circuit. The scanning of the pixel driving circuit includes inputting an initial signal of the initial signal line to the first electrode of the light-emitting unit and the gate of the driving transistor; The gate driving circuit is used to control the pixel driving circuits connected to different data line groups to write the initial signal of the initial signal line to the first electrode of the light-emitting unit and the gate of the driving transistor in a time-division manner through the reset signal line.

12. The display panel according to claim 11, wherein, The first electrode of the driving transistor forms the data writing node, and the data writing circuit includes: The fourth transistor has its first terminal connected to the data line and its second terminal connected to the first terminal of the driving transistor. The compensation circuit includes: The second transistor has a first terminal connected to the gate of the driving transistor and a second terminal connected to the second terminal of the driving transistor. The first gating circuit includes: The eighth transistor has its first terminal connected to the first gate line, its second terminal connected to the gate of the fourth transistor and the gate of the second transistor, and its gate connected to the strobe signal terminal. The first reset circuit includes: A first transistor, wherein a first terminal of the first transistor is connected to the initial signal line and a second terminal is connected to the gate of the driving transistor; The second reset circuit includes: The seventh transistor has its first electrode connected to the initial signal line and its second electrode connected to the first electrode of the light-emitting unit. The second gating circuit includes: The tenth transistor has its first terminal connected to the reset signal line, and its second terminal connected to the gate of the first transistor and the gate of the seventh transistor. The gate of the transistor is connected to the strobe signal terminal.

13. The display panel according to claim 1, wherein, The multiple gate lines include multiple scan gate lines. The first direction is the row direction. A row of pixel driving circuits is provided with multiple scan gate lines of the same type. Among the multiple scan gate lines of the same type corresponding to a row of pixel driving circuits, the scan gate lines are connected to the pixel driving circuits connected to the same data line group, and the pixel driving circuits connected to different data line groups are connected to different scan gate lines.

14. The display panel according to claim 13, wherein, The display panel also includes: Multiple selection circuits are provided, and multiple selection circuits are provided for each row of pixel driving circuits. Multiple selection circuits and multiple scan gate lines of the same type are provided in a one-to-one correspondence with the multiple selection circuits corresponding to the same row of pixel driving circuits. Multiple scan gate lines of the same type corresponding to a row of pixel driving circuits are respectively connected to the same signal output terminal of the gate driving circuit through their corresponding selection circuits. The gating circuit is connected to the gating signal terminal, and the gating circuit is used to respond to the signal of the gating signal terminal to turn on the output terminal of the scan gate line and the gate driving circuit. Among them, the gating circuits corresponding to the pixel driving circuits that connect different data line groups are connected to different gating signal terminals.

15. The display panel according to claim 9 or 14, wherein, The pixel driving circuits connected to the same data line group form a pixel driving circuit group. The strobe signal terminal is used to output a conduction level when the pixel driving circuit connected to it is in the scanning period, and the strobe signal terminal is used to output a cut-off level when the pixel driving circuit group to which the pixel driving circuit connected to it is in the non-scanning period.

16. The display panel according to claim 13, wherein, The gate driving circuit includes multiple sub-gate driving circuits. Multiple identical scanning gate lines corresponding to the same row of pixel driving circuits are respectively configured to correspond to the multiple sub-gate driving circuits. The multiple sub-gate driving circuits are respectively used to scan the pixel driving circuits connected to them at different time periods.

17. The display panel according to any one of claims 1-14, 16, wherein, The second direction is a column direction, and the display panel includes multiple pixel units, each pixel unit including multiple pixel driving circuits adjacent to each other in the first direction; The data line group connects multiple columns of the pixel units.

18. The display panel according to claim 17, wherein, The multiple data lines form two data line groups, one data line group connecting the pixel units in the odd-numbered columns and the other data line group connecting the pixel units in the even-numbered columns.

19. The display panel according to any one of claims 1-14, 16, wherein, The data connection cable and the data line are directly connected.

20. A display device, wherein, The display device includes the display panel as described in any one of claims 1-19.

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