Coding method, decoding method, and communication apparatus

Abstract

The present application relates to the technical field of wireless communications, and provides a coding method, a decoding method, and a communication apparatus, for use in ensuring the stability of the performance of an LDPC code. The method comprises: a first communication device acquires an information bit sequence; the first communication device codes the information bit sequence on the basis of an LDPC matrix to obtain a first check bit sequence; and the first communication device acquires a first sequence, the first sequence being obtained by interleaving the information bit sequence and the first check bit sequence. On the basis of the described solution, the first communication device can interleave information bits and check bits in the LDPC code, structurally changing distribution rules of an information column and a check column and optimizing a cycle property, and thus ensuring the stability of the performance of the LDPC code.

Description

An encoding method, a decoding method, and a communication device

[0001] Cross-reference to related applications

[0002] This application claims priority to Chinese Patent Application No. 202411207263.X, filed on August 29, 2024, entitled "An Encoding Method, Decoding Method and Communication Device", the entire contents of which are incorporated herein by reference. Technical Field

[0003] This application relates to the field of wireless communication technology, and in particular to an encoding method, a decoding method, and a communication device. Background Technology

[0004] Low-density parity-check (LDPC) codes are channel coding schemes that closely approximate the Shannon limit, offering advantages such as high performance and low complexity. They have been selected by the 3rd Generation Partnership Project (3GPP) as the coding and decoding scheme for data channels in 5G communication. Mainstream LDPC codes feature a quasi-cyclic (QC) structure, which avoids bad structures such as short cycles and improves code distance by adjusting the shift of each block.

[0005] In the arrangement of information bits and parity bits in LDPC codes, the parity bit area is relatively restricted, making it difficult to achieve both easy hardware encoding and good trap set properties, i.e., it is prone to error flooring. Summary of the Invention

[0006] This application provides an encoding method, a decoding method, and a communication device to ensure the performance stability of LDPC codes.

[0007] Firstly, an encoding method is provided. This method can be executed by a first communication device. Unless otherwise specified, "first communication device" in this application can refer to a first communication device (e.g., a network device, a terminal device), a component within the first communication device (e.g., a processor, a chip, or a chip system), or a logic module or software capable of implementing all or part of the functions of the first communication device. The method includes: the first communication device acquiring an information bit sequence; the first communication device encoding the information bit sequence based on an LDPC matrix to acquire a first parity bit sequence; and the first communication device acquiring a first sequence, which is obtained by interleaving the information bit sequence and the first parity bit sequence.

[0008] Based on the above scheme, the first communication device can interleave the information bits and parity bits in the LDPC code, thereby structurally changing the distribution rules of the information column and parity column, optimizing the loop property, reducing the occurrence of short loops, and thus ensuring the performance stability of the LDPC code.

[0009] In one possible implementation, the first sequence includes L sets of information bits, where L is an integer greater than or equal to 2, and each set of information bits includes one or more information bits. The first sequence also includes Q sets of first parity bits, where Q is an integer greater than or equal to 1, and each set of first parity bits includes one or more first parity bits. The q-th set of the Q sets of first parity bits is located between two consecutive sets of information bits in the M sets of information bits, where q is an integer greater than or equal to 1 and less than or equal to Q.

[0010] Based on the above scheme, the first communication device can arrange the information bits and the first parity bits in the first sequence according to the rules, thereby interleaving the information bits and parity bits, changing the distribution rules of the information column and the parity column from the structure, reducing the occurrence of short loops, and thus ensuring the performance stability of the LDPC code.

[0011] In one possible implementation, the LDPC matrix is ​​determined based on a first basis matrix, which is determined based on a first lifting rule and a second basis matrix. The first lifting rule includes the mapping relationship between the elements in the second basis matrix and the submatrices in the first basis matrix.

[0012] Based on the above scheme, the first communication device can perform a first-stage improvement on the second basis matrix to obtain the first basis matrix, and then perform a second-stage improvement on the first basis matrix to obtain the LDPC matrix. In this way, hardware resources will not be wasted during the decoding process, and idle modules for information exchange will be avoided, thereby improving the hardware utilization of the LDPC matrix and having low implementation complexity.

[0013] In one possible implementation, the first basis matrix is ​​determined by mapping the first element included in the second basis matrix to the submatrix corresponding to the first element in the first basis matrix based on a first lifting rule.

[0014] Based on the above scheme, the first communication device can map the elements included in the second basis matrix to the corresponding submatrices, thereby obtaining the first basis matrix.

[0015] In one possible implementation, the LDPC matrix is ​​determined based on a first basis matrix, which is an M×N matrix comprising submatrices A1, B1, C1, D1, and E1. Submatrices A1, B1, C1, D1, and E1 are rows 1 to m1 and columns 1 to n1 of the first basis matrix; submatrices B1, C1, D1, and E1 are rows 1 to m1 and columns 1 to n2 of the first basis matrix; submatrices D1 and E1 are rows 1 to m1 and columns 1 to n2 of the first basis matrix; and submatrices E1 and E1 are rows 1 to m1 and columns 1 to n2 of the first basis matrix. Here, m1 is an integer greater than or equal to 1 and less than M; n1 is an integer greater than or equal to 1 and less than or equal to N; n2 is an integer greater than or equal to 1 and less than or equal to N; and n1 is less than or equal to n2. Submatrix B1 comprises one or more disjoint square matrices, the diagonals of which coincide with the diagonal of submatrix B1. Submatrix B1 is either composed entirely of zeros above its diagonal and entirely of non-zeros below its diagonal, or composed entirely of zeros below its diagonal.

[0016] In one possible implementation, the square matrix contained in submatrix B1 corresponds one-to-one with the set of Q first parity bits.

[0017] Based on the above scheme, the submatrix B1 is divided into one or more square matrices, each of which corresponds to the first parity bit set located between two consecutive sets of information bits. This allows the distribution rules of the information column and the parity column to be changed structurally, ensuring the performance stability of the LDPC code.

[0018] In one possible implementation, the q-th first parity bit set is t consecutive bits from the ZC bits corresponding to the target column. Here, the target column is the information column corresponding to the first square matrix containing the q-th first parity bit set in submatrix B1, where t belongs to [1, ZC], and ZC is an integer greater than 1.

[0019] Based on the above scheme, the t consecutive bits in the ZC bits corresponding to the target column can be the first parity bit set located between two consecutive sets of information bits. Therefore, the distribution rules of the information column and the parity column can be changed in structure to ensure the performance stability of the LDPC code.

[0020] In one possible implementation, the rows of submatrix A1 contain x regions, and the target column corresponds to the column with a weight of 1 in at least one of the x regions, where x is an integer greater than or equal to 1.

[0021] In one possible implementation, t = 1 or t = ZC. Based on the above scheme, when t = 1, full rank is guaranteed with minimal impact, saving transmission resources. When t = ZC, bit-level interleaving is not required, only block-level interleaving is needed, simplifying hardware implementation. Furthermore, the coding structure can maintain full rank, information bits and check bits are clearly defined, there are no redundant lines, and therefore no waste of transmission resources.

[0022] In one possible implementation, the n1+1 to n2th columns of submatrix B1 are located at a specified position, which is the position between the first set and the second set in submatrix A1. The row containing element 0 in the first set is the same, the row containing element 0 in the second set is the same, and the row containing element 0 in the first set is different from the row containing element 0 in the second set.

[0023] Based on the above scheme, the first check column appears at the intersection of columns represented by different sets, avoiding the waste of decoding parallelism and computing resources caused by switching connection relationships, and reducing the hardware complexity of the first communication device.

[0024] In one possible implementation, the first parity column in the second basis matrix corresponds to multiple columns in the first basis matrix, and the first parity column in the first basis matrix is ​​one of the multiple columns in the first basis matrix.

[0025] Based on the above scheme, the full rank of the verification region can be maintained, and the special structure can ensure that the number of idle cycles during the decoding process is small and the hardware utilization rate is high.

[0026] In one possible implementation, the first parity column in the second basis matrix includes at least two columns, each of which corresponds to one or more columns in the first basis matrix. The first parity column in the second basis matrix corresponds to adjacent columns among multiple columns in the first basis matrix, and the multiple columns in the first basis matrix correspond to the at least two columns. The first basis matrix is ​​determined based on the second basis matrix.

[0027] Based on the above scheme, during the multi-block parallel decoding process, the position of each query c2v can be made exactly the same without sacrificing decoding performance.

[0028] Secondly, a decoding method is provided. This method can be executed by a second communication device. Unless otherwise specified, "second communication device" in this application can refer to a second communication device (e.g., a network device, a terminal device), a component within the second communication device (e.g., a processor, a chip, or a chip system), or a logic module or software capable of implementing all or part of the functions of the second communication device. The method includes: obtaining a first sequence; deinterleaving the first sequence to obtain a deinterleaved sequence. The deinterleaved sequence is obtained by deinterleaving the information bit sequence to be decoded and a first parity bit sequence. Decoding the deinterleaved sequence based on a low-density parity-check (LDPC) matrix to obtain an information bit sequence.

[0029] In one possible implementation, the first sequence includes L sets of information bits, where L is an integer greater than or equal to 2, and each set of information bits includes one or more information bits. The first sequence also includes Q sets of first parity bits, where Q is an integer greater than or equal to 1, and each set of first parity bits includes one or more first parity bits. The q-th set of the Q sets of first parity bits is located between two consecutive sets of information bits in the M sets of information bits, where q is an integer greater than or equal to 1 and less than or equal to Q.

[0030] In one possible implementation, the LDPC matrix is ​​determined based on a first basis matrix, which is determined based on a first lifting rule and a second basis matrix. The first lifting rule includes the mapping relationship between the elements in the second basis matrix and the submatrices in the first basis matrix.

[0031] In one possible implementation, the first basis matrix is ​​determined by mapping the first element included in the second basis matrix to the submatrix corresponding to the first element in the first basis matrix based on a first lifting rule.

[0032] In one possible implementation, the LDPC matrix is ​​determined based on a first basis matrix, which is an M×N matrix comprising submatrices A1, B1, C1, D1, and E1. Submatrices A1, B1, C1, D1, and E1 are rows 1 to m1 and columns 1 to n1 of the first basis matrix; submatrices B1, C1, D1, and E1 are rows 1 to m1 and columns 1 to n2 of the first basis matrix; submatrices D1 and E1 are rows 1 to m1 and columns 1 to n2 of the first basis matrix; and submatrices E1 and E1 are rows 1 to m1 and columns 1 to n2 of the first basis matrix. Here, m1 is an integer greater than or equal to 1 and less than M; n1 is an integer greater than or equal to 1 and less than or equal to N; n2 is an integer greater than or equal to 1 and less than or equal to N; and n1 is less than or equal to n2. Submatrix B1 comprises one or more disjoint square matrices, the diagonals of which coincide with the diagonal of submatrix B1. Submatrix B1 is either composed entirely of zeros above its diagonal and entirely of non-zeros below its diagonal, or composed entirely of zeros below its diagonal.

[0033] In one possible implementation, the square matrix contained in submatrix B1 corresponds one-to-one with the set of Q first parity bits.

[0034] In one possible implementation, the q-th first parity bit set is t consecutive bits from the ZC bits corresponding to the target column. Here, the target column is the information column corresponding to the first square matrix containing the q-th first parity bit set in submatrix B1, where t belongs to [1, ZC], and ZC is an integer greater than 1.

[0035] In one possible implementation, the rows of submatrix A1 contain x regions, and the target column corresponds to the column with a weight of 1 in at least one of the x regions, where x is an integer greater than or equal to 1.

[0036] In one possible implementation, t = 1, or t = ZC.

[0037] In one possible implementation, the n1+1 to n2th columns of submatrix B1 are located at a specified position, which is the position between the first set and the second set in submatrix A1. The row containing element 0 in the first set is the same, the row containing element 0 in the second set is the same, and the row containing element 0 in the first set is different from the row containing element 0 in the second set.

[0038] In one possible implementation, the first parity column in the second basis matrix corresponds to multiple columns in the first basis matrix, and the first parity column in the first basis matrix is ​​one of the multiple columns in the first basis matrix.

[0039] In one possible implementation, the first parity column in the second basis matrix includes at least two columns, each of which corresponds to one or more columns in the first basis matrix. The first parity column in the second basis matrix corresponds to adjacent columns among multiple columns in the first basis matrix, and the multiple columns in the first basis matrix correspond to the at least two columns. The first basis matrix is ​​determined based on the second basis matrix.

[0040] Thirdly, a communication device is provided, including a processing unit and a transceiver unit.

[0041] The processing unit is used to acquire the information bit sequence. The processing unit is also used to encode the information bit sequence based on the LDPC matrix to acquire a first parity bit sequence. The processing unit is also used to acquire a first sequence, which is obtained by interleaving the information bit sequence and the first parity bit sequence. The transceiver unit is used to transmit the first sequence.

[0042] In one possible implementation, the first sequence includes L sets of information bits, where L is an integer greater than or equal to 2, and each set of information bits includes one or more information bits. The first sequence also includes Q sets of first parity bits, where Q is an integer greater than or equal to 1, and each set of first parity bits includes one or more first parity bits. The q-th set of the Q sets of first parity bits is located between two consecutive sets of information bits in the M sets of information bits, where q is an integer greater than or equal to 1 and less than or equal to Q.

[0043] In one possible implementation, the LDPC matrix is ​​determined based on a first basis matrix, which is determined based on a first lifting rule and a second basis matrix. The first lifting rule includes the mapping relationship between the elements in the second basis matrix and the submatrices in the first basis matrix.

[0044] In one possible implementation, the first basis matrix is ​​determined by mapping the first element included in the second basis matrix to the submatrix corresponding to the first element in the first basis matrix based on a first lifting rule.

[0045] In one possible implementation, the LDPC matrix is ​​determined based on a first basis matrix, which is an M×N matrix comprising submatrices A1, B1, C1, D1, and E1. Submatrices A1, B1, C1, D1, and E1 are rows 1 to m1 and columns 1 to n1 of the first basis matrix; submatrices B1, C1, D1, and E1 are rows 1 to m1 and columns 1 to n2 of the first basis matrix; submatrices D1 and E1 are rows 1 to m1 and columns 1 to n2 of the first basis matrix; and submatrices E1 and E1 are rows 1 to m1 and columns 1 to n2 of the first basis matrix. Here, m1 is an integer greater than or equal to 1 and less than M; n1 is an integer greater than or equal to 1 and less than or equal to N; n2 is an integer greater than or equal to 1 and less than or equal to N; and n1 is less than or equal to n2. Submatrix B1 comprises one or more disjoint square matrices, the diagonals of which coincide with the diagonal of submatrix B1. Submatrix B1 is either composed entirely of zeros above its diagonal and entirely of non-zeros below its diagonal, or composed entirely of zeros below its diagonal.

[0046] In one possible implementation, the square matrix contained in submatrix B1 corresponds one-to-one with the set of Q first parity bits.

[0047] In one possible implementation, the q-th first parity bit set is t consecutive bits from the ZC bits corresponding to the target column. Here, the target column is the information column corresponding to the first square matrix containing the q-th first parity bit set in submatrix B1, where t belongs to [1, ZC], and ZC is an integer greater than 1.

[0048] In one possible implementation, the rows of submatrix A1 contain x regions, and the target column corresponds to the column with a weight of 1 in at least one of the x regions, where x is an integer greater than or equal to 1.

[0049] In one possible implementation, t = 1, or t = ZC.

[0050] In one possible implementation, the n1+1 to n2th columns of submatrix B1 are located at a specified position, which is the position between the first set and the second set in submatrix A1. The row containing element 0 in the first set is the same, the row containing element 0 in the second set is the same, and the row containing element 0 in the first set is different from the row containing element 0 in the second set.

[0051] In one possible implementation, the first parity column in the second basis matrix corresponds to multiple columns in the first basis matrix, and the first parity column in the first basis matrix is ​​one of the multiple columns in the first basis matrix.

[0052] In one possible implementation, the first parity column in the second basis matrix includes at least two columns, each of which corresponds to one or more columns in the first basis matrix. The first parity column in the second basis matrix corresponds to adjacent columns among multiple columns in the first basis matrix, and the multiple columns in the first basis matrix correspond to the at least two columns. The first basis matrix is ​​determined based on the second basis matrix.

[0053] Fourthly, a communication device is provided, including a processing unit and a transceiver unit.

[0054] The transceiver unit is used to acquire a first sequence. The processing unit is used to deinterleave the first sequence to obtain a deinterleaved sequence. The deinterleaved sequence is obtained by deinterleaving the information bit sequence to be decoded and the first parity bit sequence. The processing unit is also used to decode the deinterleaved sequence based on the LDPC matrix to obtain the information bit sequence.

[0055] In one possible implementation, the first sequence includes L sets of information bits, where L is an integer greater than or equal to 2, and each set of information bits includes one or more information bits. The first sequence also includes Q sets of first parity bits, where Q is an integer greater than or equal to 1, and each set of first parity bits includes one or more first parity bits. The q-th set of the Q sets of first parity bits is located between two consecutive sets of information bits in the M sets of information bits, where q is an integer greater than or equal to 1 and less than or equal to Q.

[0056] In one possible implementation, the LDPC matrix is ​​determined based on a first basis matrix, which is determined based on a first lifting rule and a second basis matrix. The first lifting rule includes the mapping relationship between the elements in the second basis matrix and the submatrices in the first basis matrix.

[0057] In one possible implementation, the first basis matrix is ​​determined by mapping the first element included in the second basis matrix to the submatrix corresponding to the first element in the first basis matrix based on a first lifting rule.

[0058] In one possible implementation, the LDPC matrix is ​​determined based on a first basis matrix, which is an M×N matrix comprising submatrices A1, B1, C1, D1, and E1. Submatrices A1, B1, C1, D1, and E1 are rows 1 to m1 and columns 1 to n1 of the first basis matrix; submatrices B1, C1, D1, and E1 are rows 1 to m1 and columns 1 to n2 of the first basis matrix; submatrices D1 and E1 are rows 1 to m1 and columns 1 to n2 of the first basis matrix; and submatrices E1 and E1 are rows 1 to m1 and columns 1 to n2 of the first basis matrix. Here, m1 is an integer greater than or equal to 1 and less than M; n1 is an integer greater than or equal to 1 and less than or equal to N; n2 is an integer greater than or equal to 1 and less than or equal to N; and n1 is less than or equal to n2. Submatrix B1 comprises one or more disjoint square matrices, the diagonals of which coincide with the diagonal of submatrix B1. Submatrix B1 is either composed entirely of zeros above its diagonal and entirely of non-zeros below its diagonal, or composed entirely of zeros below its diagonal.

[0059] In one possible implementation, the square matrix contained in submatrix B1 corresponds one-to-one with the set of Q first parity bits.

[0060] In one possible implementation, the q-th first parity bit set is t consecutive bits from the ZC bits corresponding to the target column. Here, the target column is the information column corresponding to the first square matrix containing the q-th first parity bit set in submatrix B1, where t belongs to [1, ZC], and ZC is an integer greater than 1.

[0061] In one possible implementation, the rows of submatrix A1 contain x regions, and the target column corresponds to the column with a weight of 1 in at least one of the x regions, where x is an integer greater than or equal to 1.

[0062] In one possible implementation, t = 1, or t = ZC.

[0063] In one possible implementation, the n1+1 to n2th columns of submatrix B1 are located at a specified position, which is the position between the first set and the second set in submatrix A1. The row containing element 0 in the first set is the same, the row containing element 0 in the second set is the same, and the row containing element 0 in the first set is different from the row containing element 0 in the second set.

[0064] In one possible implementation, the first parity column in the second basis matrix corresponds to multiple columns in the first basis matrix, and the first parity column in the first basis matrix is ​​one of the multiple columns in the first basis matrix.

[0065] In one possible implementation, the first parity column in the second basis matrix includes at least two columns, each of which corresponds to one or more columns in the first basis matrix. The first parity column in the second basis matrix corresponds to adjacent columns among multiple columns in the first basis matrix, and the multiple columns in the first basis matrix correspond to the at least two columns. The first basis matrix is ​​determined based on the second basis matrix.

[0066] Fifthly, a communication device is provided for implementing the various methods described above. This communication device may be a first communication device as described in the first aspect, or a device comprising the first communication device, or a device included in the first communication device, such as a chip; or, the communication device may be a second communication device as described in the second aspect, or a device comprising the second communication device, or a device included in the second communication device. The communication device includes modules, units, or means corresponding to the methods described above, which may be implemented in hardware, software, or by hardware executing corresponding software. The hardware or software includes one or more modules or units corresponding to the functions described above.

[0067] A sixth aspect provides a communication device, comprising: a processor and a communication interface; the communication interface being used to communicate with a module outside the communication device; the processor being used to execute a computer program or instructions to cause the method described in any of the preceding aspects to be executed. The communication device may be a first communication device as described in the first aspect, or a device comprising the first communication device, or a device included in the first communication device, such as a chip; or, the communication device may be a second communication device as described in the second aspect, or a device comprising the second communication device, or a device included in the second communication device.

[0068] A seventh aspect provides a communication device, comprising: at least one processor; the processor being configured to execute a computer program or instructions stored in a memory to implement the method described in any of the preceding aspects. The memory may be coupled to the processor, or may be independent of the processor. The communication device may be a first communication device as described in the first aspect, or a device comprising the first communication device, or a device included in the first communication device, such as a chip; or, the communication device may be a second communication device as described in the second aspect, or a device comprising the second communication device, or a device included in the second communication device.

[0069] Eighthly, this application provides a communication system that may include a first communication device that performs the method described in the first aspect and a second communication device that performs the method described in the second aspect.

[0070] Ninthly, this application provides a computer-readable storage medium storing computer-readable instructions that, when read and executed by a computer, cause the computer to perform a method in any possible implementation of any of the first to second aspects described above.

[0071] In a tenth aspect, this application provides a computer program product that, when read and executed by a computer, causes the computer to perform a method in any possible implementation of any of the first to second aspects described above.

[0072] In one aspect, this application provides a chip for reading a computer program stored in a memory to execute the method in any possible implementation of any of the first to second aspects described above.

[0073] It is understandable that the technical effects of aspects two through eleven can be referenced from the technical effects of aspect one, and will not be elaborated here. Attached Figure Description

[0074] Figure 1 is a schematic diagram of a 4*4 cyclic shift matrix;

[0075] Figure 2 is a schematic diagram of the basis matrix in LDPC code;

[0076] Figure 3 is a schematic diagram of the verification matrix;

[0077] Figure 4 is a schematic diagram of the region division method of the basis matrix;

[0078] Figure 5 is a schematic diagram of a communication system architecture provided in an embodiment of this application;

[0079] Figure 6 is a schematic diagram of an information bit arrangement method for NR-LDPC;

[0080] Figure 7 is a schematic diagram of a coding / decoding process provided in an embodiment of this application;

[0081] Figure 8 is an exemplary flowchart of an encoding method provided in an embodiment of this application;

[0082] Figure 9 is a schematic diagram of a multi-segment lifting basis matrix provided in an embodiment of this application;

[0083] Figure 10 is a schematic diagram of a first sequence provided in an embodiment of this application;

[0084] Figure 11A is a schematic diagram of a region division method for a submatrix B1 provided in an embodiment of this application;

[0085] Figure 11B is a schematic diagram of another region division method of submatrix B1 provided in the embodiment of this application;

[0086] Figure 12 is a schematic diagram of another region division method of submatrix B1 provided in an embodiment of this application;

[0087] Figure 13A is a schematic diagram showing the interweaving of columns of submatrix B1 and submatrix A1 according to an embodiment of this application;

[0088] Figure 13B is a schematic diagram showing the interweaving of columns of submatrix B1 and submatrix A1 in another embodiment of this application;

[0089] Figure 14A is a schematic diagram of a set representation of a submatrix A1 provided in an embodiment of this application;

[0090] Figure 14B is a schematic diagram of a designated location provided in an embodiment of this application;

[0091] Figure 15 is a schematic diagram of a core check column in a first base matrix provided in an embodiment of this application;

[0092] Figure 16 is an exemplary flowchart of a decoding method provided in an embodiment of this application;

[0093] Figure 17 is a schematic diagram of the structure of a communication device provided in an embodiment of this application;

[0094] Figure 18 is a schematic diagram of another communication device provided in an embodiment of this application;

[0095] Figure 19 is a schematic diagram of another communication device provided in an embodiment of this application;

[0096] Figure 20 is a schematic diagram of another communication device provided in an embodiment of this application. Detailed Implementation

[0097] To facilitate understanding of the content of this application, the nouns or terms involved in the embodiments of this application will be explained below.

[0098] I. Information Bit Sequence

[0099] An information bit sequence refers to a sequence of multiple bits to be sent. For example, if the bits to be sent are 1, 0, 1, 0, 1, 1, 0, 0, 1, 0, 1, then the information bit sequence is: 10101100101.

[0100] II. Code Distance: In information encoding, the number of bits that differ between corresponding positions in two valid codes is called the code distance, also known as the Hamming distance. For example, if 10101 and 00110 differ in their first, fourth, and fifth bits respectively, then the code distance is 3.

[0101] Third, the trapping set, which exists in the bipartite graph (Tanner graph) of LDPC code, is the direct cause affecting the decoding performance of LDPC code.

[0102] IV. Error floor: Due to the presence of trap sets in the bipartite tanner graph of LDPC codes, when the signal-to-noise ratio (SNR) reaches a certain threshold, the bit error rate (BER) of some LDPC codes no longer continues to decrease rapidly with the increase of SNR, but instead exhibits a near-saturation state, which is the error floor phenomenon.

[0103] Fifth, the first promotion rule is used to promote the second basis matrix to obtain the first basis matrix. The first promotion rule includes the mapping relationship between the elements in the second basis matrix and the submatrices in the first basis matrix.

[0104] VI. Interleaving is a technique used in communication systems for data processing. Essentially, interleaving is a technique that aims to alter the structure of information to the greatest extent possible without changing its content.

[0105] VII. LDPC Code

[0106] LDPC codes are a channel coding scheme very close to the Shannon limit, characterized by high performance and low complexity. They have been adopted by 3GPP as the coding and decoding scheme for 5G communication data channels. Mainstream LDPC codes have a quasi-cyclic (QC) structure, which avoids bad structures such as short cycles and improves code distance by setting the shift amount of each block.

[0107] LDPC codes can be represented using a basis matrix, where elements are either 0 or 1. Expanding the basis matrix by adding 1 elements results in a ZC*ZC cyclic shift matrix, and expanding by adding 0 elements results in a ZC*ZC zero matrix. This expansion yields a parity-check matrix, which can be used for encoding or decoding. ZC can be referred to as the expansion factor, lifting factor, expansion value, expansion coefficient, lifting size, etc. The basis matrix can be represented as H. BG BG is an abbreviation for base graph.

[0108] For example, if the element in the i-th row and j-th column of the basis matrix is ​​1 and corresponds to a shifting value (SV), it can be represented by P. i,j This represents the shift value corresponding to the i-th row and j-th column. A shift value can be used to obtain the value of a cyclic shift.

[0109] Taking Zc=4 as an example, the matrix obtained by cyclically shifting the 4*4 identity matrix to the right by 1, 2, 3, and 0 times respectively is shown in Figure 1. That is, the number of cyclic shifts are 1, 2, 3, and 0 respectively.

[0110] The following example illustrates this. Figure 2 shows an example of the basis matrix in an LDPC code. This basis matrix is ​​a 3x3 matrix, and we assume ZC = 4, and P... 0,0 The corresponding right circular shift count is 1, P 0,1 The corresponding right circular shift count is 2, P 1,0 The corresponding right circular shift count is 3, P 1,2 The corresponding right circular shift count is 3, P 2,2 The corresponding right circular shift count is 1. After expanding the base matrix, we can obtain the parity check matrix as shown in Figure 3.

[0111] Currently, the 3GPP 38.212 protocol defines various values ​​for the lift dimension (ZC) as shown in Table 1.

[0112] Table 1

[0113] Referring to Table 1, the value of the lifting dimension ZC can be... Where j represents the j-th row in Table 1, j = 0, 1, 2, 3, 4, 5, 6, 7, a0, a1, a2, a3, a 4, a 5, a6 and a7 are 2, 3, 5, 7, 9, 11, 13, and 15 respectively. k j The value of traverses from 0 to max(k) j ), where max(k0), max(k1), max(k2), max(k3), max(k4), max(k5), max(k6), and max(k7) are 7, 7, 6, 5, 5, 5, 4, and 4, respectively.

[0114] For example, if j = 0, then a0 = 2, and k0 iterates through 0 to 7, so the value of ZC can be 2*2. 0 2*2 1 ,2*2 2 2*2 3 ,2*2 4 2*2 5 2*2 6 ,2*2 7 That is, 2, 4, 8, 16, 32, 64, 128, 256. The cases where j takes values ​​from 1 to 7 are similar and will not be elaborated further.

[0115] The protocol also stipulates that each row of ZC in Table 1 corresponds to a set of SV. When constructing the parity check matrix, the size of ZC is first determined, then the set of SV corresponding to that ZC is determined, and then the parity check matrix is ​​constructed based on ZC and SV.

[0116] Table 2 below shows some examples of a set of SVs defined in the 3GPP 212 protocol.

[0117] Table 2

[0118] Table 2 shows the basis matrix H. BG The translation values ​​SV corresponding to the elements with a value of 1 in row 0 i,j The set index i in Table 2 LS That is, the set index i in Table 1 LS Furthermore, the cyclic shift values ​​corresponding to each element with a value of 1 in the 0th row of the basis matrix BG can be obtained by taking the modulo of ZC using the corresponding translation value.

[0119] It should be noted that Table 2 only shows the translation values ​​corresponding to each element in row 0. In practice, it also includes the translation values ​​corresponding to each element in other rows (such as row 1, row 2, etc.).

[0120] Referring to Table 2, when ZC takes the values ​​of 2, 4, 8, 16, 32, 64, 128, or 256, then i LS =0, basis matrix H BG The SV values ​​of the elements with a value of 1 in row 0 are 250, 69, 226, 159, 100, 10, 59, 229, 110, 191, 9, 195, 23, 190, 35, 239, 31, 1, 0. Assuming ZC = 4, then the basis matrix H... BG The cyclic shift counts corresponding to the elements with a value of 1 in row 0 are 250 mod 4, 69 mod 4, 226 mod 4, 159 mod 4, 100 mod 4, 10 mod 4, 59 mod 4, 229 mod 4, 110 mod 4, 191 mod 4, 9 mod 4, 195 mod 4, 23 mod 4, 190 mod 4, 35 mod 4, 239 mod 4, 31 mod 4, 1 mod 4, 0 mod 4, which are 2, 1, 2, 3, 0, 2, 3, 1, 2, 3, 1, 3, 3, 2, 3, 3, 3, 1, 0. This means that the 4x4 identity matrix is ​​cyclically shifted 2, 1, 2, 3, 0, 2, 3, 1, 2, 3, 1, 3, 3, 2, 3, 3, 3, 1, 0 times to obtain the basis matrix H. BG The elements in row 0 that have a value of 1 correspond to a 4x4 matrix. For the basis matrix H...BG The elements in the 0th row that have a value of 0 correspond to a zero matrix of size 4*4.

[0121] Similarly, for other values ​​of ZC, there are corresponding translation values ​​and cyclic shift counts, as detailed in Table 2.

[0122] Similarly, for the basis matrix H BG The rows other than row 0 are also determined using a similar method to determine the corresponding Zc*Zc matrix.

[0123] In this embodiment, the lifting and translation operations of the LDPC code are described as follows: For a given lifting size ZC, from the basis matrix H... BG Upgraded to the parity check matrix H, specifically, the basis matrix H BG t in i,j (where t) i,j =1) will be replaced with a ZC×ZC matrix I(P) i,j ), where I(P i,j ) is a ZC×ZC identity matrix I cyclically shifted by P i,j One (either left or right circular shift is possible) or circular shift P i,j A matrix of degree mod ZC, P i,j The translation value corresponding to the i-th row and j-th column; basis matrix H BG The zeros in H will be replaced with a ZC×ZC matrix of all zeros. It can be seen that the purpose of lifting is to improve the basis matrix H. BG To transform it into a larger parity check matrix H, the translation aims to shift each H... BG The identity matrix corresponding to the non-zero elements is cyclically shifted into a predefined matrix.

[0124] The basis matrix can also be represented by a basis graph, and the two have a corresponding relationship. The basis graph model of LDPC code is BG = (X, Y, F), where X corresponds to the variables, Y corresponds to the check equation, and F is the edge relationship. After expansion by an expansion factor of ZC, a Tanner graph is obtained, which is a bipartite graph G = (V, C, E), where V is the variable node, C is the check node, and E is the edge relationship, corresponding to the number of columns of the check matrix N = |V| = Z. c |X|, the number of rows in the parity check matrix M = |C| = Z c The number of non-zero elements in the parity check matrix is ​​|E|=Z|F|.

[0125] In a Tanner graph, a cycle is defined as a structure that starts from a vertex, follows non-repeating edges, passes through non-repeating vertices, and eventually returns to the starting point. Since a Tanner graph is bipartite, the length of its cycles can only be an even number greater than 2, such as 4, 6, or 8. Short cycles are highly detrimental to LDPC codes, primarily in two ways: short cycles form trap sets, significantly impacting the code distance; and short cycles introduce correlations into the confidence propagation decoding algorithm, leading to inaccurate mutual information estimation. Therefore, short cycles should be avoided as much as possible in the design of LDPC codes.

[0126] 8. The basis matrix of 5G LDPC codes

[0127] The basis matrices of the 5G LDPC code include BG1 and BG2. BG1 is a 46x68 matrix, and BG2 is a 42x52 matrix. Both BG1 and BG2 have the matrix structure shown in Figure 4. The LDPC code basis matrix includes submatrices A1, B1, C1, D1, and E1. As shown in Figure 4, submatrices A1 (rows 1-m1, columns 1-n1), B1 (rows 1-m1, columns n1+1-n2), C1 (rows 1-m1, columns n2+1-N), D1 (rows m1+1-M, columns 1-n2), and E1 (rows m1+1-M, columns n2+1-N). It should be understood that m1 is an integer greater than or equal to 1 and less than M, n1 is an integer greater than or equal to 1 and less than or equal to N, n2 is an integer greater than or equal to 1 and less than or equal to N, and n1 is less than or equal to n2.

[0128] In this matrix, submatrix A1 corresponds to the high-bitrate information column, submatrix B1 corresponds to the high-bitrate core verification region, submatrix C1 is a zero matrix, submatrix D1 is the incremental redundancy part of the base matrix and corresponds to the low-bitrate region, and region E is the incremental redundancy region and is an identity matrix. The base matrix takes values ​​of 0 or 1, where 0 represents an empty element and 1 represents an edge in the base graph or the association between the verification and the variable.

[0129] For example, submatrix A1 can be columns 1 to 22 and rows 1 to 4; submatrix B1 can be columns 23 to 26 and rows 1 to 4; submatrix C1 can be columns 27 to 68 and rows 1 to 4; submatrix D1 can be columns 1 to 26 and rows 5 to 46; and submatrix E1 can be columns 27 to 68 and rows 5 to 46.

[0130] The following describes the structure of the base matrix of the LDPC code in the embodiments of this application. The base matrix of the LDPC code includes an information column and a check column.

[0131] The information columns correspond to the information bits (or information bits, system bits, etc.) and are the columns corresponding to submatrix A1. The parity columns correspond to the parity bits (or parity digits) and are the columns corresponding to submatrix B1 and submatrix C1 (or submatrix E1).

[0132] In this embodiment, the check column may include a first check column and a second check column. The bit in the sequence to be encoded corresponding to the first check column can be called the first check bit, and the bit corresponding to the second check column can be called the second check bit. The first check column is the column corresponding to submatrix B1, and the second check column is the column corresponding to submatrix C1 or submatrix E1. The second check column can also be called a raptor-like column.

[0133] Alternatively, the first check column is the check column in submatrix B1 with a column weight greater than 1, and the second check column is the remaining columns in the check column excluding the first check column; wherein, submatrix B1 contains the element 1 both above and below its diagonal.

[0134] Alternatively, the first check column can be a check column with a weight greater than 1, and the second check column can be a check column with a weight equal to 1.

[0135] Alternatively, the first check column is a check column where both the upper and lower triangles of the corresponding check area have non-zero elements, and the second check column is a check column where the upper triangle of the corresponding check area contains zeros, and only the lower triangle contains non-zero elements.

[0136] It should be noted that the "upper triangle" mentioned in the embodiments of this application may or may not include elements on the diagonal of the matrix. Similarly, the "lower triangle" mentioned in the embodiments of this application may or may not include elements on the diagonal of the matrix.

[0137] For ease of description, the "first check column" will be referred to as the "core check column" and the "first check bit" as the "core check bit". Similarly, the "second check column" will be referred to as the "extended check column" and the "second check bit" as the "extended check bit".

[0138] The technical solutions of this application can be applied to various communication systems, such as: Global System for Mobile Communications (GSM), Enhanced Data Rate for GSM Evolution (EDGE), Wideband Code Division Multiple Access (WCDMA), Time Division-Synchronization Code Division Multiple Access (TD-SCDMA), Long Term Evolution (LTE), Worldwide Interoperability for Microwave Access (WiMAX), and 5th Generation (5G) mobile communication systems, such as New Radio (NR). The technical solutions provided in this application can also be applied to future communication systems. These communication systems can also be Bluetooth communication systems, Wireless Local Area Network (WLAN) / WiFi communication systems, Narrow Band Internet of Things (NB-IoT) communication systems, etc. The technical solutions of this application can also be applied to satellite communication systems, wherein the satellite communication system can be integrated with the above-mentioned communication systems.

[0139] To facilitate understanding of the embodiments of this application, the application scenario used in this application will be described using the communication system architecture shown in FIG5 as an example. Referring to FIG5, the communication system includes a network device 101 and a terminal device 102. The communication device provided in the embodiments of this application can be applied to the network device 101 or to the terminal device 102. It is understood that FIG5 only shows one possible communication system architecture that can be applied to the embodiments of this application, and in other possible scenarios, the communication system architecture may also include other devices.

[0140] Network device 101 is a node in a radio access network (RAN), and can be referred to as access network equipment, RAN node, etc. Optionally, the RAN can be a 3GPP-related cellular system, such as a 4G mobile communication system (e.g., LTE system), a 5G mobile communication system (e.g., NR system), or a future-oriented evolution system. The RAN can also be an open access network (O-RAN or ORAN), a cloud radio access network (CRAN), or a wireless fidelity (WiFi) system. The RAN can also be a communication system that integrates two or more of the above systems.

[0141] In one possible scenario, access network equipment can be a base station, an evolved NodeB (eNodeB), an access point (AP), a transmission reception point (TRP), a next-generation NodeB (gNB), a base station in a future mobile communication system, or an access node in a WiFi system. Access network equipment can also be a macro base station, a micro base station or indoor station, a relay node or donor node, or a radio controller in a CRAN scenario. Optionally, access network equipment can also be a server, wearable device, vehicle, or in-vehicle equipment. For example, in vehicle-to-everything (V2X) technology, the access network equipment can be a roadside unit (RSU).

[0142] In another possible scenario, multiple RAN nodes collaborate to assist the terminal in achieving wireless access, with each RAN node performing a portion of the base station's functions. For example, RAN nodes can be central units (CUs), distributed units (DUs), CU-control plane (CPs), CU-user plane (UPs), or radio units (RUs), etc. CUs and DUs can be separate entities or included in the same network element, such as a baseband unit (BBU). RUs can be included in radio frequency equipment or radio frequency units, such as remote radio units (RRUs), active antenna units (AAUs), or remote radio heads (RRHs).

[0143] In different systems, CU (or CU-CP and CU-UP), DU, or RU may have different names, but those skilled in the art will understand their meaning. For example, in an ORAN system, CU can also be called an open centralized unit (O-CU) or an open CU, DU can also be called an open distributed unit (O-DU), CU-CP can also be called an open centralized unit control plane (O-CU-CP), CU-UP can also be called an open centralized unit user plane (O-CU-UP), and RU can also be called an open radio unit (O-RU). For ease of description, this application uses CU, CU-CP, CU-UP, DU, and RU as examples. Any of the units among CU (or CU-CP, CU-UP), DU, and RU in this application can be implemented through software modules, hardware modules, or a combination of software and hardware modules.

[0144] In the embodiments of this application, the functions of the network device can be executed by modules (such as chips) within the network device, or by a control subsystem that includes the functions of the network device. This control subsystem, which includes the functions of the network device, can be a control center in the aforementioned application scenarios such as smart grids, industrial control, intelligent transportation, and smart cities.

[0145] Terminal equipment 102, also known as user equipment (UE), mobile station (MS), mobile terminal (MT), etc., is a device that provides voice or data connectivity to users, and can also be an Internet of Things (IoT) device. For example, terminal equipment includes handheld devices with wireless connectivity, vehicle-mounted devices, etc. Currently, terminal devices can be: mobile phones, tablets, laptops, PDAs, mobile internet devices (MIDs), wearable devices (such as smartwatches, smart bracelets, pedometers, etc.), in-vehicle devices (such as cars, bicycles, electric vehicles, airplanes, ships, trains, high-speed trains, etc.), virtual reality (VR) devices, augmented reality (AR) devices, wireless terminals in industrial control, smart home devices (such as refrigerators, televisions, air conditioners, electricity meters, etc.), intelligent robots, workshop equipment, wireless terminals in autonomous driving, wireless terminals in remote surgery, wireless terminals in smart grids, wireless terminals in transportation safety, wireless terminals in smart cities, or wireless terminals in smart homes, and flying devices (such as intelligent robots, hot air balloons, drones, airplanes), etc. Terminal devices can also be other devices with terminal functions; for example, a terminal device can also be a device that performs terminal functions in device-to-device (D2D) communication. In this application, terminal devices with wireless transceiver functions and chips that can be installed in the aforementioned terminal devices are collectively referred to as terminal devices.

[0146] In this embodiment of the application, the functions of the terminal device can also be performed by modules (such as chips or modems) in the terminal, or by a device containing terminal functions.

[0147] Network devices and terminals can be fixed in location or mobile. They can be deployed on land, including indoors or outdoors, handheld or vehicle-mounted; they can also be deployed on water; and they can be deployed in the air on airplanes, balloons, and artificial satellites. The embodiments of this application do not limit the application scenarios of the network devices and terminals.

[0148] In the embodiments of this application, "at least one" refers to one or more, and "more than one" refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, and / or c can represent: a, b, c, a and b, a and c, b and c, or a, b, and c, where each of a, b, and c can be an element itself or a set containing one or more elements.

[0149] In this application, terms such as "exemplary," "in some embodiments," and "in other embodiments" are used to indicate that something is an example, illustration, or description. Any embodiment or design that is described as "exemplary" in this application should not be construed as being more preferred or advantageous than other embodiments or designs. Rather, the term "exemplary" is used to present the concept in a specific manner.

[0150] In this application, the terms "of," "corresponding (relevant)," and "corresponding" may sometimes be used interchangeably. It should be noted that, unless a distinction is emphasized, their intended meanings are consistent. Similarly, in the embodiments of this application, "communication" and "transmission" may sometimes be used interchangeably. It should be noted that, unless a distinction is emphasized, their intended meanings are consistent. For example, transmission can include sending and / or receiving, and can be a noun or a verb.

[0151] In this application, "instruction" can include direct instruction, indirect instruction, explicit instruction, and implicit instruction. When describing a certain instruction information for the purpose of instructing A, it can be understood that the instruction information carries A, directly instructs A, or indirectly instructs A.

[0152] It should be noted that the terms "first" and "second" used in the embodiments of this application are used only for the purpose of distinguishing descriptions and should not be construed as indicating or implying relative importance or order.

[0153] Currently, the information bit arrangement of NR-LDPC is shown in Figure 6. The information bits, core parity bits, and extended parity bits are arranged as shown in Figure 6. The information bits correspond to the information columns of the base diagram, and the parity bits correspond to the parity columns of the base diagram. For example, in NR's BG1, the information columns are 1-22, and the parity columns are 23-68, with the core parity columns being 23-26 and the extended parity columns being 27-68.

[0154] It should be understood that the above example uses column number 1 as the starting point for illustration. In this article, the starting number can be 0 or 1.

[0155] In the arrangement of information bits and parity bits in 5G LDPC codes, submatrix B1 needs to be capable of parallel encoding and adaptable to different requirements. Therefore, it requires fixed shift values ​​for different lifting sizes, which imposes significant limitations. This makes it difficult to achieve both easy hardware encoding and good trap set properties, and it is prone to error flooring. Furthermore, because the column-to-column encoding structure of submatrix B1 needs to satisfy characteristics such as full row rank, it is incompatible with highly parallel hardware decoding methods, resulting in additional wasted computational resources and latency.

[0156] Therefore, this application provides an encoding and decoding method. Taking the communication system shown in Figure 1 as an example, to ensure the reliability of communication between devices, the transmitting end can encode the information to be transmitted, and correspondingly, the receiving end decodes the encoded information after receiving it. As shown in the encoding and decoding process in Figure 7, the source signal from the transmitting end is transmitted on the channel after sequentially undergoing source encoding, channel encoding, rate matching, and modulation. After receiving the signal, the receiving end sequentially undergoes demodulation and rate matching, channel decoding, and source decoding to obtain the destination signal. The transmitting end and the receiving end can be either network devices or terminal devices, respectively. It can be understood that in downlink communication, the network device is the transmitting end and the terminal device is the receiving end; in uplink communication, the terminal device is the transmitting end and the network device is the receiving end. The network device can be either a transmitting end or a receiving end. Furthermore, this application does not exclude the possibility that both the transmitting end and the receiving end are terminal devices, in which case D2D communication occurs between the transmitting end and the receiving end. The method provided in this application can be used in the channel encoding process.

[0157] Figure 8 shows a flowchart of an encoding method. This method can be applied to a first communication device. The first communication device can be the sending end in the encoding / decoding flow shown in Figure 7; correspondingly, the second communication device can be the receiving end in the encoding / decoding flow shown in Figure 7. Unless otherwise specified, the term "first communication device" in this application can refer to the first communication device itself (e.g., a network device, a terminal device), a component within the first communication device (e.g., a processor, a chip, or a chip system), or a logic module or software capable of implementing all or part of the functions of the first communication device. Similarly, unless otherwise specified, the term "second communication device" in this application can refer to the second communication device itself (e.g., a network device, a terminal device), a component within the second communication device (e.g., a processor, a chip, or a chip system), or a logic module or software capable of implementing all or part of the functions of the second communication device.

[0158] For example, when the first communication device is a terminal device, the second communication device can be a network device, or the second communication device can also be a terminal device; when the first communication device is a network device, the second communication device can be a terminal device, or the second communication device can also be a terminal device. The method includes:

[0159] S801: The first communication device acquires the information bit sequence.

[0160] The information bit sequence can be the information bit sequence to be encoded. For example, the information bit sequence can be a source-encoded information bit sequence.

[0161] S802: The first communication device encodes the information bit sequence based on the LDPC matrix to obtain the core check bit sequence.

[0162] The LDPC matrix can be either a generator matrix or a parity check matrix. For example, the LDPC matrix can be obtained by lifting the first base matrix according to the lifting size ZC and cyclically shifting it according to the translation value SV. The first base matrix can be either BG1 or BG2 of the 5G LDPC code.

[0163] In one possible implementation, the first basis matrix can be obtained from the second basis matrix. For example, the first communication device can map the elements contained in the second basis matrix to their corresponding submatrices to obtain the first basis matrix. Exemplarily, the first basis matrix can be determined by the second basis matrix and a first promotion rule. The first promotion rule includes the mapping relationship between the elements in the second basis matrix and the submatrices in the first basis matrix.

[0164] For example, the first communication device can map the elements (such as the first element) included in the second basis matrix to the corresponding submatrix (such as the submatrix corresponding to the first element) in the first basis matrix. In this way, the first communication device can obtain the first basis matrix, and then obtain the LDPC matrix, such as the parity check matrix of the LDPC, based on the lift dimension, translation value, and the first basis matrix. That is to say, in this embodiment, the LDPC matrix can be obtained from the stored second basis matrix through a multi-stage lift. The following explanation is in conjunction with Figure 9.

[0165] Referring to Figure 9, the first communication device can store the second basis matrix and determine the submatrix mapped to each element in the second basis matrix. For example, the first communication device can determine the submatrix mapped to each element in the second basis matrix according to a first lifting rule. Assume the first lifting rule indicates that element 1 can be mapped to submatrix [1 1], element 3 can be mapped to submatrix [1 0], element 2 can be mapped to submatrix [0 1], and element 0 can be mapped to submatrix [0 0]. The first communication device can map each element in the second basis matrix to obtain the first basis matrix shown in Figure 9. The first communication device can lift and cyclically shift each non-zero position in the first basis matrix according to the lifting size and translation value to obtain the parity check matrix of the LDPC code.

[0166] It should be understood that the mapping relationship between the elements of the second basis matrix and the submatrices of the first basis matrix shown in Figure 9 is merely illustrative. Each element of the second basis matrix has multiple possibilities; if each element is promoted to, or mapped to, an a×b submatrix, then the number of element types in the second basis matrix is ​​at most 2^n. a×b indivual.

[0167] Based on the above scheme, the first communication device can store the second basis matrix, improve the first basis matrix based on the second basis matrix, and improve the LDCP matrix for encoding based on the first basis matrix. This can ensure high hardware utilization of the LDPC matrix and low implementation complexity.

[0168] S803: The first communication device acquires the first sequence.

[0169] The first sequence can be obtained by interleaving an information bit sequence and a core check bit sequence. For example, the first sequence may include an information bit sequence, a core check bit sequence, and an extended check bit sequence. The information bit sequence and the core check bit sequence in the first sequence can be arranged in an alternating pattern.

[0170] For example, after encoding an information bit sequence, the first communication device may interleave the information bit sequence and a core check bit sequence to obtain a first sequence. For another example, the information columns and core check columns in the LDPC matrix may be arranged in a cross pattern. The first communication device may arrange the information bit sequence and the core check bit sequence according to the positions of the information columns and core check columns in the LDPC matrix, and after encoding the information bit sequence based on the LDPC matrix to obtain the core check bit sequence, obtain the first sequence. For yet another example, the first communication device may arrange the information bits, core check bits, and extended check bits in the manner shown in FIG. 6. After receiving the first sequence, the second communication device may interleave the information bits and the core check bits, and decode the interleaved first sequence.

[0171] In an embodiment of the present application, the first sequence includes L information bit sets, and each information bit set includes one or more information bits. Among them, the first sequence further includes Q core check bit sets, and each core check bit set includes one or more core check bits. It should be understood that the q-th core check bit set among the Q core check bit sets is located between two consecutive information bit sets among the M information bit sets. Here, Q is an integer greater than or equal to 1, q is an integer greater than or equal to 1 and less than or equal to Q, and L is an integer greater than or equal to 2.

[0172] For the sake of easy distinction, in an embodiment of the present application, the core check bit set located between two consecutive information bit sets is referred to as a first core check bit set, and the first core check bit set may include one or more first core check bits. In this article, the first core check bits located between two consecutive information bit sets may also be referred to as "cross check bits". Optionally, the first sequence in an embodiment of the present application may further include a second core check bit set located between the information bit sequence and the extended check bit sequence, and the second core check bit set may include one or more second core check bits. The q-th core check bit set described above may be understood as the first core check bit set.

[0173] For example, in the first sequence c, there are at least two positions i1 and i2, where i1 < i2 - 1, j1, j2 ≥ 0 such that are both information bits, are both information bits, and is a non-information bit, and at the same time i2 > i1 + j1 + 1. If there are 3 or more positions i1 < i2 < i3 <..., then i1 and i2 satisfy the above conditions, i2 and i3 satisfy the above conditions, and so on.

[0174] The following description uses two positions as an example. For instance, in the first sequence containing two information bit sequences, for i1+j1... <k<i2,c k At least one of them is a core check bit. For example, c k All of these are core check bits. The first sequence will be described below with reference to Figure 10.

[0175] Referring to Figure 10, the first sequence contains two information bit sequences, and these two information bit sequences contain a first core check bit (also known as a cross-check bit). Figure 10 illustrates this using the example of one first core check bit in two information bit sequences. During communication, there can be more first core check bits between the two information bit sequences, such as two, three, or even more.

[0176] In one possible implementation, the submatrix B1 contained in the first base matrix can be divided into multiple regions. For example, submatrix B1 may include one or more disjoint square matrices. A square matrix can be understood as a matrix with an equal number of rows and columns. The diagonals of these square matrices coincide with the diagonal of submatrix B1. In one possible case, the submatrix B1 is a matrix of all zeros above its diagonal and a matrix of non-zeros below its diagonal. In another possible case, the submatrix B1 is a matrix of all zeros below its diagonal and a matrix of non-zeros above its diagonal.

[0177] Referring to Figure 11A, a schematic diagram is shown of submatrix B1 divided into multiple regions. In Figures 11Aa and 11B, submatrix B1 is divided into two square matrices, the diagonals of which overlap with the diagonal of submatrix B1. Specifically, in Figure 11Aa, the area above the diagonal of submatrix B1 is a non-zero matrix, and the area below the diagonal is a matrix of all zeros. In Figure 11Aab, the area above the diagonal of submatrix B1 is a matrix of all zeros, and the area below the diagonal is a non-zero matrix. In Figures 11Aac and 11D, submatrix B1 is divided into three square matrices, the diagonals of which overlap with the diagonal of submatrix B1. Specifically, in Figure 11Aac, the area above the diagonal of submatrix B1 is a matrix of all zeros, and the area below the diagonal is a non-zero matrix. In Figure 11Aad, the area above the diagonal of submatrix B1 is a non-zero matrix, and the area below the diagonal is a matrix of all zeros.

[0178] It should be understood that Figure 11A shows a schematic diagram of dividing submatrix B1 into two or three square matrices. In actual communication, submatrix B1 can be divided into even more square matrices.

[0179] In some embodiments, the square matrices contained in submatrix B1 correspond one-to-one with the first core check bit set. For example, submatrix B1 may contain W square matrices, each corresponding one-to-one with one of the W first core check bit sets, where W is an integer greater than or equal to 1 and less than or equal to Q. The following explanation uses the basis matrix (first basis matrix) of the LDPC code as an example. The submatrix B1 contained in the first basis matrix can be as shown in Figure 11B. This submatrix B1 can be divided into two square matrices, namely... and In Figure 11B, the matrix above the diagonal of submatrix B1 is all zeros, and the matrix below the diagonal of submatrix B1 is non-zero. (Square matrix) This can correspond to a first core check bit set, a square matrix. It can correspond to a first core check bit set.

[0180] Based on the above scheme, the submatrix B1 is divided into one or more square matrices, each of which corresponds to a core parity bit set located between two consecutive sets of information bits. This allows for structural changes in the distribution rules of the information and parity columns, ensuring the performance stability of the LDPC code.

[0181] In one possible scenario, during the lifting process, the columns of the first basis matrix are expanded to ZC columns to form a parity check matrix. In other words, each column of the first basis matrix corresponds to ZC bits. In this case, the first core parity check bit set can be t consecutive bits from the ZC bits corresponding to the target column in the first basis matrix. Here, ZC is an integer, and t belongs to [1, ZC]. The target column can be the information column corresponding to the square matrix corresponding to this first core parity check bit set. For example, the rows of submatrix A1 can contain x regions, and the target column can correspond to a column with a column weight of 1 in at least one of the x regions. Here, x is an integer greater than or equal to 1.

[0182] For example, referring to Figure 12, submatrix B1 is divided into two square matrices. The rows of submatrix A1 contain two regions: region 1 contains the first and second rows of submatrix A1, and region 2 contains the third and fourth rows of submatrix A1. Region 1 corresponds to the square matrix... Area 2 Corresponding Square In Figure 12, the square array This can correspond to the first core check bit set A between the first information bit sequence and the second information bit sequence, a square matrix. This can correspond to the first core check bit set B between the second and third information bit sequences. Then, the first core check bit set A can be t consecutive bits from the ZC bits corresponding to the target column, and the target column can contain a square matrix. The portion of region 1 with a column weight of 1, such as the target column, can be the first column contained in submatrix A1. In other words, the first core check bit set A can be t consecutive bits from the ZC bits corresponding to the first column contained in submatrix A1. For example, Figure 12 illustrates this with t=1. Similarly, the first core check bit set B can be t consecutive bits from the ZC bits corresponding to the target column, and the target column can contain a square matrix. The portion of region 2 with a column weight of 1, such as the target column, can be the fourth column contained in submatrix A1. In other words, the first core check bit set B can be t consecutive bits from the ZC bits corresponding to the fourth column contained in submatrix A1. For example, Figure 12 illustrates this with t=1 as an example.

[0183] In another possible implementation, t = ZC. Here, t = ZC can also be understood as the columns of submatrix B1 interleaving with the columns of submatrix A1. For example, the columns of submatrix B1 are located at specified positions in submatrix A1. In one possible case, each column of submatrix B1 can be located at a specified position in submatrix A1, as shown in Figure 13A. In another possible case, multiple columns of submatrix B1 can be located at specified positions in submatrix A1, as shown in Figure 13B.

[0184] Figure 13B illustrates this using the example of two columns in submatrix B1 located at specified positions. In actual communication, submatrix B1 may contain more than one column, such as three columns located at specified positions in submatrix A1. Furthermore, in actual communication, the relative order of the check columns may not change during interleaving; for example, the positions of the first two check columns and the last two check columns may remain unchanged before and after interleaving.

[0185] In some embodiments, the specified position can be a position between the first set and the second set in submatrix A1. Specifically, the rows containing element 0 are the same in the first set and the same in the second set, but the rows containing element 0 in the first set are different from those in the second set. Alternatively, the rows containing element 1 in each column are the same in the first set and the same in the second set, but the rows containing element 1 in the first set are different from those in the second set.

[0186] Referring to Figure 14A, if submatrix A1 has rows 1, ..., m, then columns can be represented by sets of row numbers with a value of 1. For example, columns 1 to 3 in the above figure can be represented by {2, 3, 4}, columns 4 to 6 can be represented by {1, 3, 4}, ..., and the arrangement of submatrix A1 is such that columns represented by the same set are adjacent. In this implementation, the result of the interweaving of the core verification column and the information column is that the core verification column can be located at the intersection of columns represented by different sets, such as between columns 3 and 4, or between columns 6 and 7, or between columns 9 and 10, as shown in Figure 14B.

[0187] Based on the above scheme, the core verification column appears at the intersection of columns represented by different sets, avoiding the waste of decoding parallelism and computing resources caused by switching connection relationships, thus reducing the hardware complexity of the first communication device.

[0188] In this embodiment, since the first basis matrix can be determined by the second basis matrix, the relevant description in S802 can be referred to. The second basis matrix can contain three types of columns: the first type corresponds to information bits, and after promotion, its corresponding column in the first basis matrix is ​​entirely an information column; the second type corresponds to both information bits and core check bits, and after promotion, its corresponding column in the first basis matrix is ​​both an information column and a core check bit; the third type corresponds to extended check bits, and after promotion, its corresponding column in the first basis matrix is ​​entirely extended check bits. The second type of column in the second basis matrix, after promotion, corresponds to one core check column in the first basis matrix.

[0189] For example, when a second base matrix is ​​promoted to a first base matrix, a certain core check column in the second base matrix may be promoted to one or more columns in the first base matrix. Therefore, in this embodiment, the core check column in the first base matrix is ​​defined as one of one or more columns in the first base matrix. For instance, if a core check column R in the second base matrix is ​​promoted to the first and second columns in the first base matrix, then the core check column R in the first base matrix can be one of the first and second columns.

[0190] In some embodiments, the core check column corresponds to an adjacent column in the first basis matrix. For example, the core check column in the second basis matrix includes at least two columns, each of which corresponds to one or more columns in the first basis matrix. Therefore, the core check column in the second basis matrix corresponds to an adjacent column among multiple columns in the first basis matrix. In this case, multiple columns in the first basis matrix correspond to at least two columns in the second basis matrix.

[0191] For example, referring to Figure 15, the second base matrix contains 4 core check columns. Through the first-stage boosting, the second base matrix is ​​boosted to the first base matrix, and each column in the second base matrix is ​​boosted to two columns. Therefore, the 4 core check columns in the second base matrix are boosted to 8 columns, and the core check columns in the first base matrix can be 4 of these 8 columns. For example, the first core check column in the second base matrix is ​​the second of the two columns corresponding to the first core check column in the first base matrix, and the second core check column in the second base matrix is ​​the first of the two columns corresponding to the second core check column in the first base matrix. Similarly, the third core check column in the second base matrix is ​​the second of the two columns corresponding to the third core check column in the first base matrix, and the fourth core check column in the second base matrix is ​​the first of the two columns corresponding to the fourth core check column in the first base matrix.

[0192] Based on the above scheme, during the multi-block parallel decoding process, the position of each query c2v can be made exactly the same without sacrificing decoding performance.

[0193] In this embodiment of the application, the first communication device can obtain a first sequence through the embodiment shown in FIG8. The first communication device can send the first sequence.

[0194] This application also provides a decoding method. Referring to Figure 16, an exemplary flowchart of a decoding method provided in this application is shown. This method can be applied to a second communication device. The second communication device can be the receiving end in the encoding / decoding flow shown in Figure 7. For example, when the first communication device is a terminal device or a module (such as a chip) in a terminal device, the second communication device can be a terminal device or a module (such as a chip) in a terminal device; or the second communication device can also be a network device or a module (such as a chip) in a network device; when the first communication device is a network device or a module (such as a chip) in a network device, the second communication device can be a module (such as a chip) in a terminal device. The method includes:

[0195] S1601: The second communication device acquires the first sequence.

[0196] For example, the second communication device can receive a first sequence from the first communication device. The first sequence can be referred to in the aforementioned description of the first sequence acquired by the first communication device, and will not be repeated here. For instance, the second communication device can receive a received value sequence from the first communication device. This received value sequence can be a sequence obtained after the first communication device modulates, frequency-converts, or otherwise manipulates the first sequence and transmits it through a wireless transmission environment. The second communication device can obtain the first sequence by performing demodulation or other operations on the received value sequence.

[0197] S1602: The second communication device deinterleaves the first sequence to obtain the deinterleaved sequence.

[0198] The deinterleaved sequence can be obtained by deinterleaving the information bit sequence to be decoded and the core parity bit sequence. For example, a second communication device can deinterleave the information bit sequence to be decoded and the core parity bit sequence to obtain the deinterleaved sequence.

[0199] S1603: The second communication device decodes the deinterleaved sequence based on the LDPC matrix to obtain the information bit sequence.

[0200] The LDPC matrix can be referred to the relevant description in the embodiment shown in Figure 8, and will not be repeated here. The second communication device can decode the deinterleaved sequence based on the obtained LDPC matrix to obtain the information bit sequence.

[0201] Optionally, in S1602, if the information bit sequence and the core check bit sequence in the first sequence sent by the first communication device are not interleaved, then the second communication device can interleave the information bits and the core check bits in the first sequence to obtain an interleaved sequence. Then, in S1603, the second communication device can decode the interleaved sequence based on the LDPC matrix to obtain the information bit sequence.

[0202] Based on the concept of the above embodiments, and referring to FIG17, this application provides a communication device 1700, which includes a processing unit 1701 and a transceiver unit 1702. The device 1700 can be a communication device, or it can be a device applied to a communication device that can support the communication device in executing encoding and decoding methods.

[0203] The transceiver unit can also be referred to as a transceiver module, transceiver, transceiver machine, transceiver device, etc. The processing unit can also be referred to as a processor, processing board, processing unit, processing device, etc. Optionally, the device in the transceiver unit used to implement the receiving function can be considered as a receiving unit. It should be understood that the transceiver unit is used to execute the sending and receiving operations of the communication device in the above method embodiments, and the device in the transceiver unit used to implement the sending function can be considered as a sending unit; that is, the transceiver unit includes a receiving unit and a sending unit.

[0204] Furthermore, it should be noted that if the device is implemented using a chip / chip circuit, the transceiver unit can be an input / output circuit and / or a communication interface, performing input operations (corresponding to the aforementioned receiving operations) and output operations (corresponding to the aforementioned sending operations); the processing unit is an integrated processor, microprocessor, or integrated circuit.

[0205] The following describes in detail the implementation of this device 1700 in both the transmitting and receiving ends.

[0206] By way of example, when the device 1700 is applied to the transmitting end, the operations performed by its various units will be described in detail.

[0207] In one optional implementation, the communication device 1700 can be applied to a transmitting end to execute the method performed by the transmitting end, specifically, for example, the method performed by the transmitting end in the embodiment shown in FIG8.

[0208] For example, processing unit 1701 is used to acquire an information bit sequence. Processing unit 1701 is also used to encode the information bit sequence based on an LDPC matrix to acquire a first parity bit sequence. Processing unit 1701 is also used to acquire a first sequence, which is obtained by interleaving the information bit sequence and the first parity bit sequence. Transceiver unit 1702 is used to transmit the first sequence.

[0209] By way of example, the operations performed by each unit of the device 1700 when it is applied to the receiving end will be described in detail.

[0210] In one alternative implementation, the communication device 1700 can be applied to a receiving end to execute the method executed by the receiving end, specifically, for example, the method executed by the receiving end in the embodiment shown in FIG16 above.

[0211] For example, transceiver unit 1702 is used to acquire a first sequence. Processing unit 1701 is used to deinterleave the first sequence to obtain a deinterleaved sequence. The deinterleaved sequence is obtained by deinterleaving the information bit sequence to be decoded and the first parity bit sequence. Processing unit 1701 is also used to decode the deinterleaved sequence based on the LDPC matrix to obtain an information bit sequence.

[0212] Based on the concept of the embodiments, as shown in FIG18, this application provides a communication device 1800. The communication device 1800 includes a processor 1810. Optionally, the communication device 1800 may further include a memory 1820 for storing instructions executed by the processor 1810, or storing input data required by the processor 1810 to execute the instructions, or storing data generated after the processor 1810 executes the instructions. The processor 1810 can implement the method shown in the above method embodiments through the instructions stored in the memory 1820.

[0213] Based on the concept of the embodiments, as shown in FIG19, this application provides a communication device 1900, which may be a chip or a chip system. Optionally, in this application embodiment, the chip system may be composed of chips, or may include chips and other discrete devices.

[0214] The communication device 1900 may include at least one processor 1910 coupled to a memory, which may optionally be located within or outside the device. For example, the communication device 1900 may also include at least one memory 1920. The memory 1920 stores computer programs, configuration information, computer programs or instructions, and / or data necessary for implementing any of the above embodiments; the processor 1910 may execute the computer program stored in the memory 1920 to perform the methods in any of the above embodiments. Optionally, the memory may also be integrated with the processor.

[0215] The coupling in this embodiment is an indirect coupling or communication connection between devices, units, or modules, which can be electrical, mechanical, or other forms, used for information exchange between devices, units, or modules. Processor 1910 may operate in conjunction with memory 1920. This embodiment does not limit the specific connection medium between the transceiver 1930, processor 1910, and memory 1920.

[0216] The communication device 1900 may also include a transceiver 1930, through which the communication device 1900 can interact with other devices. The transceiver 1930 may be a circuit, a bus, a transceiver, or any other device that can be used for information interaction, or a signal transceiver unit. As shown in Figure 19, the transceiver 1930 includes a transmitter 1931, a receiver 1932, and an antenna 1933. Furthermore, when the communication device 1900 is a chip-type device or circuit, the transceiver in the communication device 1900 may also be an input / output circuit and / or a communication interface, capable of inputting data (or receiving data) and outputting data (or transmitting data). The processor may be an integrated processor, a microprocessor, or an integrated circuit, and the processor can determine the output data based on the input data.

[0217] In one possible implementation, the communication device 1900 can be applied to a communication device. Specifically, the communication device 1900 can be a communication device or an apparatus capable of supporting a communication device and implementing the functions of the transmitting end or receiving end in any of the above embodiments. The memory 1920 stores the necessary computer programs, computer programs or instructions and / or data for implementing the functions of the transmitting end or receiving end in any of the above embodiments. The processor 1910 can execute the computer programs stored in the memory 1920 to perform the methods executed by the transmitting end or receiving end in any of the above embodiments.

[0218] In the embodiments of this application, the processor may be a general-purpose processor, a digital signal processor, an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components, and may implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this application. The general-purpose processor may be a microprocessor or any conventional processor. The steps of the methods disclosed in the embodiments of this application can be directly manifested as being executed by a hardware processor, or executed by a combination of hardware and software modules within the processor.

[0219] In the embodiments of this application, the memory can be non-volatile memory, such as a hard disk drive (HDD) or a solid-state drive (SSD), or it can be volatile memory, such as random-access memory (RAM). The memory can also be any other medium capable of carrying or storing desired program code in the form of instructions or data structures, and accessible by a computer, but is not limited thereto. The memory in the embodiments of this application can also be a circuit or any other device capable of implementing storage functions, used to store computer programs, computer program or instruction and / or data.

[0220] Based on the above embodiments, referring to FIG20, this application embodiment also provides another communication device 2000, including: an input / output interface 2010 and a logic circuit 2020; the input / output interface 2010 is used to receive code instructions and transmit them to the logic circuit 2020; the logic circuit 2020 is used to run the code instructions to execute the method executed by the sending end or the receiving end in any of the above embodiments.

[0221] The following is a detailed description of the operations performed by the device 2000 at the transmitting or receiving end.

[0222] In one optional implementation, the communication device 2000 can be applied to a transmitting end to execute the method executed by the transmitting end, specifically, for example, the method executed by the transmitting end in the embodiment shown in FIG8 above.

[0223] For example, logic circuit 2020 is used to acquire the information bit sequence. Logic circuit 2020 is also used to encode the information bit sequence based on the LDPC matrix to acquire the first parity bit sequence. Logic circuit 2020 is also used to acquire a first sequence, which is obtained by interleaving the information bit sequence and the first parity bit sequence. Input / output interface 2010 is used to output the first sequence.

[0224] Since the communication device 2000 provided in this embodiment can be applied to a transmitting end to execute the method described above, the technical effects it can achieve can be referred to the above method embodiment, and will not be repeated here.

[0225] In one optional implementation, the communication device 2000 can be applied to a receiving end to execute the method performed by the receiving end, specifically, for example, the method performed by the receiving end in the embodiment shown in FIG16 above.

[0226] For example, input / output interface 2010 is used to input a first sequence. Logic circuit 2020 is used to deinterleave the first sequence to obtain a deinterleaved sequence. The deinterleaved sequence is obtained by deinterleaving the information bit sequence to be decoded and the first parity bit sequence. Logic circuit 2020 is also used to decode the deinterleaved sequence based on an LDPC matrix to obtain an information bit sequence.

[0227] Since the communication device 2000 provided in this embodiment can be applied to a receiving end to execute the method described above, the technical effects it can achieve can be referred to the above method embodiment, and will not be repeated here.

[0228] Based on the above embodiments, this application also provides a communication system, which includes at least one receiving end and at least one transmitting end. The technical effects obtained can be referred to the above method embodiments, and will not be repeated here.

[0229] Based on the above embodiments, this application also provides a computer-readable storage medium storing a computer program or instructions. When the instructions are executed, the method performed by the communication device in any of the above embodiments is implemented. The computer-readable storage medium may include various media capable of storing program code, such as a USB flash drive, portable hard drive, read-only memory, random access memory, magnetic disk, or optical disk.

[0230] To achieve the functions of the communication devices shown in Figures 17-20, this application embodiment also provides a chip, including a processor, for supporting the communication device in implementing the functions involved in the transmitting or receiving end in the above method embodiments. In one possible design, the chip is connected to a memory or the chip includes a memory for storing necessary computer programs, instructions, and data for the transmitting or receiving end.

[0231] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0232] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer programs or instructions. These computer programs or instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in one or more blocks of the flowchart illustrations and / or one or more blocks of the block diagrams.

[0233] These computer programs or instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means that implement the functions specified in one or more flowcharts and / or one or more block diagrams.

[0234] These computer programs or instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process, such that the instructions, which execute on the computer or other programmable apparatus, provide steps for implementing the functions specified in one or more flowcharts and / or one or more block diagrams.

Claims

1. An encoding method, characterized in that, include: Obtain the information bit sequence; The information bit sequence is encoded based on the low-density parity-check code (LDPC) matrix to obtain the first parity bit sequence. Obtain a first sequence, which is obtained by interleaving the information bit sequence and the first check bit sequence.

2. A decoding method, characterized in that, include: Obtain the first sequence; The first sequence is deinterleaved to obtain a deinterleaved sequence; wherein the deinterleaved sequence is obtained by deinterleaving the information bit sequence to be decoded and the first parity bit sequence. The deinterleaved sequence is decoded using a low-density parity-check (LDPC) matrix to obtain an information bit sequence.

3. The method according to claim 1 or 2, characterized in that, The first sequence includes L sets of information bits, where L is an integer greater than or equal to 2, and each set of information bits includes one or more information bits; wherein, the first sequence also includes Q sets of first parity bits, where Q is an integer greater than or equal to 1, and each set of first parity bits includes one or more first parity bits, wherein the q-th set of the Q sets of first parity bits is located between two consecutive sets of information bits in the M sets of information bits, and q is an integer greater than or equal to 1 and less than or equal to Q.

4. The method according to any one of claims 1 to 3, characterized in that, The LDPC matrix is ​​determined based on a first basis matrix, which is determined based on a first lifting rule and a second basis matrix. The first lifting rule includes the mapping relationship between the elements in the second basis matrix and the submatrices in the first basis matrix.

5. The method according to claim 4, characterized in that, The first basis matrix is ​​determined in the following way: The first element included in the second basis matrix is ​​mapped to the submatrix corresponding to the first element in the first basis matrix based on the first lifting rule.

6. The method according to any one of claims 3 to 5, characterized in that, The LDPC matrix is ​​determined based on a first base matrix, which is an M×N matrix. The first base matrix includes submatrices A1, B1, C1, D1, and E1. Submatrices A1 are rows 1 to m1 and columns 1 to n1 of the first base matrix; submatrices B1 are rows 1 to m1 and columns (n1+1) to n2 of the first base matrix; submatrices C1 are rows 1 to m1 and columns (n2+1) to N of the first base matrix; submatrices D1 are rows (m1+1) to M and columns 1 to n2 of the first base matrix; and submatrices E1 are rows (m1+1) to M and columns (n2+1) to N of the first base matrix. Wherein, m1 is an integer greater than or equal to 1 and less than M; n1 is an integer greater than or equal to 1 and less than or equal to N; and n2 is an integer greater than or equal to 1 and less than or equal to N, where n1 is less than or equal to n2. Wherein, the submatrix B1 comprises one or more disjoint square matrices, the diagonals of the one or more square matrices coinciding with the diagonal of the submatrix B1; wherein, the submatrix B1 is a matrix of all zeros above its diagonal and a matrix of non-zeros below its diagonal, or the submatrix B1 is a matrix of non-zeros above its diagonal and a matrix of all zeros below its diagonal.

7. The method according to claim 6, characterized in that, The square matrix contained in the submatrix B1 corresponds one-to-one with the Q sets of first parity bits.

8. The method according to claim 7, characterized in that, The q-th first check bit set is t consecutive bits among the ZC bits corresponding to the target column; wherein, the target column is the information column corresponding to the first square matrix corresponding to the q-th first check bit set contained in the submatrix B1, t belongs to [1, ZC], and ZC is an integer greater than 1.

9. The method according to claim 8, characterized in that, The submatrix A1 contains x regions in its rows, and the target column corresponds to a column with a column weight of 1 in at least one of the x regions, where x is an integer greater than or equal to 1.

10. The method according to claim 8 or 9, characterized in that, t = 1, or t = ZC.

11. The method according to claim 4 or 5, characterized in that, The n1+1 to n2 columns of the submatrix B1 are located at a specified position, which is the position between the first set and the second set in the submatrix A1. The row containing element 0 in the first set is the same, the row containing element 0 in the second set is the same, and the row containing element 0 in the first set is different from the row containing element 0 in the second set.

12. The method according to claim 11, characterized in that, The first check column in the second base matrix corresponds to multiple columns in the first base matrix, and the first check column in the first base matrix is ​​one of the multiple columns in the first base matrix.

13. The method according to claim 11, characterized in that, The first check column in the second basis matrix includes at least two columns, each of the at least two columns corresponding to one or more columns in the first basis matrix, the first check column in the second basis matrix corresponding to adjacent columns in the plurality of columns in the first basis matrix, and the plurality of columns in the first basis matrix corresponding to the at least two columns; wherein, the first basis matrix is ​​determined based on the second basis matrix.

14. A communication device, characterized in that, The device includes a processor coupled to a memory for storing programs or instructions that, when executed by the processor, cause the device to perform the method as described in any one of claims 1, 3 to 13.

15. A communication device, characterized in that, The device includes a processor coupled to a memory for storing programs or instructions that, when executed by the processor, cause the device to perform the method as described in any one of claims 2 to 13.

16. A chip, characterized in that, The chip includes: Communication interface; A processor is configured to invoke and execute the instructions via the communication interface, causing a device equipped with the chip system to perform the method as described in any one of claims 1, 3 to 13.

17. A chip, characterized in that, The chip includes: Communication interface; A processor is configured to invoke and execute the instructions via the communication interface, causing a device equipped with the chip system to perform the method as described in any one of claims 2 to 13.

18. A computer program product, characterized in that, It includes computer execution instructions, which, when executed on a computer, cause the computer to perform the method as described in any one of claims 1, 3 to 13, or cause the electronic device to perform the method as described in any one of claims 2 to 13.

19. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer-executable instructions that, when invoked by an electronic device, cause the electronic device to perform the method as described in any one of claims 1, 3 to 13, or cause the electronic device to perform the method as described in any one of claims 2 to 13.

20. A communication system, characterized in that, It includes a communication device for performing the method as described in any one of claims 1, 3 to 13, and a communication device for performing the method as described in any one of claims 2 to 13.

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