Photosensitive pixel circuit, image sensor chip, and electronic device

Abstract

The present application relates to the technical field of electronics, and discloses a photosensitive pixel circuit, an image sensor chip, and an electronic device. The photosensitive pixel circuit provided in the present application comprises: a SPAD pixel array and at least one digital counter located outside the SPAD pixel array; the SPAD pixel array comprises a plurality of SPAD pixel units; and at least two SPAD pixel units among the plurality of SPAD pixel units are connected to the same digital counter among the at least one digital counter, and the at least two SPAD pixel units share the same digital counter, wherein the number of the at least one digital counter is less than the number of the plurality of SPAD pixel units.

Description

Photosensitive pixel circuits, image sensor chips and electronic devices

[0001] Cross-reference to related applications

[0002] This application claims priority to Chinese Patent Application No. 202411196883.8, filed on August 29, 2024, entitled "Photosensitive Pixel Circuit, Image Sensor Chip and Electronic Device", the entire contents of which are incorporated herein by reference. Technical Field

[0003] This application belongs to the field of electronic technology, specifically relating to a photosensitive pixel circuit, an image sensor chip, and an electronic device. Background Technology

[0004] In CMOS image sensors (Complementary Metal-Oxide Semiconductor Image Sensors, CIS), single-photon avalanche transistors (SPADs) can be used as pixel photosensitive devices in image sensors. SPAD pixel units composed of SPADs have ultra-high sensitivity at the single-photon sensing level, and their imaging capabilities are very significant.

[0005] In related technologies, each SPAD pixel unit integrates a digital counter, which counts once after the SPAD receives a photon, giving the SPAD pixel unit ultra-high sensitivity at the single-photon sensing level. However, because each SPAD pixel unit must integrate a corresponding digital counter, the SPAD pixel unit size becomes too large, affecting the effective resolution of the photosensitive pixel circuit in the CIS chip. Summary of the Invention

[0006] This application provides a photosensitive pixel circuit, an image sensor chip, and an electronic device, solving the technical problem in the related art where the excessively large size of SPAD pixels affects the effective resolution of the photosensitive pixel circuit in the CIS chip.

[0007] In a first aspect, embodiments of this application propose a photosensitive pixel circuit, comprising: a SPAD pixel array and at least one digital counter located outside the SPAD pixel array; the SPAD pixel array comprises a plurality of SPAD pixel units; at least two of the plurality of SPAD pixel units are connected to the same digital counter among the at least one digital counter, and the at least two SPAD pixel units share the same digital counter; wherein the number of the at least one digital counter is less than the number of the plurality of SPAD pixel units.

[0008] In a second aspect, embodiments of this application provide an image sensor chip, including: a photosensitive pixel circuit as described in the first aspect.

[0009] Thirdly, embodiments of this application provide an electronic device, including: an image sensor chip as described in the second aspect.

[0010] In this embodiment of the application, the photosensitive pixel circuit includes a SPAD pixel array and at least one digital counter located outside the SPAD pixel array; the SPAD pixel array includes a plurality of SPAD pixel units; at least two of the plurality of SPAD pixel units are connected to the same digital counter among the at least one digital counter, and the at least two SPAD pixel units share the same digital counter; wherein, the number of the at least one digital counter is less than the number of the plurality of SPAD pixel units. Thus, since the digital counter is located outside the SPAD pixel array, which comprises multiple SPAD pixel units, and the digital counter is located outside each SPAD pixel unit, compared to the related technologies that integrate a digital counter inside each SPAD pixel unit, this application significantly reduces the complexity of the circuitry within the SPAD pixel unit and shrinks the size of the SPAD pixel unit. Furthermore, since at least two SPAD pixel units are connected to the same digital counter in at least one digital counter and can share the same digital counter, the number of at least one digital counter is less than the number of multiple SPAD pixel units. Compared to the related technologies where each SPAD pixel unit uses a separate digital counter within the SPAD pixel unit, this application effectively reduces the number of digital counters in the photosensitive pixel circuit. Consequently, more SPAD pixel units can be arranged per unit chip area, improving the effective resolution of the photosensitive pixel circuit. Attached Figure Description

[0011] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which:

[0012] Figure 1 is a schematic diagram of a SPAD pixel unit in the related technology;

[0013] Figure 2 is a schematic diagram of an image sensor chip in the related technology;

[0014] Figure 3 is a schematic diagram of a photosensitive pixel circuit provided in an embodiment of this application;

[0015] Figure 4 is a schematic diagram of another photosensitive pixel circuit provided in an embodiment of this application;

[0016] Figure 5 is a schematic diagram of another photosensitive pixel circuit provided in an embodiment of this application;

[0017] Figure 6 is a schematic diagram of a digital counter in a photosensitive pixel circuit provided in an embodiment of this application;

[0018] Figure 7 is a partial schematic diagram of a photosensitive pixel circuit provided in an embodiment of this application;

[0019] Figure 8 is a partial schematic diagram of another photosensitive pixel circuit provided in an embodiment of this application;

[0020] Figure 9 is a schematic diagram of an image sensor chip provided in an embodiment of this application;

[0021] Figure 10 is a schematic diagram of an electronic device provided in an embodiment of this application.

[0022] Figure Label Explanation: 10-Photosensitive pixel circuit; 20-Image sensor chip; 30-Electronic device; 100-Pixel layer; 200-Logic layer; 300-Connection point; 110-SPAD pixel array; 111-SPAD pixel unit; 120-Digital counter; 130-Clock and control circuit; 1301-Ring counter; 1302-First decoder; 1303-Clock circuit; 1304-Second decoder; 1305-Digital counter control circuit; 1306-Valve switch control circuit; 1307-Third decoder; 140-Signal processing circuit; 150-Port circuit; PMOS-PMOS switching transistor; SPAD-Single-photon avalanche transistor; NOT-Inverter; SEL-Pixel selection switch transistor; SCLK-Clock signal; SSEL-Control... Control signal; SPIX - Pixel output signal; SRST - Counter reset signal; VDD - Power supply voltage signal; VSS - Low level signal; SPAD1 - First SPAD; SPAD2 - Second SPAD; SPADY - Yth SPAD; TX1 - Valve switch transistor; TX2 - Valve switch transistor; TXY - Valve switch transistor; STX1 - Valve switch control signal; STX2 - Valve switch control signal; STXY - Valve switch control signal; DFF1 - First D flip-flop; DFF2 - Second D flip-flop; DFF3 - Third D flip-flop; DFFL - Lth ​​D flip-flop. Detailed Implementation

[0023] The embodiments of this application will now be described in detail. Examples of these embodiments are illustrated in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0024] The terms "first" and "second" in the specification and claims of this application may explicitly or implicitly include one or more of the features. In the description of this application, unless otherwise stated, "multiple" means two or more. Furthermore, "and / or" in the specification and claims indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0025] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "connected" and "linked" should be interpreted broadly. For example, they can refer to a direct connection, an indirect connection through an intermediate medium, or a connection within two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0026] In image sensors, SPAD pixel units possess ultra-high sensitivity at the single-photon sensing level. For example, referring to Figure 1, in related technologies, a SPAD pixel unit may include a SPAD, a PMOS transistor, an inverter (NOT), and a digital counter. The positive terminal of the SPAD is connected to a low-level signal VSS, the negative terminal of the SPAD is connected to the drain of the PMOS transistor and the inverter, the source of the PMOS transistor receives the power supply voltage signal VDD, the gate of the PMOS transistor receives the clock signal SCLK, and the inverter (NOT) is connected to the digital counter. The working principle of the SPAD pixel unit can be as follows: Under the modulation of the clock signal SCLK, a transition in the clock signal SCLK pulls up the negative terminal voltage Vc of the SPAD, called SPAD charging; when the SPAD senses a photon during exposure, it conducts, pulling down the negative terminal voltage Vc, called SPAD quenching; the SPAD continuously cycles between quenching and charging during exposure, causing the waveform of the negative terminal voltage Vc to form an analog pulse signal. This analog pulse signal is rectified by the inverter to form a square wave pulse signal Vp, which is then output to the digital counter. In theory, a digital counter counts once after each photon is received by the SPAD; if N photons arrive at the SPAD, the digital counter counts N times. However, because each SPAD pixel unit in related technologies must integrate a corresponding digital counter to count the photons sensed by the SPAD, the size of the SPAD pixel unit is too large and difficult to shrink. This results in an inability to integrate a large number of SPAD pixels per unit chip area to improve the effective resolution of the photosensitive pixel circuitry in the image sensor chip.

[0027] Based on this, this application provides a photosensitive pixel circuit. The concept of this application is to remove the digital counter from within the SPAD pixel unit, placing the digital counter outside each SPAD pixel unit. Compared to related technologies that integrate a digital counter within each SPAD pixel unit, this application significantly reduces the complexity of the circuitry within the SPAD pixel unit and shrinks the size of the SPAD pixel unit. Furthermore, multiple SPAD pixel units are connected to the same digital counter via the same output wire and can share the same digital counter. This reduces the number of digital counters in the photosensitive pixel circuit to the number of SPAD pixel units in the SPAD pixel array. Compared to related technologies where each SPAD pixel unit uses a separate digital counter within the SPAD pixel unit, this application effectively reduces the number of digital counters in the photosensitive pixel circuit. Consequently, more SPAD pixel units can be arranged per unit chip area, improving the effective resolution of the photosensitive pixel circuit.

[0028] Furthermore, referring to Figure 2, in the related technology, each SPAD pixel unit may include a clock and control circuit, a digital counter, and a readout circuit. When the excitation signal arrives at the clock and control circuit, the clock and control circuit outputs a clock signal SCLK, which controls the quenching and charging of the SPAD device and is counted by the digital counter. The counting result is read by the readout circuit and output as a pixel output signal. Referring to Figure 2, the image sensor chip includes a stacked pixel layer and a logic layer. The image sensor chip may include multiple SPAD pixel units and auxiliary circuits such as signal processing circuits and port circuits. The SPADs in each SPAD pixel unit are placed in the pixel layer to form a SPAD array. The pixel circuits (such as PMOS transistors, digital counters, etc.) in each SPAD pixel unit other than the SPADs are placed in the logic layer to form a pixel circuit array. The pixel circuit array occupies a large area of ​​the logic layer and must correspond one-to-one with the SPAD array in the pixel layer. Therefore, auxiliary circuits such as signal processing circuits and port circuits can only be placed outside the pixel circuit array of the logic layer, resulting in the layout area of ​​the logic layer being larger than that of the pixel layer. Due to the inconsistency in the layout area of ​​the pixel layer and the logic layer, the stacking structure and optical performance of the image sensor chip in the Compact Camera Module (CCM) module are affected.

[0029] Based on this, this application provides a photosensitive pixel circuit that can place a SPAD pixel array composed of multiple SPAD pixel units in the pixel layer, eliminating the need to set up a pixel circuit array in the logic layer that corresponds one-to-one with the SPAD array. The space saved can be used to place a digital counter and auxiliary circuits such as signal processing circuits and port circuits, so as to achieve the same layout area between the logic layer and the pixel layer, thereby improving the optical performance of the image sensor in the CCM module.

[0030] Figure 3 is a schematic diagram of a photosensitive pixel circuit provided in an embodiment of this application.

[0031] As shown in FIG3, the photosensitive pixel circuit 10 provided in this application embodiment may include: a SPAD pixel array 110 and at least one digital counter 120 located outside the SPAD pixel array;

[0032] SPAD pixel array 110 includes a plurality of SPAD pixel units 111; at least two SPAD pixel units 111 are connected to the same digital counter 120 in at least one digital counter, and at least two SPAD pixel units 111 share the same digital counter 120.

[0033] In this case, the number of at least one digital counter 120 is less than the number of multiple SPAD pixel units 111.

[0034] In this embodiment, each SPAD pixel unit 111 in the SPAD pixel array may include a SPAD device and a corresponding pixel circuit, but does not include clock and control circuits or a digital counter. The pixel output signal SPIX output by the SPAD pixel unit is a digital square wave signal, such as a 1-bit binary digital signal.

[0035] In this embodiment, multiple SPAD pixel units 111 share a single output wire that is electrically connected to a digital counter 120. The connection point 300 of the output wire at the chip interlayer region can be achieved using Cu-Cu (copper-copper) bonding or through-silicon via (TSV) technology.

[0036] In this embodiment of the application, compared with the integration of a digital counter in the SPAD pixel unit in the related art, the present application removes the digital counter 120 from the SPAD pixel unit 111, thereby reducing the size of the SPAD pixel unit 111 and significantly reducing the complexity of the pixel circuit in the SPAD pixel unit 111.

[0037] Furthermore, in this embodiment, multiple SPAD pixel units 111 share a single output wire and are electrically connected to a digital counter 120, and share a single digital counter 120. Compared with the related technology in which a digital counter is integrated in each SPAD pixel unit, this effectively reduces the number of digital counters 120. Consequently, more SPAD pixel units can be arranged per unit chip area, improving the effective resolution of the photosensitive pixel circuit.

[0038] The photosensitive pixel circuit provided in this application includes a SPAD pixel array and at least one digital counter located outside the SPAD pixel array; the SPAD pixel array includes a plurality of SPAD pixel units; at least two of the plurality of SPAD pixel units are connected to the same digital counter in the at least one digital counter, and the at least two SPAD pixel units share the same digital counter; wherein the number of the at least one digital counter is less than the number of the plurality of SPAD pixel units. Since the digital counter is located outside the SPAD pixel array, which comprises multiple SPAD pixel units, this application significantly reduces the complexity of the circuitry within each SPAD pixel unit compared to related technologies that integrate a digital counter within each SPAD pixel unit, thus reducing the size of the SPAD pixel unit. Furthermore, because at least two SPAD pixel units are connected to and can share the same digital counter in at least one digital counter, the number of at least one digital counter is less than the number of multiple SPAD pixel units. Compared to related technologies where each SPAD pixel unit uses a separate digital counter within the SPAD pixel unit, this application effectively reduces the number of digital counters in the photosensitive pixel circuit. Consequently, more SPAD pixel units can be arranged per unit chip area, improving the effective resolution of the photosensitive pixel circuit.

[0039] In practical applications, at least two SPAD pixel units from multiple SPAD pixel units are connected to the same digital counter from at least one digital counter, and share the same digital counter. Different connection methods are possible. For example, multiple SPAD pixel units located in the same column may all be connected to and share the same digital counter. Another example is that multiple SPAD pixel units located in the same column may be divided into multiple groups of SPAD pixel units, with each group containing at least two SPAD pixel units. Each group of SPAD pixel units is connected to and shares the same digital counter. Examples are given below.

[0040] In a specific embodiment, taking Figure 3 as an example, the SPAD pixel array 110 may include M*N SPAD pixel units, where M is the number of rows and N is the number of columns, M is a positive integer greater than 1, and N is a positive integer; the number of the at least one digital counter 120 is N;

[0041] In the SPAD pixel array 110, M SPAD pixel units 111 located in the same column are connected to the same digital counter 120 among the N digital counters, and the M SPAD pixel units share the same digital counter 120.

[0042] In this embodiment of the application, the photosensitive pixel circuit 10 may include M rows and N columns of SPAD pixel units and a row and N columns of digital counter 120. The M SPAD pixel units 111 in each column can be connected to a corresponding digital counter 120 through the same output wire and share the same digital counter 120.

[0043] In this way, since the M SPAD pixel units 111 located in the same column share a single output wire and are electrically connected to a digital counter 120, and the M SPAD pixel units 111 share a single digital counter 120, compared with the related technology in which a digital counter is integrated in each SPAD pixel unit, the number of digital counters 120 is reduced by M times. As a result, more SPAD pixel units can be arranged on a unit chip area, improving the effective resolution of the photosensitive pixel circuit.

[0044] Specifically, taking Figure 3 as an example, the M SPAD pixel units 111 located in the i-th column of the SPAD pixel array 110 are connected to the i-th digital counter 120 in the N digital counters, where i is less than or equal to N;

[0045] The i-th digital counter 120 is used to count the photons sensed by the M SPAD pixel units 111 in the i-th column in time segments.

[0046] For example, the first digital counter 120 can be used to count the photons sensed by each of the M SPAD pixel units 111 in the first column. The second digital counter 120 can be used to count the photons sensed by each of the M SPAD pixel units 111 in the second column. And so on, the Nth digital counter 120 can count the photons sensed by each SPAD pixel unit 111 in the Nth column individually.

[0047] In this way, by having M SPAD pixel units 111 share a single digital counter 120, M*N SPAD pixel units 111 can be counted by a row of N digital counters 120, thus achieving the effective operation of M*N SPAD pixel units 111.

[0048] In other embodiments (not shown), at least two SPAD pixel units can be connected to the same digital counter through other connection methods. For example, the SPAD pixel array may include M*N SPAD pixel units, where M is the number of rows and N is the number of columns, M is a positive integer greater than 1, and N is a positive integer; the number of at least one digital counter 120 may be 2*N.

[0049] In the SPAD pixel array 110, the first Q SPAD pixel units 111 in the same column are connected to one of the 2N digital counters 120, and the last MQ SPAD pixel units 111 in the same column are connected to another of the 2N digital counters 120, wherein Q is less than M and Q is greater than or equal to 2.

[0050] In this way, by having Q SPAD pixel units 111 share one digital counter 120, and by having MQ SPAD pixel units 111 share one digital counter 120, M*N SPAD pixel units 111 can be counted by two rows of 2N digital counters 120, thus realizing the effective operation of M*N SPAD pixel units 111.

[0051] It should be noted that, in the embodiments of this application, when at least two SPAD pixel units are connected to the same digital counter, this application does not limit the specific position of the at least two SPAD pixel units in the SPAD pixel array.

[0052] Furthermore, in this embodiment of the application, the type of digital counter can be a single-input digital counter or a multi-input digital counter, and the number of digital counters can be one or more. This embodiment of the application can set the type and number of digital counters according to actual needs.

[0053] For example, in other embodiments (not shown in the figure), the digital counter in the photosensitive pixel circuit can be a multiple-input multiple-output (MIMO) digital counter, and the number of digital counters can be one. For instance, the digital counter can include N input terminals, and can be used to simultaneously count pixel output signals input to the N input terminals. The SPAD pixel array can include M*N SPAD pixel units, where M is the number of rows, N is the number of columns, M is a positive integer greater than 1, and N is a positive integer; wherein, the M SPAD pixel units in the first column are connected to the first input terminal of the digital counter through the same output wire, the M SPAD pixel units in the second column are connected to the second input terminal of the digital counter through the same output wire, and so on, with the M SPAD pixel units in the Nth column connected to the Nth input terminal of the digital counter through the same output wire.

[0054] The digital counter can be used to count the photons sensed by the M SPAD pixel units in the first column, count the photons sensed by the M SPAD pixel units in the second column, and so on, to count the photons sensed by each SPAD pixel unit in the Nth column.

[0055] Furthermore, the digital counter can be used to synchronously count pixel output signals from different input terminals. For example, the digital counter can be used to synchronously count photons sensed by N SPAD pixel units in the first row, synchronously count photons sensed by N SPAD pixel units in the second row, and so on, synchronously counting photons sensed by N SPAD pixel units in the Mth row.

[0056] In this way, by connecting M SPAD pixel units in the same column to the same input terminal of the digital counter through the same output wire, and connecting SPAD pixel units in different columns to different input terminals of the digital counter, M*N SPAD pixel units can share a digital counter with N input terminals for counting, thus realizing the efficient operation of M*N SPAD pixel units.

[0057] In another specific embodiment, the photosensitive pixel circuit can be a multi-layer stacked structure. Referring to FIG3, the photosensitive pixel circuit 10 may include a pixel layer 100 and a logic layer 200 stacked together; the SPAD pixel array 110 may be located in the pixel layer 100.

[0058] For example, referring to FIG4, the SPAD pixel unit 111 in the SPAD pixel array 110 of pixel layer 100 may include: a PMOS switching transistor, a SPAD, an inverter NOT, and a pixel selection switching transistor SEL.

[0059] Alternatively, referring to Figure 5, the SPAD pixel unit 111 in the SPAD pixel array 110 of pixel layer 100 may include: a PMOS switching transistor, Y SPADs, Y valve switching transistors, an inverter NOT, and a pixel selection switching transistor SEL.

[0060] It should be noted that in related technologies, each SPAD pixel unit is generally distributed across the pixel layer and the logic layer. For example, referring to Figure 2, in related technologies, the SPADs in each SPAD pixel unit are placed in the pixel layer to form a SPAD array, while the pixel circuits (such as PMOS transistors, inverters (NOT), digital counters, etc.) in each SPAD pixel unit are placed in the logic layer to form a pixel circuit array. The pixel circuit array occupies a large area of ​​the logic layer and must correspond one-to-one with the SPAD array in the pixel layer.

[0061] Referring to Figure 3, in this embodiment of the application, each SPAD pixel unit in the SPAD pixel array 110 is evenly distributed on the pixel layer 100, eliminating the need to set up a pixel circuit array in the logic layer that corresponds one-to-one with the SPAD array, thus avoiding the SPAD pixel units being scattered in the pixel layer and the logic layer.

[0062] Furthermore, in this embodiment, each SPAD pixel unit does not include a digital counter and clock and control circuit, which greatly simplifies the circuit structure of the SPAD pixel unit and significantly reduces the unit area of ​​the SPAD pixel unit.

[0063] In this way, the SPAD pixel units with simplified circuit structure are concentrated in the pixel layer, avoiding the SPAD pixel units being scattered in the pixel layer and logic layer. This makes the chip area occupied by the SPAD pixel array 110 more concentrated. Furthermore, since the chip area occupied by the SPAD pixel units is greatly reduced, the chip area occupied by the SPAD pixel array 110 is also reduced. More SPAD pixel units can be arranged per unit chip area, improving the effective resolution of the photosensitive pixel circuit.

[0064] Of course, in other embodiments, the clock and control circuit can also be set inside each SPAD pixel unit. The specific layout of the clock and control circuit can be set according to actual needs, and the application does not impose specific restrictions on this.

[0065] In a specific embodiment, taking FIG4 or FIG5 as an example, the photosensitive pixel circuit 10 may further include a clock and control circuit 130, a signal processing circuit 140 and a port circuit 140; at least one digital counter 120, clock and control circuit 130, signal processing circuit 140 and port circuit 150 are located in logic layer 200.

[0066] In this embodiment, the clock and control circuit 130 is connected to the SPAD pixel unit 111 of the pixel layer 100 via wires. Similarly, the connection point 300 of the wires in the chip cross-layer region is made by Cu-Cu bonding or TSV process.

[0067] In this embodiment, the digital counting signal (e.g., multi-bit digital signal) output by the digital counter 120 is scanned or transmitted to the signal processing circuit 140 for subsequent image signal processing and buffering, and finally output through the port circuit 150 and transmitted to the outside of the photosensitive pixel circuit.

[0068] In this embodiment, compared with related technologies, since the pixel circuit array corresponding to the SPAD array is eliminated in the logic layer, the chip area saved in the logic layer can be used to place the digital counter 120 and auxiliary circuits such as clock and control circuit 130, signal processing circuit 140, and port circuit 150. This makes it possible for the pixel layer chip and the logic layer chip to have the same area, effectively improving the stacking design and optical performance of the image sensor chip in the CCM module.

[0069] For example, taking Figure 3 as an example, the photosensitive pixel circuit 10 may include a pixel layer 100 and a logic layer 200. A SPAD pixel array 110 is arranged on the pixel layer 100, and at least one digital counter 120, a clock and control circuit 130, a signal processing circuit 140 and a port circuit 150 are arranged on the logic layer. The area of ​​the pixel layer and the area of ​​the logic layer may be the same.

[0070] Thus, in this embodiment of the application, by eliminating the need to set up a pixel circuit array that corresponds one-to-one with the SPAD array in the logic layer, the chip area saved in the logic layer can be used to place the digital counter 120 and auxiliary circuits such as clock and control circuit 130, signal processing circuit 140, and port circuit 150. This makes the layout area of ​​the pixel layer the same as that of the logic layer, which can avoid the impact on the stacking and optical performance of the photosensitive pixel circuits in the CCM module due to the inconsistent size of the pixel layer and the logic layer.

[0071] In a specific embodiment, in order to achieve single-photon sensing level photosensitive performance of the SPAD pixel unit, taking Figure 4 as an example, the SPAD pixel unit 111 may include: a PMOS switching transistor, a SPAD, an inverter NOT, and a pixel selection switching transistor SEL.

[0072] A PMOS switching transistor has a gate, a source, and a drain. The gate of the PMOS switching transistor is used to receive the clock signal SCLK, the source of the PMOS switching transistor is used to receive the power supply voltage signal VDD, and the drain of the PMOS switching transistor is connected to the inverter NOT.

[0073] The negative terminal of SPAD is connected to the inverter NOT and is located between the drain of the PMOS switching transistor and the inverter NOT; the inverter NOT is connected to the pixel selection switching transistor SEL, and the pixel selection switching transistor SEL is connected to one of the at least one digital counters, digital counter 120.

[0074] The positive terminal of the SPAD can be connected to a low-level signal VSS. Under the modulation of the clock signal SCLK, the clock signal changes, pulling up the negative terminal voltage of the SPAD, which is called SPAD charging; when the SPAD senses photons during exposure, it turns on, pulling down the negative terminal voltage of the SPAD, which is called SPAD quenching.

[0075] In this embodiment, the working principle of the SPAD pixel unit 111 may include: under the modulation of the clock signal SCLK, the SPAD device continuously cycles between quenching and charging under exposure, forming an analog pulse signal; the inverter NOT can be regarded as a 1-bit analog-to-digital converter, converting the analog pulse signal into a digital square wave signal. When the pixel selection switch transistor SEL receives the control signal SSEL (which can be understood as the pixel output selection signal), it transmits the converted digital square wave signal as the pixel output signal SPIX through the output wire to the corresponding digital counter 120, so that the digital counter 120 can perform digital counting processing on the photons sensed by the SPAD device.

[0076] Each time a photon is received by the SPAD, the digital counter counts once. If X photons arrive at the SPAD, the digital counter counts X times.

[0077] The PMOS switching transistor can be equivalent to a variable resistor, which controls the magnitude of the analog pulse signal flowing through the SPAD to prevent the peak value of the analog pulse signal from being too large or too small.

[0078] In this way, the single-photon sensing performance of the SPAD pixel unit is achieved through the SPAD pixel unit 111 and the digital counter outside the SPAD pixel unit 111.

[0079] In another specific embodiment, in order to improve the resolution of the photosensitive pixel circuit and adapt to different lighting scenes, the SPAD pixel unit can use a composite structure. Taking Figure 5 as an example, the SPAD pixel unit 111 includes: Y SPADs, PMOS switching transistors, inverter NOT, Y valve switching transistors and pixel selection switching transistor SEL; Y is a positive integer greater than 1.

[0080] The PMOS switching transistor has a gate, a source, and a drain. The gate of the PMOS switching transistor is used to receive the clock signal SCLK, the source of the PMOS switching transistor is used to receive the power supply voltage signal, and the drain of the PMOS switching transistor is connected to the inverter.

[0081] Y SPADs are connected in parallel, and the negative terminal of the kth SPAD among the Y SPADs is connected to the inverter NOT through the kth valve switching transistor TX, where k is less than or equal to Y;

[0082] The inverter NOT is connected to the pixel selection switch transistor SEL, and the pixel selection switch transistor SEL is connected to one of the at least one digital counters, digital counter 120.

[0083] In this embodiment, the SPAD pixel unit includes Y SPAD devices: SPAD1, SPAD2…SPADY and Y valve switching transistors TX1, TX2…TXY. Each SPAD device is connected to a separate valve switching transistor TX, and each valve switching transistor TX is controlled by an independent valve switching control signal STX. The Y valve switching transistors TX1, TX2…TXY are controlled by a set of valve switching control signals [STX1…STXY]. For example, the first valve switching transistor TX1 is controlled by an independent valve switching control signal STX1, the second valve switching transistor TX2 is controlled by an independent valve switching control signal STX2, and so on, with the Yth valve switching transistor TXY controlled by an independent valve switching control signal STXY. The valve switching control signals STX can be generated by the clock and control circuit 130 and transmitted to each row of SPAD pixel units via parallel wires.

[0084] For example, the negative terminal of the first SPAD device SPAD1 is connected to the inverter NOT through the first valve switching transistor TX1, the negative terminal of the second SPAD device SPAD1 is connected to the inverter NOT through the second valve switching transistor TX2, and so on, the negative terminal of the Yth SPAD device SPADY is connected to the inverter NOT through the Yth valve switching transistor TXY.

[0085] In this embodiment, the analog pulse signals generated by the Y SPAD devices are converged at one point after passing through their respective individual valve switching transistors, and share a PMOS switching transistor, as well as the subsequent inverter NOT and pixel selection switching transistor SEL.

[0086] For different lighting conditions, the number of analog pulse signals generated by one or more SPAD devices will be increased in the time domain. For example, in a dark scene, all Y SPAD devices are enabled to increase the photosensitive area per unit area. After the valve switching transistor corresponding to each SPAD device is turned on, it is connected to the PMOS switching transistor to complete the charging process after quenching. In a bright scene, due to the large number of photons, the valve switching control signal STX can be used to control the operation of one SPAD device, while the valve switching transistors corresponding to the other SPAD devices remain off.

[0087] Thus, in this embodiment of the application, a single SPAD pixel unit includes multiple independent SPAD devices, which can perform SPAD signal output synthesis operation for the required scene, thereby improving the resolution of the photosensitive pixel circuit and adapting to different lighting scenes, thus improving resolution and enhancing scene adaptability.

[0088] In practical applications, the digital counter 120 can adopt a ripple counter architecture. In a specific example, referring to Figure 6, the count value [SL…S2 S1] output by the digital counter 120 is an L-bit binary number; the digital counter 120 may include L series-connected D flip-flops DFF1, DFF2…DFFL;

[0089] Each D flip-flop has a clock input terminal CLK, a data input terminal D, a reset terminal RST, an output terminal Q, and an inverted output terminal Q'. The clock input terminal CLK of the first D flip-flop DFF1 is connected to the SPAD pixel unit 111 and is used to receive the pixel output signal SPIX. The data input terminal D of the first D flip-flop DFF1 is connected to the inverted output terminal Q' of the first D flip-flop DFF1. The reset terminal RST of the first D flip-flop DFF1 is used to receive the counter reset signal SRST. The output terminal Q of the first D flip-flop DFF1 is used to output the first bit S1 of the count value.

[0090] The clock input terminal CLK of the second D flip-flop DFF2 is connected to the inverted output terminal Q' of the first D flip-flop DFF1. The data input terminal D of the second D flip-flop DFF2 is connected to the inverted output terminal Q' of the second D flip-flop DFF2. The reset terminal RST of the second D flip-flop DFF2 is used to receive the counter reset signal SRST. The output terminal Q of the second D flip-flop DFF2 is used to output the second bit S2 of the count value.

[0091] Similarly, the clock input of the m-th D flip-flop is connected to the inverted output of the (m-1)-th D flip-flop, the data input of the m-th D flip-flop is connected to the inverted output of the m-th D flip-flop, the reset terminal of the m-th D flip-flop is used to receive the counter reset signal, and the output terminal of the m-th D flip-flop is used to output the m-th bit of the count value; 2≤m≤L.

[0092] In this embodiment, the pixel output signal SPIX output by the SPAD pixel unit 111 can be input to the clock output CLK of the first D flip-flop DFF1 and drive the entire counter 120 to perform binary counting. The first D flip-flop DFF1 will output the least significant bit, while the Lth D flip-flop DFFL will output the most significant bit. When counting stops, the L-bit digital signal [SL…S2 S1] will be transmitted to the subsequent signal processing circuit 140 for further processing.

[0093] In this way, the digital counter 120 can use the structure of a ripple counter to perform digital counting processing on the pixel output signal SPIX (i.e., 1-bit digital signal) output by the SPAD pixel unit 111 to obtain an L-bit digital signal [SL…S2 S1].

[0094] Of course, in other embodiments, the digital counter 120 may also be constructed using other types of counters, and this application does not impose specific restrictions on this.

[0095] In another specific embodiment, this application may use a clock and control circuit 130 to provide a clock signal SCLK and a control signal SSEL to the SPAD pixel array. Referring again to Figure 4 or Figure 5 as an example, the photosensitive pixel circuit 10 may include: a clock and control circuit 130; the clock and control circuit 130 is connected to the SPAD pixel array 110 and is used to provide the SPAD pixel array 110 with the clock signal SCLK and the control signal SSEL.

[0096] The clock signal SCLK is used to control the PMOS switching transistor in the SPAD pixel unit 111 to turn on; the control signal SSEL is used to control the pixel selection switching transistor SEL in the SPAD pixel unit 111 to turn on.

[0097] For example, in the embodiments of this application, the clock signal SCLK and control signal SSEL generated by the clock and control circuit 130 reach any one or more rows of SPAD pixel units 111 in the pixel layer 100 through wires, and each row of SPAD pixel units 111 in the pixel layer 100 shares one clock signal SCLK and control signal SSEL.

[0098] The clock signal SCLK can be used to charge the SPAD device. Under the modulation of the clock signal SCLK, the SPAD device continuously cycles between quenching and charging under exposure, forming an analog pulse signal.

[0099] In this process, after the inverter converts the analog pulse signal into a digital square wave signal, the control signal SSEL controls the SPAD pixel unit 111 to output the pixel output signal SPIX. When the pixel selection switch transistor SEL receives the control signal SSEL, it transmits the digital square wave signal converted by the inverter as the pixel output signal SPIX to the corresponding digital counter 120 through the output wire.

[0100] Thus, in this embodiment of the application, the clock signal SCLK and the control signal SSEL generated by the clock and control circuit 130 control each row of SPAD pixel units 111 to operate normally.

[0101] In a specific example, since each row of SPAD pixels shares a clock and control signal output from the clock and control circuit, the clock and control circuit can be designed using a row scanner, which is implemented by a decoder to transmit row parallel signals.

[0102] In practical applications, the SPAD pixel array 110 may include M rows of SPAD pixel units 111. To provide control signals to each row of SPAD pixel units 111, taking Figure 7 as an example, the clock and control circuit 130 may include: a ring counter 1301 and a first decoder 1302; the ring counter 1301 is connected to the first decoder 1302; the first decoder 1302 is connected to the M rows of SPAD pixel units 111 through M wires and is used to provide control signals SSEL to the M rows of SPAD pixel units 111.

[0103] The ring counter 1301 is used to control the first decoder 1302 to select at least one row of SPAD pixel units from the M rows of SPAD pixel units and provide the control signal SSEL.

[0104] In this embodiment, for a SPAD pixel array with M rows, the control signal SSEL required for each row of SPAD pixel units is provided by a first decoder 1302 with M row outputs. Specifically, a ring counter 1301 controls the first decoder 1302 to provide the control signal SSEL. The first decoder 1302 outputs the control signal SSEL to the corresponding row conductor to control the output of a row of SPAD pixel units.

[0105] Thus, in this embodiment of the application, a first decoder 1302 with M rows of output provides a control signal SSEL to the M rows of SPAD pixel units, so that each row of SPAD pixels shares one control signal SSEL output by the first decoder 1302.

[0106] In a specific example, in order to provide a clock signal to at least one row of SPAD pixel units 111, taking Figure 7 as an example, the clock and control circuit 130 may also include: a clock circuit 1303 and a second decoder 1304.

[0107] Clock circuit 1303 is connected to second decoder 1304; clock circuit 1303 is used to generate clock signal and output clock signal to second decoder 1304.

[0108] The second decoder is connected to the M rows of SPAD pixel units 111 via M wires and is used to provide the clock signal SCLK to the M rows of SPAD pixel units;

[0109] The ring counter 1301 is connected to the second decoder 1304; the ring counter 1301 is also used to control the second decoder 1304 to select at least one row of SPAD pixel units from the M rows of SPAD pixel units to provide the clock signal SCLK.

[0110] In this embodiment, for a SPAD pixel array with M rows, the clock signal SCLK required for each row of SPAD pixel units can be provided by a second decoder 1304 with M row outputs. The clock signal SCLK is provided by a clock circuit 1303 (e.g., a phase-locked loop) and output to the corresponding row line to a row of SPAD pixel units via the second decoder 1304.

[0111] Simultaneously, the output signal of the ring counter 1301 provides pixel row selection for the second decoder 1304. For example, the second decoder 1304 can be controlled to select one or more rows of SPAD pixel units from M rows to provide the clock signal SCLK.

[0112] Thus, in this embodiment of the application, a second decoder 1304 with M rows of output provides a clock signal SCLK to the M rows of SPAD pixel units, so that each row of SPAD pixels shares one clock signal SCLK output by the second decoder 1304.

[0113] In a specific example, in order to control the digital counter 120 to perform a new round of counting, taking Figure 7 as an example, the clock and control circuit 130 may further include: a digital counter control circuit 1305; the digital counter control circuit 1305 is connected to at least one digital counter 120 and is used to provide a counter reset signal SRST to at least one digital counter 120.

[0114] In practical applications, after one frame of image processing is completed, the digital counter needs to start a new round of counting. If a new round of counting is required, the clock and control circuit 130 needs to output a counter reset signal SRST to clear and reset the digital counter 120. The counting reset of each digital counter 120 in the photosensitive pixel circuit 10 is performed synchronously. The counter reset signal SRST output by the digital counter control circuit 1305 can simultaneously reset all digital counters 120 in the photosensitive pixel circuit.

[0115] In this way, the present application provides a counter reset signal SRST to all digital counters 120 through the digital counter control circuit 1305, thereby controlling the digital counters 120 to perform a new round of counting.

[0116] In practical applications, when the SPAD pixel unit 111 includes Y valve switch transistors, in order to control the Y valve switch transistors, taking Figure 8 as an example, the clock and control circuit 130 may also include: valve switch control circuit 1306 and third decoder 1307.

[0117] The valve switch control circuit 1306 is connected to the third decoder 1307; the valve switch control circuit 1306 is used to generate a valve switch control signal and output the valve switch control signal to the third decoder 1307.

[0118] The third decoder 1307 is connected to the M rows of SPAD pixel units 111 via M wires and is used to provide valve switching control signals to the M rows of SPAD pixel units 111.

[0119] The ring counter 1301 is connected to the third decoder 1307; the ring counter 1301 is also used to control the third decoder 1307 to select at least one row of SPAD pixel units from the M rows of SPAD pixel units to provide valve switching control signals;

[0120] The valve switch control signal is used to control at least one of the Y valve switch transistors to turn on.

[0121] In this embodiment, each row of SPAD pixel units shares a set of valve switch control signals [STX1…STXY] provided by the valve switch control circuit 1306. A separate M-row output third decoder 1307 within the clock and control circuit provides scanning and signal allocation for each row. This separate M-row output third decoder 1307 receives valve switch control signals for SPAD pixel units in different modes from the valve switch control circuit 1306, and the selection of SPAD pixel rows is also provided by a ring counter.

[0122] For example, referring to Figure 5, when the valve switch control signal STX1 in [STX1…STXY] is a high-level signal and the other valve switch control signals STX2…STXY are low-level signals, the first valve switch transistor TX1 is turned on, and the other valve switch transistors TX2…TXY are turned off. The first SPAD device SPAD1 in the SPAD pixel unit 111 works, and the other SPAD devices do not work. This working mode is suitable for bright scenes.

[0123] For example, referring to Figure 5, when all the valve switch control signals in [STX1…STXY] are high-level signals, the control transistors TX1, TX2…TXY of the Y valve switches are all turned on, and the Y SPAD devices SPAD1, SPAD2…SPADY in the SPAD pixel unit 111 are all working, increasing the effective photosensitive area of ​​the SPAD pixel unit 111. This working mode is suitable for dim scenes.

[0124] Thus, in this embodiment of the application, a third decoder 1307 with M rows of output provides a set of valve switch control signals [STX1…STXY] to each row of SPAD pixel units, so that each row of SPAD pixels shares a set of valve switch control signals [STX1…STXY] output by the third decoder 1307.

[0125] In practical applications, taking Figure 3 as an example, the photosensitive pixel circuit 10 may further include a signal processing circuit 140 and a port circuit 140; the signal processing circuit 140 and the port circuit 150 are located in the logic layer 200. The input terminal of the signal processing circuit 140 is connected to at least one digital counter 120, and the output terminal of the signal processing circuit 140 is connected to the port circuit 150.

[0126] The signal processing circuit 140 is used to process the count value output by at least one digital counter 120 to obtain the target image signal;

[0127] Port circuit 150 is used to output the target image signal.

[0128] In this way, the digital counting signals (e.g., multi-bit digital signals) output by the digital counter 120 are all scanned or transmitted to the signal processing circuit 140 for subsequent image signal processing and buffering, and finally transmitted to the outside of the photosensitive pixel circuit through the port circuit 150.

[0129] Based on the same concept as the photosensitive pixel circuit provided in any of the above embodiments, this application also provides an image sensor chip.

[0130] Referring to FIG9, an embodiment of this application provides an image sensor chip 20, which may include the photosensitive pixel circuit 10 provided in any of the above embodiments.

[0131] In the embodiments of this application, the image sensor chip 20 may include the photosensitive pixel circuit 10 provided in any of the above embodiments, and may implement all the functions of the photosensitive pixel circuit 10 provided in any of the above embodiments. To avoid repetition, it will not be described again here.

[0132] Based on the same concept as the image sensor chip provided in any of the above embodiments, this application also provides an electronic device.

[0133] Referring to FIG10, an embodiment of this application provides an electronic device 30, which may include the image sensor chip 20 provided in any of the above embodiments.

[0134] In practical applications, the electronic device 30 may include at least one CCM module, and each CCM module may include an image sensor chip 20. The image sensor communicates bidirectionally with the image signal processor (ISP) module in the application processor (AP) or system on chip (SoC) via a port link. The AP / SoC sends control signals to the image sensor in each CCM module, and after generating an image signal, the image sensor sends it back to the ISP module in the AP / SoC for backend processing.

[0135] In this embodiment, the electronic device 30 may be a device with a camera function. The electronic device may be a terminal or other devices besides a terminal. For example, the electronic device may be a mobile phone, tablet computer, laptop computer, PDA, in-vehicle electronic device, mobile internet device (MID), augmented reality (AR) / virtual reality (VR) device, robot, wearable device, ultra-mobile personal computer (UMPC), netbook, or personal digital assistant (PDA), etc. It may also be a server, network attached storage (NAS), personal computer (PC), etc., and this embodiment does not specifically limit the scope.

[0136] In the embodiments of this application, the electronic device 30 may include the image sensor chip 20 provided in any of the above embodiments, and may implement all the functions of the image sensor chip 20. To avoid repetition, it will not be described again here.

[0137] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0138] Although embodiments of this application have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of this application, the scope of which is defined by the claims and their equivalents.

Claims

1. A photosensitive pixel circuit, wherein, include: A single-photon avalanche transistor SPAD pixel array and at least one digital counter located outside the SPAD pixel array; The SPAD pixel array includes multiple SPAD pixel units; At least two of the plurality of SPAD pixel units are connected to the same digital counter in the at least one digital counter, and the at least two SPAD pixel units share the same digital counter; The number of the at least one digital counter is less than the number of the plurality of SPAD pixel units.

2. The photosensitive pixel circuit according to claim 1, wherein the SPAD pixel array comprises M*N SPAD pixel units, where M is the number of rows and N is the number of columns, M is a positive integer greater than 1, and N is a positive integer; the number of the at least one digital counter is N; in, The M SPAD pixel units located in the same column of the SPAD pixel array are connected to the same digital counter among the N digital counters, and the M SPAD pixel units share the same digital counter.

3. The photosensitive pixel circuit according to claim 2, wherein, The M SPAD pixel units located in the i-th column of the SPAD pixel array are connected to the i-th digital counter in the N digital counters, where i is less than or equal to N; The i-th digital counter is used to count the photons sensed by the M SPAD pixel units in the i-th column in time segments.

4. The photosensitive pixel circuit according to claim 1, wherein, The photosensitive pixel circuit includes a stacked pixel layer and a logic layer, and the SPAD pixel array is located in the pixel layer; The SPAD pixel unit in the SPAD pixel array includes: a P-channel metal-oxide-semiconductor PMOS switching transistor, a SPAD, an inverter, and a pixel selection switching transistor.

5. The photosensitive pixel circuit according to claim 4, wherein, The photosensitive pixel circuit also includes a clock and control circuit, a signal processing circuit, and a port circuit; the at least one digital counter, the clock and control circuit, the signal processing circuit, and the port circuit are located in the logic layer.

6. The photosensitive pixel circuit according to claim 4 or 5, wherein, The area of ​​the pixel layer is the same as the area of ​​the logic layer.

7. The photosensitive pixel circuit according to claim 1, wherein, The SPAD pixel unit includes: a PMOS switching transistor, a SPAD, an inverter, and a pixel selection switching transistor; The PMOS switching transistor has a gate, a source, and a drain. The gate of the PMOS switching transistor is used to receive a clock signal, the source of the PMOS switching transistor is used to receive a power supply voltage signal, and the drain of the PMOS switching transistor is connected to the inverter. The negative terminal of the SPAD is connected to the inverter and is located between the drain of the PMOS switching transistor and the inverter; the inverter is connected to the pixel selection switching transistor, and the pixel selection switching transistor is connected to one of the at least one digital counters.

8. The photosensitive pixel circuit according to claim 1, wherein, The SPAD pixel unit includes: Y SPADs, a PMOS switching transistor, an inverter, Y valve switching transistors, and a pixel selection switching transistor; Y is a positive integer greater than 1. The PMOS switching transistor has a gate, a source, and a drain. The gate of the PMOS switching transistor is used to receive a clock signal, the source of the PMOS switching transistor is used to receive a power supply voltage signal, and the drain of the PMOS switching transistor is connected to the inverter. Y SPADs are connected in parallel, and the negative terminal of the kth SPAD among the Y SPADs is connected to the inverter through the kth valve switching transistor, where k is less than or equal to Y; The inverter is connected to the pixel selection switch transistor, and the pixel selection switch transistor is connected to one of the at least one digital counters.

9. The photosensitive pixel circuit according to claim 1, wherein, The digital counter outputs an L-bit binary number; the digital counter comprises L D flip-flops connected in series. Each of the D flip-flops has a clock input, a data input, a reset, an output, and an inverted output. The clock input of the first D flip-flop is connected to the SPAD pixel unit and is used to receive the pixel output signal. The data input of the first D flip-flop is connected to the inverted output of the first D flip-flop. The reset of the first D flip-flop is used to receive the counter reset signal. The output of the first D flip-flop is used to output the first bit of the count value. The clock input of the m-th D flip-flop is connected to the inverted output of the (m-1)-th D flip-flop, the data input of the m-th D flip-flop is connected to the inverted output of the m-th D flip-flop, the reset terminal of the m-th D flip-flop is used to receive the counter reset signal, and the output terminal of the m-th D flip-flop is used to output the m-th bit of the count value; 2≤m≤L.

10. The photosensitive pixel circuit according to any one of claims 4, 7, and 8, wherein, Also includes: Clock and control circuits; The clock and control circuit is connected to the SPAD pixel array and is used to provide clock signals and control signals to the SPAD pixel array; The clock signal is used to control the PMOS switching transistor in the SPAD pixel unit to turn on; the control signal is used to control the pixel selection switching transistor in the SPAD pixel unit to turn on.

11. The photosensitive pixel circuit according to claim 10, wherein, The SPAD pixel array comprises M rows of SPAD pixel units; The clock and control circuit includes: a ring counter and a first decoder; the ring counter is connected to the first decoder; the first decoder is connected to the M rows of SPAD pixel units through M wires and is used to provide control signals to the M rows of SPAD pixel units; The ring counter is used to control the first decoder to select at least one row of SPAD pixel units from the M rows of SPAD pixel units to provide control signals.

12. The photosensitive pixel circuit according to claim 11, wherein, The clock and control circuit also includes: a clock circuit and a second decoder; The clock circuit is connected to the second decoder; the clock circuit is used to generate a clock signal and output the clock signal to the second decoder. The second decoder is connected to the M rows of SPAD pixel units via M wires and is used to provide clock signals to the M rows of SPAD pixel units; The ring counter is connected to the second decoder; the ring counter is also used to control the second decoder to select at least one row of SPAD pixel units from the M rows of SPAD pixel units to provide a clock signal.

13. The photosensitive pixel circuit according to claim 11, wherein, In the case where the SPAD pixel unit includes Y valve switch transistors, the clock and control circuit further includes: a valve switch control circuit and a third decoder; The valve switch control circuit is connected to the third decoder; the valve switch control circuit is used to generate a valve switch control signal and output the valve switch control signal to the third decoder. The third decoder is connected to the M rows of SPAD pixel units via M wires and is used to provide valve switching control signals to the M rows of SPAD pixel units; The ring counter is connected to the third decoder; the ring counter is also used to control the third decoder to select at least one row of SPAD pixel units from the M rows of SPAD pixel units to provide valve switching control signals; The valve switch control signal is used to control at least one of the Y valve switch transistors to turn on.

14. The photosensitive pixel circuit according to claim 10, wherein, The clock and control circuit further includes a digital counter control circuit; the digital counter control circuit is connected to the at least one digital counter and is used to provide a counter reset signal to the at least one digital counter.

15. The photosensitive pixel circuit according to claim 5, wherein, The input terminal of the signal processing circuit is connected to the at least one digital counter, and the output terminal of the signal processing circuit is connected to the port circuit. The signal processing circuit is used to process the count value output by the at least one digital counter to obtain the target image signal; The port circuit is used to output the target image signal.

16. An image sensor chip, wherein, Includes the photosensitive pixel circuit according to any one of claims 1-15.

17. An electronic device, wherein, Includes the image sensor chip as described in claim 16.

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