Frequency synthesizer

Abstract

A frequency synthesizer is disclosed which comprises a fractional- N synthesizer configured to provide a synthesized frequency signal based on a first reference frequency signal while controlled based on a second or third reference frequency signal, wherein the first reference frequency signal has higher frequency than the second and third reference frequency signals. The frequency synthesizer also comprises a first frequency divider configured to provide a first divided frequency signal based on the synthesized frequency signal while controlled by a first divider ratio, first phase difference circuitry configured to determine a first phase difference between the first divided frequency signal and the third reference frequency signal, wherein the first divider ratio is determined based on the first phase difference, and switching circuitry configured to cause the fractional-N synthesizer to be controlled based on the third reference frequency signal responsive to loss of the second reference frequency signal. Corresponding circuitry arrangement, integrated circuit, and electronic apparatus are also disclosed.

Description

[0001] P110495W001

[0002] 1

[0003] FREQUENCY SYNTHESIZER

[0004] TECHNICAL FIELD

[0005] The present disclosure relates generally to the field of electronic circuitry. More particularly, it relates to circuitry for provision of a synthesized frequency signal.

[0006] BACKGROUND

[0007] A synthesized frequency signal is useful in a wide range of electronic applications. One illustrative example is communication applications in general. In a more particular example, a radio frequency (RF) signal with long term phase accuracy is typically needed for joint coherent transmission (JCT) among two or more access points.

[0008] Synthesizing frequency signals using a relatively high reference clock frequency typically entails advantages such as relatively low phase noise and / or spurious interference. However, it typically entails also some problems. Some examples of such potential problems include: relatively low frequency accuracy when using a reference source implemented using a crystal oscillator (XO), relatively high sensitivity to changes in ambient conditions (e.g., temperature, vibration, shock, etc.) for output signal frequency and / or phase, relatively high power consumption for signal distribution, and relatively high distribution loss in terms of signal purity.

[0009] In an attempt to solve these problems an XO may be placed locally - close to the frequency synthesizer - and a control loop may be formed around the frequency synthesizer to improve the accuracy of frequency and / or phase, wherein the control loop uses a stable, relatively low, frequency signal as reference (a so called "golden" reference, also referred to herein as a primary reference frequency signal). An example of this approach is described in US 10,505,555 B2.

[0010] However, there may be problems with the availability and / or quality of the golden reference. For example, there may be disruptions in the availability and / or deterioration of the quality when the golden reference is obtained from a remote source via wireless (over the air) communication reception (e.g., due to attenuation, interference, noise, etc.). Alternatively or additionally, there may be disruptions in the availability when the golden reference is obtained P110495W001

[0011] 2 from a remote source via wired communication reception, (e.g., due to a relatively low update rate of communication protocols such as Ethernet). Disruptions in availability and / or deterioration of the quality of the golden reference entails poor performance of the control loop, or even open loop operation, which in turn results in deteriorated accuracy of frequency and / or phase for the synthesized frequency signal.

[0012] Therefore, there is a need for alternative - and preferably improved - frequency synthesizer approaches.

[0013] SUMMARY

[0014] It should be emphasized that the term "comprises / comprising" (replaceable by "includes / including") when used in this specification is taken to specify the presence of stated features, integers, steps, or components, but does not preclude the presence or addition of one or more other features, integers, steps, components, or groups thereof. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0015] Generally, when an arrangement is referred to herein, it is to be understood as a physical product; e.g., an electronic apparatus. The physical product may comprise one or more parts, such as controlling circuitry in the form of one or more controllers, one or more processors, or the like.

[0016] It is an object of some embodiments to solve or mitigate, alleviate, or eliminate at least some of the above or other disadvantages.

[0017] A first aspect is a frequency synthesizer comprising a fractional-N synthesizer configured to provide a synthesized frequency signal based on a first reference frequency signal while controlled based on a second or third reference frequency signal, wherein the first reference frequency signal has higher frequency than the second and third reference frequency signals. The frequency synthesizer also comprises a first frequency divider configured to provide a first divided frequency signal based on the synthesized frequency signal while controlled by a first divider ratio, and first phase difference circuitry configured to determine a first phase difference between the first divided frequency signal and the third reference frequency signal, wherein the first divider ratio is determined based on the first phase difference. Furthermore, the P110495W001

[0018] 3 frequency synthesizer comprises switching circuitry configured to cause the fractional-N synthesizer to be controlled based on the third reference frequency signal responsive to loss of the second reference frequency signal.

[0019] In some embodiments, the first frequency divider and the first phase difference circuitry form a first loop for establishing a relation between the third reference frequency signal and the second reference frequency signal.

[0020] In some embodiments, the first phase difference circuitry comprises a first phase detector configured to receive the first divided frequency signal and the third reference frequency signal as inputs, and a first loop filter configured to receive an output of the first phase detector as input and to provide the first phase difference.

[0021] In some embodiments, the switching circuitry is configured to activate averaging over time of the first phase difference responsive to loss of the second reference frequency signal.

[0022] In some embodiments, the switching circuitry comprises a divider multiplexer configured to provide the first divider ratio as the first phase difference or, responsive to loss of the second reference frequency signal, as the first phase difference averaged over time.

[0023] In some embodiments, the switching circuitry comprises a synthesizer multiplexer configured to cause the fractional-N synthesizer to be controlled based on the second reference frequency signal or, responsive to loss of the second reference frequency signal, based the third reference frequency signal.

[0024] In some embodiments, the frequency synthesizer further comprises a second frequency divider configured to provide a second divided frequency signal based on the synthesized frequency signal while controlled by a second divider ratio, and second phase difference circuitry configured to determine a second phase difference between the second divided frequency signal and the second reference frequency signal, wherein the second phase difference is configured for control of the fractional-N synthesizer.

[0025] In some embodiments, the second frequency divider and the second phase difference circuitry form a second loop for locking the fractional-N synthesizer control to the second reference frequency signal. P110495W001

[0026] 4

[0027] In some embodiments, the second phase difference circuitry comprises a second phase detector configured to receive the second divided frequency signal and the second reference frequency signal as inputs, and a second loop filter configured to receive an output of the second phase detector as input and to provide the second phase difference.

[0028] In some embodiments, the synthesizer multiplexer is configured to provide control of the fractional-N synthesizer based on the second phase difference or, responsive to loss of the second reference frequency signal, based on the first phase difference.

[0029] In some embodiments, the switching circuitry is configured to, responsive to loss of the second reference frequency signal, provide control of the fractional-N synthesizer based on the second phase difference averaged over time and compensated based on the first phase difference.

[0030] In some embodiments, the frequency synthesizer further comprises a differentiator configured to determine a trend of the second phase difference, and transition compensation circuitry configured to apply a transition compensation for the fractional-N synthesizer control responsive to loss of the second reference frequency signal, wherein the transition compensation corresponds to the determined trend of the second phase difference.

[0031] In some embodiments, the frequency synthesizer further comprises offset compensation circuitry configured to adjust the first divider ratio based on a frequency offset of the third reference frequency signal.

[0032] In some embodiments, the adjustment of the first divider ratio comprises subtraction - from a value of the first divider ratio - of a weighted version of the value, wherein the weight corresponds to a frequency ratio between the frequency offset and the third reference frequency signal.

[0033] A second aspect is a circuitry arrangement comprising the frequency synthesizer of the first aspect.

[0034] In some embodiments, the circuitry arrangement further comprises a source of the third reference frequency signal.

[0035] In some embodiments, the circuitry arrangement further comprises a detector configured to detect presence of the second reference frequency signal, and to provide an indication of loss P110495W001

[0036] 5 of the second reference frequency signal to the switching circuitry responsive to non-detection of presence.

[0037] In some embodiments, the circuitry arrangement further comprises mapping circuitry configured to determine the frequency offset based on a temperature of the source of the third reference frequency signal.

[0038] In some embodiments, the circuitry arrangement further comprises a temperature sensor configured to measure the temperature of the source of the third reference frequency signal.

[0039] A third aspect is an integrated circuit comprising the frequency synthesizer of the first aspect, and / or the circuitry arrangement of the second aspect.

[0040] A fourth aspect is an electronic apparatus comprising the frequency synthesizer of the first aspect, and / or the circuitry arrangement of the second aspect, and / or the integrated circuit of the third aspect.

[0041] In some embodiments, the electronic apparatus is a radio access node or a wireless communication device.

[0042] A fifth aspect is a frequency synthesizer comprising a fractional-N synthesizer configured to provide a synthesized frequency signal based on a first reference frequency signal while controlled based on a second reference frequency signal, wherein the first reference frequency signal has higher frequency than the second reference frequency signal. The frequency synthesizer also comprises a frequency divider configured to provide a divided frequency signal based on the synthesized frequency signal while controlled by a divider ratio, and phase difference circuitry configured to determine a phase difference between the divided frequency signal and the second reference frequency signal, wherein the phase difference is configured for controlling the fractional-N synthesizer. Furthermore, the frequency synthesizer comprises offset compensation circuitry configured to adjust a nominal value of the divider ratio based on a frequency offset of the second reference frequency signal.

[0043] In some embodiments, the adjustment of the nominal value of the divider ratio comprises subtraction - from the nominal value - of a weighted version of the nominal value, wherein the weight corresponds to a frequency ratio between the frequency offset and the second reference frequency signal. P110495W001

[0044] 6

[0045] In some embodiments, the phase difference circuitry comprises a phase detector configured to receive the divided frequency signal and the second reference frequency signal as inputs, and a loop filter configured to receive an output of the phase detector as input and to provide the phase difference.

[0046] A sixth aspect is a circuitry arrangement comprising the frequency synthesizer of the fifth aspect and a source of the second reference frequency signal.

[0047] In some embodiments, the circuitry arrangement further comprises mapping circuitry configured to determine the frequency offset based on a temperature of the source of the second reference frequency signal.

[0048] In some embodiments, the circuitry arrangement further comprises a temperature sensor configured to measure the temperature of the source of the second reference frequency signal.

[0049] A seventh aspect is an integrated circuit comprising the frequency synthesizer of the fifth aspect, and / or the circuitry arrangement of the sixth aspect.

[0050] An eighth aspect is an electronic apparatus comprising the frequency synthesizer of the fifth aspect, and / or the circuitry arrangement of the sixth aspect, and / or the integrated circuit of the seventh aspect.

[0051] In some embodiments, the electronic apparatus is a radio access node or a wireless communication device.

[0052] In some embodiments, any of the above aspects may additionally have features identical with or corresponding to any of the various features as explained above for any of the other aspects.

[0053] An advantage of some embodiments is that alternative frequency synthesizer approaches are provided.

[0054] Alternatively or additionally, an advantage of some embodiments is that improved frequency synthesizer approaches are provided.

[0055] Yet alternatively or additionally, an advantage of some embodiments is that provision of a synthesized frequency signal using relatively high reference clock frequency is enabled. P110495W001

[0056] 7

[0057] Yet alternatively or additionally, an advantage of some embodiments is that - when a (relatively high reference clock frequency) oscillator close to the frequency synthesizer is used together with a control loop based on a (relatively low frequency) primary reference frequency signal - a backup function is provided for loss of availability and / or quality deterioration of the primary reference frequency signal.

[0058] Yet alternatively or additionally, an advantage of some embodiments is that - when a (relatively high reference clock frequency) oscillator close to the frequency synthesizer is used together with a control loop based on a (relatively low frequency) primary reference frequency signal and a backup function for loss of availability and / or quality deterioration of the golden reference - smooth switching (e.g., in terms of phase) between the primary reference frequency signal and the backup function is enabled.

[0059] Yet alternatively or additionally, an advantage of some embodiments is that provision of a synthesized frequency signal using relatively high reference clock frequency accuracy is enabled.

[0060] Yet alternatively or additionally, an advantage of some embodiments is that provision of a synthesized frequency signal with relatively high phase accuracy is enabled.

[0061] Yet alternatively or additionally, an advantage of some embodiments is that provision of a synthesized frequency signal with relatively low power consumption for signal distribution is enabled.

[0062] Yet alternatively or additionally, an advantage of some embodiments is that provision of a synthesized frequency signal with relatively low distribution loss in terms of signal purity is enabled.

[0063] Yet alternatively or additionally, an advantage of some embodiments is that provision of a synthesized frequency signal with relatively low sensitivity to changes in ambient conditions (e.g., temperature, vibration, shock, etc.) is enabled.

[0064] Yet alternatively or additionally, an advantage of some embodiments is that - when a (relatively high reference clock frequency) oscillator is used together with a control loop based on a (relatively low frequency) reference frequency signal - mitigation is provided for variations in the reference frequency signal due to temperature changes at its source. P110495W001

[0065] 8

[0066] BRIEF DESCRIPTION OF THE DRAWINGS

[0067] Further objects, features and advantages will appear from the following detailed description of embodiments, with reference being made to the accompanying drawings. The drawings are not necessarily to scale, emphasis instead being placed upon illustrating the example embodiments.

[0068] Figure 1 is a schematic block diagram illustrating an example frequency synthesizer according to some embodiments;

[0069] Figure 2 is a schematic block diagram illustrating an example frequency synthesizer with offset compensation according to some embodiments;

[0070] Figure 3 is a schematic block diagram illustrating an example electronic apparatus according to some embodiments;

[0071] Figure 4 is a schematic block diagram illustrating an example frequency synthesizer with first and second control loops according to some embodiments;

[0072] Figure 5 is a schematic block diagram illustrating an example frequency synthesizer with transition compensation between first and second control loops according to some embodiments; and

[0073] Figure 6 is a schematic block diagram illustrating an example frequency synthesizer with offset compensation according to some embodiments.

[0074] DETAILED DESCRIPTION

[0075] As already mentioned above, it should be emphasized that the term "comprises / comprising" (replaceable by "includes / including") when used in this specification is taken to specify the presence of stated features, integers, steps, or components, but does not preclude the presence or addition of one or more other features, integers, steps, components, or groups thereof. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0076] Embodiments of the present disclosure will be described and exemplified more fully hereinafter with reference to the accompanying drawings. The solutions disclosed herein can, however, be P110495W001

[0077] 9 realized in many different forms and should not be construed as being limited to the embodiments set forth herein.

[0078] Some embodiments presented herein aim to provide an alternative (e.g., improved) frequency synthesizer, which is configured to provide a synthesized frequency signal using a relatively high reference clock frequency, while avoiding one or more potential problems associated with such synthesizing. For example, problems with availability and / or quality of a primary reference frequency signal (golden reference) are addressed by some embodiments. Even though such problems are mainly referred to herein as related to availability - and loss - of the primary reference frequency signal, it should be understood that quality deterioration which causes the primary reference frequency signal to be unsuitable for use is intended to be encompassed in the terminology of "loss" of the primary reference frequency signal, and that signal quality is intended to be encompassed in the terminology of "availability" of the primary reference frequency signal. Alternatively or additionally, problems with frequency offset caused by temperature variation are addressed by some embodiments.

[0079] Figure 1 schematically illustrates a frequency synthesizer (FS) 100 according to some embodiments. The FS 100 comprises a signal source 110 (REF 1; e.g., a high frequency crystal oscillator - HF XO) providing a reference frequency signal 111 with relatively high frequency (referred to as a first reference frequency signal). A control loop (referred to as a second control loop, or a second loop) is configured to improve accuracy based on a reference frequency signal 121 with relatively low frequency (LF REF; golden / primary reference, referred to as a second reference frequency signal).

[0080] The signal source 110 may be comprised in the frequency synthesizer 100 (as illustrated in Figure 1). Alternatively, the signal source 110 may be external to the frequency synthesizer 100 and configured to provide the reference frequency signal 111 as an input to the frequency synthesizer 100. When the signal source 110 is external to the frequency synthesizer 100, it may typically (but not necessarily) be located relatively close to the frequency synthesizer 100 (e.g., in a same device as the frequency synthesizer 100). For example, the signal source 110 may be embodied on the same hardware chip as the frequency synthesizer, or in hardware placed adjacently to the frequency synthesizer and / or with relatively short connection circuitry to the frequency synthesizer. P110495W001

[0081] 10

[0082] To address situations when the availability and / or quality of the reference frequency signal 121 is problematic, another reference frequency signal 131 with relatively low frequency (LF REF; referred to as a third reference frequency signal) is available as backup for the accuracy improvement, wherein a relation is established between the backup reference frequency signal 131 and the reference frequency signal 121 when the latter is available. The FS 100 comprises circuitry for switching between the reference frequency signals 121 and 131 in relation to the accuracy improvement control.

[0083] Thus, the first reference frequency signal has higher frequency than the second and third reference frequency signals. Generally, the second and third reference frequency signals may have the same or different frequencies. For example, the third reference frequency signal may be free-running and a relation is established between the third reference frequency signal and the second reference frequency signal (when the latter is available) by a control loop (referred to as a first control loop, or a first loop).

[0084] The relation established between the third reference frequency signal 131 and the second reference frequency signal 121 may be any suitable relation. For example, first control loop may cause the third reference frequency signal 131 to have the same frequency as the second reference frequency signal 121.

[0085] Typically, the second reference frequency signal 121 (golden reference) is provided by a signal source 120 (REF 2) which is remote from the FS 100 (or otherwise unreliable in terms of availability and / or quality). For example, the second reference frequency signal 121 may be obtained from a remote source via wireless communication reception with varying quality of transfer, or via disruptive wired communication reception. The second reference frequency signal 121 may be obtained via reception from a remote source in any suitable way. For example, using a global navigation satellite system (GNSS) signal(s) and / or remotely generated atomic clock signal(s).

[0086] Also typically, the third reference frequency signal 131 (backup reference) is provided by a signal source 130 (REF 3) which is relatively close to the FS 100. For example, a micro electromechanical system (MEMS) resonator may be used to implement the signal source 130. P110495W001

[0087] 11

[0088] The signal source 130 may be implemented on a same integrated circuit as the FS 100, and / or may be comprised in the same electronic apparatus as the FS 100. In some embodiments, the same signal source 130 is used to provide a reference frequency signal (e.g., a third reference frequency signal 131) in parallel to two or more frequency synthesizers (or other circuitry utilizing a reference frequency signal).

[0089] The second and third reference frequency signals 121, 131 are typically more stable (in terms of frequency, which leads to more accurate phase) than the first reference frequency signal 111 (e.g., due to the lower frequency), while the third reference frequency signal 131 may be less stable (in terms of frequency) than the second reference frequency signal 121 (e.g., due to trading off stability against cost). Thus, the second reference frequency signal 121 (golden reference) is typically most stable among the frequency reference signals. The third reference frequency signal 131 (backup reference) may be seen as a (relatively cost-efficient) safe guard in terms of stability to enable the synthesized signal to remain stable as long as possible (in terms of frequency and / or phase).

[0090] The FS 100 comprises a fractional-N synthesizer 112 (FNS; e.g., a high bandwidth fractional-N RF synthesizer) configured to provide a synthesized frequency signal 113 (e.g., a local oscillator - LO - output) based on the first reference frequency signal 111 while being controlled based on the second reference frequency signal 121, or based on the third reference frequency signal 131 when the second reference frequency signal 121 is unavailable or otherwise not useable. The general function of a fractional-N synthesizer is well known and will not be elaborated on further herein.

[0091] The control of the FNS 112 is illustrated in Figure 1 as a controller 114 (CNTR; e.g., controlling circuitry) configured to control the FNS 112 by a control signal 117 based on a received signal 115, wherein the signal 115 is based on the second reference frequency signal 121, or based on the third reference frequency signal 131 when the second reference frequency signal 121 is unavailable or otherwise not useable. For example, the signal 115 may be a representation of a phase difference between the second or third (as applicable) reference frequency signal 121, 131 and a frequency divided version of the synthesized frequency signal 113.

[0092] In some embodiments, the controller 114 acquires a frequency control word (FCW; not shown) and outputs an adjusted version FCW' as the control signal 117, wherein the adjustment is based P110495W001

[0093] 12 on the signal 115. For example, the signal 115 may be a digital representation of the phase difference between the second or third (as applicable) reference frequency signal 121, 131 and the frequency divided version of the synthesized frequency signal 113, and the adjustment may comprise adding the signal 115 to FCW to provide FCW'.

[0094] To improve accuracy of the synthesized frequency signal 113 based on the reference frequency signal 121 (when it is available), a control loop (the second loop) of the FS 100 may comprise a frequency divider 122 (FD 2; referred to as a second frequency divider) and phase difference circuitry 124 (PDC 2; referred to as second phase difference circuitry) configured to provide the signal 115 for control of the FNS 112. Thus, the second frequency divider 122 and the second phase difference circuitry 124 form a second loop for locking the fractional-N synthesizer control to the second reference frequency signal 121.

[0095] The second frequency divider 122 may be configured to provide a divided frequency signal 123 (referred to as a second divided frequency signal) based on the synthesized frequency signal 113 while controlled by a divider ratio (now shown; referred to as a second divider ratio). The general function of a frequency divider is well known and will not be elaborated on further herein. The second divider ratio may, for example, comprise a nominal value Nnom2representing a ratio between a desired frequency of the synthesized frequency signal 113 and the frequency of the second reference frequency signal 121; e.g., where f11, f113, f121represent the frequencies of 111, 113, 121 respectively.

[0096] The second phase difference circuitry 124 may be configured to determine a phase difference 125 (referred to as a second phase difference) between the second divided frequency signal 123 and the second reference frequency signal 121. The second phase difference 125 is configured for control of the fractional-N synthesizer 112. For example, the second phase difference 125 may be provided as the signal 115 for control of the FNS 112 when the reference frequency signal 121 is available.

[0097] For example, the second phase difference circuitry 124 may comprise a phase detector (RD; e.g., a digital phase detector) configured to receive the second divided frequency signal 123 and the second reference frequency signal 121 as inputs (and output a momentary phase difference), and a loop filter (LF; e.g., a digital loop filter) configured to receive an output of the phase detector as input and to provide the second phase difference 125 as output. The general P110495W001

[0098] 13 function of phase difference circuitry (e.g., comprising a phase detector and a loop filter) is well known and will not be elaborated on further herein.

[0099] When the second reference frequency signal 121 is unavailable, the third reference frequency signal 131 is used to improve accuracy of the synthesized frequency signal. To this end, a control loop (the first loop) of the FS 100 may comprise another frequency divider 132 (FD 1; referred to as a first frequency divider) and another phase difference circuitry 134 (PDC 1; referred to as first phase difference circuitry) configured to provide the signal 115 for control of the FNS 112. Thus, the first frequency divider 132 and the first phase difference circuitry 134 form a first loop for locking the fractional-N synthesizer control to the third reference frequency signal 131 when the second reference frequency signal 121 is unavailable.

[0100] The first frequency divider 132 may be configured to provide a divided frequency signal 133 (referred to as a first divided frequency signal) based on the synthesized frequency signal 113 while controlled by a divider ratio 137, 137' (referred to as a first divider ratio). The first divider ratio may, for example, comprise a value Nstbrepresenting a ratio between and a desired frequency of the synthesized frequency signal 113 and the frequency of the third reference frequency signal 131; e.g., Nstb= represent the frequencies of 111, 113, 131 respectively.

[0101] The first phase difference circuitry 134 may be configured to determine a phase difference 135 (referred to as a first phase difference) between the first divided frequency signal 133 and the third reference frequency signal 131. The first phase difference 135 is configured for control of the fractional-N synthesizer 112. For example, a combination of the first phase difference 135 and the second phase difference 125 may be provided as the signal 115 for control of the FNS 112 when the reference frequency signal 121 is unavailable.

[0102] For example, the first phase difference circuitry 134 may comprise a phase detector (RD; e.g., a digital phase detector) configured to receive the first divided frequency signal 133 and the third reference frequency signal 131 as inputs (and output a momentary phase difference), and a loop filter (LF; e.g., a digital loop filter) configured to receive an output of the phase detector as input and to provide the first phase difference 135 as output. P110495W001

[0103] 14

[0104] The first loop of the FS 100 is also configured to align FNS control based on the third reference frequency signal 131 to the FNS control based on the second reference frequency signal 121 when the second reference frequency signal 121 is available. To this end, the first divider ratio 137, 137' may be determined based on the first phase difference 135. For example, the first phase difference 135 may be provided as the first divider ratio 137, 137' for controlling the first frequency divider 132. Thus, the first frequency divider 132 and the first phase difference circuitry 134 form a first loop for establishing a relation between the third reference frequency signal 131 and the second reference frequency signal 121 when the second reference frequency signal 121 is available (by phase locking the first frequency divider 132).

[0105] When the second reference frequency signal 121 is unavailable, the third reference frequency signal 131 is used to improve accuracy of the synthesized frequency signal. To this end, the FS 100 comprises switching circuitry 150a, 150b (SW) configured to cause the fractional-N synthesizer 112 to be controlled based on the third reference frequency signal 131 responsive to loss of the second reference frequency signal 121.

[0106] The switching circuitry 150b may comprise a synthesizer multiplexer 156 (MUX) configured to cause the fractional-N synthesizer 112 to be controlled based on the second reference frequency signal 121 or, responsive to loss of the second reference frequency signal 121, based the third reference frequency signal 131. For example, the output of the synthesizer multiplexer 156 may be provided as the signal 115 for control of the FNS 112.

[0107] In some embodiments, the input of the synthesizer multiplexer 156 which is selected when the second reference frequency signal 121 is available receives the second phase difference 125, and the input of the synthesizer multiplexer 156 which is selected when the second reference frequency signal 121 is unavailable receives a combination of the first phase difference 135 and the second phase difference 125.

[0108] The switching circuitry 150a, 150b may be configured to - responsive to loss of the second reference frequency signal 121 - activate averaging (AVG) 152 over time of the first phase difference 135 and / or averaging (AVG) 158 overtime of the second phase difference 125. Either or both of 125 and 135 may typically comprise some noise, and the accuracy may be improved by averaging. It should be noted, however, that a solution without averaging may be equally applicable. In the latter case, the current value may be adjusted for any noise. P110495W001

[0109] 15

[0110] The combination of the first phase difference 135 and the second phase difference 125 may, for example, correspond to the second phase difference 125 averaged 158 over time and compensated 159a, 159b based on the first phase difference 135. The compensation based on the first phase difference 135 may, for example, correspond to addition of a difference between the first phase difference 135 and the first phase difference 135 averaged 152 over time.

[0111] When the second reference frequency signal 121 is lost, a switch (or handover) to the third reference frequency signal 131 should typically be implemented in a smooth manner using the state at the time the second reference frequency signal 121 is lost as a starting point. Such smooth switching (handover) may be achieved by starting off from the second phase difference 125 as averaged 158 (where the result of the compensation 159b should be close to zero at the starting point since it represents the present value of second phase difference 125 minus the average value from 158) and then letting changes from the starting point value for the third phase difference 135 be transferred through the compensation 159a and operate in a closed loop fashion. In addition to enabling selective control of the fractional-N synthesizer 112, the switching circuitry 150a may comprise a divider multiplexer (MUX) 154 configured to provide the first phase difference 135 as the first divider ratio 137, 137' when the second reference frequency signal 121 is available, and to provide the first phase difference 135 averaged 152 over time responsive to loss of the second reference frequency signal 121.

[0112] Typically, the switching circuitry is also configured to perform operations in reverse responsive to the second reference frequency signal 121 becoming available again.

[0113] More generally, the switching circuitry 150a, 150b may be configured to perform any suitable functions that provide selective control of the fractional-N synthesizer 112 based on the second and / or third reference frequency signals 121, 131 and depending on the availability of the second reference frequency signal 121. Alternatively or additionally, the switching circuitry 150 may be configured to perform any suitable functions that provide selective control of the first divider ratio 137, 137' based on the first phase difference 135 and depending on the availability of the second reference frequency signal 121.

[0114] In some embodiments, the switching may be suitably scheduled. For example, scheduled switching may be beneficial for time division duplex (TDD) communication where the second reference frequency signal 121 is obtained through the receiver and simply is not available P110495W001

[0115] 16 during transmission. Alternatively or additionally, scheduled switching may be beneficial for saving power if reception of the second reference frequency signal 121 is power consuming.

[0116] In association with the switching, it may be beneficial to apply suitable compensation for any difference between the second and third reference frequency signals 121, 131. For example, a suitable ramp (or other suitable transfer function) may be applied to avoid phase discontinuities. For example, the compensation for difference(s) between the second and third reference frequency signals 121, 131 may aim to capture a current frequency drift (of REF 1) and continue to apply a modified control 115 at the same rate (i.e., matching the current frequency drift) from the starting point at handover.

[0117] For example, difference compensation may be implemented in the FS 100 by a differentiator 160 (DIFF) configured to determine a trend of the second phase difference 125 (e.g., due to frequency drift), and transition compensation circuitry 162 (TC) configured to apply a corresponding transition compensation (e.g., a ramp based on the trend) in association with switching (typically during a time window directly following the switch).

[0118] The difference compensation circuitry (e.g., 160, 162) may be seen as comprised in the switching circuitry, or as external to the switching circuitry.

[0119] Similar considerations may be applied for switching responsive to the second reference frequency signal 121 becoming available again.

[0120] The difference compensation may, for example, be applied by adjustment of the difference between the first phase difference 135 and the first phase difference 135 averaged 152 over time.

[0121] In some embodiments, the FS 100 is comprised in a circuitry arrangement, which may (or may not) also comprise the source 130 of the third reference frequency signal 131.

[0122] In any case, the circuitry arrangement may further comprise a detector 128 (DET) configured to detect presence (and / or absence) of the second reference frequency signal 121. The detector 128 is also configured to provide an indication 129 of loss of the second reference frequency signal 121 to the switching circuitry 150a, 150b (and to the difference compensation circuitry) responsive to non-detection of presence. P110495W001

[0123] 17

[0124] Generally, the indication 129 of loss of the second reference frequency signal 121 may be implemented in any suitable way. For example, it may comprise a first signal value while the second reference frequency signal 121 is available and a second signal value while the second reference frequency signal 121 is unavailable, a signal value while the second reference frequency signal 121 is available and no signal value while the second reference frequency signal 121 is unavailable, no signal value while the second reference frequency signal 121 is available and a signal value while the second reference frequency signal 121 is unavailable, a first signal pulse when the second reference frequency signal 121 becomes available and a second signal pulse when the second reference frequency signal 121 becomes unavailable, etc.

[0125] In some embodiments, the detector 128 is comprised in the FS 100.

[0126] In some implementations, the third reference frequency signal 131 is varying depending on a temperature of the signal source 130, thereby introducing a potential frequency offset in the first loop when it is not at nominal temperature. To this end, the FS 100 may comprise offset compensation circuitry 170 (OC) configured to adjust 172 (ADJ) the first divider ratio 137, 137' based on a frequency offset 171 of the third reference frequency signal 131. For example, the adjustment 172 may comprise subtracting a compensation value 136 from the first divider ratio 137 to provide an adjusted first divider ratio 137', wherein the compensation value 136 is based on the frequency offset 171. For example, the compensation value 136 may be a weighted version of the first divider ratio 137 before adjustment. The weight may, for example, correspond to a frequency ratio between the frequency offset 171 and the third reference frequency signal 131.

[0127] The frequency offset 171 may be obtained in any suitable way. For example, the FS 100 (or a circuitry arrangement comprising the FS 100) may comprise mapping circuitry 174 (MAP; e.g., based on a look-up table) configured to determine the frequency offset 171 based on a temperature of the signal source 130. The temperature of the signal source 130 may be obtained by a temperature sensor 176 (TEMP) configured to measure the temperature of the signal source 130. For example, the mapping from sensed temperature to frequency offset may be based on measurements, simulations, or otherwise known characteristics of the signal source 130. P110495W001

[0128] 18

[0129] Figure 2 schematically illustrates a frequency synthesizer (FS) 200 with offset compensation according to some embodiments. The FS 200 comprises a signal source 210 (REF 1; e.g., a high frequency crystal oscillator - HF XO) providing a reference frequency signal 211 with relatively high frequency (referred to as a first reference frequency signal). A control loop is configured to improve accuracy based on a reference frequency signal 231 with relatively low frequency (LF REF; referred to as a second reference frequency signal). Thus, the first reference frequency signal has higher frequency than the second reference frequency signal.

[0130] The second reference frequency signal 231 may be provided by a signal source 230 (REF 2) which is comprised in, or relatively close to, the FS 200 (e.g., comprised in the same circuitry arrangement as the FS 200). For example, the signal source 230 may be implemented on a same integrated circuit as the FS 200, and / or may be comprised in the same electronic apparatus as the FS 200.

[0131] The second reference frequency signal 231 is typically more stable than the first reference frequency signal 211 (e.g., due to the lower frequency).

[0132] The FS 200 comprises a fractional-N synthesizer (FNS) 212 configured to provide a synthesized frequency signal 213 (e.g., a local oscillator- LO - output) based on the first reference frequency signal 211 while being controlled based on the second reference frequency signal 231. The general function of a fractional-N synthesizer is well known and will not be elaborated on further herein.

[0133] The control of the FNS 212 is illustrated in Figure 2 as a controller 214 (CNTR; e.g., controlling circuitry) configured to control the FNS 212 by a control signal 217 based on a received signal 215, wherein the signal 215 is based on the second reference frequency signal 231. For example, the signal 215 may be a representation of a phase difference between the second reference frequency signal 231 and a frequency divided version of the synthesized frequency signal 213.

[0134] In some embodiments, the controller 214 acquires a frequency control word (FCW; not shown) and outputs an adjusted version FCW' as the control signal 217, wherein the adjustment is based on the signal 215. For example, the signal 215 may be a digital representation of the phase difference between the second reference frequency signal 231 and the frequency divided P110495W001

[0135] 19 version of the synthesized frequency signal 213, and the adjustment may comprise adding the signal 215 to FCW to provide FCW'.

[0136] To improve accuracy of the synthesized frequency signal 213 based on the reference frequency signal 231, a control loop of the FS 200 may comprise a frequency divider 232 (FD) and phase difference circuitry 234 (PDC) configured to provide the signal 215 for control of the FNS 212. Thus, the frequency divider 232 and the phase difference circuitry 234 form a loop for locking the fractional-N synthesizer control to the second reference frequency signal 231.

[0137] The frequency divider 232 may be configured to provide a divided frequency signal 233 based on the synthesized frequency signal 213 while controlled by a divider ratio 237, 237'. The general function of a frequency divider is well known and will not be elaborated on further herein. The divider ratio 237, 237' may, for example, be based on a nominal value Nnomand may represent a ratio between a desired frequency of the synthesized frequency signal 213 and the frequency of the second reference frequency signal 231 with offset compensation as described in the following; e.g., Nstb= , / 231 represent the frequencies of 211, 213, 231 respectively, and focrepresents the offset compensation.

[0138] The phase difference circuitry 234 may be configured to determine a phase difference 235 between the divided frequency signal 233 and the second reference frequency signal 231. The phase difference 235 is configured for control of the fractional-N synthesizer 212. For example, the phase difference 235 may be provided as the signal 215 for control of the FNS 212.

[0139] For example, the phase difference circuitry 234 may comprise a phase detector (RD; e.g., a digital phase detector) configured to receive the divided frequency signal 233 and the second reference frequency signal 231 as inputs (and output a momentary phase difference), and a loop filter (LF; e.g., a digital loop filter) configured to receive an output of the phase detector as input and to provide the phase difference 235 as output. The general function of phase difference circuitry (e.g., comprising a phase detector and a loop filter) is well known and will not be elaborated on further herein.

[0140] To address situations when the second reference frequency signal 231 is varying depending on a temperature of the signal source 230, thereby introducing a potential frequency offset in the control loop when it is not at nominal temperature, the FS 200 comprises offset compensation P110495W001

[0141] 20 circuitry 270 (OC) configured to adjust 272 (ADJ) the divider ratio 237, 237' based on a frequency offset 271 of the second reference frequency signal 231. For example, the adjustment 272 may comprise subtracting a compensation value Ncorr236 from a nominal value Nnom237 of the divider ratio to provide an adjusted divider ratio Nstb237', wherein the compensation value 236 is based on the frequency offset 271. For example, the compensation value 236 may be a weighted version of the nominal value of the divider ratio 237. The weight may, for example, correspond to a frequency ratio between the frequency offset 271 and the second reference frequency signal 231.

[0142] In some embodiments the adjustment 272 approximates (linearizes) Ntb= ^211 FCWby using thereby avoiding to perform a division for every update of the offset (i.e., every update of the sensed temperature), since the division operations can be realized by one-time calculations. Alternatively, a mapping function foc-> Nstbmay be provided (e.g., in the form of a look-up table) to implement Nstb= ^211 FCW. f231 +f0C

[0143] The frequency offset 271 may be obtained in any suitable way. For example, the FS 200 (or a circuitry arrangement comprising the FS 200) may comprise mapping circuitry 274 (MAP; e.g., based on a look-up table) configured to determine the frequency offset 271 based on a temperature of the signal source 230. The temperature of the signal source 230 may be obtained by a temperature sensor 276 (TEMP) configured to measure the temperature of the signal source 230. P110495W001

[0144] 21

[0145] Figure 3 schematically illustrates an example electronic apparatus (APP) 330 according to some embodiments. The electronic apparatus 330 comprises a frequency synthesizer (FS) 300 as described and exemplified herein (compare with 100 of Figure 1 and 200 of Figure 2).

[0146] For example, the electronic apparatus 330 may be a communication apparatus (e.g., a radio access node, a wireless communication device, a signal receiver, a signal transmitter, a signal transceiver, etc.). More generally, the electronic apparatus 330 may be any electronic device where a synthesized frequency signal is beneficial.

[0147] Examples of a wireless communication device include a mobile telephone for wireless (e.g., cellular) communication, a user equipment (UE) according to the Third Generation Partnership Program (3GPP) standard, and a station (STA) according to the IEEE 802.11 standard. Examples of a radio access node include a base station for wireless (e.g., cellular) communication, a NodeB (or correspondingly) according to the Third Generation Partnership Program (3GPP) standard, and an access point (AP) according to the IEEE 802.11 standard. Particularly, an example of a radio access node is a radio unit (RU) for distributed multiple-input multiple-output (MIMO) communication.

[0148] In some embodiments, the frequency synthesizer 300 is comprised in a circuitry arrangement (ARR) 310, which is in turn comprised in the electronic apparatus 330. For example, the circuitry arrangement 310 may comprise - in addition to the frequency synthesizer 300 - one or more of: a detector configured to detect presence of a reference frequency signal (compare with 128 of Figure 1), a source of a reference frequency signal (compare with 130 of Figure 1 and 230 of Figure 2), a temperature sensor (176) configured to measure the temperature of the source (compare with 176 of Figure 1 and 276 of Figure 2), and mapping circuitry configured to determine a frequency offset based on the temperature of the source (compare with 174 of Figure 1 and 274 of Figure 2).

[0149] In some embodiments, the frequency synthesizer 300 and / or the circuitry arrangement 310 is / are implemented on an integrated circuit (IC) 320, which is comprised in the electronic apparatus 330. P110495W001

[0150] 22

[0151] Figure 4 schematically illustrates a frequency synthesizer (FS) 400 with first and second control loops according to some embodiments. The FS 400 may be seen as an example of the FS 100 of Figure 1.

[0152] The FS 400 comprises a signal source 410 (REF 1; compare with 110 of Figure 1) providing a first reference frequency signal 411 with relatively high frequency (compare with 111 of Figure 1). A second control loop is configured to improve accuracy based on a second reference frequency signal 421 with relatively low frequency (compare with 121 of Figure 1).

[0153] To address situations when the availability and / or quality of the second reference frequency signal 421 is problematic, a third reference frequency signal 431 with relatively low frequency (compare with 131 of Figure 1) is available as backup for the accuracy improvement, wherein a relation is established between the third reference frequency signal 431 and the second reference frequency signal 421 when the latter is available. The FS 400 comprises circuitry for switching between the reference frequency signals 421 and 431 in relation to the accuracy improvement control.

[0154] Thus, the first reference frequency signal has higher frequency than the second and third reference frequency signals. Generally, the second and third reference frequency signals may have the same or different frequencies. For example, the third reference frequency signal may be free-running and a relation may be established between the third reference frequency signal and the second reference frequency signal (when the latter is available) by a control loop (referred to as a first control loop, or a first loop).

[0155] Typically, the second reference frequency signal 421 is provided by a signal source 420 (REF 2; compare with 120 of Figure 1) which is remote from the FS 400 (or otherwise unreliable in terms of availability and / or quality). For example, the second reference frequency signal 421 may be obtained from a remote source via wireless communication reception with varying quality of transfer, or via disruptive wired communication reception.

[0156] Also typically, the third reference frequency signal 431 is provided by a signal source 430 (REF 3; compare with 130 of Figure 1) which is relatively close to the FS 400. For example, the signal source 430 may be implemented on a same integrated circuit as the FS 400, and / or may be comprised in the same electronic apparatus as the FS 400. P110495W001

[0157] 23

[0158] The second and third reference frequency signals 421, 431 are typically more stable than the first reference frequency signal 411, while the third reference frequency signal 431 may be less stable than the second reference frequency signal 421.

[0159] The FS 400 comprises a fractional-N synthesizer 412 (FNS; compare with 112 of Figure 1) configured to provide a synthesized frequency signal 413 (compare with 113 of Figure 1) based on the first reference frequency signal 411 while being controlled based on the second reference frequency signal 421, or based on the third reference frequency signal 431 when the second reference frequency signal 421 is unavailable or otherwise not useable.

[0160] The control of the FNS 412 is illustrated in Figure 4 as an adder 414 configured to control the FNS 412 by a control signal 417 based on a received signal 415, wherein the signal 415 is based on the second reference frequency signal 421, or based on the third reference frequency signal 431 when the second reference frequency signal 421 is unavailable or otherwise not useable. The signal 415 is a representation of a phase difference 235 between the second or third (as applicable) reference frequency signal 421, 431 and a frequency divided version of the synthesized frequency signal 413.

[0161] In some embodiments, the adder 414 acquires a frequency control word (FCW) 416 and outputs an adjusted version FCW' as the control signal 417, wherein the adjustment comprises adding the signal 415 to the FCW 416, wherein the signal 415 is a digital representation of the phase difference between the second or third (as applicable) reference frequency signal 421, 431 and the frequency divided version of the synthesized frequency signal 413.

[0162] To improve accuracy of the synthesized frequency signal 413 based on the reference frequency signal 421 (when it is available), a control loop of the FS 400 comprises a second frequency divider422 (FD 2; compare with 122 of Figure 1) and second phase difference circuitry 424 (PDC 2; compare with 124 of Figure 1) configured to provide the signal 415 for control of the FNS 412. Thus, the second frequency divider 422 and the second phase difference circuitry 424 form a second loop for locking the fractional-N synthesizer control to the second reference frequency signal 421.

[0163] The second frequency divider 422 is configured to provide a second divided frequency signal 423 (compare with 123 of Figure 1) based on the synthesized frequency signal 413 while P110495W001

[0164] 24 controlled by a second divider ratio (now shown). The second divider ratio may, for example, comprise a nominal value Nnom 2representing a ratio between a desired frequency of the synthesized frequency signal 413 and the frequency of the second reference frequency signal 421.

[0165] The second phase difference circuitry 424 is configured to determine a second phase difference 425 (compare with 125 of Figure 1) between the second divided frequency signal 423 and the second reference frequency signal 421. The second phase difference 425 is configured for control of the fractional-N synthesizer 412. To this end, the second phase difference 425 is provided as the signal 415 for control of the FNS 412 when the reference frequency signal 421 is available.

[0166] The second phase difference circuitry 424 comprises a phase detector (RD; e.g., a digital phase detector) configured to receive the second divided frequency signal 423 and the second reference frequency signal 421 as inputs (and output a momentary phase difference), and a loop filter (LF; e.g., a digital loop filter) configured to receive an output of the phase detector as input and to provide the second phase difference 425 as output.

[0167] When the second reference frequency signal 421 is unavailable, the third reference frequency signal 431 is used to improve accuracy of the synthesized frequency signal. To this end, a first control loop of the FS 400 comprises a first frequency divider 432 (FD 1; compare with 132 of Figure 1) and a first phase difference circuitry 434 (PDC 1; compare with 134 of Figure 1) configured to provide the signal 415 for control of the FNS 412. Thus, the first frequency divider 432 and the first phase difference circuitry 434 form a first loop for locking the fractional-N synthesizer control to the third reference frequency signal 431.

[0168] The first frequency divider 432 is configured to provide a first divided frequency signal 433 (compare with 133 of Figure 1) based on the synthesized frequency signal 413 while controlled by a first divider ratio 437. The first divider ratio may, for example, comprise a value Nstbrepresenting a ratio between a desired frequency of the synthesized frequency signal 413 and the frequency of the third reference frequency signal 431.

[0169] The first phase difference circuitry 434 is configured to determine a first phase difference 435 (compare with 135 of Figure 1) between the first divided frequency signal 433 and the third P110495W001

[0170] 25 reference frequency signal 431. The first phase difference 435 is configured for control of the fractional-N synthesizer 412. To this end, a combination of the first phase difference 435 and the second phase difference 425 is provided as the signal 415 for control of the FNS 412 when the reference frequency signal 421 is unavailable.

[0171] The first phase difference circuitry 434 comprises a phase detector (RD; e.g., a digital phase detector) configured to receive the first divided frequency signal 433 and the third reference frequency signal 431 as inputs (and output a momentary phase difference), and a loop filter (LF; e.g., a digital loop filter) configured to receive an output of the phase detector as input and to provide the first phase difference 435 as output.

[0172] The first loop of the FS 400 is also configured to align FNS control based on the third reference frequency signal 431 to the FNS control based on the second reference frequency signal 421 when the second reference frequency signal 421 is available. To this end, the first divider ratio 437 is determined based on the first phase difference 435 such that the first phase difference 435 is provided as the first divider ratio 437 for controlling the first frequency divider 432. Thus, the first frequency divider 432 and the first phase difference circuitry 434 form a first loop for establishing a relation between the third reference frequency signal 431 and the second reference frequency signal 421.

[0173] When the second reference frequency signal 421 is unavailable, the third reference frequency signal 431 is used to improve accuracy of the synthesized frequency signal. To this end, the FS 400 comprises switching circuitry 450a, 450b (SW; compare with 150a, 150b of Figure 1) configured to cause the fractional-N synthesizer 412 to be controlled based on the third reference frequency signal 431 responsive to loss of the second reference frequency signal 421.

[0174] The switching circuitry 450b comprises a synthesizer multiplexer 456 (MUX; compare with 156 of Figure 1) configured to cause the fractional-N synthesizer 412 to be controlled based on the second reference frequency signal 421 or, responsive to loss of the second reference frequency signal 421, based the third reference frequency signal 431. The output of the synthesizer multiplexer 456 is provided as the signal 415 for control of the FNS 412.

[0175] The input of the synthesizer multiplexer 456 which is selected when the second reference frequency signal 421 is available receives the second phase difference 425, and the input of the P110495W001

[0176] 26 synthesizer multiplexer 456 which is selected when the second reference frequency signal 421 is unavailable receives a combination of the first phase difference 435 and the second phase difference 425.

[0177] The switching circuitry 450a, 450b is configured to - responsive to loss of the second reference frequency signal 421 - activate averaging (AVG; compare with 152 of Figure 1) 452 over time of the first phase difference 435 and averaging (AVG; compare with 158 of Figure 1) 458 over time of the second phase difference 425. The activation is illustrated by switches 451.

[0178] The combination of the first phase difference 435 and the second phase difference 425 corresponds to the second phase difference 425 averaged 458 over time and compensated 459a, 459b based on the first phase difference 435. The compensation based on the first phase difference 435 corresponds to addition 459b of a difference 459a between the first phase difference 435 and the first phase difference 435 averaged 452 over time.

[0179] In addition to enabling selective control of the fractional-N synthesizer 412, the switching circuitry 450a comprises a divider multiplexer 454 (MUX; compare with 154 of Figure 1) configured to provide the first phase difference 435 as the first divider ratio 437 when the second reference frequency signal 421 is available, and to provide the first phase difference 435 averaged 452 over time responsive to loss of the second reference frequency signal 421.

[0180] Typically, the switching circuitry is also configured to perform operations in reverse responsive to the second reference frequency signal 421 becoming available again.

[0181] In some embodiments, the FS 400 is comprised in a circuitry arrangement, which may (or may not) also comprise the source 430 of the third reference frequency signal 431.

[0182] In any case, the circuitry arrangement further comprises a detector 428 (DET; compare with 128 of Figure 1) configured to detect presence (and / or absence) of the second reference frequency signal 421. The detector428 is also configured to provide an indication 429 of loss of the second reference frequency signal 421 to the switching circuitry 450a, 450b (more precisely, to the synthesizer multiplexer 456, to the divider multiplexer 454, and to the switches 451) responsive to non-detection of presence.

[0183] Figure 5 schematically illustrates a frequency synthesizer (FS) 500 with first and second control loops according to some embodiments. The FS 500 may be seen as an example of the FS 100 of P110495W001

[0184] 27

[0185] Figure 1, and as an extension of the FS 400 of Figure 4. In Figure 5, reference numbers 510, 511, 512, 513, 514, 515, 516, 517, 520, 521, 522, 523, 524, 525, 528, 529, 530, 531, 532, 533, 534, 535, 537, 550a, 550b, 551, 552, 554, 556, 558, 559a, and 559b correspond - respectively - to reference numbers 410, 411, 412, 413, 414, 415, 416, 417, 420, 421, 422, 423, 424, 425, 428, 429, 430, 431, 432, 433, 434, 435, 437, 450a, 450b, 451, 452, 454, 456, 458, 459a, and 459b of Figure 4.

[0186] In association with switching as described in Figure 4, it may be beneficial to apply suitable compensation for any phase difference between the second and third reference frequency signals 521, 531 to avoid phase discontinuities.

[0187] Difference compensation is implemented in the FS 500 by a differentiator 560 (DIFF) and transition compensation circuitry 562 (TC).

[0188] The differentiator 560 is configured to determine a trend of the second phase difference 525. In the example of Figure 5, this is achieved by determining a difference between a previous sample of the second phase difference 525 and a current sample of the second phase difference 525, and filtering the difference in a low pass filter (LPF) 561 to provide the determined trend.

[0189] The transition compensation circuitry 562 is configured to apply transition compensation corresponding to the trend in association with switching. In the example of Figure 5, this is achieved by activating sample-and-hold circuitry 563 (S / H) responsive to loss of the second reference frequency signal 521 (as indicated by 529), whereby the sample-and-hold circuitry 563 outputs the trend as determined at the point in time when the second reference frequency signal 521 was lost. A transition compensation multiplexer 564 (MUX) is controlled by 529 to pass the output 567 of the sample-and-hold circuitry while the second reference frequency signal 521 is unavailable and to pass a default value 568 (e.g., "zero") while the second reference frequency signal 521 is available. Summation circuitry 565 (SUM) accumulates the MUX output to form a suitable ramp which is added to the difference provided by 559a (the difference between the first phase difference 535 and the first phase difference 535 averaged 552 over time). The summation circuitry 565 is typically reset for each switching occasion (as indicated by 529). P110495W001

[0190] 28

[0191] Similar considerations may be applied for switching responsive to the second reference frequency signal 121 becoming available again.

[0192] Figure 6 schematically illustrates a frequency synthesizer (FS) 600 with offset compensation according to some embodiments. The FS 600 may be seen as an example of the FS 200 of Figure 2.

[0193] The FS 600 comprises a signal source 610 (REF 1; compare with 210 of Figure 2) providing a first reference frequency signal 611 with relatively high frequency (compare with 211 of Figure 2). A control loop is configured to improve accuracy based on a second reference frequency signal 631 with relatively low frequency (compare with 231 of Figure 2). Thus, the first reference frequency signal has higher frequency than the second reference frequency signal.

[0194] The second reference frequency signal 631 may be provided by a signal source 630 (REF 2; compare with 230 of Figure 2) which is comprised in, or relatively close to, the FS 600 (e.g., comprised in the same circuitry arrangement as the FS 600). For example, the signal source 630 may be implemented on a same integrated circuit as the FS 600, and / or may be comprised in the same electronic apparatus as the FS 600.

[0195] The second reference frequency signal 631 is typically more stable than the first reference frequency signal 611 (e.g., due to the lower frequency).

[0196] The FS 600 comprises a fractional-N synthesizer 612 (FNS; compare with 212 of Figure 2) configured to provide a synthesized frequency signal 613 (compare with 213 of Figure 2) based on the first reference frequency signal 611 while being controlled based on the second reference frequency signal 631.

[0197] The control of the FNS 612 is illustrated in Figure 6 as an adder 614 configured to control the FNS 612 by a control signal 617 based on a received signal 615, wherein the signal 615 is based on the second reference frequency signal 631. The signal 615 is a representation of a phase difference 635 between the second reference frequency signal 631 and a frequency divided version of the synthesized frequency signal 613.

[0198] In some embodiments, the adder 614 acquires a frequency control word (FCW) 616 and outputs an adjusted version FCW' as the control signal 617, wherein the adjustment comprises adding the signal 615 to the FCW 616, wherein the signal 615 is a digital representation of the phase P110495W001

[0199] 29 difference between the second reference frequency signal 631 and the frequency divided version of the synthesized frequency signal 613.

[0200] To improve accuracy of the synthesized frequency signal 613 based on the reference frequency signal 631, a control loop of the FS 600 comprises a frequency divider 632 (FD; compare with

[0201] 232 of Figure 2) and phase difference circuitry 634 (PDC; compare with 234 of Figure 2) configured to provide the signal 615 for control of the FNS 612. Thus, the frequency divider 632 and the phase difference circuitry 634 form a loop for locking the fractional-N synthesizer control to the second reference frequency signal 631.

[0202] The frequency divider 632 is configured to provide a divided frequency signal 633 (compare with

[0203] 233 of Figure 2) based on the synthesized frequency signal 613 while controlled by a divider ratio 637, 637'. The divider ratio 637, 637' may, for example, be based on a nominal value Nnomand may represent a ratio between a desired frequency of the synthesized frequency signal 213 and the frequency of the second reference frequency signal 231.

[0204] The phase difference circuitry 634 is configured to determine a phase difference 635 between the divided frequency signal 633 and the second reference frequency signal 631. The phase difference 635 is configured for control of the fractional-N synthesizer 612. To this end, the phase difference 635 is provided as the signal 615 for control of the FNS 612.

[0205] The phase difference circuitry 634 comprises a phase detector (RD; e.g., a digital phase detector) configured to receive the divided frequency signal 633 and the second reference frequency signal 631 as inputs (and output a momentary phase difference), and a loop filter (LF; e.g., a digital loop filter) configured to receive an output of the phase detector as input and to provide the phase difference 635 as output.

[0206] To address situations when the second reference frequency signal 631 is varying depending on a temperature of the signal source 630, thereby introducing a potential frequency offset in the control loop when it is not at nominal temperature, the FS 600 comprises offset compensation circuitry in the form of a frequency controller 670 (FC; compare with 270 of Figure 2) configured to adjust the divider ratio 637, 637' based on a frequency offset 671 of the second reference frequency signal 631. P110495W001

[0207] 30

[0208] In the example of Figure 6, the adjustment is implemented by an adder 672 configured to subtract a compensation value 636 from a nominal value Nnomof the divider ratio 637 to provide an adjusted divider ratio 637', wherein the compensation value 636 is based on the frequency offset 671. For example, the compensation value 636 may be a weighted version of the nominal value of the divider ratio 637. The weight may, for example, correspond to a frequency ratio between the frequency offset 671 and the second reference frequency signal 631.

[0209] The frequency offset 671 may be obtained in any suitable way. In the example of Figure 6, temperature dependent frequency offset sensing and determination is represented by a varying impedance 674 associated with the signal source 630 and configured to sense the frequency offset 671.

[0210] It should be noted that a feature described and / or exemplified in connection with one of the Figures herein may be equally applicable (as suitable) to the approach of any other one of the Figures even if it is not explicitly mentioned in connection thereto.

[0211] For sixth generation (6G) communication systems, an intended use case is joint coherent transmission (JCT) among access points. In JCT, it is beneficial (and may even be necessary) to have access to a radio frequency (RF) local oscillator (LO) signal with long term phase accuracy. The more stable the RF LO phase is, the smaller the frequency and / or phase drift is between access points, and the longer the transmission can go on (e.g., with beam-forming gain) without re-calibration among the access points .

[0212] More generally, a RF LO signal with low phase noise and other imperfections is beneficial in that it can enable use of more advanced modulation schemes and / or allocation of more of an emission budget to transmitter non-linearity (thereby improving power efficiency).

[0213] One contributor to phase noise is the frequency reference (compare with REF 1) used to synthesize the RF LO signal. A relatively high reference clock frequency reference may be beneficial since it leads to reduction of phase noise multiplication from the frequency reference to the RF LO frequency, and moves reference induced spurious further away from the carrier (enabling improved suppression by filtering). However, a relatively high reference frequency may also be associated with one or more problems. For example, the frequency accuracy is P110495W001

[0214] 31 typically reduced as the reference frequency increases when the reference source is implemented using a crystal oscillator (XO), the sensitivity for the output frequency and phase to ambient conditions (e.g., temperature, vibration, shock, etc.) is typically increased as the reference frequency increases, and - in relation to signal distribution - power consumption and / or signal purity loss is typically increased as the reference frequency increases.

[0215] As already mentioned, and as exemplified in US 10,505,555 B2, an attempt to solve these problems may include placing an XO (compare with REF 1) with relatively high frequency locally - close to the frequency synthesizer - and forming a control loop around the frequency synthesizer to improve the accuracy of frequency and / or phase, wherein the control loop uses a stable, relatively low, frequency signal as reference (a so called "golden" reference; compare with REF 2 in Figures 1, 4, and 5). However, it may be a requirement that the control loop operates continuously (e.g., if the XO is free-running), which may be problematic is the golden reference is not continuously available. For example, the golden reference may be obtained from a central source for different peripheral access points in a JCT system (i.e., the golden reference source is physically distant from the access points). In many applications, it is expected that reception of the golden reference may be interrupted and / or of varying quality. Losing the golden reference means that the RF LO phase alignment would be lost completely, or would rely on some open loop compensation (e.g., through look-up tables for temperature variation), or would rely on some mitigation of temperature sensitivity by placing the XO in a well-controlled environment (which would be costly).

[0216] Some embodiments address these problems by use of a redundant frequency reference signal (compare with REF 3 in Figures 1, 4, and 5) as described herein when the golden reference is lost. For example, a system for frequency synthesis may have an RF fractional-N synthesizer locked to a high frequency free running reference clock (compare with REF 1) and controlled through a golden reference (compare with REF 2 in Figures 1, 4, and 5). A fractional frequency divider (compare with FD 1 in Figures 1, 4, and 5) may be connected to the output of the synthesizer, phase detector may compare the fractional frequency divider output with a locally generated reference clock (compare with REF 3 in Figures 1, 4, and 5), and a loop filter may be connected to the phase detector to provide an output which is used for divider ratio control of the fractional frequency. Averaging and sampling circuitry may be used to lock the FCW and the divider ratio to respective moving averages, and multiplexers may be used to select between P110495W001

[0217] 32 averaged values and continuously updated values depending on the availability of the golden reference.

[0218] Operating the frequency synthesizer system, the second loop (compare with FD 2 and PDC 2 in Figures 1, 4, and 5) is closed and phase locked when the golden reference is present. In parallel thereto, the first loop (compare with FD 1 and PDC 1 in Figures 1, 4, and 5) is also closed, but instead of controlling the fractional-N synthesizer (compare with FNS in Figures 1, 4, and 5) as the second loop does, the first loop controls the divider ratio of its own fractional divider (compare with FD 1 in Figures 1, 4, and 5). Thereby, a frequency relationship is established between golden and local references (compare with REF 2 and REF 3 in Figures 1, 4, and 5). Phase alignment may also be accomplished between the LO output and the local reference. Thus, the first loop can take over the control of the fractional-N synthesizer from the second loop when needed.

[0219] The described embodiments and their equivalents may be realized in hardware. For example, the embodiments may be performed by specialized circuitry, such as application specific integrated circuits (ASIC) or application-specific circuitry within an integrated circuit. The specialized circuitry may, for example, be associated with or comprised in an electronic apparatus such as a communication apparatus (e.g., a radio access node or a wireless communication device). Thus, embodiments may appear within an electronic apparatus (such as a communication apparatus) comprising arrangements, circuitry, and / or logic according to any of the embodiments described herein.

[0220] Generally, all terms used herein are to be interpreted according to their ordinary meaning in the relevant technical field, unless a different meaning is clearly given and / or is implied from the context in which it is used.

[0221] Reference has been made herein to various embodiments. However, a person skilled in the art would recognize numerous variations to the described embodiments that would still fall within the scope of the claims.

[0222] For example, the partition of functional blocks into particular units is by no means intended as limiting. Contrarily, these partitions are merely examples. Functional blocks described herein as P110495W001

[0223] 33 one unit may be split into two or more units. Furthermore, functional blocks described herein as being implemented as two or more units may be merged into fewer (e.g. a single) unit.

[0224] Any feature of any of the embodiments disclosed herein may be applied to any other embodiment, wherever suitable. Likewise, any advantage of any of the embodiments may apply to any other embodiments, and vice versa.

[0225] Hence, it should be understood that the details of the described embodiments are merely examples brought forward for illustrative purposes, and that all variations that fall within the scope of the claims are intended to be embraced therein.

Claims

P110495W00134CLAIMS1. A frequency synthesizer (100, 300, 400, 500) comprising: a fractional-N synthesizer (112, 412, 512) configured to provide a synthesized frequency signal (113, 413, 513) based on a first reference frequency signal (111, 411, 511) while controlled (114, 117, 414, 417, 514, 517) based on a second or third reference frequency signal (121, 131, 421, 431, 521, 531), wherein the first reference frequency signal has higher frequency than the second and third reference frequency signals; a first frequency divider (132, 432, 532) configured to provide a first divided frequency signal (133, 433, 533) based on the synthesized frequency signal (113, 413, 513) while controlled by a first divider ratio (137, 137', 437, 537); first phase difference circuitry (134, 434, 534) configured to determine a first phase difference (135, 435, 535) between the first divided frequency signal (133, 433, 533) and the third reference frequency signal (131, 431, 531), wherein the first divider ratio (137, 137', 437, 537) is determined based on the first phase difference (135, 435, 535); and switching circuitry (150a, 150b, 450a, 450b, 550a, 550b) configured to cause the fractional-N synthesizer (112, 412, 512) to be controlled based on the third reference frequency signal (131, 431, 531) responsive to loss of the second reference frequency signal (121, 421, 521).

2. The frequency synthesizer (100, 300, 400, 500) of claim 1, wherein the first frequency divider(132, 432, 532) and the first phase difference circuitry (134, 434, 534) form a first loop for establishing a relation between the third reference frequency signal (131, 431, 531) and the second reference frequency signal (121, 421, 521).

3. The frequency synthesizer (100, 300, 400, 500) of any of claims 1 through 2, wherein the first phase difference circuitry (134, 434, 534) comprises: a first phase detector configured to receive the first divided frequency signal (133, 433, 533) and the third reference frequency signal (131, 431, 531) as inputs; and a first loop filter configured to receive an output of the first phase detector as input and to provide the first phase difference (135, 435, 535).P110495W001354. The frequency synthesizer (100, 300, 400, 500) of any of claims 1 through 3, wherein the switching circuitry (150a, 450a, 550a) is configured to activate averaging (152, 452, 552) over time of the first phase difference (135, 435, 535) responsive to loss of the second reference frequency signal (121, 421, 521).

5. The frequency synthesizer (100, 300, 400, 500) of claim 4, wherein the switching circuitry(150a, 450a, 550a) comprises a divider multiplexer (154, 454, 554) configured to provide the first divider ratio (137, 137', 437, 537) as the first phase difference (135, 435, 535) or, responsive to loss of the second reference frequency signal (121, 421, 521), as the first phase difference (135, 435, 535) averaged (152, 452, 552) over time.

6. The frequency synthesizer (100, 300, 400, 500) of any of claims 1 through 5, wherein the switching circuitry (150b, 450b, 550b) comprises a synthesizer multiplexer (156, 456, 556) configured to cause the fractional-N synthesizer (112, 412, 512) to be controlled based on the second reference frequency signal (121, 421, 521) or, responsive to loss of the second reference frequency signal (121, 421, 521), based the third reference frequency signal (131, 431, 521).

7. The frequency synthesizer (100, 300, 400, 500) of any of claims 1 through 6, further comprising: a second frequency divider (122, 422, 522) configured to provide a second divided frequency signal (123, 423, 523) based on the synthesized frequency signal (113, 413, 513) while controlled by a second divider ratio; and second phase difference circuitry (124, 424, 524) configured to determine a second phase difference (125, 425, 525) between the second divided frequency signal (123, 423, 523) and second reference frequency signal (121, 421, 521), wherein the second phase difference (125, 425, 525) is configured for control of the fractional-N synthesizer (112, 412, 512).

8. The frequency synthesizer (100, 300, 400, 500) of claim 7, wherein the second frequency divider (122, 422, 522) and the second phase difference circuitry (124, 424, 524) form a second loop for locking the fractional-N synthesizer control to the second reference frequency signal (121, 421, 521).P110495W001369. The frequency synthesizer (100, 300, 400, 500) of any of claims 7 through 8, wherein the second phase difference circuitry (124, 424, 524) comprises: a second phase detector configured to receive the second divided frequency signal (123, 423, 523) and the second reference frequency signal (121, 421, 521) as inputs; and a second loop filter configured to receive an output of the second phase detector as input and to provide the second phase difference (125, 425, 525).

10. The frequency synthesizer (100, 300, 400, 500) of any of claims 7 through 9 when combined with claim 6, wherein the synthesizer multiplexer (156, 456, 556) is configured to provide control of the fractional-N synthesizer based on the second phase difference (125, 425, 525) or, responsive to loss of the second reference frequency signal (121, 421, 521), based on the first phase difference (135, 435, 535).

11. The frequency synthesizer (100, 300, 400, 500) of any of claims 7 through 10, wherein the switching circuitry (150a, 150b, 450a, 450b, 550a, 550b) is configured to, responsive to loss of the second reference frequency signal (121, 421, 421), provide control of the fractional-N synthesizer (112, 412, 512) based on the second phase difference (125, 425, 525) averaged (158, 458, 558) overtime and compensated (159a, 159b, 459a, 459b, 559a, 559b) based on the first phase difference (135, 435, 535).

12. The frequency synthesizer (100, 300, 500) of any of claims 7 through 11, further comprising: a differentiator (160, 560) configured to determine a trend of the second phase difference (125, 525); and transition compensation circuitry (162, 562) configured to apply a transition compensation for the fractional-N synthesizer control (117, 517) responsive to loss of the second reference frequency signal (121, 521), wherein the transition compensation corresponds to the determined trend of the second phase difference.

13. The frequency synthesizer (100, 300) of any of claims 1 through 12, further comprising: offset compensation circuitry (170) configured to adjust (172) the first divider ratio (137, 137') based on a frequency offset (171) of the third reference frequency signal (131).P110495W0013714. The frequency synthesizer (100, 300) of claim 13, wherein the adjustment (172) of the first divider ratio comprises subtraction - from a value (137) of the first divider ratio - of a weighted version of the value, wherein the weight corresponds to a frequency ratio between the frequency offset (171) and the third reference frequency signal (131).

15. A circuitry arrangement (310) comprising the frequency synthesizer (100, 300, 400, 500) of any of claims 1 through 14.

16. The circuitry arrangement (310) of claim 15, further comprising a source (130, 430, 530) of the third reference frequency signal (131, 431, 531).

17. The circuitry arrangement (310) of any of claims 15 through 16, further comprising a detector (128, 428, 528) configured to detect presence of the second reference frequency signal (121, 421, 521), and to provide an indication (129, 429, 529) of loss of the second reference frequency signal (121, 421, 521) to the switching circuitry (150a, 150b, 450a, 450b, 550a, 550b) responsive to non-detection of presence.

18. The circuitry arrangement (310) of any of claims 15 through 17 when combined with any of claims 13 through 14, further comprising mapping circuitry (174) configured to determine the frequency offset (171) based on a temperature of the source (130) of the third reference frequency signal (131).

19. The circuitry arrangement (310) of claim 18, further comprising a temperature sensor (176) configured to measure the temperature of the source (130) of the third reference frequency signal (131).

20. An integrated circuit (320) comprising the frequency synthesizer (100, 300, 400, 500) of any of claims 1 through 14, and / or the circuitry arrangement (310) of any of claims 15 through 19.

21. An electronic apparatus (330) comprising the frequency synthesizer (100, 300, 400, 500) of any of claims 1 through 14, and / or the circuitry arrangement (310) of any of claims 15 through 19, and / or the integrated circuit (320) of claim 20.

22. The electronic apparatus (330) of claim 21, wherein the electronic apparatus is a radio access node or a wireless communication device.

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