Scheduling an access operation

Abstract

There is provided a method performed by a controller for scheduling a first access operation. The method comprises scheduling (202) a first time period in which a host device is allowed to perform a first access operation to access a peripheral device via a serial interface. The first time period is scheduled to avoid overlapping a second time period in which the host device is allowed to perform a second access operation to access the peripheral device via the serial interface.

Description

[0001] P111503W001

[0002] 1

[0003] SCHEDULING AN ACCESS OPERATION

[0004] Technical Field

[0005] The disclosure relates to methods for scheduling an access operation, and a controller configured to operate in accordance with those methods.

[0006] Background

[0007] Optical fiber has emerged as the most commonly used transmission medium in telecommunications. Service providers depend on optical fiber to reliably transport a continuously growing amount of data traffic, as optical fiber provides large bandwidth and low data loss. These key attributes make fiber the predominant choice for multiple communication applications ranging from telecommunication backbone infrastructure to metro and aggregation segments down to access networks serving fixed users and mobile access infrastructure (e.g. Fifth Generation (5G) Radio Access Network (RAN)).

[0008] Electronic process miniaturization paired with the advent of photonic integration has allowed the manufacturing of high-rate optical transceivers (e.g. up to 800 Gbps) in small pluggable formats (e.g. Small Form Factor Pluggable (SFP) or Quad SFP (QSFP) standardized by the Small Form Factor (SFF) committee) directly interconnected by optical fibers. Many of these optical transceivers can be housed in a single telecommunication equipment or data communication equipment, allowing for easy scaling of capacity provisioning as required by traffic demand trends.

[0009] Due to the large capacity of data transported by optical links, attention needs to be paid to the telecommunication infrastructure monitoring said optical links. This monitoring helps to ensure that faults can be prevented (where possible), and fast and reliable diagnostics can be provided when optical links fail (e.g. go down). As such, telecommunication infrastructure experiencing long traffic disruptions and cumbersome troubleshooting and repair procedures may affect said monitoring, causing high operational costs for service providers and disruption for service consumers.

[0010] Monitoring and diagnostic functions for optical links can exploit information provided by optical transceivers. Optical transceivers provide useful information (e.g. parameter P111503W001

[0011] 2 measurements) concerning their own status and the status of an optical link. Parameters like optical transmitted and received powers, laser bias current, operating temperature, polarization state rate of change, carrier frequency offset, Bit Error Rate (BER), etc., can be exploited for monitoring and diagnostic functions.

[0012] These parameters may be sampled or measured by internal sensors of the optical transceiver and the data made available through standardized digital interfaces (e.g. via an Inter-Integrated Circuit (I2C) interface) to host equipment. The data can then be made available to any software application that can exploit the data to build data-driven applications.

[0013] The set of available parameters and their allocation in a dedicated memory are defined by the SFF and Content Management Interoperability Services (CMIS) standardization bodies. Within CMIS, an extension of parameters (versatile diagnostic monitoring) has been added to include, for example, coherent receiver parameters.

[0014] The refresh rate of the parameter measurements is typically in the several to tenths of milliseconds, e.g. in the millisecond scale, allowing for fast variations of the measured values of the parameters to be detected. However, network management systems and / or dedicated analytics platforms typically acquire data periodically from telecommunication equipment (e.g. the optical transceiver) in a time frame of seconds, and provide performance management statistics on even slower timescales (e.g. 15 minutes).

[0015] While these timescales are sufficient for applications such as alarm reporting and for detecting slow analogue parameter fluctuations (e.g. temperature), they can be too slow for capturing sudden changes in fast-varying measurements. Fast varying measurements may be recorded for parameters such as received optical power (which can be used to determine fiber breakage), transmitted optical power and laser bias current (which can be used to identify a shutdown), polarization state changes, etc.

[0016] The received optical power from an optical transceiver is a source of data that helps root cause analysis of an optical link fault, provided that measurements of the received optical power can be sampled at a reasonable speed (e.g. 5 ms). In particular, different types P111503W001

[0017] 3 of faults induce different transient behaviour of the received optical power from its steady state normal operation value to its loss due to the link disruption.

[0018] “Real-Time Monitoring of Cable Break in a Live Network using a Coherent Transceiver Prototype", M. Mazur et al., 2024 Optical Fiber Communications Conference and Exhibition (OFC), suggests that polarization fluctuations, monitored with a coherent receiver, can be used as a means to foresee fiber problems.

[0019] The sampling speed required to capture the transients of specific fast-varying parameters (e.g. received optical power, polarization state, Forward Error Correction (FEC), etc.) stored in peripheral devices, such as optical transceivers, relies on reliable and fast access to these parameters from a serial interface. However, these serial interfaces are typically managed by a microprocessor (uP) of the host equipment, which also performs many other tasks making its sampling unstable and unreliable. On the other hand, serial interfaces can be accessed by having more robust Hardware (HW) implementations (e.g. a Field Programmable Gate Array (FPGA), an Application Specific Integrated Circuit (ASIC), etc.) take exclusive control of access to the memory (e.g. I2C resource) of the peripheral device, but this could hinder the standard operation, control, and management of access to the peripheral device (e.g. transceiver) by the uP.

[0020] It is therefore an object of the disclosure to obviate or eliminate at least some of the above-described disadvantages associated with existing techniques. For example, a reliable, managed access to the serial interface by the host equipment is needed that supports, e.g. at substantially the same time, both the fast access (e.g. monitoring or reading) of the memory of the peripheral device as well as the normal operations (e.g. transceiver operations) performed by the uP.

[0021] Therefore, according to a first aspect of the disclosure, there is provided a method performed by a controller for scheduling a first access operation. The method comprises scheduling a first time period in which a host device is allowed to perform a first access operation to access a peripheral device via a serial interface. The first time period is scheduled to avoid overlapping a second time period in which the host device is allowed P111503W001

[0022] 4 to perform a second access operation to access the peripheral device via the serial interface.

[0023] According to a second aspect of the disclosure, there is provided a controller for scheduling a first access operation. The controller comprises processing circuitry configured to cause the controller to schedule a first time period in which a host device is allowed to perform a first access operation to access a peripheral device via a serial interface. The first time period is scheduled to avoid overlapping a second time period in which the host device is allowed to perform a second access operation to access the peripheral device via the serial interface.

[0024] In some embodiments, the controller may comprise at least one memory for storing instructions which, when executed by the processing circuitry, cause the controller to operate in this way.

[0025] According to another aspect of the disclosure, there is provided a computer program comprising instructions which, when executed by processing circuitry, cause the processing circuitry to perform the method described earlier.

[0026] According to another aspect of the disclosure, there is provided a computer program product, embodied on a non-transitory machine-readable medium, comprising instructions which are executable by processing circuitry to cause the processing circuitry to perform the method described earlier.

[0027] Thus, embodiments of the present disclosure may provide an improved method for scheduling an access operation.

[0028] Embodiments of the present disclosure enable improved data handling by facilitating the scheduling of time periods dedicated to access operations, which may be performed at different rates. The methods disclosed herein enable robust performance of access operations (e.g. being performed at different rates), since interference between such operations is avoided. For example, the methods avoid the fast reading of data stored (e.g. in a memory) at a peripheral device interfering with normal operations involving (e.g. the slow reading of) said data. In this way, the access operations are more efficient and more reliable. P111503W001

[0029] 5

[0030] Brief of the drawinqs

[0031] For a better understanding of the techniques, and to show how they may be put into effect, reference will now be made, by way of example, to the accompanying drawings, in which:

[0032] Figure 1 is a block diagram illustrating a controller according to an embodiment;

[0033] Figure 2 is a block diagram illustrating a method performed by a controller according to an embodiment;

[0034] Figure 3 is a block diagram illustrating a system according to an embodiment;

[0035] Figure 4 is a block diagram illustrating a system according to an embodiment;

[0036] Figure 5 is a diagram illustrating the scheduling of a first time period;

[0037] Figure 6 is a diagram illustrating the scheduling of a first time period;

[0038] Figure 7 is a flowchart illustrating a method for determining whether a first access operation is allowed to be performed; and

[0039] Figure 8 is a diagram illustrating the scheduling of a first time period.

[0040] Detailed Description

[0041] Generally, all terms used herein are to be interpreted according to their ordinary meaning in the relevant technical field, unless a different meaning is clearly given and / or is implied from the context in which it is used. All references to a / an / the element, apparatus, component, means, step, etc. are to be interpreted openly as referring to at least one instance of the element, apparatus, component, means, step, etc., unless explicitly stated otherwise. The steps of any methods disclosed herein do not have to be performed in the exact order disclosed, unless a step is explicitly described as following or preceding another step and / or where it is implicit that a step must follow or precede P111503W001

[0042] 6 another step. Any feature of any of the embodiments disclosed herein may be applied to any other embodiment, wherever appropriate. Likewise, any advantage of any of the embodiments may apply to any other embodiments, and vice versa. Other objectives, features and advantages of the enclosed embodiments will be apparent from the following description.

[0043] Some of the embodiments contemplated herein will now be described more fully with reference to the accompanying drawings. Other embodiments, however, are contained within the scope of the subject-matter disclosed herein, the disclosed subject-matter should not be construed as limited to only the embodiments set forth herein; rather, these embodiments are provided by way of example to convey the scope of the subject-matter to those skilled in the art.

[0044] In some instances, detailed descriptions of well-known methods, nodes, interfaces, circuits, and devices are omitted so as not to obscure the description with unnecessary detail. Those skilled in the art will appreciate that the functions described may be implemented in one or more nodes using hardware circuitry (e.g. analogue and / or discrete logic gates interconnected to perform a specialised function, ASICs, Programmable Logic Arrays (PLAs), etc.) and / or using software programs and data in conjunction with one or more digital microprocessors or general-purpose computers. Nodes that communicate using an air interface also have suitable radio communications circuitry. Moreover, where appropriate the technology can additionally be considered to be embodied entirely within any form of computer-readable memory, such as solid-state memory, magnetic disk, or optical disk containing an appropriate set of computer instructions that would cause a processor to carry out the techniques described herein.

[0045] As mentioned earlier, there are described herein improved techniques that facilitate fast reading of selected parameters related to a peripheral device. For example, the techniques can facilitate a host device performing both fast reading of selected parameters of a peripheral device, and normal operations of a uP with respect to a larger number of parameters of the peripheral device. The fast reading has minimal impact on the normal operation and vice versa. For example, the fast reading can be performed without compromising the read and write operations of the uP. P111503W001

[0046] 7

[0047] The parameters may relate to an optical transceiver. Examples of the parameters may include, but are not limited to, any one or more of a transmit optical power, a receive optical power, a laser bias current, an operating temperature, a polarization state change, a rate of polarization state change, a carrier frequency offset, a bit error rate, and an FEC, etc.

[0048] As used herein, the term “normal operation” may refer to slow data processing, in which data stored (e.g. in the memory) at the peripheral device is processed relatively slowly. For example, slow data processing may comprise one or more parameters (or measured values of one or more parameters) being accessed at a slow rate (e.g. on a timescale of hundreds of milliseconds to seconds). This slow rate may also be referred to herein as a “first rate”. That is, a uP of the host device may perform access operations on the data stored (e.g. in the memory) at the peripheral device every 100 ms to 1 s, for example, or slower at every 1 s to 10 s, for example, in order to obtain one or more slow varying parameters (or measured values of one or more slow varying parameters).

[0049] An example of a normal operation includes the processing of measured values of a large number of parameters of an optical transceiver, wherein the large number of parameters exhibit slow transient behaviour (e.g. temperature, alarms, etc.). The normal operation may include a single access operation (e.g. a “one shot” or “one time” access operation) or multiple access operations (e.g. periodic or non-periodic access operations).

[0050] As used herein, the term “fast reading” may refer to fast data processing, in which data stored (e.g. in a memory) at a peripheral device is processed relatively quickly. For example, fast data processing may comprise one or more parameters (or measured values of one or more parameters) being accessed at a fast rate (e.g. on a timescale of milliseconds). This fast rate may also be referred to herein as a “second rate”. That is, a host device may perform access operations on the data stored (e.g. in the memory) at the peripheral device every 0.5 to 10 ms, for example, or slower at every 50 or 100 ms, for example, in order to obtain one or more fast varying parameters (or measured values of one or more fast varying parameters).

[0051] An example of fast reading includes the processing of (e.g. measured values of) selected parameters of an optical transceiver, wherein the selected parameters exhibit fast transient behaviour (e.g. received optical power, polarization state, FEC, etc.). P111503W001

[0052] 8

[0053] As used herein, the term “data processing” can refer to data access, such as reading data (e.g. sampling or acquiring data) and / or writing data. Similarly, as used herein, the term “processing operation” can refer to an access operation, such as a read operation and / or a write operation.

[0054] Embodiments of the present disclosure may be performed by a controller (which may also be referred to herein as an “interface controller”). The controller may comprise processing circuitry (or logic), such as an FPGA, ASIC, etc. The controller can act as an interface controller with respect to a peripheral device by mediating (or intercepting) access operations, such as uP requests, attempted on (e.g. a memory of) the peripheral device.

[0055] Figure 1 illustrates a controller 10 in accordance with an embodiment. The controller 10 is for scheduling a first access operation. In some embodiments, the controller 10 referred to herein can refer to equipment capable, configured, arranged and / or operable to communicate directly or indirectly with the host device referred to herein, the peripheral device referred to herein, and / or with other nodes or equipment to enable and / or to perform the functionality described herein. In some embodiments, the controller 10 referred to herein can, for example, be a physical node (e.g. a physical machine or server) or a virtual node (e.g. a virtual machine, VM).

[0056] As illustrated in Figure 1 , the controller 10 comprises processing circuitry (or logic) 12. The processing circuitry 12 controls the operation of the controller 10 and can implement the method described herein in respect of the controller 10. The processing circuitry 12 can be configured or programmed to control the controller 10 in the manner described herein. The processing circuitry 12 can comprise one or more hardware components, such as one or more processors, one or more processing units, one or more multi-core processors and / or one or more modules. In particular implementations, each of the one or more hardware components can be configured to perform, or is for performing, individual or multiple steps of the method described herein in respect of the controller 10. In some embodiments, the processing circuitry 12 can be configured to run software to perform the method described herein in respect of the controller 10. The software may be containerised according to some embodiments. Thus, in some embodiments, the processing circuitry 12 may be configured to run a container to perform the method P111503W001

[0057] 9 described herein in respect of the controller 10.

[0058] Briefly, the processing circuitry 12 of the controller 10 is configured to schedule a first time period in which a host device is allowed to perform a first access operation to access (e.g. a memory at) a peripheral device via a serial interface, such as at a first rate (e.g. the slow rate discussed above). The first time period is scheduled to avoid overlapping a second time period in which the host device is allowed to perform a second access operation to access (e.g. the memory) at the peripheral device via the serial interface, such as at a second rate (e.g. the fast rate discussed above). More detail on this operation of the controller 10 is discussed below with reference to Figures 2-8.

[0059] As illustrated in Figure 1 , in some embodiments, the controller 10 may optionally comprise a memory 14. The memory 14 of the controller 10 can comprise a volatile memory or a non-volatile memory. In some embodiments, the memory 14 of the controller 10 may comprise a non-transitory media. Examples of the memory 14 of the controller 10 include, but are not limited to, a random access memory (RAM), a read only memory (ROM), a mass storage media such as a hard disk, a removable storage media such as a compact disk (CD) or a digital versatile disk (DVD), and / or any other memory.

[0060] The processing circuitry 12 of the controller 10 can be communicatively coupled (e.g. connected) to the memory 14 of the controller 10. In some embodiments, the memory 14 of the controller 10 may be for storing program code or instructions which, when executed by the processing circuitry 12 of the controller 10, cause the controller 10 to operate in the manner described herein in respect of the controller 10. For example, in some embodiments, the memory 14 of the controller 10 may be configured to store program code or instructions that can be executed by the processing circuitry 12 of the controller 10 to cause the controller 10 to operate in accordance with the method described herein in respect of the controller 10. Alternatively or in addition, the memory 14 of the controller 10 can be configured to store any information, data, messages, requests, responses, indications, notifications, signals, or similar, that are described herein. The processing circuitry 12 of the controller 10 may be configured to control the memory 14 of the controller 10 to store any of the information, data, messages, requests, responses, indications, notifications, signals, or similar, that are described herein.

[0061] In some embodiments, as illustrated in Figure 1 , the controller 10 may optionally P111503W001

[0062] 10 comprise a communications interface 16. The communications interface 16 of the controller 10 can be communicatively coupled (e.g. connected) to the processing circuitry 12 of the controller 10 and / or the memory 14 of the controller 10. The communications interface 16 of the controller 10 may be operable to allow the processing circuitry 12 of the controller 10 to communicate with the memory 14 of the controller 10 and / or vice versa. Similarly, the communications interface 16 of the controller 10 may be operable to allow the processing circuitry 12 of the controller 10 to communicate with any one or more nodes (e.g. the host device and / or the peripheral device) referred to herein and / or any other node. The communications interface 16 of the controller 10 can be configured to transmit and / or receive any of the information, data, messages, requests, responses, indications, notifications, signals, or similar, that are described herein. In some embodiments, the processing circuitry 12 of the controller 10 may be configured to control the communications interface 16 of the controller 10 to transmit and / or receive any of the information, data, messages, requests, responses, indications, notifications, signals, or similar, that are described herein.

[0063] Although the controller 10 is illustrated in Figure 1 as comprising a single memory 14, it will be appreciated that the controller 10 may comprise at least one memory (i.e. a single memory or a plurality of memories) 14 that operate in the manner described herein. Similarly, although the controller 10 is illustrated in Figure 1 as comprising a single communications interface 16, it will be appreciated that the controller 10 may comprise at least one communications interface (i.e. a single communications interface or a plurality of communications interfaces) 16 that operate in the manner described herein. It will also be appreciated that Figure 1 only shows the components required to illustrate an embodiment of the controller 10 and, in practical implementations, the controller 10 may comprise additional or alternative components to those shown.

[0064] Figure 2 illustrates a method performed by the controller 10 in accordance with an embodiment. The method is for scheduling a first access operation. The controller 10 described earlier with reference to Figure 1 can be configured to operate in accordance with the method of Figure 2. The method can be performed by or under the control of the processing circuitry 12 of the controller 10 according to some embodiments.

[0065] With reference to Figure 2, as illustrated by block 202, the method comprises scheduling a first time period in which a host device is allowed to perform a first access operation to P111503W001

[0066] 11 access (e.g. a memory at) a peripheral device via a serial interface. More specifically, the controller 10 (e.g. the processing circuitry 12 of the controller 10) schedules the first time period in which the host device is allowed to perform the first access operation to access (e.g. the memory at) the peripheral device via the serial interface. The first time period is scheduled to avoid overlapping a second time period in which the host device is allowed to perform a second access operation to access (e.g. the memory at) the peripheral device via the serial interface.

[0067] The first access operation may provide access for a microprocessor, and / or the second access operation may provide access for determination of one or more parameters from the peripheral device. The microprocessor may be configured to provide for transmission and / or receiving of data from the peripheral device.

[0068] The controller may be hardware circuitry, such as an FPGA or ASIC.

[0069] The first time period can be defined as a length (or portion) of time. The first time period may also be referred to herein as a “first time interval”. The second time period can be defined as a length (or portion) of time. The second time period may also be referred to herein as a “second time interval”. The duration of the first time period may be greater than, equal to, or less than the duration of the second time period.

[0070] The first time period in which the host device is allowed to perform the first access operation may be a first time period in which the host device is allowed to perform the first access operation at a first rate and the second time period in which the host device is allowed to perform the second access operation may be a second time period in which the host device is allowed to perform the second access operation at a second rate. The second rate may be greater than the first rate.

[0071] It should be appreciated that the first rate may correspond to the average rate at which the first access operation is allowed to be performed during the first time period, such as the number of first access operations that are allowed to be performed per unit of time (e.g. per second) during the first time period. Similarly, the second rate may correspond to the average rate at which the second access operation is allowed to be performed during the second time period, such as the number of second access operations that are allowed to be performed per unit of time (e.g. per second) during the second time period. P111503W001

[0072] 12

[0073] It should also be appreciated that performing the first access operation during the first time period can comprise performing a single first access operation (e.g. a single write operation or a single read operation) during the first time period, or multiple first access operations (e.g. multiple write operations, multiple read operations, or a combination of one or more write operations and one or more read operations) during the first time period. In the case of performing multiple first access operations during the first time period, the first access operations may be performed periodically (e.g. at regular time intervals) during the first time period or non-periodically (i.e. at irregular time intervals) during the first time period.

[0074] Similarly, performing the second access operation during the second time period can comprise performing a single second access operation (e.g. a single write operation or a single read operation) during the second time period, or multiple second access operations (e.g. multiple write operations, multiple read operations, or a combination of one or more write operations and one or more read operations) during the second time period. In the case of performing multiple second access operations during the second time period, the second access operations may be performed periodically (e.g. at regular time intervals) during the second time period.

[0075] In some embodiments, the first time period may be scheduled in response to detecting whether a first length of time needed for the host device to perform the first access operation is greater than a second length of time until the second time period begins. In some embodiments, the first length of time may be (e.g. measured) based on a quantity (e.g. number of bytes / bits) of data to be accessed in the first access operation.

[0076] If the first length of time is detected to be less than or equal to the second length of time, scheduling the first time period may comprise scheduling the first time period to begin and end before the second time period begins. If the first length of time is detected to be greater than the second length of time, scheduling the first time period may comprise scheduling the first time period to begin after the second time period ends. If the first length of time is detected to be greater than the second length of time, scheduling the first time period may comprise: scheduling the first time period to end before the second time period starts and in which the host device is allowed to perform a first part of the first access operation; and scheduling another first time period to begin after the second P111503W001

[0077] 13 time period ends and in which the host device is allowed to perform a second part of the first access operation. In this embodiment, the total duration of the first time period and the another first time period may be greater than, equal to, or less than the duration of the second time period.

[0078] Although not illustrated in Figure 2, in some embodiments, the method may comprise storing an index indicative of a point in the first access operation at which the first part of the first access operation ends. More specifically, the controller 10 (e.g. the processing circuitry 12 of the controller 10 and / or processing circuitry performing the I2C smart + Time Base functionality discussed in relation to Figure 4) may store (e.g. in the memory 14 of the controller 10) the index indicative of a point in the first access operation at which the first part of the first access operation ends.

[0079] Although not illustrated in Figure 2, in some embodiments, the method may comprise reducing the second time period. More specifically, the controller 10 (e.g. the processing circuitry 12 of the controller 10) may reduce the second time period. In these embodiments, scheduling the first time period to avoid overlapping the second time period may comprise scheduling the first time period to avoid overlapping the reduced second time period.

[0080] Although not illustrated in Figure 2, in some embodiments, the method may comprise: at the beginning of the second time period, providing a first indication to the host device that the second time period has begun; and at an end of the second time period, providing a second indication to the host device that the second time period has ended. More specifically, the controller 10 (e.g. the processing circuitry 12 of the controller 10) may: at the beginning of the second time period, provide the first indication to the host device that the second time period has begun; and at the end of the second time period, provide the second indication to the host device that the second time period has ended. In these embodiments, the first indication may comprise an End of Transmission (EOT) signal set to a first value and the second indication may comprise the EOT signal set to a second value.

[0081] Although not illustrated in Figure 2, in some embodiments, the method may comprise scheduling the first time period in response to receiving a first request from the host device. More specifically, the controller 10 (e.g. the processing circuitry 12 of the P111503W001

[0082] 14 controller 10) may schedule the first time period in response to receiving the first request from the host device. In these embodiments, the first request may be a request for the first access operation to be performed.

[0083] Although not illustrated in Figure 2, in some embodiments, the method may comprise intercepting the first request from the host device before the first request reaches the peripheral device. More specifically, the controller 10 (e.g. the processing circuitry 12 of the controller 10) may intercept the first request from the host device before the first request reaches the peripheral device.

[0084] Although not illustrated in Figure 2, in some embodiments, the method may comprise scheduling the second time period. More specifically, the controller 10 (e.g. the processing circuitry 12 of the controller 10) may schedule the second time period.

[0085] Although not illustrated in Figure 2, in some embodiments, the method may comprise one or both of: initiating performance of the first access operation in the first time period; and initiating performance of the second access operation in the second time period. More specifically, the controller 10 (e.g. the processing circuitry 12 of the controller 10) may initiate the performance of the first access operation and / or the second access operation.

[0086] The first access operation to access (e.g. the memory at) the peripheral device may comprise one or both of a first read operation to read data from (e.g. the memory at) the peripheral device and a first write operation to write data to (e.g. the memory at) the peripheral device. Similarly, the second access operation to access (e.g. the memory at) the peripheral device may comprise one or both of a second read operation to read data from (e.g. the memory at) the peripheral device and a second write operation to write data to the (e.g. memory at) the peripheral device.

[0087] The performance of the first access operation (e.g. a single first access operation or multiple first access operations) in the first time period can be initiated at a rate that is less than or equal to the first rate. The performance of the second access operation (e.g. a single second access operation or multiple second access operations) in the second time period can be initiated at a rate that is equal to or greater than the second rate. P111503W001

[0088] 15

[0089] In some embodiments, a first configuration may be utilised for performance of the first access operation and a second configuration may be utilised for performance of the second access operation. Although not illustrated in Figure 2, in some embodiments, the method may comprise initiating a switch between utilisation of the first configuration and utilisation of the second configuration based on the first time period and the second time period. More specifically, the controller 10 (e.g. the processing circuitry 12 of the controller 10) may initiate the switch between utilisation of the first configuration and utilisation of the second configuration.

[0090] The host device may comprise the controller 10. The serial interface may be: an Inter- Integrated Circuit (I2C) interface; a Serial Peripheral Interface (SPI); or a Universal Asynchronous Receiver / Transmitter (UART) interface. The peripheral device may comprise an optical transceiver and / or a memory that stores data relating to an optical link. The data may comprise measured values of a plurality of parameters monitored by the peripheral device. For example, the plurality of parameters may comprise one or more of: optical transmitted power, optical received power, laser bias current, operating temperature, polarization state change, rate of polarization state change, carrier frequency offset, bit error rate, and forward error correction.

[0091] Embodiments of the present disclosure allow shared access to a serial interface of a device. The device may also be referred to herein as a “peripheral device” or an “I2C peripheral device”. The device may be, for example, an optical transceiver. The shared access to a serial interface allows a host device to perform reliable fast acquisition of (e.g. data relating to) specific parameters from the device (e.g. a memory of the device) and, at substantially the same time, controlled access by a uP of the host device for normal operations. The host device may also be referred to herein as “host equipment”.

[0092] Some embodiments are based on a HW implementation of interface controller functions and / or a logic to provide timing between fast reading of selected parameters (which may also be referred to herein as “fast monitoring”, “I2C smart access”, “I2C smart”, “I2C smart acquisition”, “I2C smart reading”, “second access operations”, etc.) and processing of uP (i.e. microprocessor) requests (which may also be referred to herein as “normal operations”, “requested operations”, “uP requested operations”, “uP operations”, “first access operations”, transmit / receive of data using the peripheral device, e.g. optical transceiver, etc.). P111503W001

[0093] 16

[0094] The timing logic may reserve periodic, stable time slots for the fast monitoring, Tsmart(which may also be referred to herein as “I2C smart time-slots”, “Tsmart I2C smart read”, etc.) interleaved by time periods when uP operations are processed (i.e. normal operation), TuP(which also may be referred to herein as “uP time-slots”). Data that is requested and / or processed for the fast reading and the uP requests may be stored in separate HW Random Access Memory (RAM) sections.

[0095] There is provided a method to control a shared access to a peripheral device via a serial interface (e.g. I2C interface) between a uP and a controller (e.g. an FPGA or ASIC) 10, with the controller 10 acting as an interface controller. The controller 10 can perform fast and deterministic access (e.g. acquisition) of selected data from the peripheral device and may store the data in a memory 14. The controller can manage and mediate a uP request to access the peripheral device, in order not to interfere with the fast acquisition of selected data.

[0096] In one embodiment, the controller 10 may limit the uP requests in operations that can be fulfilled in the time between two fast data acquisition by the controller 10.

[0097] The controller 10 (e.g. HW logic of the controller 10) may evaluate the amount of data that can be processed in a uP time slot after a uP request has been received. The controller 10 (e.g. HW logic of the controller 10) may perform the uP request (only) if enough time is available. Otherwise, the controller 10 (e.g. HW logic of the controller 10) may cause the uP request to be refused. In some aspects, the controller or access controlling component schedules the access using hardware circuitry, e.g. a FPGA or ASIC. As such, the access scheduling can be carried out rapidly and efficiently.

[0098] In another embodiment, the controller 10 may fulfil all requests by splitting long access requirements into multiple available slots, i.e. splitting into a shorter time slot to allow sharing.

[0099] The controller 10 (e.g. HW logic of the controller 10) may split the uP request into multiple time slots, e.g. such that different parts of the first access operation are performed in different uP time-slots. In this case, the processed data may be merged in a HW memory map area devoted to the uP. Thus, the controller 10 (e.g. HW logic of the controller 10) P111503W001

[0100] 17 is capable of always performing a uP request, e.g. regardless of the resources required to perform the uP request. Only minor delays for the uP request may be incurred due to the interleaved second access operation (e.g. I2C smart) time slots. Furthermore, the splitting of the uP request may be transparent to the uP. For example, the controller 10 (e.g. HW logic of the controller 10) may confirm that the uP request has been performed and completed (e.g. via an EOT signal), such as when (e.g. only when) all data has been processed for the uP request.

[0101] There is also provided a system (or network) comprising the controller 10 described herein. A method performed by the system comprises the method described herein (e.g. with reference to Figure 2) in respect of the controller 10. Embodiments of this system are illustrated in Figure 3 and Figure 4.

[0102] Figure 3 is a block diagram of a system comprising a controller 10, a host device 20, a peripheral device 30 (e.g. a device that is, or that comprises, an optical transceiver), and a serial interface 40. The controller 10 may correspond to the controller 10 discussed with reference to Figure 1. In Figure 3, the host device 20 comprises the controller 10. However, it will be understood that the controller 10 may instead be separate from (e.g. remote from or external to) the host device 20.

[0103] The host device 20 can communicate with the peripheral device 30 via the serial interface 40. For example, the host device 20 may comprise a uP and the uP may communicate with the peripheral device 30 via the serial interface 40. In an example, the host device 20 (e.g. the uP of the host device 20) may, for normal operations, process data from (e.g. a memory at) the peripheral device 30 at the first rate discussed above. The host device 20 may also perform or attempt (e.g. via requesting) fast reading of data from (e.g. the memory at) the peripheral device 30 at the second rate discussed above.

[0104] The host device 20 may operate in a network. The network can be any type of network. For example, the network may be a communications or telecommunications network, for example, an optical network. The network may be a mobile network, such as a fifth generation (5G) mobile network, a sixth generation (6G) mobile network, or any other generation mobile network. Although some examples have been provided for the type of network, it will be understood that the network can be any other type of network. The P111503W001

[0105] 18 host device 20 may comprise a network management system or a dedicated analytics platform.

[0106] The peripheral device 30 may comprise a memory. The memory of the peripheral device 30 may be accessed by the host device 20 (e.g. by a microprocessor (uP) of the host device 20) via the serial interface 40. The memory of the peripheral device 30 can comprise data. The data may comprise a plurality of parameters, or measured values of a plurality of parameters, which may be monitored or acquired by the peripheral device 30. For example, the memory of the peripheral device 30 may store data relating to an optical link. In this case and in other cases, the parameters may comprise any one or one or more of: optical transmitted power; optical received power; laser bias current; operating temperature; polarization state change; rate of polarization state change; carrier frequency offset; bit error rate; and FEC. In some aspects, the peripheral device is an optical transceiver, e.g. a SFP. In some aspects, the peripheral device is accessed with a I2C connection.

[0107] The controller 10 controls the serial interface 40 such that certain types of access to the peripheral device 30 are allowed or disallowed. For example, in a scheduled first time period, the host device 20 may be allowed to perform or attempt (e.g. via requesting) a first access operation to access (e.g. the memory at) the peripheral device 30 via the serial interface 40, such as at the first rate. In a scheduled second time period, the host device 20 may be allowed to perform a second access operation to access (e.g. the memory at) the peripheral device 30 via the serial interface 40, such as at the (e.g. faster) second rate.

[0108] The serial interface 40 may be any one of an I2C interface, an SPI, a UART interface, or any other serial interface.

[0109] Figure 4 is a block diagram of a more detailed system. The system comprises blocks with functionalities corresponding to those of the components of Figure 3, such as the controller 10, the host device 20, the peripheral device 30 (referred to as an “SFP” in Figure 4), and the serial interface 40 (referred to as an “I2C controller interface” in Figure 4). The serial interface 40 interfaces to the peripheral device 30. For brevity, repetition of the functions of these components is omitted with reference to Figure 4 but will be understood to apply. P111503W001

[0110] 19

[0111] In Figure 4, the controller 10 is a Finite State Machine (FSM). However, any other form of controller 10 is also possible. The controller 10 of Figure 4 can communicate with one or more of the other functional blocks illustrated in Figure 4, such as the first configuration block 403 and the second configuration block 404. In Figure 4, the controller 10 is separate from the first configuration block 403 and the second configuration block 404. However, it will be understood that the controller 10 may instead comprise the first configuration block 403 and the second configuration block 404. In Figure 4, the host device 20 comprises the controller 10. However, it will be understood that the controller 10 may instead be separate from (e.g. remote from or external to) the host device 20. The system illustrated in Figure 4 comprises additional functional blocks.

[0112] It should be appreciated that Figure 4 is a conceptual representation of a system and does not necessarily represent exact physical HW blocks. Furthermore, whilst Figure 4 utilises functional blocks to represent the system, the system may instead be represented in any other suitable manner (e.g. by modules etc.).

[0113] Referring back to Figure 2, as illustrated by block 202, a first time period is scheduled. Block 202 of Figure 2 may be performed by the controller (e.g. FSM) 10 of Figure 4. In the first time period, the host device 20 is allowed to perform a first access operation to access (e.g. a memory at) the peripheral device 30 via the serial interface 40, e.g. at a first rate. The first time period is scheduled to avoid overlapping a second time period in which the host device 20 is allowed to perform a second access operation to access (e.g. the memory at) the peripheral device 30 via the serial interface 40, e.g. at a second rate. The second rate may be greater than the first rate. In some aspects, the first and second access operations are for different purposes. For example, the first access operation may be for normal operation, as controlled by the microprocessor, e.g. for transmit / receive or communication of data. The second access operation may be reading one or more parameter from the communication channel or transceiver signals. In some examples, the second access operation may be a read only operation, i.e. the second access operation is not for transmission on the interface. The scheduling requirements for the first and second access operations may be different. For example, the first access operation may require as much access time as possible, although the exact time may be flexible. The second access operation may require a shorter access time, although the P111503W001

[0114] 20 exact time of access and / or periodicity of access may be precise e.g. with less or no flexibility.

[0115] Once the first time period has been scheduled, the controller 10 may initiate performance of the first access operation in the first time period.

[0116] As discussed above, the first access operation may be referred to herein as a “normal operation”, “requested operation”, “uP requested operation”, “uP operation”, etc. The first access operation may comprise one or both of a first read operation to read data from (e.g. the memory of) the peripheral device 30 and a first write operation to write data to (e.g. the memory of) the peripheral device 30.

[0117] As discussed above, the second access operation may be referred to herein as a “fast reading”, “fast monitoring”, “I2C smart access”, “I2C smart”, “I2C smart acquisition”, “I2C smart reading”, etc. The second access operation may comprise one or both of a second read operation to read data from (e.g. the memory of) the peripheral device 30 and a second write operation to write data to (e.g. the memory of) the peripheral device 30.

[0118] The second time period may be scheduled by the controller 10, or any other suitable component in communication with the controller 10. The second time period may be scheduled to occur periodically. For example, the second time period may be scheduled for respective sample periods (e.g. scheduled at the beginning or end of respective sample periods). The duration of time between successive second time periods may be greater than, equal to, or less than the duration of each second time period.

[0119] Once scheduled, the controller 10 may initiate performance of the second access operation in the second time period (e.g. throughout the duration of the second time period).

[0120] Once initiated, the second access operation may comprise continuously acquiring data during the second time period. For example, the second access operation may comprise multiple second access operations (e.g. read and / or write operations) performed periodically. The acquired data may be stored in a dedicated memory, e.g. as data P111503W001

[0121] 21 samples. The host device 20 may monitor the data (or data samples) to detect the occurrence of an event (e.g. a fast variation in measured values of parameters such as received optical power (indicating fiber breakage), transmitted optical power and laser bias current (identifying a shutdown), a polarization state change, etc).

[0122] In response to detecting the event, the host device 20 may stop (e.g. interrupt, halt, or pause) the second access operation, e.g. in order to allow the host device 20 or other external entities to download the stored data (e.g. as a time series of data samples). The downloaded data can then be processed (e.g. using software) by the host device 20 or other external entities (e.g. at higher levels). Once downloading of the data is completed, the host device 20 may re-initiate (e.g. restart or resume) the second access operation in the second time period (or a subsequent second time period) and optionally also ready itself to detect the occurrence of a new event.

[0123] If no event is detected before the dedicated memory has been filled, the oldest acquired data may be discarded (e.g. using a shift register) such that, in continuous operation, the dedicated memory comprises (e.g. is full with) the latest acquired n data (or data samples), where n is a positive integer.

[0124] The scheduling of the second time period may be performed by utilising an I2C Smart + Time Base block 402 of the system of Figure 4. This block 402 may schedule the second time period (e.g. by setting the time base for the second access operation, such as a periodic I2C smart fast read from the peripheral device 30). In Figure 4, the controller 10 is shown to be separate from the I2C Smart + Time Base block 402. However, it will be understood that the controller 10 may instead comprise the I2C Smart + Time Base block 402. For example, in a hardware implementation of the system of Figure 4, the I2C Smart + Time Base block 402 functionality may be performed by the processing circuitry 12 of the controller 10. For example, the control of the scheduling of access between a microprocessor (uP) 406 and the parameter reading (I2C smart fast read) may be by hardware circuitry, e.g. an FPGA or ASIC.

[0125] A first configuration is utilised for performance of the first access operation and a second configuration is utilised for performance of the second access operation. For example, the controller 10 may initiate a switch between utilisation of the first configuration and utilisation of the second configuration based on the first time period and the second time P111503W001

[0126] 22 period. This is illustrated in Figure 4 by the controller 10 having access to the first configuration block 403 and the second configuration block 404.

[0127] The first configuration block 403 (which may also be referred to herein as a “CFG uP block”) contains the first configuration (e.g. I2C configuration settings, toggle parameters, etc.) for enabling the uP 406 to perform the first access operation (which can be a normal access operation, such as a normal I2C operation). The first configuration may define (or set) the parameters to be accessed (such as read, e.g. periodically read) and a read frequency (e.g. which may be equal to or less than the first rate). A memory (e.g. a RAM area) associated with the first configuration and / or the first time period may be dedicated for the storage of data processed for the first access operation. This memory may be included in the first configuration block 403.

[0128] The second configuration block 404 (which may also be referred to herein as a “CFG I2C Smart” block) contains the second configuration (e.g. an I2C configuration or I2C smart configuration) for enabling the host device 20 to perform the second access operation (which can be a smart access operation, such as an I2C smart acquisition or fast read). The second configuration may define (or set) the parameters to be accessed (such as read, e.g. periodically read) and a read frequency (which may be equal to or greater than the second rate). A memory (e.g. a RAM area) associated with the second configuration and / or the second time period may be dedicated for the storage of data processed for the second access operation. This memory may be included in the second configuration block 404.

[0129] The host device 20 may configure the first configuration and / or the second configuration. For example, the host device 20 may configure the access (e.g. read and / or write) requests from / to the peripheral device 30 for the first access operation, such as the normal access operation. The host device 20 may configure the access (e.g. read and / or write) requests from / to the peripheral device 30 for the second access operation, such as the fast acquisition of parameters or I2C smart operation.

[0130] It may be that the first access operation and the second access operation are performed, executed, or actuated by different components of the system, such as different components of the host device 20. For example, a uP 406 of the host device 20 may utilise the first configuration to perform, execute, or actuate the first access operation P111503W001

[0131] 23

[0132] (e.g. to manage the access (e.g. read and / or write) request from / to the peripheral device 30 for the first access operation, such as the normal access operation). Circuitry of the host device 20 (e.g. the controller 10 and / or the I2C Smart + Time Base block 402) may utilise the second configuration to perform, execute, or actuate the second access operation (e.g. to manage the access (e.g. read and / or write) request from / to the peripheral device 30 for the second access operation, such as the fast acquisition of parameters or I2C smart operation).

[0133] The I2C Smart + Time Base block 402 may be utilised to toggle the connection of the I2C controller interface 40 to the first configuration block 403 or the second configuration block 404 depending on the running time slot. That is, in a scheduled first time period, the I2C controller interface 40 may be connected to the first configuration block 403. In a scheduled second time period, the I2C controller interface 40 may be connected to the second configuration block 404. This may be achieved by having the controller (e.g. FSM) 10 switch the configuration of the I2C controller interface 40, such that the controller (e.g. FSM) 10 can control the host device’s access to the peripheral device 30. The controller (e.g. FSM) 10 can cause the I2C controller interface 40 to communicate with the peripheral device 30 in either a first mode, which can also be referred to as a “uP mode” (i.e. according to the first configuration), or a second mode, which can also be referred to as an “I2C smart mode” (i.e. according to the second configuration). For simplicity, this change (or switch) between configurations is represented with a Multiplexer (MUX) 408 in Figure 4.

[0134] As discussed above, in the first time period, the host device 20 is allowed to perform the first access operation to access (e.g. the memory at) the peripheral device 30 via the serial interface 40, e.g. at the first rate. In the second time period, the host device 20 is allowed to perform the second access operation to access (e.g. the memory at) the peripheral device via the serial interface 40, e.g. at the second rate.

[0135] As discussed in more detail below, this may be achieved by the controller (e.g. FSM) 10 controlling access to the peripheral device 30. For example, the controller (e.g. FSM) 10 may be dedicated for enabling and / or disabling the first access operations (e.g. the uP operations) depending on whether there is time slot availability for the first access operation (e.g. depending on whether a first time period has been or can be scheduled). P111503W001

[0136] 24

[0137] In this way, the controller 10 can prevent first access operations from being performed or attempted at the same time as second access operations.

[0138] It may be the case that the uP 406 needs to start the first access operation when (e.g. a bus of) the serial interface 40 is free. The controller 10 can provide, when (e.g. a bus of) the serial interface 40 is free, a first indication to the host device 20 at the beginning of the second time period. The first indication may indicate to the host device 20 that the second time period has begun. The controller 10 may also provide, at an end of the second time period, a second indication to the host device 20 that the second time period has ended. The first and second indications may thus indicate to the host device 20 that a time period, TuP, has begun in which first access operations are allowed.

[0139] The first indication may comprise an EOT signal set to a first value. The first value can indicate that the second time period has begun. The second indication may comprise the EOT signal set to a second value. The second value can indicate the that the second time period has ended. For example, the controller 10 may provide an EOT signal to indicate to the uP 406 (and thus make the uP 406 aware) that TuPhas begun (i.e. the serial interface 40, or a bus of the serial interface 40, is free) and / or that TuPhas ended (i.e. the serial interface 40, or a bus of the serial interface 40, is not free).

[0140] For example, during a scheduled second time period (e.g. a smart I2C access time), Tsmart, the EOT may be set to a first value (e.g. 0) so that the uP 406 refrains from performing or attempting the first access operation and instead waits for TuP(which is the free window for the first access operation). The EOT may be set to a second value (e.g. 1) when Tsmartends, or a second access operation is terminated, and TuPbegins (which is when the time-slot available for the first access operations starts).

[0141] The first time period may be scheduled in response to the controller 10 detecting whether a first length of time needed for the host device 20 to perform the first access operation is greater than a second length of time (also referred to herein as a “working window”, Tww) until the second time period begins. The first length of time may be (e.g. measured) based on a quantity of data to be accessed in the first access operation. The quantity of data may be a number of bits or bytes to be processed for the first access operation. P111503W001

[0142] 25

[0143] The first length of time and the second length of time can be detected by the controller 10 because the first access operation is not allowed to overlap with any second access operation, meaning the controller 10 ensures that any first access operation performed during TuPis concluded before any scheduled second time period beings (e.g. before a new I2C smart access is initiated).

[0144] The first time period may be scheduled in response to the controller 10 receiving a first request from the host device 20. The first request may be a request for the first access operation to be performed. The controller 10 may receive the first request by intercepting the first request before the first request reaches the peripheral device 30. The working window may then correspond to the time period between the time of interception of the first request and the beginning of the second time period.

[0145] For example, the working window (and thus the operation time of the uP 406) can be calculated based on TuPand Tsmart, which may both be dependent on the sampling frequency of the second access operation (e.g. I2C smart) and the speed (e.g. clock speed) of the serial interface 40. The maximum working window of the uP 406 corresponds to TuPand the sampling period can be denoted by Ts. Assuming Ts> TSmart’Tupcanbe calculated as: luPls1smart'

[0146] Typically, TuP> Tsmartsince the second access operation (e.g. fast acquisition) performed by the host device 20 may be limited to (e.g. only performed for) a few selected or relevant parameters.

[0147] The maximum number of bits / bytes available for performing the first access operation (NuP) during TuPis approximately:

[0148] NuP= R * TuP, where R is the interface bitrate.

[0149] However, this calculation of NuPneglects possible delays between the start of TuPand an actual request or attempt at performance of the first access operation. That is, the number of actual bytes that can be processed for the first access operation during TuP P111503W001

[0150] 26 factual)isusually less than NuP, since Nactuaidepends on the instant that the first access operation is attempted or requested within TuP. The controller (e.g. FSM) 10 may therefore monitor the time instant that a first request for a first access operation is received or intercepted by the controller 10, such that the exact time when the uP 406 tries accessing the serial interface 40 is known. This can improve the accuracy of the calculation.

[0151] The working window can be determined by determining the time difference between the instant that the uP 406 tries accessing the serial interface 40 and a start of the second time period. Nactualcan then be calculated as: actual - R * T’ww -

[0152] Figures 5 and 6 illustrate embodiments in which the first time period is scheduled in response to detecting whether a first length of time needed for the host device 20 to perform the first access operation is greater than a second length of time until the second time period begins. The scheduling avoids the first time period from overlapping with one or more second time periods.

[0153] It may be the case that the first length of time is detected to be less than or equal to the second length of time. In this case, the scheduling of the first time period may comprise scheduling the first time period to begin and end before the second time period begins.

[0154] Figure 5 illustrates such an embodiment. In more detail, Figure 5 illustrates an embodiment in which the first length of time 508 is detected to be less than the second length of time 510, and thus the first time period 500 is scheduled to begin and end before the second time period (Tsmart) 506 begins.

[0155] In Figure 5, the first time period 500 is scheduled within a sampling period (Ts) 501. Ts501 is labelled an “I2C smart sampling period” as an example in Figure 5. Ts501 is a time period in which second access operations are allowed. The first time period 500 is scheduled for a first access operation 504 requested (at time instant X) during a time period TuP505 in which first access operations are allowed. TuP505 is the time period between the second time period Tsmart2506 and another (earlier) second time period (Tsmart) 507. Tsmartl507 is labelled an “I2C smart read” period as an example in the P111503W001

[0156] 27

[0157] Figure 5. Tsma507 is scheduled at the beginning of Ts501 , and Tsmart2506 is scheduled (e.g. immediately) after Ts501 ends.

[0158] As mentioned earlier, in Figure 5, the first time period 500 is scheduled in response to the reception of a first request (at time instant X) for the first access operation 504 during TuP505. The time period between X and the end of TuP505 corresponds to Tww510 for this embodiment. As illustrated in Figure 5, the first length of time 508 needed for the host device 20 to perform the first access operation 504 is shorter than Tww510. Thus, the first time period 500 is scheduled within Tww510, as the first access operation 504 will conclude before Tsmart506 begins.

[0159] However, in some cases, the first length of time 510 may be greater than the second length of time 508. This is not necessarily predictable for the controller 10, as the first access operation 502 may have a non-fixed duration, and the first access operation 502 may be requested at a random instant during TuP505.

[0160] For example, as previously indicated, the uP 406 of the host device 20 may synchronize its operations with scheduled second time periods by reading an indication (e.g. EOT signal) provided by the controller 10. However, there may be a time delay between the indication (e.g. EOT signal) being read by the uP 406 and the time the uP 406 decides to attempt (e.g. via requesting) a first access operation. As such, even if the uP 406 attempts the first access operation during TuP, there may no longer be enough time or resources in TuPfor the first access operation to be performed and concluded during TuP.

[0161] Embodiments of the present disclosure propose methods for how the controller 10 handles first access operations that require more resources than are available in Tww.

[0162] For example, it may be the case that the first length of time is detected to be greater than the second length of time. In this case, the scheduling of the first time period may comprise scheduling the first time period to begin after the second time period ends. This can be beneficial where first access operations (e.g. uP operations) are “time- bounded” within a single sampling period. That is, if a first access operation is requested or attempted during a first TuPof a first Tsand there is insufficient time during the first TuPfor the first access operation to be performed and concluded, (the entirety of) this first access operation may be postponed to a second TuPof a second Ts. P111503W001

[0163] 28

[0164] Figure 6 illustrates such a time-bounded situation. In more detail, Figure 6 illustrates an embodiment in which the first length of time 608 is detected to be greater than the second length of time 610, and thus the first time period 600 is scheduled to begin after the second time period (Tsmar) 606 ends.

[0165] In Figure 6, the first time period 600 is scheduled within a second Ts(or “next cycle”). The first time period 600 is scheduled for a first access operation 604 requested (at time instant X) during a TuP605. The second Tsoccurs after the first Ts601.

[0166] TuP605 is the time period between the second time period Tsmart606 and another (earlier) second time period (Tsmartl) 607. Tsmar607 is labelled an “I2C smart read” period as an example in the Figure 6. Tsmart607 is scheduled at the beginning of Ts601 , and Tsmart606 is scheduled (e.g. immediately) after Ts601 has ended.

[0167] As mentioned earlier, in Figure 6, the first time period 600 is scheduled in response to the reception of a first request (at time instant X) for the first access operation 604 during TuP605. The time period between X and the end of TuP605 corresponds to Tww610 for this embodiment.

[0168] As illustrated in Figure 6, the first length of time 608 needed for the host device 20 to perform the first access operation 604 is longer than Tww610. Thus, the first time period 600 is scheduled to occur after Tsmart606 ends (e.g. during a TuPof the second Ts). This is because the first access operation 604 would not conclude before Tsmar606 begins if the first access operation 604 were performed in Tww.

[0169] The controller 10 may monitor or control uP access (to the peripheral device 30 via the serial interface 40) to determine the instant in time, X, between points 1 and 2 in Figure 6. The controller 10 may then calculate the time (e.g. in bytes) available or remaining for the uP 406 to conclude the attempted first access operation between time instant X and the end of the first Ts(i.e. Tww610). The controller 10 may calculate the remaining time based on the speed (e.g. clock speed) of the serial (e.g. I2C) interface and the time of the next second access operation (e.g. the next sampling of the I2c smart). In this way, the controller 10 can decide whether to allow the second access operation or force the EOT first value (e.g. EOT=0) to allow it in the next cycle. P111503W001

[0170] 29

[0171] The controller 10 may determine whether a completion condition for the first access operation is verified. This can involve the controller 10 determining whether Tww610 is greater than, equal to, or less than the time required for the first access operation to be performed.

[0172] If Tww610 does not provide enough time for the first access operation to be performed and concluded, the controller 10 may freeze the first access operation 604. For example, if Tww610 is less than the time required for the first access operation 604 to be performed 608, the controller (e.g. FSM) 10 may intercept a START signal for the first access (e.g. read and / or write) operation 604 transmitted from the uP 406 to the peripheral device 30 via the serial interface 40.

[0173] The first access operation may then be executed after the next scheduled second time period 606 (i.e. in a TuPof the second Ts). The uP 406 may be prevented from attempting (e.g. via requesting) the first access operation during TuP605, such as by setting the EOT to the second value (e.g. 0).

[0174] The embodiments discussed with reference to Figure 6 may be particularly beneficial in situations where the second access operation is the same each time 606, 607 it is performed and is prioritized over the first access operation 604, and Tsmartland Tsmart2are fixed (i.e. where the Tsmartoperation time and window are fixed). Whilst TuP605 may also fixed, it will be appreciated that first access operations may be attempted (e.g. via request) at any time during TuP605, and this time may change for each Ts(causing Nagualand Tww 610 to vary for each first access operation).

[0175] Referring to both Figures 5 and 6, the maximum number of bytes that can be read in TuP505, 605 (i.e. NuP) is deterministic, as TuP505, 605 is known or can be calculated. Specifically, TuP505, 605 is the time period between successive Tsmarts. NuPcan be stored in a uP configuration area (e.g. in the first configuration block 403) to avoid the uP 406 attempting to perform (e.g. via request) a first access operation 504, 604 for TuP505, 605 that would never fit within an available window (e.g. within TuP505, 605, due to the time, resources, and / or processed data required for the first access operation 504, 604). P111503W001

[0176] 30

[0177] Alternatively, if the uP 406 attempts to perform a first access operation 504, 604 that would never fit within an available window (e.g. within TuP505, 605), the controller (e.g. FSM) 10 can prevent it from being initiated.

[0178] Figure 7 illustrates such a situation. In more detail. Figure 7 is a flowchart of a method for preventing a uP 406 from attempting to perform a first access operation for a TuPthat would never fit within the TuP. The method of Figure 7 may be performed by any suitable controller 10 in any suitable system. For example, the controller 10 described earlier with reference to Figures 1 , 3 and Figure 4 can be configured to operate in accordance with the method of Figure 7. The method can be performed by or under the control of the processing circuitry 12 of the controller 10 according to some embodiments.

[0179] At step 702, the controller 10 determines whether an operation is never allowed, such as based on the time, resources, and / or processed data required for the first access operation.

[0180] If the first access operation will always be too large to be performed in TuP(e.g. it is always longer than TuP, it always requires too much data to be processed in TuP, etc.), the operation is never allowed, and the method progresses to step 704. At step 704, the controller 10 blocks the uP 406 from performing (e.g. requesting) first access operations until the first access operation is changed. This may comprise changing the number of parameters for which data is processed as part of the first access operation. The controller 10 may also provide NuPto the uP 406.

[0181] Returning to step 702, if the first access operation is not always too large to be performed in TuP(e.g. it is not longer than TuP, it does not require too much data to be processed in TuP, etc.), the operation is sometimes allowed, and the method progresses to step 706. At step 706, the controller 10 determines whether a first time period can be scheduled in the TuPin which the first access operation is intercepted. The controller 10 determines if the first time period can be scheduled in the working window. For example, the controller 10 may determine whether the first time period can be performed and concluded before the next Tsmartbegins.

[0182] If the first time period can be performed and concluded (e.g. the number of bits / bytes required for the first access operation is smaller than Tww), the operation is allowed, and P111503W001

[0183] 31 the method progresses to step 708. At step 708, the controller 10 allows the uP 406 to perform the operation (e.g. immediately).

[0184] Returning to step 706, if the first time period cannot be performed and concluded (e.g. the number of bits / bytes required for the first access operation is larger than Tww), the operation is not allowed, and the method progresses to step 710. At step 710, the controller 10 determines whether the operation is allowed in the next sampling period. If the number of bytes to process for the operation has not increased between steps 702 and 706 and / or if the next sampling period is equal to or longer than the current sampling period, the operation is allowed as this determination has already been performed in step 702.

[0185] If the controller 10 determines that the operation is allowed in the next sampling period, the method progresses to step 712. At step 712, the controller 10 allows the uP 406 to perform the operation in the next sampling period. That is, the uP 406 can perform the operation in the next sampling period.

[0186] Returning to step 710, if the controller 10 determines that the operation is not allowed in the next sampling period (e.g. because the number of bytes to process for the operation increased between steps 702 and 706 and / or the next sampling period is shorter than the current sampling period), the method returns to step 704.

[0187] An example is now provided in which it is determined whether the first time period can be scheduled before the next scheduled second time period or after the next scheduled second time period. The following notation is used:

[0188] - N = Number of bytes to be accessed (e.g. read) for the second access operation (e.g. by I2C smart) in each cycle

[0189] - M = Number of bytes to be accessed (e.g. read) for the first access operation (e.g. by the uP)

[0190] -Tbtt = = Bit duration over the serial (e.g. I2C) interface 40, where R is the bitrate.

[0191] Assuming 31 bits are allocated for dummy writing or other protocols and an I2C frame protocol defining bytes that are 9 bits long (and it will be understood that variants for P111503W001

[0192] 32 other implementations are also possible), and assuming the uP 406 makes full use of its time slot (TuP), the maximum value of M is calculated as:

[0193] Tbit* (31 + M * 9) = Ts- (31 + N * 9) * Tbit

[0194] If the serial interface has a speed (i.e. R) of 100 KHz, N = 2 (e.g. based on the typical optical power available for fast reading), and the (e.g. I2C smart) sampling period Tsis 1 ms, then:

[0195] Tbit=0'01ms

[0196] - M = 1 / 9 (100 — 62) — 2 = 4 — 2 = 2 byte read by uP

[0197] Alternatively, if the serial interface has a speed (i.e. R) is 400 KHz, but N remains 2 and the (e.g. I2C smart) sampling period remains 1ms, then:

[0198] Tbit=0.0025 ms

[0199] - M = 1 / 9 (400 - 62) - 2 = 37.3 - 2 = 35 byte read by uP

[0200] Another option for handling first access operations that require more resources than are available in a working window comprises splitting the requested first access operation over multiple sample periods.

[0201] Other embodiments disclosing methods for handling first access operations that require more resources than are available in Twwwill now be discussed.

[0202] In these embodiments, the first time period may be scheduled to end before the second time period starts. In this first time period, the host device 20 is allowed to perform a first part of the first access operation. Another first time period may be scheduled to begin after the second time period ends. In this other first time period, the host device 20 is allowed to perform a second part of the first access operation. Although the splitting is described herein in relation to two parts, it will be understood that this is only one example and the first access operation may be split into more than two parts, if appropriate, and the same ideas apply. The splitting of the first access operation into multiple first time P111503W001

[0203] 33 periods reduces any delay imposed by scheduling the first time period to begin after the second time period has ended.

[0204] Figure 8 Illustrates such an embodiment. In more detail, Figure 8 illustrates an embodiment in which the first length of time 808 is detected to be greater than the second length of time 810, and thus the first time period 800 (in which the host device 20 is allowed to perform a first part of the first access operation 804) is scheduled and another first time period 802 (in which the host device 20 is allowed to perform a second part of the first access operation 804) is scheduled. As such, the first and second parts of the first access operation 804 are scheduled in different sample periods.

[0205] As with Figures 5 and 6, TuP805 is the time period between the second time period Tsmarti806(labelled as an “I2C smart read” period as an example in Figure 8) and another (earlier) second time period Tsma807. Tsmar807 is scheduled at the beginning of Ts801 , and Tsmar806 is scheduled (e.g. immediately) after Ts801 ends.

[0206] As mentioned earlier, in Figure 8, the first time period 800 and the other first time period 802 are scheduled in response to the reception of a first request (at time instant X) for the first access operation 804 during TuP805. The time period between X and the end of TuP805 corresponds to Tww810 for this embodiment.

[0207] As illustrated in Figure 8, the first length of time 808 needed for the host device 20 to perform the first access operation 804 is longer than Tww810. Thus, a first time period 800 is scheduled to occur before Tsmart2806 begins (i.e. during Tww810). The other first time period 802 is scheduled to occur after Tsmart2806 ends (i.e. during a TuPof the second Ts). This is because the first access operation 804, if attempted to be performed only in Tww810, would not conclude before the Tsmart2806 begins.

[0208] Therefore, forthe embodiment represented by Figure 8, there may be no need to perform an assessment of the length of time needed forthe first access operation to be performed with respect to the available time (Tww810) within TuP805. If the first length of time is too long, the first access operation 804 is split, with a first part of the first access operation 804 being performed in the scheduled first time period 800 and a second part of the first access operation 804 being perform in the other scheduled first time period 802. P111503W001

[0209] 34

[0210] It may be the case that at least part of the first access operation 804 is always allowed to be performed in TuP805 in which the uP 406 attempts the first access operation 804. If the time remaining within this TuP(i.e. Tww810) is insufficient for the first access operation 804 to be concluded, the controller 10 may split the first access operation 804 into two or more parts, with respective parts being performed in respective first time periods scheduled in the TuPof different sampling periods. In this way, the uP can always perform its operations.

[0211] In some embodiments where a first access operation 804 is split, an index may be stored (e.g. in a memory 14, such as a RAM, of the controller 10). The index is indicative of a point in the first access operation 804 at which the first part of the first access operation 804 ends. For example, the index may indicate (e.g. exactly) where the first access operation 804 stopped in the first time period 800. This allows the serial interface 40 to know which data is left to be processed (e.g. accessed, such as read and / or written) when the second part of the first access operation 804 is performed in the other first time period 802. The first access operation 804 can thus be completed.

[0212] Once both the first and second parts (or all) of the first access operation 804 have been performed, the processed (e.g. read) data can be merged (e.g. contiguously) in the memory.

[0213] This behaviour may be transparent to the uP 406, particularly if the EOT changes state only after the first access operation 804 has been completed.

[0214] Whilst the splitting of the first access operation 804 may introduce a small delay in the completion of the first access operation 804, it can provide any one or both of the following advantages: robust, fast (e.g. I2C smart) reading of (e.g. the memory of) the peripheral device 30; and

[0215] - transparent (e.g. fully transparent), normal operation of the uP 406 that ignores, or does not interfere with, the fast (e.g. I2C smart) reading of (e.g. the memory of) the peripheral device 30.

[0216] The controller 10 may reduce the second time period. For example, if a second access operation has wrongly been configured with too many parameters to be accessed (e.g. P111503W001

[0217] 35 read) for a given Ts, then a (e.g. automatic) reduction of the sampling period may be applied to leave some space for the first access operation(s). The scheduling of the first time period to avoid overlapping the second time period may then comprise the first time period being scheduled to avoid overlapping the reduced second time period.

[0218] The data (e.g. data time series) processed (e.g. acquired) for the first access operation may be offloaded to a cloud infrastructure to prevent the controller 10 from saturating its memory 14. It also allows analytics or ML based applications that utilise this data to be executed in the cloud.

[0219] There is also provided a computer program comprising instructions which, when executed by processing circuitry (such as the processing circuitry 12 of the controller 10 described herein), cause the processing circuitry to perform at least part of the method described herein. There is provided a computer program product, embodied on a non- transitory machine-readable medium, comprising instructions which are executable by processing circuitry (such as the processing circuitry 12 of the controller 10 described herein) to cause the processing circuitry to perform at least part of the method described herein. There is provided a computer program product comprising a carrier containing instructions for causing processing circuitry (such as the processing circuitry 12 of the controller 10 described herein) to perform at least part of the method described herein. In some embodiments, the carrier can be any one of an electronic signal, an optical signal, an electromagnetic signal, an electrical signal, a radio signal, a microwave signal, or a computer-readable storage medium.

[0220] In some embodiments, the controller 10 functionality described herein can be performed by hardware. Thus, in some embodiments, the controller 10 described herein can be a hardware entity. However, it will also be understood that optionally at least part or all of the controller 10 functionality described herein can be virtualised. For example, the functions performed by the controller 10 described herein can be implemented in software running on generic hardware that is configured to orchestrate the controller 10 functionality described herein. Thus, in some embodiments, the controller 10 described herein can be a virtual node. In some embodiments, at least part or all of the controller 10 functionality described herein may be performed in a network enabled cloud. Thus, the method described herein can be realised as a cloud implementation according to some embodiments. The controller 10 functionality described herein may all be at the P111503W001

[0221] 36 same location or at least some of the controller 10 functionality may be distributed, e.g. the controller 10 functionality may be performed by one or more different nodes.

[0222] It will be understood that at least some or all of the method steps described herein can be automated in some embodiments. That is, in some embodiments, at least some or all of the method steps described herein can be performed automatically. The method described herein can be a computer-implemented method.

[0223] Thus, in the manner described herein, embodiments of the present disclosure provide an improved method for scheduling an access operation.

[0224] In particular, embodiments of the present disclosure enable improved data handling by facilitating the scheduling of time periods dedicated to access operations, which may be performed at different rates. The methods disclosed herein enable robust performance of access operations (e.g. being performed at different rates), since interference between such operations is avoided. For example, the methods avoid the fast reading of data stored (e.g. in a memory) at a peripheral device interfering with normal operations involving (e.g. the slow reading of) said data. In this way, the access operations are more efficient and more reliable.

[0225] The controller described herein can be a hardware controller (e.g. an ASIC or FPGA), which is able to make periodic / fast readings from the peripheral device (such as an optical transceiver, e.g. SFP) over a serial interface (e.g. an I2C interface), without affecting the normal operation of the microprocessor sending / receiving data on the peripheral device.

[0226] Embodiments of the present disclosure can be employed to ensure that quick variations (e.g. those occurring on a time scale of milliseconds) in measured values of parameters can be reliably detected by a host device, as the fast reading can be performed without requiring or relying on a uP of the host device to alter its normal operations involving the parameters. For example, the uP can avoid altering the rate at which it samples data from (e.g. the memory at) the peripheral device for the normal operations. At the same time, as the uP is still allowed to access the data during the scheduled time periods dedicated for this access, the normal operations of the uP are substantially unaffected. P111503W001

[0227] 37

[0228] In the manner described herein, embodiments of the present disclosure may provide any one or more of the following advantages:

[0229] - enabling fast and reliable monitoring of fast-changing device parameters;

[0230] - offloading fast and repetitive data acquisition tasks from the uP;

[0231] - supporting Artificial Intelligence (AI)ZMachine Learning (ML)Zanalytics applications on opto-modules; and

[0232] - enabling (e.g. via a HW enabler) advanced data streaming to foster data driven applications.

[0233] Embodiments of the present application may, for example, be used for basebands andZor implemented in Fronthaul (FH)ZBackhaul (BH) routers.

[0234] It should be noted that the above-mentioned embodiments illustrate rather than limit the idea, and that those skilled in the art will be able to design many alternative embodiments without departing from the scope of the appended claims. The word “comprising” does not exclude the presence of elements or steps other than those listed in a claim, “a” or “an” does not exclude a plurality, and a single processor or other unit may fulfil the functions of several units recited in the claims. Any reference signs in the claims shall not be construed so as to limit their scope.

Claims

1. P111503W00138CLAIMS1 . A method performed by a controller (10) for scheduling a first access operation, the method comprising:- scheduling (202) a first time period (500, 600, 800, 802) in which a host device (20) is allowed to perform a first access operation (604, 804) to access a peripheral device (30) via a serial interface (40), wherein the first time period (500, 600, 800, 802) is scheduled to avoid overlapping a second time period (506, 606, 806) in which the host device (20) is allowed to perform a second access operation to access the peripheral device (30) via the serial interface (40).

2. The method as claimed in claim 1 , wherein the first access operation provides access for a microprocessor (406), and / or the second access operation provides access for determination of one or more parameter from the peripheral device (30).

3. The method as claimed in claim 2, wherein the microprocessor (406) is configured to provide for transmission and / or receiving of data from the peripheral device (30).

4. The method as claimed in any one of the preceding claims, wherein the controller (10) is hardware circuitry.

5. The method as claimed in any one of the preceding claims, wherein: the first time period (500, 600, 800, 802) in which the host device (20) is allowed to perform the first access operation (604, 804) is a first time period (500, 600, 800, 802) in which the host device (20) is allowed to perform the first access operation (604, 804) at a first rate; and the second time period (506, 606, 806) in which the host device (20) is allowed to perform the second access operation is a second time period (506, 606, 806) in which the host device (20) is allowed to perform the second access operation at a second rate; and the second rate is greater than the first rate.

6. The method as claimed in any of the preceding claims, the method comprising:P111503W00139- scheduling the first time period (500, 600, 800, 802) in response to detecting whether a first length of time (508, 608, 808) needed for the host device (20) to perform the first access operation (504, 604, 804) is greater than a second length of time (510, 610, 810) until the second time period (506, 606, 806) begins.

7. The method as claimed in claim 6, wherein the first length of time (508, 608, 808) is based on a quantity of data to be accessed in the first access operation (504, 604, 804).

8. The method as claimed in claim 6 or 7, wherein if the first length of time (508) is detected to be less than or equal to the second length of time (510), scheduling the first time period comprises:- scheduling the first time period (500) to begin and end before the second time period (506) begins.

9. The method as claimed in any of claims 6 to 8, wherein if the first length of time (608) is detected to be greater than the second length of time (610), scheduling the first time period comprises:- scheduling the first time period (600) to begin after the second time period (606) ends.

10. The method as claimed in any of claims 6 to 8, wherein if the first length of time (804) is detected to be greater than the second length of time (810), scheduling the first time period comprises:- scheduling the first time period (800) to end before the second time period (806) starts and in which the host device (20) is allowed to perform a first part of the first access operation (804); and- scheduling another first time period (802) to begin after the second time period (806) ends and in which the host device (20) is allowed to perform a second part of the first access operation (804).

11. The method as claimed in claim 10, the method comprising:- storing an index indicative of a point in the first access operation (804) at which the first part of the first access operation (804) ends.P111503W0014012. The method as claimed in any of the preceding claims, the method comprising:- reducing the second time period (506, 606, 806); and wherein scheduling the first time period (500, 600, 800, 802) to avoid overlapping the second time period (506, 606, 806) comprises scheduling the first time period (500, 600, 800, 802) to avoid overlapping the reduced second time period (506, 606, 806).

13. The method as claimed in any of the preceding claims, the method comprising:- at the beginning of the second time period (506, 606, 806), providing a first indication to the host device (20) that the second time period (506, 606, 806) has begun; and- at an end of the second time period (506, 606, 806), providing a second indication to the host device (20) that the second time period (506, 606, 806) has ended.

14. The method as claimed in claim 13, wherein the first indication comprises an End of Transmission, EOT, signal set to a first value and the second indication comprises the EOT signal set to a second value.

15. The method as claimed in any of the preceding claims, the method comprising:- scheduling the first time period (500, 600, 800, 802) in response to receiving a first request from the host device (20), wherein the first request is a request for the first access operation to be performed.

16. The method as claimed in claim 15, the method comprising:- intercepting the first request from the host device (20) before the first request reaches the peripheral device (30).

17. The method as claimed in any of the preceding claims, the method comprising:- scheduling the second time period (506, 606, 806).

18. The method as claimed in any of the preceding claims, the method comprising one or both of: initiating performance of the first access operation (504, 604, 804) in the first time period (500, 600, 800, 802); andP111503W00141- initiating performance of the second access operation in the second time period (506, 606, 806).

19. The method as claimed in any of the preceding claims, wherein:- the first access operation (504, 604, 804) to access peripheral device (30) comprises one or both of a first read operation to read data from the peripheral device (30) and a first write operation to write data to the peripheral device (30); and / or- the second access operation to access the peripheral device (30) comprises one or both of a second read operation to read data from the peripheral device (30) and a second write operation to write data to the peripheral device (30).

20. The method as claimed in any of the preceding claims, wherein a first configuration is utilised for performance of the first access operation and a second configuration is utilised for performance of the second access operation.

21. The method as claimed in claim 20, the method comprising:- initiating a switch between utilisation of the first configuration and utilisation of the second configuration based on the first time period (500, 600, 800, 802) and the second time period (506, 606, 806).

22. The method as claimed in any of the preceding claims, wherein the host device (20) comprises the controller (10).

23. The method as claimed in any of the preceding claims, wherein the peripheral device (30) comprises an optical transceiver and / or the peripheral device (30) stores data relating to an optical link.

24. The method as claimed in any of the preceding claims, wherein the data comprises measured values of a plurality of parameters monitored by the peripheral device (30).

25. The method as claimed in claim 24, wherein the plurality of parameters comprises one or more of: optical transmitted power, optical received power, laser biasP111503W00142 current, operating temperature, polarization state change, rate of polarization state change, carrier frequency offset, bit error rate, and forward error correction.

26. The method as claimed in any of the preceding claims, wherein the serial interface (40) is: an Inter- Integrated Circuit, I2C, interface; a Serial Peripheral Interface, SPI; or a Universal Asynchronous Receiver / Transmitter, UART, interface.

27. A controller (10) for scheduling a first access operation, the controller (10) comprising processing circuitry (12) configured to cause the controller (10) to:- scheduling a first time period (500, 600, 800, 802) in which a host device (20) is allowed to perform a first access operation (504, 604, 804) to access a peripheral device (30) via a serial interface (40), wherein the first time period (500, 600, 800, 802) is scheduled to avoid overlapping a second time period (506, 606, 806) in which the host device (20) is allowed to perform a second access operation to access the peripheral device (30) via the serial interface (40).

28. A controller (10) as claimed in claim 27, wherein the processing circuitry (12) is configured to cause the controller (10) to perform the method according to any of claims 2 to 26.

29. A computer program comprising instructions which, when executed by processing circuitry, cause the processing circuitry to perform the method according to any of claims 1 to 26.

30. A computer program product, embodied on a non-transitory machine-readable medium, comprising instructions which are executable by processing circuitry to cause the processing circuitry to perform the method according to any of claims 1 to 26.

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