Clock recovery apparatus for optical transceiver of plant control system (PCS) in nuclear power plant

Abstract

The present invention relates to a clock recovery apparatus for an optical transceiver of a plant control system (PCS) in a nuclear power plant, capable of improving reliability and extending service life by simply implementing a clock recovery circuit in the optical transceiver of the PCS, and capable of smoothly receiving input data even when a transmission clock of the optical transceiver is not synchronized. The clock recovery apparatus for an optical transceiver of a PCS in a nuclear power plant of the present invention comprises: a clock generation unit that generates a sampling clock for receiving input data; and a buffer that receives the input data on the basis of the generated sampling clock and transmits the received input data to a decoder.

Description

Clock recovery device for optical transceiver in nuclear power plant control system (PCS)

[0001] The present invention relates to a clock recovery device for an optical transceiver of a Plant Control System (PCS) of a nuclear power plant, and more particularly, to recover a clock for data reception based on data that does not include clock information. In addition, the present invention relates to a clock recovery device for an optical transceiver of a Plant Control System (PCS) of a nuclear power plant, which can configure a clock recovery circuit with a simple circuit so as to be highly reliable and have an extended lifespan in a nuclear power plant.

[0002] Typically, the power plant control system (PCS) of a nuclear power plant is an integrated control system that collects and analyzes information on various control devices and processes, such as pumps, fans, dampers, and power circuit breakers, and controls and monitors system devices through hand switches in the main control room and remote shutdown control panel.

[0003] This control system uses an optical communication network with high communication speed and excellent data reliability, and is responsible for performing communication between all cabinets.

[0004] Optical communication networks are responsible for signal transmission between each cabinet, and efforts have been made to build a safer optical communication network because it has the characteristics of fast communication speeds and can ensure communication stability with few external disturbances and distance restrictions.

[0005] As an example, Republic of Korea Patent Publication No. 10-2010-0125898 discloses a power plant control system optical communication network inspection device and method that enables inspection of an optical communication network without changing the existing optical communication network, thereby preventing the occurrence of costs due to changes in additional communication network configuration and the occurrence of delays due to work.

[0006] However, even in this case, there is a disadvantage in that the clock recovery used in the optical transceiver is complex and has a short lifespan, which can cause failure.

[0007] The purpose of the present invention is to provide a clock recovery device for an optical transceiver of a power plant control system (PCS) of a nuclear power plant, which can increase reliability and extend lifespan by simply implementing a clock recovery circuit in the optical transceiver of the power plant control system.

[0008] Another purpose of the present invention is to provide a clock recovery device for an optical transceiver of a nuclear power plant control system (PCS) that can smoothly perform reception of input data even when it is not synchronized with the transmission clock of the optical transceiver.

[0009] A clock recovery device for a nuclear power plant control system (PCS) optical transceiver according to the present invention may include a clock generation unit that generates a sampling clock for receiving input data, and a buffer that receives input data based on the generated sampling clock and transmits the received data to a decoder.

[0010] Here, the clock generation unit may include a multi-phase generator that delays a reference clock to generate four multi-phases, a first counter that performs counting for each multi-phase based on a 'HIGH' state of input data and outputs a high data extraction clock, a second counter that performs counting for each multi-phase based on a 'LOW' state of input data and outputs a low data extraction clock, and a mixer that mixes the output of the first counter and the output of the second counter to generate a sampling clock.

[0011] Additionally, the multiphase may include a first multiphase clock, a second multiphase clock, a third multiphase clock, and a fourth multiphase clock in 90 degree units.

[0012] Here, the first counter can start counting by multi-phase when the input data changes from 'low' to 'high' in the reset state.

[0013] Additionally, the first counter can be switched to a reset state when the input data changes from 'high' to 'low'.

[0014] Here, the high data extraction clock can output a clock pulse at the starting point of performing counting in the second multi-phase within the first counter.

[0015] Additionally, the second counter can start counting by multi-phase when the input data changes from 'high' to 'low' in the reset state.

[0016] Here, the second counter can be switched to a reset state when the input data changes from 'low' to 'high'.

[0017] Additionally, the raw data extraction clock can output a clock pulse at the starting point of the second multi-phase counting within the second counter.

[0018] Here, the sampling clock can be mixed by 'OR'ing the high data extraction clock and the low data extraction clock.

[0019] The clock recovery device for an optical transceiver of a power plant control system (PCS) of a nuclear power plant according to the present invention has the advantage of increasing reliability and extending the lifespan by simply implementing a clock recovery circuit in the optical transceiver of the power plant control system.

[0020] In addition, the clock recovery device for a nuclear power plant control system (PCS) optical transceiver according to the present invention has the advantage of being able to smoothly perform reception of input data even if it is not synchronized with the transmission clock of the optical transceiver.

[0021] FIG. 1 is a block diagram showing a clock recovery device for a nuclear power plant control system (PCS) optical transceiver according to one embodiment of the present invention.

[0022] Fig. 2 is a timing diagram showing signals inside the clock generation unit of Fig. 1.

[0023] Hereinafter, specific embodiments for carrying out the present invention will be described with reference to the attached drawings.

[0024] When describing the present invention, terms such as "first" and "second" may be used to describe various components. However, the components may not be limited by these terms. The terms are used solely to distinguish one component from another. For example, without departing from the scope of the present invention, the first component could be referred to as the "second component," and similarly, the second component could also be referred to as the "first component."

[0025] When it is said that a component is connected or connected to another component, it can be understood that it may be directly connected or connected to that other component, but there may also be other components in between.

[0026] The terminology used in this specification is for the purpose of describing specific embodiments only and is not intended to limit the present invention. Singular expressions may include plural expressions unless the context clearly dictates otherwise.

[0027] In this specification, terms such as “include” or “have” are intended to indicate the presence of a feature, number, step, operation, component, part, or combination thereof described in the specification, and can be understood as not excluding in advance the possibility of the presence or addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof.

[0028] Additionally, the shape and size of elements in the drawing may be exaggerated for clearer explanation.

[0029] Hereinafter, a clock recovery device for an optical transceiver of a nuclear power plant control system (PCS) according to the present invention will be described in detail with reference to the attached drawings.

[0030]

[0031] FIG. 1 is a block diagram showing a clock recovery device for a nuclear power plant control system (PCS) optical transceiver according to one embodiment of the present invention, and FIG. 2 is a detailed timing diagram for explaining FIG. 1 in detail.

[0032] Hereinafter, a clock recovery device for a nuclear power plant control system (PCS) optical transceiver according to one embodiment of the present invention will be described with reference to FIGS. 1 and 2.

[0033] First, referring to FIG. 1, a clock recovery device for a nuclear power plant control system (PCS) optical transceiver according to one embodiment of the present invention comprises a clock generation unit (100) that generates a sampling clock for receiving input data, and a buffer (200) that receives input data based on the generated sampling clock and transmits the received data to a decoder (300).

[0034] Since the input data does not contain a clock signal, the clock signal must be extracted from the input data.

[0035] In particular, reliability, such as mean time between failures (MTBF), is very important for electronic circuits used in nuclear power plants. MTBF has the disadvantage of becoming shorter as the circuit becomes more complex, so it is necessary to extract a highly reliable clock signal using a simple circuit.

[0036] The commonly used PLL (Phase Locked Loop) has a disadvantage of a short MTBF due to its complex internal circuit, but the clock recovery device for an optical transceiver of a nuclear power plant control system (PCS) according to the present invention has the advantage of a long MTBF by being implemented using only a simple counter and gate.

[0037] To implement this, the clock generation unit (100) according to the present invention is composed of a multi-phase generator (110) that delays a reference clock to generate four multi-phases, a first counter (121) that performs counting for each multi-phase based on a 'HIGH' state of input data and outputs a high data extraction clock (HCLK), a second counter (122) that performs counting for each multi-phase based on a 'LOW' state of input data and outputs a low data extraction clock (LCLK), and a mixer (130) that mixes the output of the first counter (121) and the output of the second counter (122) to generate a sampling clock (SCLK).

[0038] That is, data can be restored by generating a clock corresponding to 'high' of input data in the first counter (121) and generating a clock corresponding to 'low' of input data in the second counter (122).

[0039] At this time, multiple input data can be used, for example, first input data (RX0) and second input data (RX1) can be received, and since the input data are synchronized, one of them can be used to generate a clock.

[0040] For example, based on the first input data (RX0), a high data extraction clock (HCLK) and a low data extraction clock (LCLK) are generated, and then a sampling clock (SCLK) is generated by combining them through 'OR' in a mixer (130), so that the first input data (RX0) can be sampled in the first buffer (210) to transmit the first reception data to the decoder (300), and the second input data (RX1) can be sampled in the second buffer (220) to transmit the second reception data to the decoder (300).

[0041] Therefore, the clock recovery device for a nuclear power plant control system (PCS) optical transceiver according to the present invention is implemented with a simple circuit and has the advantage of high reliability and long MTBF, which is described in detail in FIG. 2.

[0042]

[0043] Figure 2 is a timing diagram showing signals inside the clock generation unit (100) of Figure 1.

[0044] As can be seen in Fig. 2, the multi-phase includes a first multi-phase clock (CLK0), a second multi-phase clock (CLK1), a third multi-phase clock (CLK2), and a fourth multi-phase clock (CLK3) in 90-degree increments. That is, the first multi-phase clock (CLK0) may be a clock delayed by 0 degrees, the second multi-phase clock (CLK1) by 90 degrees, the third multi-phase clock (CLK2) by 180 degrees, and the fourth multi-phase clock (CLK3) by 270 degrees.

[0045] Here, the first counter (121) starts counting by multi-phase when the input data changes from 'low' to 'high' in the reset state, and switches to the reset state when it changes from 'high' to 'low'.

[0046] For example, when counting is performed on the first input data (RX0), it can be seen that it is reset at the first timing (T1) and counting starts from the fourth timing (T4).

[0047] Inside the first counter (121), a first multi-phase high counter (HC0), a second multi-phase high counter (HC1), a third multi-phase high counter (HC2), and a fourth multi-phase high counter (HC3) may be used, which perform counting using the first multi-phase clock (CLK0), the second multi-phase clock (CLK1), the third multi-phase clock (CLK2), and the fourth multi-phase clock (CLK3), respectively. When the first input data (RX0) becomes 'high' and counting starts, the timing at which counting is performed may all be different.

[0048] That is, it can be seen that the fourth multi-phase high counter (HC3) performs counting first at the fourth timing (T4), and after a 90-phase delay, the first multi-phase high counter (HC0) counts as 1 at the fifth timing (T5).

[0049] At this time, when the first input data (RX0) remains 'high', it can be seen that the fourth multi-phase high counter (HC3) starts counting with 2 first, and the first multi-phase high counter (HC0) counts with 2 second at the sixth timing (T6).

[0050] Here, the high data extraction clock (HCLK) is a clock pulse output at the starting point of performing counting in the second multi-phase within the first counter (121). For example, it can be seen that the high data extraction clock (HCLK) is output at the fifth timing (T5) and the sixth timing (T6).

[0051] Similarly, the second counter (122) starts counting by multi-phase when the input data changes from 'high' to 'low' in the reset state, and switches to the reset state when it changes from 'low' to 'high'.

[0052] For example, when counting is performed on the first input data (RX0), it can be seen that it is reset at the fourth timing (T4) and counting starts from the first timing (T1).

[0053] Inside the second counter (122), a first multi-phase low counter (LC0), a second multi-phase low counter (LC1), a third multi-phase low counter (LC2), and a fourth multi-phase low counter (LC3) may be used, which perform counting using the first multi-phase clock (CLK0), the second multi-phase clock (CLK1), the third multi-phase clock (CLK2), and the fourth multi-phase clock (CLK3), respectively. When the first input data (RX0) becomes 'low' and counting starts, the timing at which counting is performed may all be different.

[0054] That is, it can be seen that the 4th multi-phase local counter (LC3) performed counting first at the 1st timing (T1), and after a 90-phase delay, the 1st multi-phase local counter (LC0) counted as 1 at the 2nd timing (T2).

[0055] At this time, if the first input data (RX0) maintains 'low', it can be seen that the fourth multi-phase local counter (LC3) starts counting with 2 first, and the first multi-phase local counter (LC0) counts with 2 second at the third timing (T3).

[0056] Here, the raw data extraction clock (LCLK) is a clock pulse output at the starting point of performing counting in the second multi-phase within the second counter (122). For example, it can be seen that the raw data extraction clock (LCLK) is output at the second timing (T2) and the third timing (T3).

[0057] Additionally, a sampling clock (SCLK) can be generated by ORing a high data extraction clock (HCLK) and a low data extraction clock (LCLK) in a mixer (130).

[0058]

[0059] As described above, the clock recovery device for an optical transceiver of a power plant control system (PCS) of a nuclear power plant according to the present invention has the advantage of increasing reliability and extending lifespan by simply implementing a clock recovery circuit in the optical transceiver of the power plant control system, and also has the advantage of smoothly performing reception of input data even if it is not synchronized with the transmission clock of the optical transceiver.

[0060]

[0061] Those skilled in the art will appreciate that the various illustrative logical blocks, modules, processors, means, circuits, and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, various forms of programs or design code (referred to herein, for convenience, as software), or a combination of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the overall system. Those skilled in the art may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.

[0062] The description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments without departing from the scope of the present invention. Therefore, the present invention is not intended to be limited to the embodiments disclosed herein, but is to be construed in the broadest scope consistent with the principles and novel features disclosed herein.

[0063] The present invention relates to a clock recovery device for an optical transceiver of a power plant control system (PCS) of a nuclear power plant, and can be used in the optical transceiver of a power plant control system (PCS) of a nuclear power plant.

Claims

1. A clock generation unit that generates a sampling clock for receiving input data; and A clock recovery device for an optical transceiver of a nuclear power plant control system (PCS), comprising a buffer that receives the input data based on the generated sampling clock and transmits it to a decoder.

2. In paragraph 1, The above clock generation unit is a multi-phase generator that delays a reference clock to generate four multi-phases; A first counter that performs counting for each multi-phase based on the 'HIGH' state of the above input data and outputs a high data extraction clock; A second counter that performs counting for each multi-phase based on the 'LOW' state of the above input data and outputs a low data extraction clock; and A clock recovery device for a nuclear power plant control system (PCS) optical transceiver, characterized by including a mixer that generates a sampling clock by mixing the output of the first counter and the output of the second counter.

3. In paragraph 2, A clock recovery device for an optical transceiver of a nuclear power plant control system (PCS), characterized in that the above multi-phase includes a first multi-phase clock, a second multi-phase clock, a third multi-phase clock, and a fourth multi-phase clock in 90 degree units.

4. In paragraph 3, A clock recovery device for a nuclear power plant control system (PCS) optical transceiver, characterized in that the first counter starts counting for each multi-phase when the input data changes from 'low' to 'high' in a reset state.

5. In paragraph 4, A clock recovery device for a nuclear power plant control system (PCS) optical transceiver, characterized in that the first counter is switched to a reset state when the input data changes from 'high' to 'low'.

6. In paragraph 5, A clock recovery device for a nuclear power plant control system (PCS) optical transceiver, characterized in that the high data extraction clock outputs a clock pulse at the starting point of performing counting as the second among the multi-phases in the first counter.

7. In paragraph 6, A clock recovery device for a nuclear power plant control system (PCS) optical transceiver, characterized in that the second counter starts counting for each multi-phase when the input data changes from 'high' to 'low' in a reset state.

8. In paragraph 7, A clock recovery device for a nuclear power plant control system (PCS) optical transceiver, characterized in that the second counter is switched to a reset state when the input data changes from 'low' to 'high'.

9. In paragraph 8, A clock recovery device for a nuclear power plant control system (PCS) optical transceiver, characterized in that the above raw data extraction clock outputs a clock pulse at the starting point where counting is performed for the second time among the multi-phases in the second counter.

10. In paragraph 9, A clock recovery device for an optical transceiver of a nuclear power plant control system (PCS), characterized in that the sampling clock is a clock that mixes the high data extraction clock and the low data extraction clock as an 'OR'.

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