Display panel and display apparatus

Abstract

The present application provides a display panel and a display apparatus. The display panel comprises a substrate and a driving circuit layer. The driving circuit layer comprises a plurality of pixel driving circuits. A shielding portion is provided on the side of a light-emitting control signal line distant from the substrate. A first connecting portion is provided on the side of the shielding portion distant from the light-emitting control signal line. The orthographic projection of the portion of the first connecting portion overlapping the light-emitting control signal line on the shielding portion is located in the shielding portion.

Description

Display panel and display device

[0001] The present application claims priority to the Chinese patent application No. 202411230731.5, filed on September 3, 2024, the entire contents of which are incorporated herein by reference. TECHNICAL FIELD

[0002] The present application relates to the technical field of display, in particular to a display panel and a display device. BACKGROUND

[0003] Organic Light-Emitting Diode (OLED) display technology is a new type of display technology, which has gradually attracted people's attention due to its unique advantages such as low power consumption, high saturation, fast response time and wide viewing angle, and occupies a certain position in the field of panel display technology. SUMMARY

[0004] At present, there is a parasitic capacitance between the node position connected by the driving transistor, the switching transistor and the light-emitting control transistor in the pixel driving circuit and the light-emitting control signal line. When the pulse width modulation (PWM) mode is turned on, the frequency of the light-emitting control signal increases, and the light-emitting control signal line will cause multiple couplings at the node position connected by the driving transistor, the switching transistor and the light-emitting control transistor, so that the voltage at the node position connected by the driving transistor, the switching transistor and the light-emitting control transistor changes, resulting in the problem of uneven brightness of the display panel.

[0005] Therefore, it is necessary to provide a display panel and a display device to improve this defect.

[0006] In a first aspect, embodiments of the present application provide a display panel, comprising a substrate and a driving circuit layer, the driving circuit layer is arranged on one side of the substrate, the driving circuit layer comprises a plurality of pixel driving circuits, and each pixel driving circuit comprises:

[0007] a switching transistor, a first electrode of the switching transistor is connected to a data signal line, a second electrode of the switching transistor is connected to a first node, and a switching gate of the switching transistor is connected to a first scan signal line;

[0008] a driving transistor, a first electrode of the driving transistor is connected to the first node, a second electrode of the driving transistor is connected to a second node, and a driving gate of the driving transistor is connected to a third node;

[0009] a first light emitting control transistor, a first electrode of the first light emitting control transistor being connected to a first power signal line, a second electrode of the first light emitting control transistor being connected to the first node, and a first light emitting control gate of the first light emitting control transistor being connected to a light emitting control signal line;

[0010] a first reset transistor, a first electrode of the first reset transistor being connected to a first reset signal line, a second electrode of the first reset transistor being connected to the first node, and a first reset gate of the first reset transistor being connected to a second scan signal line;

[0011] The driving circuit layer further comprises a first connecting portion and a shielding portion. The first connecting portion is connected between the second electrode of the first reset transistor and the first node. The light emitting control signal line is arranged on one side of the substrate. The shielding portion is arranged on a side of the light emitting control signal line away from the substrate. The first connecting portion is arranged on a side of the shielding portion away from the light emitting control signal line. A normal projection of the first connecting portion on the substrate partially overlaps a normal projection of the light emitting control signal line on the substrate. A normal projection of the portion of the first connecting portion overlapping the light emitting control signal line on the shielding portion is located in the shielding portion.

[0012] In a second aspect, embodiments of the present application also provide a display device. The display device comprises a display panel. The display panel comprises a substrate and a driving circuit layer. The driving circuit layer is arranged on one side of the substrate. The driving circuit layer comprises a plurality of pixel driving circuits. Each pixel driving circuit comprises:

[0013] a switch transistor, a first electrode of the switch transistor being connected to a data signal line, a second electrode of the switch transistor being connected to a first node, and a switch gate of the switch transistor being connected to a first scan signal line;

[0014] a driving transistor, a first electrode of the driving transistor being connected to the first node, a second electrode of the driving transistor being connected to a second node, and a driving gate of the driving transistor being connected to a third node;

[0015] a first light emitting control transistor, a first electrode of the first light emitting control transistor being connected to a first power signal line, a second electrode of the first light emitting control transistor being connected to the first node, and a first light emitting control gate of the first light emitting control transistor being connected to a light emitting control signal line;

[0016] a first reset transistor, a first electrode of the first reset transistor being connected to a first reset signal line, a second electrode of the first reset transistor being connected to the first node, and a first reset gate of the first reset transistor being connected to a second scan signal line;

[0017] The driving circuit layer further includes a first connecting portion and a shielding portion. The first connecting portion is connected between the second electrode of the first reset transistor and the first node. The light-emitting control signal line is arranged on one side of the substrate. The shielding portion is arranged on a side of the light-emitting control signal line away from the substrate. The first connecting portion is arranged on a side of the shielding portion away from the light-emitting control signal line. The first connecting portion is arranged in partial overlap with the light-emitting control signal line on the substrate. A projection of the first connecting portion on the shielding portion is located in the shielding portion. BRIEF DESCRIPTION OF DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the embodiments, the following will briefly introduce the drawings needed to be used in the embodiments. Obviously, the drawings in the following description only disclose some of the embodiments, and for those skilled in the art, other drawings can also be obtained from these drawings without creative effort.

[0019] FIG. 1 is a circuit diagram of a pixel driving circuit in a display panel according to an embodiment of the present application;

[0020] FIG. 2 is a schematic diagram of a film layer structure of a display panel according to an embodiment of the present application;

[0021] FIG. 3 is a film layer diagram of a first active layer in a display panel according to an embodiment of the present application;

[0022] FIG. 4 is a film layer diagram of a first gate layer in a display panel according to an embodiment of the present application;

[0023] FIG. 5 is a laminated diagram of the first active layer and the first gate layer in a display panel according to an embodiment of the present application;

[0024] FIG. 6 is a film layer diagram of an oxide semiconductor layer in a display panel according to an embodiment of the present application;

[0025] FIG. 7 is a laminated diagram of the first active layer, the first gate layer and the oxide semiconductor layer in a display panel according to an embodiment of the present application;

[0026] FIG. 8 is a film layer diagram of a second gate layer in a display panel according to an embodiment of the present application;

[0027] FIG. 9 is a laminated diagram of the first active layer, the first gate layer, the oxide semiconductor layer and the second gate layer in a display panel according to an embodiment of the present application;

[0028] FIG. 10 is a schematic diagram of an opening in a display panel according to an embodiment of the present application;

[0029] FIG. 11 is a film layer diagram of a first source-drain layer in a display panel according to an embodiment of the present application;

[0030] FIG. 12 is a stack diagram of a first active layer, a first gate layer, an oxide semiconductor layer, a second gate layer and a first source-drain layer in the display panel of the present application;

[0031] FIG. 13 is a structural schematic diagram of a display device provided by an embodiment of the present application.

[0032] Reference signs:

[0033] 1, substrate;

[0034] 2, drive circuit layer; 201, barrier layer; 2011, first barrier layer; 2012, second barrier layer; 202, shielding layer; 203, buffer layer; 204, first active layer; 2041, first active part; 205, first gate insulating layer; 206, first gate layer; 207, first interlayer dielectric layer; 208, oxide semiconductor layer; 209, second gate insulating layer; 210, second gate layer; 211, second interlayer dielectric layer; 212, first source-drain layer; 213, first planarization layer; 214, second source-drain layer; 215, second planarization layer;

[0035] 3, light emitting device layer; 301, anode layer; 302, pixel definition layer; 303, spacer layer;

[0036] T1, drive transistor; T2, switch transistor; T3, compensation transistor; T4, second reset transistor; T5, first light emitting control transistor; T6, second light emitting control transistor; T7, third reset transistor; T8, first reset transistor; Cst, storage capacitor; Cboost, boost capacitor;

[0037] Pscan1, first scan signal line; Pscan2, second scan signal line; Nscan1, third scan signal line; Nscan2, fourth scan signal line; VDD, first power signal line; VSS, second power signal line; Vi1, first reset signal line; Vi-Gate, second reset signal line; EM, light emitting control signal line; Vi-Ano, third reset signal line.

[0038] 1000, display device; 100, display panel; 200, housing. Embodiments of the present application

[0039] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application.

[0040] In the description of the present application, it needs to be understood that the terms "upper", "lower" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the purpose of facilitating the description of the present application and simplifying the description, and do not indicate or imply that the devices or elements indicated must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present application. In addition, the terms "first", "second" are only for the purpose of description, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the technical features indicated. Therefore, the features defined as "first", "second" can explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of "a plurality of" is two or more, unless otherwise specifically limited.

[0041] The present application can repeatedly refer to numbers and / or letters in different embodiments. Such repetition is for the purpose of simplification and clarity, and in itself does not indicate the relationship between the various embodiments and / or arrangements discussed.

[0042] Embodiments of the present application provide a display panel and a display device, which can improve the uniformity of brightness of the display panel.

[0043] In order to achieve the above-mentioned purpose, embodiments of the present application provide a display panel, comprising a substrate and a driving circuit layer, the driving circuit layer is arranged on one side of the substrate, the driving circuit layer comprises a plurality of pixel driving circuits, the pixel driving circuit comprises:

[0044] a switching transistor, a first electrode of the switching transistor is connected to a data signal line, a second electrode of the switching transistor is connected to a first node, and a switching gate of the switching transistor is connected to a first scan signal line;

[0045] a driving transistor, a first electrode of the driving transistor is connected to the first node, a second electrode of the driving transistor is connected to a second node, and a driving gate of the driving transistor is connected to a third node;

[0046] a first light-emitting control transistor, a first electrode of the first light-emitting control transistor is connected to a first power supply signal line, a second electrode of the first light-emitting control transistor is connected to the first node, and a first light-emitting control gate of the first light-emitting control transistor is connected to a light-emitting control signal line;

[0047] a first reset transistor, a first electrode of the first reset transistor is connected to a first reset signal line, a second electrode of the first reset transistor is connected to the first node, and a first reset gate of the first reset transistor is connected to a second scan signal line;

[0048] The driving circuit layer further includes a first connecting part and a shielding part, the first connecting part is connected between the second electrode of the first reset transistor and the first node; the light-emitting control signal line is arranged on one side of the substrate, the shielding part is arranged on the side of the light-emitting control signal line away from the substrate, and the first connecting part is arranged on the side of the shielding part away from the light-emitting control signal line; the orthographic projection of the first connecting part on the substrate and the orthographic projection of the light-emitting control signal line on the substrate are partially overlapped, and the orthographic projection of the part of the first connecting part overlapping with the light-emitting control signal line on the shielding part is located in the shielding part.

[0049] Optionally, the shielding part is connected with the first power signal line.

[0050] Optionally, the driving circuit layer includes:

[0051] a first active layer arranged on one side of the substrate;

[0052] a first gate layer arranged on the side of the first active layer away from the substrate, the gate layer including the light-emitting control signal line;

[0053] an oxide semiconductor layer arranged on the side of the first gate layer away from the first active layer;

[0054] a second gate layer arranged on the side of the oxide semiconductor layer away from the first gate layer; and

[0055] a first source-drain layer arranged on the side of the second gate layer away from the oxide semiconductor layer;

[0056] The oxide semiconductor layer includes the shielding part, and the first source-drain layer includes the first connecting part.

[0057] Optionally, the pixel driving circuit further includes a storage capacitor, a first storage plate of the storage capacitor being connected to the third node, and a second storage plate of the storage capacitor being connected to the first power signal line.

[0058] The first gate layer includes a first storage plate, the oxide semiconductor layer includes a second storage plate, and the shielding part and the second storage plate are arranged continuously.

[0059] Optionally, the first scan signal line, the light-emitting control signal line and the second scan signal line are arranged in a first direction and are spaced apart in a second direction, the first direction being different from the second direction.

[0060] The second storage electrode plate is arranged on the substrate, and the normal projection of the second storage electrode plate on the substrate is arranged between the normal projection of the first scan signal line on the substrate and the normal projection of the light-emitting control signal line on the substrate. The normal projection of the shielding portion on the substrate is arranged on the side of the normal projection of the second storage electrode plate on the substrate close to the normal projection of the light-emitting control signal line on the substrate.

[0061] Optionally, the first connection portion includes a first sub-connection portion and a second sub-connection portion, the first sub-connection portion is arranged to extend along the first direction, the second sub-connection portion is arranged to extend along the second direction, the first sub-connection portion is connected between the second electrode of the first light-emitting control transistor and the second sub-connection portion, and the second sub-connection portion is connected between the first sub-connection portion and the second electrode of the first reset transistor.

[0062] Optionally, the normal projection of the first sub-connection portion on the substrate partially overlaps the normal projection of the second storage electrode plate on the substrate, a part of the normal projection of the second sub-connection portion on the substrate overlaps the normal projection of the second storage electrode plate on the substrate, and another part of the normal projection of the second sub-connection portion on the substrate overlaps the normal projection of the shielding portion on the substrate.

[0063] Optionally, the normal projection of the first connection portion on the substrate partially overlaps the normal projection of the first storage electrode plate on the substrate.

[0064] Optionally, the width of the shielding portion along the first direction is greater than the width of the second sub-connection portion along the first direction.

[0065] Optionally, the width of the shielding portion along the second direction is greater than the width of the light-emitting control signal line along the second direction.

[0066] Optionally, the pixel driving circuit further includes:

[0067] a compensation transistor, a first electrode of the compensation transistor is connected to the third node, a second electrode of the compensation transistor is connected to the second node, and a compensation gate of the compensation transistor is connected to a third scan signal line;

[0068] a second reset transistor, a first electrode of the second reset transistor is connected to a second reset signal line, a second electrode of the second reset transistor is connected to the third node, and a second reset gate of the second reset transistor is connected to a fourth scan signal line;

[0069] a second light emitting control transistor, a first electrode of the second light emitting control transistor is connected to the second node, a second electrode of the second light emitting control transistor is connected to a fourth node, and a second light emitting control gate of the second light emitting control transistor is connected to the light emitting control signal line;

[0070] a third reset transistor, a first electrode of the third reset transistor is connected to a third reset signal line, a second electrode of the third reset transistor is connected to the fourth node, and a second light emitting control gate of the third reset transistor is connected to the second scan signal line;

[0071] a boost capacitor, a first boost plate of the boost capacitor is connected to the third node, and a second boost plate of the boost capacitor is connected to the first scan signal line.

[0072] Embodiments of the present application also provide a display device, which comprises the display panel as described above.

[0073] In the display panel of the embodiments of the present application, the shielding portion is arranged on the side of the light emitting control signal line away from the substrate, the first connecting portion is arranged on the side of the shielding portion away from the light emitting control signal line, and the orthographic projection of the portion of the first connecting portion overlapping with the light emitting control signal line on the shielding portion is located in the shielding portion. In this way, the first connecting portion is spaced apart from the light emitting control signal line by the shielding portion, so as to reduce the parasitic capacitance between the light emitting control signal line and the first connecting portion, and the influence of the voltage change of the light emitting control signal line on the voltages of the first node and the third node of the pixel driving circuit is reduced, thereby the uniformity of the brightness of the display panel can be improved.

[0074] Embodiments of the present application provide a display panel, which is shown in combination with FIG. 1 and FIG. 2. FIG. 1 is a circuit diagram of a pixel driving circuit in the display panel provided by the embodiments of the present application, and FIG. 2 is a schematic diagram of the film layer structure of the display panel provided by the embodiments of the present application. The display panel 100 comprises a substrate 1 and a driving circuit layer 2. The driving circuit layer 2 is arranged on one side of the substrate 1. The driving circuit layer 2 comprises a plurality of pixel driving circuits 20. The display panel 100 further comprises a plurality of light emitting devices 21. Each pixel driving circuit 20 is electrically connected to a corresponding light emitting device 21.

[0075] In the embodiment of the present application, the pixel driving circuit 20 comprises a switch transistor T2, a driving transistor T1, a first light-emitting control transistor T5 and a first reset transistor T8. The first electrode of the switch transistor T2 is connected to the data signal line Data, the second electrode of the switch transistor T2 is connected to the first node A, and the switch gate of the switch transistor T2 is connected to the first scan signal line Pscan1. The first electrode of the driving transistor T1 is connected to the first node A, the second electrode of the driving transistor T1 is connected to the second node B, and the driving gate of the driving transistor T1 is connected to the third node Q. The first electrode of the first light-emitting control transistor T5 is connected to the first power supply signal line VDD, the second electrode of the first light-emitting control transistor T5 is connected to the first node A, and the first light-emitting control gate of the first light-emitting control transistor T5 is connected to the light-emitting control signal line EM. The first electrode of the first reset transistor T8 is connected to the first reset signal line Vi1, the second electrode of the first reset transistor T8 is connected to the first node A, and the first reset gate of the first reset transistor T8 is connected to the second scan signal line Pscan2.

[0076] In the embodiment of the present application, the driving circuit layer 2 further comprises a first connecting part and a shielding part. The first connecting part is connected between the second electrode of the first reset transistor T8 and the first node A. The light-emitting control signal line EM is arranged on one side of the substrate 1. The shielding part is arranged on the side of the light-emitting control signal line EM away from the substrate 1. The first connecting part is arranged on the side of the shielding part away from the light-emitting control signal line EM. The orthographic projection of the first connecting part on the substrate 1 partially overlaps the orthographic projection of the light-emitting control signal line EM on the substrate 1. The orthographic projection of the part of the first connecting part overlapping the light-emitting control signal line EM on the shielding part is located within the shielding part.

[0077] In the embodiment of the present application, the shielding part is arranged on the side of the light-emitting control signal line EM away from the substrate 1. The first connecting part is arranged on the side of the shielding part away from the light-emitting control signal line EM. The orthographic projection of the part of the first connecting part overlapping the light-emitting control signal line EM on the shielding part is located within the shielding part. In this way, the first connecting part is spaced apart from the light-emitting control signal line EM by the shielding part, so as to reduce the parasitic capacitance between the light-emitting control signal line EM and the first connecting part. In this way, the influence of the voltage change of the light-emitting control signal line EM on the voltages of the first node A and the third node Q of the pixel driving circuit is reduced, so that the uniformity of the brightness of the display panel can be improved.

[0078] In some embodiments, the light-emitting device 21 can be any one of a light-emitting diode, an organic light-emitting diode, a mini light-emitting diode, a micro light-emitting diode chip and other light sources.

[0079] In some embodiments, as shown in FIG. 1, the pixel driving circuit 20 includes a switch transistor T2, a driving transistor T1, a compensation transistor T3, a second reset transistor T4, a first light emitting control transistor T5, a second light emitting control transistor T6, a third reset transistor T7, a first reset transistor T8, a storage capacitor Cst, and a boost capacitor Cboost.

[0080] As shown in FIG. 1, a first electrode of the switch transistor T2 is connected to a data signal line Data, a second electrode of the switch transistor T2 is connected to a first node A, and a switch gate of the switch transistor T2 is connected to a first scan signal line Pscan1. A first electrode of the driving transistor T1 is connected to the first node A, a second electrode of the driving transistor T1 is connected to a second node B, and a driving gate of the driving transistor T1 is connected to a third node Q. A first electrode of the compensation transistor T3 is connected to the third node Q, a second electrode of the compensation transistor T3 is connected to the second node B, and a compensation gate of the compensation transistor T3 is connected to a third scan signal line Nscan1. A first electrode of the second reset transistor T4 is connected to a second reset signal line Vi-Gate, a second electrode of the second reset transistor T4 is connected to the third node Q, and a first reset gate of the second reset transistor T4 is connected to a fourth scan signal line Nscan2. A first electrode of the first light emitting control transistor T5 is connected to a first power signal line VDD, a second electrode of the first light emitting control transistor T5 is connected to the first node A, and a first light emitting control gate of the first light emitting control transistor T5 is connected to a light emitting control signal line EM. A first electrode of the second light emitting control transistor T6 is connected to the second node B, a second electrode of the second light emitting control transistor T6 is connected to a fourth node C, and a second light emitting control gate of the second light emitting control transistor T6 is connected to the light emitting control signal line EM. A first electrode of the third reset transistor T7 is connected to a third reset signal line Vi-Ano, a second electrode of the third reset transistor T7 is connected to the fourth node C, and a third reset gate of the third reset transistor T7 is connected to a second scan signal line Pscan2. A first electrode of the first reset transistor T8 is connected to a first reset signal line Vi1, a second electrode of the first reset transistor T8 is connected to the first node A, and a first reset gate of the first reset transistor T8 is connected to the second scan signal line Pscan2. A first storage plate of the storage capacitor Cst is connected to the first power signal line VDD, and a second storage plate of the storage capacitor Cst is connected to the third node Q. A first boost plate of the boost capacitor Cboost is connected to the first scan signal line Pscan1, and a second boost plate of the boost capacitor Cboost is connected to the third node Q. An anode of the light emitting device 21 is connected to the fourth node C, and a cathode of the light emitting device 21 is connected to a second power signal line VSS.

[0081] In the embodiments of the present application, the first source signal line VDD is a direct-current high-voltage power signal line, and the first power signal line VDD is used to provide a constant-voltage high-level signal to the pixel driving circuit 20. The second power signal line VSS is a direct-current low-voltage power signal line, and the second power signal line VSS is used to provide a constant-voltage low-level signal to the pixel driving circuit 20.

[0082] In the embodiments of the present application, the driving transistor T1, the switching transistor T2, the first light-emitting control transistor T5, the second light-emitting control transistor T6, the third reset transistor T7, and the first reset transistor T8 can be one of a P-type transistor and an N-type transistor, and the compensation transistor T3 and the second reset transistor T4 can be the other one of a P-type transistor and an N-type transistor. The present application is described by taking the driving transistor T1, the switching transistor T2, the first light-emitting control transistor T5, the second light-emitting control transistor T6, the third reset transistor T7, and the first reset transistor T8 as P-type transistors, and the compensation transistor T3 and the second reset transistor T4 as N-type transistors as an example.

[0083] It should be noted that in the embodiments of the present application, the first electrode of the transistor is one of the source and the drain, and the second electrode is the other one of the source and the drain, and the first electrode and the second electrode of each transistor can be the same or different.

[0084] It should also be noted that in the following embodiments, the angle between the first direction X and the second direction Y is greater than 0° and less than or equal to 90°. For example, the first direction X is the horizontal direction, and the second direction Y is the vertical direction.

[0085] In some embodiments, the shielding portion is connected to the first power signal line VDD. The connection of the shielding portion to the first power signal line VDD can mean that the shielding portion is directly connected to the first power signal line VDD, or that the shielding portion is connected to the first power signal line VDD through other conductive traces. In this way, the shielding portion can be connected to the direct-current high-voltage power signal. Since the direct-current high-voltage power signal transmitted by the first power signal line VDD has high stability, the shielding portion connected to the direct-current high-voltage power signal can be used to shield the high-frequency light-emitting control signal transmitted by the light-emitting control signal line EM, thereby effectively reducing the coupling capacitance between the first node A and the light-emitting control signal line EM.

[0086] In actual applications, the shielding portion can not only be connected to the first power signal line VDD, but also be connected to the second reset signal line Vi-Gate that transmits a direct-current signal. In this way, the coupling capacitance between the first node A and the light-emitting control signal line EM can also be effectively reduced.

[0087] The film layer structure of the pixel driving circuit of the present application is described below with respect to the circuit structure shown in FIG. 1.

[0088] In some embodiments, the display panel includes a substrate 1, a first gate layer 206, an oxide semiconductor layer 208, a second gate layer 210, and a first source-drain layer 212. The first gate layer 206 is disposed on one side of the substrate 1, and the gate layer 206 includes an emission control signal line EM. The oxide semiconductor layer 208 is disposed on a side of the first gate layer 206 away from the substrate 1, the second gate layer 210 is disposed on a side of the oxide semiconductor layer 208 away from the first gate layer 206, the first source-drain layer 212 is disposed on a side of the second gate layer 210 away from the oxide semiconductor layer 208, the oxide semiconductor layer 208 includes a shielding portion, and the first source-drain layer 212 includes a first connecting portion.

[0089] As shown in FIG. 2, the display panel includes a substrate 1, a barrier layer 201 disposed on the substrate 1, a shielding layer 202 disposed on the barrier layer 201, a buffer layer 203 disposed on the shielding layer 202, a first active layer 204 disposed on the buffer layer 203, a first gate insulating layer 205 disposed on the first active layer 204, a first gate layer 206 disposed on the first gate insulating layer 205, a first interlayer dielectric layer 207 disposed on the first gate layer 206, an oxide semiconductor layer 208 disposed on the first interlayer dielectric layer 207, a second gate insulating layer 209 disposed on the oxide semiconductor layer 208, a second gate layer 210 disposed on the second gate insulating layer 209, a second interlayer dielectric layer 211 disposed on the second gate layer 210, a first source-drain layer 212 disposed on the second interlayer dielectric layer 211, a first planarization layer 213 disposed on the first source-drain layer 212, a second source-drain layer 214 disposed on the first planarization layer 213, and a second planarization layer 215 disposed on the second source-drain layer 214.

[0090] As shown in FIG. 2, the barrier layer 201 is disposed on the substrate 1, and the buffer layer 203 is disposed on the barrier layer 201. The barrier layer 201 and the buffer layer 203 are used to isolate the shielding layer 202 and the upper metal material. The barrier layer 201 and the buffer layer 203 can each be a single-layer structure or a stacked structure formed of at least one of silicon nitride, silicon oxide, and silicon oxynitride.

[0091] In some embodiments, as shown in FIG. 2, the barrier layer 201 is a stacked structure formed by stacking a first barrier layer 2011 and a second barrier layer 2012. The first barrier layer 2011 is made of one of silicon nitride and silicon oxide, the second barrier layer 2012 is made of the other of silicon nitride and silicon oxide, and the shielding layer 202 is disposed between the first barrier layer 2011 and the second barrier layer 2012.

[0092] The first active layer 204 is disposed on the surface of the buffer layer 203 away from the barrier layer 201, and the material of the first active layer 204 includes a silicon semiconductor material, which can be amorphous silicon or low-temperature polysilicon.

[0093] The first gate insulating layer 205 is disposed on the surface of the first active layer 204 away from the buffer layer 203, the first interlayer dielectric layer 207 is disposed on the surface of the first gate layer 206 away from the first gate insulating layer 205, the second gate insulating layer 209 is disposed on the surface of the oxide semiconductor layer 208 away from the first interlayer dielectric layer 207, and the second interlayer dielectric layer 211 is disposed on the surface of the second gate layer 210 away from the second gate insulating layer 209. The first gate insulating layer 205, the first interlayer dielectric layer 207, the second gate insulating layer 209, and the second interlayer dielectric layer 211 can be a single-layer structure or a stacked-layer structure formed by at least one of silicon nitride, silicon oxide, and silicon oxynitride.

[0094] In the embodiment of the present application, the first gate insulating layer 205 and the second gate insulating layer 209 are a single-layer structure formed by silicon oxide material, the first interlayer dielectric layer 207 and the second interlayer dielectric layer 211 are a stacked-layer structure formed by silicon oxide and silicon nitride material, and the silicon nitride material layer is located on the side of the silicon oxide material layer away from the oxide semiconductor layer 208.

[0095] The first gate layer 206 is disposed on the surface of the first gate insulating layer 205 away from the first active layer 204, the second gate layer 210 is disposed on the surface of the second gate insulating layer 209 away from the oxide semiconductor layer 208, the first source-drain layer 212 is disposed on the surface of the second interlayer dielectric layer 211 away from the second gate layer 210, and the second source-drain layer 214 is disposed on the surface of the first planar layer 213 away from the first source-drain layer 212. The first gate layer 206, the second gate layer 210, the first source-drain layer 212, and the second source-drain layer 214 are respectively disposed on the corresponding insulating layer or interlayer dielectric layer, and can be a single-layer structure formed by at least one of copper, molybdenum, titanium, aluminum, silver, etc., or a stacked-layer structure formed by at least two of the above metal materials.

[0096] The oxide semiconductor layer 208 is disposed on the surface of the first interlayer dielectric layer 207 away from the first gate layer 206, and the material of the oxide semiconductor layer 208 can be indium gallium zinc oxide.

[0097] As shown in Figure 2, the first planarization layer 213 is disposed on the first source-drain layer 212, and the second planarization layer 215 is disposed on the second source-drain layer 214. The materials of the first planarization layer 213 and the second planarization layer 215 can be at least one inorganic insulating material selected from silicon nitride, silicon oxide, or silicon oxynitride, or they can be organic insulating materials with leveling properties.

[0098] As shown in Figure 2, in an embodiment of this application, the display panel further includes a light-emitting device layer 3. The light-emitting device layer 3 is disposed on the side of the second planarization layer 215 away from the second source-drain layer 214. The light-emitting device layer 3 includes an anode layer 301 disposed on the second planarization layer 215, a pixel definition layer 302 disposed on the anode layer 301, a spacer layer 303 disposed on the pixel definition layer 302, a light-emitting material layer and a cathode layer (not shown in the figure) disposed on the pixel definition layer 302.

[0099] As shown in Figure 3, which is a film layer diagram of the first active layer in the display panel of this application, the first active layer 204 includes the driving active part T1A of the driving transistor T1, the switching active part T2A of the switching transistor T2, the first light-emitting control active part T5A of the first light-emitting control transistor T5, the second light-emitting control active part T6A of the second light-emitting control transistor T6, the third reset active part T7A of the third reset transistor T7, and the first reset active part T8A of the first reset transistor T8.

[0100] As shown in Figure 3, the driving active part T1A, the switching active part T2A, the first light-emitting control active part T5A, the second light-emitting control active part T6A, and the third reset active part T7A are connected to each other. The first reset active part T8A is separated from the other active parts. The switching active part T2A, the first light-emitting control active part T5A, and the first reset active part T8A are all elongated and extend along the second direction Y. The second light-emitting control active part T6A and the second reset active part T7A are both "L" shaped. The driving active part T1A is "U" shaped and is located between the first light-emitting control active part T5A and the second light-emitting control active part T6A.

[0101] As shown in Figure 3, the first terminal of the active switch TA2, the first terminal of the active drive T1A, and the first terminal of the first light-emitting control transistor T5A are all connected to the first connection point P1. The second terminal of the active drive T1A and the first terminal of the second light-emitting control active transistor T6A are connected to the second connection point P2. The second terminal of the first light-emitting control active transistor T5A and the second terminal of the second light-emitting control active transistor T6A are connected to the third connection point P3.

[0102] In the embodiment, the first connection point P1 is the first node A, the second connection point P2 is the second node B, and the third connection point P3 is a point where the anode of the light-emitting device 21 is located, i.e., the third connection point P3 is the fourth node C.

[0103] As shown in FIG. 4, the first gate layer 206 includes a driving gate T1G of a driving transistor T1, a switching gate T2G of a switching transistor T2, a first light-emitting control gate T5G of a first light-emitting control transistor T5, a second light-emitting control gate T6G of a second light-emitting control transistor T6, a third reset gate T7G of a third reset transistor T7, a first reset gate T8G of a first reset transistor T8, a first storage plate Cst1 of a storage capacitor Cst, a first boost plate Cboost1 of a boost capacitor Cboost, a first scan signal line Pscan1, a second scan signal line Pscan2, a light-emitting control signal line EM, and a third reset signal line Vi-Ano.

[0104] As shown in FIG. 4, the first scan signal line Pscan1, the second scan signal line Pscan2, the light-emitting control signal line EM, and the third reset signal line Vi-Ano are arranged along the first direction X, and are arranged at intervals along the second direction Y. The driving gate T1G and the first storage plate Cst1 are arranged between the first scan signal line Pscan1 and the light-emitting control signal line EM, the second scan signal line Pscan2 is arranged on a side of the light-emitting control signal line EM away from the driving gate T1G, and the third reset signal line Vi-Ano is arranged on a side of the second scan signal line Pscan2 away from the light-emitting control signal line EM. The first light-emitting control gate T5G and the second light-emitting control gate T6G are connected to the light-emitting control signal line EM, and the second reset gate T7G and the first reset gate T8G are connected to the first scan signal line Pscan1.

[0105] In the embodiment, the driving gate T1G can be reused as the first storage plate Cst1 of the storage capacitor Cst, the light-emitting control signal line EM can be directly used as the first light-emitting control gate T5G and the second light-emitting control gate T6G, the first scan signal line Pscan1 can be directly used as the switching gate T2G and the first boost plate Cboost1 of the boost capacitor Cboost, and the second scan signal line Pscan2 can be directly used as the second reset gate T7G and the first reset gate T8G.

[0106] In combination with FIG. 4 and FIG. 5, FIG. 5 is a layer stack diagram of the first active layer and the first gate layer in the display panel of the present application. The driving gate T1G partially overlaps the driving active part T1A, and the part where the driving gate T1G overlaps the driving active part T1A is the channel of the driving active part T1A. The switching gate T2G partially overlaps the switching active part T2A, and the part where the switching gate T2G overlaps the switching active part T2A is the channel of the switching active part T2A. The first light-emitting control gate T5G partially overlaps the first light-emitting control active part T5A, and the part where the first light-emitting control gate T5G overlaps the first light-emitting control active part T5A is the channel of the first light-emitting control active part T5A. The second light-emitting control gate T6G partially overlaps the second light-emitting control active part T6A, and the part where the second light-emitting control gate T6G overlaps the second light-emitting control active part T6A is the channel of the second light-emitting control active part T6A. The second reset gate T7G partially overlaps the second reset active part T7A, and the part where the second reset gate T7G overlaps the second reset active part T7A is the channel of the second reset active part T7A. The first reset gate T8G partially overlaps the first reset active part T8A, and the part where the first reset gate T8G overlaps the first reset active part T8A is the channel of the first reset active part T8A.

[0107] As shown in FIG. 6, FIG. 6 is a film layer diagram of the oxide semiconductor layer in the display panel of the present application. The oxide semiconductor layer 208 includes the compensation active part T3A of the compensation transistor T3, the second reset active part T4A of the second reset transistor T4, the second storage plate Cst2 of the storage capacitor Cst, the second boost plate Cboost2 of the boost capacitor Cboost, and the shielding part 2081.

[0108] As shown in FIG. 6, the compensation active part T13A and the second reset active part T4A are arranged along the second direction Y, the second storage plate Cst2 has a block structure, the shielding part 2081 has a block structure, and the top corners of the second storage plate Cst2 and the shielding part 2081 can be right angles or can be chamfered. In the same pixel driving circuit, the compensation active part T13A and the second reset active part T14 are arranged continuously, and the second storage plate Cst2 and the shielding part 2081 are arranged continuously. In the adjacent two pixel driving circuits, the second storage plate Cst2 of one pixel driving circuit is arranged continuously with the second storage plate Cst2 of the adjacent other pixel driving circuit.

[0109] In combination with FIG. 6 and FIG. 7, FIG. 7 is a stack diagram of the first active layer, the first gate layer and the oxide semiconductor layer in the display panel of the present application, the first storage plate Cst1 and the second storage plate Cst2 are arranged in an overlapping manner to form a storage capacitor Cst, the area of the second storage plate Cst2 is greater than the area of the first storage plate Cst1, and the orthographic projection of the first storage plate Cst1 on the substrate 1 is located within the orthographic projection of the second storage plate Cst2 on the substrate 1. The second storage plate Cst2 is provided with a first hole H1, the first hole H1 penetrates through the second storage plate Cst2 and exposes the underlying driving gate T1G. The portion of the first scan signal line Pscan1 overlapping with the second boost plate Cboost2 can be used as the first boost plate Cboost1, and the first boost plate Cboost1 and the second boost plate Cboost2 form a boost capacitor Cboost.

[0110] As shown in FIG. 7, the orthographic projection of the second storage plate Cst1 on the substrate 1 is arranged between the orthographic projection of the first scan signal line Pscan1 on the substrate 1 and the orthographic projection of the emission control signal line EM on the substrate 1, the orthographic projection of the shielding portion 2081 on the substrate 1 is arranged on the side of the orthographic projection of the second storage plate Cst2 on the substrate 1 close to the orthographic projection of the emission control signal line EM on the substrate 1, and the orthographic projection of the shielding portion 2081 on the substrate 1 partially overlaps with the orthographic projection of the emission control signal line EM on the substrate 1. The shielding portion 2081 extends from the side of the emission control signal line EM close to the first scan signal line Pscan1 to the side of the emission control signal line EM away from the first scan signal line Pscan1, and partially overlaps with the emission control signal line EM.

[0111] As shown in FIG. 8, FIG. 8 is a film layer diagram of the second gate layer in the display panel of the present application, the second gate layer 210 includes the compensation gate T3G of the compensation transistor T3, the second reset gate T4G of the second reset transistor T4, the third scan signal line Nscan1, the fourth scan signal line Nscan2 and the first reset signal line Vi1.

[0112] As shown in FIG. 8, the third scan signal line Nscan1, the fourth scan signal line Nscan2 and the first reset signal line Vi1 are arranged in the first direction X, the third scan signal line Nscan1, the fourth scan signal line Nscan2 and the first reset signal line Vi1 are arranged in the second direction Y, and the first scan signal line Nscan1 is arranged between the fourth scan signal line Nscan2 and the first reset signal line Vi1. The third scan signal line Nscan1 can be multiplexed as the compensation gate T3G of the compensation transistor T3, and the fourth scan signal line Nscan2 can be multiplexed as the second reset gate T4G of the second reset transistor T4.

[0113] As shown in FIGS. 8 and 9, FIG. 9 is a cross-sectional view of the first active layer, the first gate layer, the oxide semiconductor layer, and the second gate layer in the display panel of the present application. The compensation gate T3G partially overlaps the compensation active part T3A. The part where the compensation gate T3G overlaps the compensation active part T3A is the channel of the compensation active part T3A. The second reset gate T4G partially overlaps the second reset active part T4A. The part where the second reset gate T4G overlaps the second reset active part T4A is the channel of the second reset active part T4A.

[0114] As shown in FIG. 9, the orthogonal projection of the third scan signal line Nscan1 on the substrate 1 is arranged between the orthogonal projection of the first scan signal line Pscan1 on the substrate 1 and the orthogonal projection of the second storage plate Cst2 on the substrate 1. The orthogonal projection of the fourth scan signal line Nscan2 on the substrate 1 is arranged between the orthogonal projection of the first scan signal line Pscan1 on the substrate 1 and the orthogonal projection of the third reset signal line Vi-Ano on the substrate 1.

[0115] As shown in FIGS. 10 to 12, FIG. 10 is a schematic diagram of the opening in the display panel of the present application. FIG. 11 is a film layer diagram of the first source-drain layer in the display panel of the present application. FIG. 12 is a cross-sectional view of the first active layer, the first gate layer, the oxide semiconductor layer, the second gate layer, and the first source-drain layer in the display panel of the present application. The first source-drain layer 212 includes a first connecting part 2121. The first connecting part 2121 is connected between the second electrode of the first reset transistor T8 and the first node A.

[0116] As shown in FIG. 11, the first end of the first connecting part 2121 is connected to the first end of the first light-emitting control active part T5A, the first end of the switch active part T2A, and the first end of the driving active part T1A through the second hole H2. The second end of the first connecting part 2121 is connected to the first end of the first reset active part T8A through the third hole H3. The orthogonal projection of the first connecting part 2121 on the substrate 1 partially overlaps the orthogonal projection of the light-emitting control signal line EM on the substrate 1. The orthogonal projection of the part where the first connecting part 2121 overlaps the light-emitting control signal line EM on the shielding part 2081 is located inside the shielding part 2081.

[0117] In combination with FIG. 1 and FIG. 11, when the pulse width modulation mode is turned on, the frequency of the light emitting control signal transmitted by the light emitting control signal line EM becomes high. Since the first connection portion 2121 connected to the first node A partially overlaps the light emitting control signal line EM, the light emitting control signal line EM generates multiple couplings to the first connection portion 2121, which indirectly generates multiple couplings to the first node A, causing the potential of the first node A to change. Due to the gate-source parasitic capacitance of the driving transistor T1, the potential of the third node Q also changes, thereby directly affecting the current of the driving transistor T1, causing the uneven brightness of the display panel when displaying low gray scale images to be aggravated. In this embodiment, the shielding portion 2081 is additionally arranged between the first connection portion 2121 and the light emitting control signal line EM, and the first connection portion 2121 is spaced apart from the light emitting control signal line EM by the shielding portion 2081. In this way, the vertical coupling capacitance between the first connection portion 2121 and the light emitting control signal line EM is reduced, that is, the coupling capacitance between the first node A and the light emitting control signal line EM is reduced, and the proportion of the total capacitance of the coupling capacitance between the light emitting control signal line EM and the first node A at the first node A is reduced. In this way, the influence of the high frequency of the light emitting control signal on the potential of the first node A is reduced, and the voltage coupling of the first node A is prevented from affecting the potential of the third node Q, thereby improving the uniformity of the brightness of the display panel.

[0118] In this embodiment, the shielding portion 2081 and the second storage plate Cst2 are continuously arranged, and the shielding portion 2081 and the second storage plate Cst2 can be regarded as two parts of the same oxide semiconductor pattern. This embodiment can also be regarded as increasing the area of the second storage plate Cst2, so that the second storage plate Cst2 extends between the first connection portion 2121 and the light emitting control signal line EM. Since the second storage plate Cst2 is connected to the first power signal line VDD, the direct current high voltage power signal transmitted by the first power signal line VDD has high stability. In this way, the second storage plate Cst2 can shield the light emitting control signal with high frequency transmitted by the light emitting control signal line EM, thereby effectively reducing the vertical coupling capacitance and part of the lateral capacitance between the first node A and the light emitting control signal line EM.

[0119] In this embodiment, the second hole H2 penetrates the second interlayer dielectric layer 211, the second gate insulating layer 209, the first interlayer dielectric layer 207, and the first gate insulating layer 205, and the third hole H3 penetrates the second interlayer dielectric layer 211, the second gate insulating layer 209, the first interlayer dielectric layer 207, and the first gate insulating layer 205.

[0120] As shown in FIGS. 10-12, the first connecting portion 2121 includes a first sub-connecting portion 21211 and a second sub-connecting portion 21212. The first sub-connecting portion 21211 is arranged to extend along the first direction X, and the second sub-connecting portion 21212 is arranged to extend along the second direction Y. The first sub-connecting portion 21211 is connected between the second electrode of the first light-emitting control transistor T5 and the second sub-connecting portion 21212, and the second sub-connecting portion 21212 is connected between the first sub-connecting portion 21211 and the second electrode of the first reset transistor T8.

[0121] In this embodiment, the first electrode and the second electrode of the first light-emitting control transistor T5 can be formed by conductorizing the first end and the second end of the first light-emitting control active portion T5A. Therefore, the first end and the second end of the first light-emitting control active portion T5A can be regarded as the first electrode and the second electrode of the first light-emitting control transistor T5. The same applies to other transistors, which will not be described here again.

[0122] As shown in FIGS. 10-12, the first sub-connecting portion 21211 is arranged to partially overlap the normal projection of the second storage plate Cst2 on the substrate 1, and a part of the second sub-connecting portion 21212 is arranged to overlap the normal projection of the second storage plate Cst2 on the substrate 1, and another part of the second sub-connecting portion 21212 is arranged to overlap the normal projection of the shielding portion 2081 on the substrate 1.

[0123] In this embodiment, by increasing the area of the second storage plate Cst2 and changing the layout of the first connecting portion 2121, the overlapping area of the first connecting portion 2121 and the second storage plate Cst2 is increased. This not only makes the part of the first connecting portion 2121 overlapping the light-emitting control signal line EM overlap the shielding portion 2081, thereby reducing the vertical coupling capacitance between the first node A and the light-emitting control signal line EM, but also makes the part of the first connecting portion 2121 not overlapping the light-emitting control signal line EM overlap the shielding portion 2081 or the second storage plate Cst2, thereby reducing the lateral coupling capacitance between the first node A and the light-emitting control signal line EM, further reducing the coupling capacitance between the first node A and the light-emitting control signal line EM, and further improving the brightness uniformity of the display panel in the pulse width modulation mode.

[0124] In some embodiments, the normal projection of the first connecting portion 2121 on the substrate 1 partially overlaps the normal projection of the first storage plate on the substrate.

[0125] As shown in FIGS. 10-12, the first sub-connection portion 21211 of the first connection portion 2121 extends above the first storage plate Cst1 in the first direction X and partially overlaps the first storage plate Cst1 in the thickness direction, the second sub-connection portion 21212 extends above the first storage plate Cst1 in the second direction Y and partially overlaps the first storage plate Cst1 in the thickness direction, and the portion of the first connection portion 2121 that overlaps the first storage plate Cst1 also overlaps the second storage plate Cst2. In this way, by changing the path of the first connection portion 2121, the first connection portion 2121 can be routed more toward the first storage plate Cst1 and the second storage plate Cst2, thereby increasing the overlap area of the first connection portion 2121 with the second storage plate Cst2, and thus increasing the shielding area of the second storage plate Cst2 and the shielding portion 2081 for the first connection portion 2121, so as to further reduce the lateral coupling capacitance between the first node A and the light-emitting control signal line EM.

[0126] As shown in FIG. 12, the width of the shielding portion 2081 along the first direction X is greater than the width of the second sub-connection portion 21212 along the first direction X. The width of the second sub-connection portion 21212 along the first direction X is the line width of the second sub-connection portion 21212, and by making the width of the shielding portion 2081 along the first direction X greater than the line width of the second sub-connection portion 21212, the shielding portion 2081 can shield the areas on both sides of the second sub-connection portion 21212, so as to further reduce the lateral coupling capacitance between the first connection portion 2121 and the light-emitting control signal line EM.

[0127] As shown in FIGS. 7 and 12, the width of the shielding portion 2081 along the second direction Y is greater than the width of the light-emitting control signal line EM along the second direction Y. It should be noted that the width of the light-emitting control signal line EM along the second direction Y refers to the width of the portion of the light-emitting control signal line EM that overlaps the first connection portion 2121 along the second direction Y, i.e., the width of the shielding portion 2081 along the second direction Y is greater than the line width of the portion of the light-emitting control signal line EM that overlaps the first connection portion 2121, and in this way, the shielding portion 2081 can shield the areas on both sides of the light-emitting control signal line EM, so as to further reduce the lateral coupling capacitance between the first connection portion 2121 and the light-emitting control signal line EM.

[0128] As shown in FIGS. 10-12, the first source-drain layer 212 includes a second connection portion 2122, which is arranged in a strip shape along a direction intersecting the first direction X and the second direction Y. A first end of the second connection portion 2122 is connected to the drive gate T1G through a fourth hole H4, and a second end of the second connection portion 2122 is connected to a first end of the compensation active portion T3A, a first end of the second reset active portion T4A, and the first boost plate Cboost1 through a fifth hole H5.

[0129] In this embodiment, the fourth hole H4 penetrates the second interlayer dielectric layer 211, the second gate insulating layer 209, and the first interlayer dielectric layer 207, and the fifth hole H5 penetrates the second interlayer dielectric layer 211, the second gate insulating layer 209, the first interlayer dielectric layer 207, and the first gate insulating layer 205.

[0130] As shown in FIGS. 10-12, the first source-drain layer 212 includes a third connection portion 2123, which is arranged in a strip shape along the second direction Y. A first end of the third connection portion 2123 is connected to a second end of the compensation active portion T3A through a sixth hole H6, and a second end of the third connection portion 2123 is connected to a first end of the drive active portion T1A and a first end of the second light-emitting control active portion T6A through a seventh hole H7.

[0131] In this embodiment, the sixth hole penetrates the second interlayer dielectric layer 211 and the second gate insulating layer 209, and the seventh hole H7 penetrates the second interlayer dielectric layer 211, the second gate insulating layer 209, the first interlayer dielectric layer 207, and the first gate insulating layer 205.

[0132] As shown in FIGS. 10-12, the first source-drain layer 212 includes a second reset signal line Vi-Gate and a first power supply signal line VDD, which are arranged to extend along the first direction X. The first power supply signal line VDD is connected to the second storage plate Vst2 through an eighth hole H8, the first power supply signal line VDD is connected to a second end of the first light-emitting control active portion T5A through a ninth hole H9, and the second reset signal line Vi-Gate is connected to a second end of the second reset active portion T14A through a sixteenth hole H16.

[0133] In this embodiment, the eighth hole H8 penetrates the second interlayer dielectric layer 211 and the second gate insulating layer 209, and the ninth hole H9 penetrates the second interlayer dielectric layer 211, the second gate insulating layer 209, the first interlayer dielectric layer 207, and the first gate insulating layer 205.

[0134] As shown in FIGS. 10-12, the first source-drain layer 212 further includes a fourth connecting portion 2124, which is in a block structure, and the fourth connecting portion 2124 is in a rectangular shape, and the top corners of the rectangular shape can be right-angled or chamfered. The fourth connecting portion 2124 is connected to the second end of the switch active portion T2A through the tenth hole H10.

[0135] In this embodiment, the tenth hole H10 penetrates through the second interlayer dielectric layer 211, the second gate insulating layer 209, the first interlayer dielectric layer 207, and the first gate insulating layer 205.

[0136] As shown in FIGS. 10-12, the first source-drain layer 212 further includes a fifth connecting portion 2125 and a sixth connecting portion 2126, the fifth connecting portion 2125 is in a block structure, and the sixth connecting portion 2126 is in a long strip structure extending along the first direction X, and the fifth connecting portion 2125 is connected to the second end of the second light-emitting control active portion T6A and the first end of the third reset active portion T7A through the eleventh hole H11. The first end of the sixth connecting portion 2126 is connected to the second end of the third reset active portion T7A through the twelfth hole H12, and the second end of the sixth connecting portion 2126 is connected to the third reset signal line Vi-Ano through the thirteenth hole H13.

[0137] In this embodiment, the eleventh hole H11 penetrates through the second interlayer dielectric layer 211, the second gate insulating layer 209, the first interlayer dielectric layer 207, and the first gate insulating layer 205, the twelfth hole H12 penetrates through the second interlayer dielectric layer 211, the second gate insulating layer 209, the first interlayer dielectric layer 207, and the first gate insulating layer 205, and the thirteenth hole H13 penetrates through the second interlayer dielectric layer 211, the second gate insulating layer 209, and the first interlayer dielectric layer 207.

[0138] As shown in FIGS. 10-12, the first source-drain layer 212 further includes a seventh connecting portion 2127, which is in a long strip structure extending along the first direction X, and the first end of the seventh connecting portion 2127 is connected to the second end of the first reset active portion T8A through the fourteenth hole H14, and the second end of the seventh connecting portion 2127 is connected to the first reset signal line Vi1 through the fifteenth hole H15.

[0139] In this embodiment, the fourteenth hole H14 penetrates through the second interlayer dielectric layer 211, the second gate insulating layer 209, the first interlayer dielectric layer 207, and the first gate insulating layer 205, and the fifteenth hole H15 penetrates through the second interlayer dielectric layer 211.

[0140] In the embodiment of the present application, the second source-drain layer 214 includes a data signal line Data, which is arranged extending along the second direction Y and is arranged spaced apart along the first direction X.

[0141] In some embodiments, the first scan signal line Pscan1 is a first scan signal line Pscan(n), the second scan signal line Pscan2 is a second scan signal line Pscan(n-1), the third scan signal line Nscan1 is a third scan signal line Nscan(n), and the fourth scan signal line Nscan2 is a fourth scan signal line Nscan(n-5), where n is a positive integer.

[0142] Embodiments of the present application also provide a display device. In combination with FIG. 13, FIG. 13 is a structural schematic diagram of a display device provided by embodiments of the present application. The display device 1000 includes a display panel 100 and a housing 200. The display panel 100 is arranged on the housing 200. The display panel 100 can be any one of the display panels 100 provided by the above embodiments. The display device 1000 can be a mobile display device, such as a smart phone, a smart watch, a tablet computer, a notebook computer, or the like. The display device 1000 can also be a fixed display device, such as a television, a desktop computer, or the like.

[0143] The display panel provided by the embodiments of the present application includes a substrate and a driving circuit layer. The driving circuit layer includes a plurality of pixel driving circuits. Each pixel driving circuit includes a switching transistor, a driving transistor, a first light-emitting control transistor, and a first reset transistor. The shielding portion is arranged on the side of the light-emitting control signal line away from the substrate. The first connecting portion is arranged on the side of the shielding portion away from the light-emitting control signal line. The normal projection of the part of the first connecting portion overlapping with the light-emitting control signal line on the shielding portion is located in the shielding portion. In this way, the shielding portion is used to separate the first connecting portion and the light-emitting control signal line, so as to reduce the parasitic capacitance between the light-emitting control signal line and the first connecting portion. In this way, the influence of the voltage change of the light-emitting control signal line on the voltages of the first node and the third node of the pixel driving circuit is reduced, so that the uniformity of the brightness of the display panel can be improved.

[0144] To sum up, although the above preferred embodiments are disclosed in the present application, the above preferred embodiments are not used to limit the present application. Those skilled in the art can make various modifications and decorations without departing from the spirit and scope of the present application. Therefore, the protection scope of the present application is based on the scope defined by the claims.

Claims

1. A display panel, comprising a substrate and a drive circuit layer, the drive circuit layer being disposed on one side of the substrate, the drive circuit layer comprising a plurality of pixel drive circuits, each of the pixel drive circuits comprising: a switching transistor, a first electrode of the switching transistor being connected to a data signal line, a second electrode of the switching transistor being connected to a first node, a switching gate of the switching transistor being connected to a first scan signal line; a drive transistor, a first electrode of the drive transistor being connected to the first node, a second electrode of the drive transistor being connected to a second node, a drive gate of the drive transistor being connected to a third node; a first light emitting control transistor, a first electrode of the first light emitting control transistor being connected to a first power signal line, a second electrode of the first light emitting control transistor being connected to the first node, a first light emitting control gate of the first light emitting control transistor being connected to a light emitting control signal line; a first reset transistor, a first electrode of the first reset transistor being connected to a first reset signal line, a second electrode of the first reset transistor being connected to the first node, a first reset gate of the first reset transistor being connected to a second scan signal line; wherein the drive circuit layer further comprises a first connection portion and a shielding portion, the first connection portion being connected between the second electrode of the first reset transistor and the first node; the light emitting control signal line being disposed on one side of the substrate, the shielding portion being disposed on a side of the light emitting control signal line away from the substrate, the first connection portion being disposed on a side of the shielding portion away from the light emitting control signal line; a normal projection of the first connection portion on the substrate and a normal projection of the light emitting control signal line on the substrate partially overlap, a normal projection of a portion of the first connection portion overlapping the light emitting control signal line on the shielding portion being located within the shielding portion. The shielding portion is connected to the first power signal line. The drive circuit layer comprises: a first active layer disposed on one side of the substrate; a first gate layer disposed on a side of the first active layer away from the substrate, the gate layer comprising the light emitting control signal line; an oxide semiconductor layer disposed on a side of the first gate layer away from the first active layer; a second gate layer disposed on a side of the oxide semiconductor layer away from the first gate layer; and a first source-drain layer disposed on a side of the second gate layer away from the oxide semiconductor layer; wherein the oxide semiconductor layer comprises the shielding portion, and the first source-drain layer comprises the first connection portion. The pixel drive circuit further comprises a storage capacitor, a first storage plate of the storage capacitor being connected to the third node, a second storage plate of the storage capacitor being connected to the first power signal line; wherein the first gate layer comprises a first storage plate, the oxide semiconductor layer comprises a second storage plate, and the shielding portion and the second storage plate are continuously disposed. ​ ​ 2. The display panel of claim 1, wherein, ​ 3. The display panel of claim 1, wherein, ​ ​ ​ ​ ​ ​ ​ 4. The display panel of claim 3, wherein, ​ ​ 5. The display panel of claim 4, wherein, The first scan signal line, the light-emitting control signal line and the second scan signal line are arranged to extend along a first direction and are arranged to be spaced apart along a second direction, the first direction being different from the second direction; The second storage electrode plate is arranged to have a projection on the substrate between a projection of the first scan signal line on the substrate and a projection of the light-emitting control signal line on the substrate, and the shielding portion is arranged to have a projection on the substrate on a side of the projection of the second storage electrode plate on the substrate close to the projection of the light-emitting control signal line on the substrate.

6. The display panel of claim 5, wherein, The first connection portion includes a first sub-connection portion and a second sub-connection portion, the first sub-connection portion is arranged to extend along the first direction, the second sub-connection portion is arranged to extend along the second direction, the first sub-connection portion is connected between the second electrode of the first light-emitting control transistor and the second sub-connection portion, and the second sub-connection portion is connected between the first sub-connection portion and the second electrode of the first reset transistor.

7. The display panel of claim 6, wherein, The projection of the first sub-connection portion on the substrate is arranged to partially overlap the projection of the second storage electrode plate on the substrate, a part of the projection of the second sub-connection portion on the substrate is arranged to overlap the projection of the second storage electrode plate on the substrate, and another part of the projection of the second sub-connection portion on the substrate is arranged to overlap the projection of the shielding portion on the substrate.

8. The display panel of claim 7, wherein, The projection of the first connection portion on the substrate is arranged to partially overlap the projection of the first storage electrode plate on the substrate.

9. The display panel of claim 7, wherein, The width of the shielding portion along the first direction is greater than the width of the second sub-connection portion along the first direction.

10. The display panel of claim 7, wherein, The width of the shielding portion along the second direction is greater than the width of the light-emitting control signal line along the second direction.

11. The display panel of any one of claims 1 to 10, wherein, The pixel driving circuit further includes: a compensation transistor, a first electrode of the compensation transistor being connected to the third node, a second electrode of the compensation transistor being connected to the second node, and a compensation gate of the compensation transistor being connected to a third scan signal line; a second reset transistor, a first electrode of the second reset transistor being connected to a second reset signal line, a second electrode of the second reset transistor being connected to the third node, and a second reset gate of the second reset transistor being connected to a fourth scan signal line; a second light-emitting control transistor, a first electrode of the second light-emitting control transistor being connected to the second node, a second electrode of the second light-emitting control transistor being connected to a fourth node, and a second light-emitting control gate of the second light-emitting control transistor being connected to the light-emitting control signal line; a third reset transistor, a first electrode of the third reset transistor being connected to a third reset signal line, a second electrode of the third reset transistor being connected to the fourth node, and a second light-emitting control gate of the third reset transistor being connected to the second scan signal line; a boost capacitor, a first boost plate of the boost capacitor being connected to the third node, a second boost plate of the boost capacitor being connected to the first scan signal line.

12. A display device comprising a display panel, the display panel comprising a substrate and a drive circuit layer provided on one side of the substrate, the drive circuit layer comprising a plurality of pixel drive circuits, the pixel drive circuit comprising: a switching transistor, a first electrode of the switching transistor being connected to a data signal line, a second electrode of the switching transistor being connected to a first node, a switching gate of the switching transistor being connected to a first scan signal line; a drive transistor, a first electrode of the drive transistor being connected to the first node, a second electrode of the drive transistor being connected to a second node, a drive gate of the drive transistor being connected to a third node; a first light emission control transistor, a first electrode of the first light emission control transistor being connected to a first power supply signal line, a second electrode of the first light emission control transistor being connected to the first node, a first light emission control gate of the first light emission control transistor being connected to a light emission control signal line; a first reset transistor, a first electrode of the first reset transistor being connected to a first reset signal line, a second electrode of the first reset transistor being connected to the first node, a first reset gate of the first reset transistor being connected to a second scan signal line; wherein the drive circuit layer further comprises a first connection portion and a shielding portion, the first connection portion being connected between the second electrode of the first reset transistor and the first node; the light emission control signal line being provided on one side of the substrate, the shielding portion being provided on a side of the light emission control signal line away from the substrate, the first connection portion being provided on a side of the shielding portion away from the light emission control signal line; a normal projection of the first connection portion on the substrate partially overlaps with a normal projection of the light emission control signal line on the substrate, a normal projection of a portion of the first connection portion overlapping with the light emission control signal line on the shielding portion being located within the shielding portion.

13. The display device of claim 12, wherein, the shielding portion is connected to the first power supply signal line.

14. The display device of claim 12, wherein, the drive circuit layer comprises: a first active layer provided on one side of the substrate; a first gate layer provided on a side of the first active layer away from the substrate, the gate layer comprising the light emission control signal line; an oxide semiconductor layer provided on a side of the first gate layer away from the first active layer; a second gate layer provided on a side of the oxide semiconductor layer away from the first gate layer; and a first source-drain layer provided on a side of the second gate layer away from the oxide semiconductor layer; wherein the oxide semiconductor layer comprises the shielding portion, and the first source-drain layer comprises the first connection portion.

15. The display device of claim 14, wherein, the pixel drive circuit further comprises a storage capacitor, a first storage plate of the storage capacitor being connected to the third node, a second storage plate of the storage capacitor being connected to the first power supply signal line; The first gate layer includes a first storage plate, the oxide semiconductor layer includes a second storage plate, and the shielding portion is continuously provided with the second storage plate.

16. The display device of claim 15, wherein, The first scan signal line, the light emission control signal line, and the second scan signal line are provided along a first direction and are spaced apart along a second direction different from the first direction. A projection of the second storage plate on the substrate is disposed between a projection of the first scan signal line on the substrate and a projection of the light emission control signal line on the substrate, and a projection of the shielding portion on the substrate is disposed on a side of the projection of the second storage plate on the substrate close to the projection of the light emission control signal line on the substrate.

17. The display device of claim 16, wherein, The first connection portion includes a first sub-connection portion and a second sub-connection portion, the first sub-connection portion is provided along the first direction, the second sub-connection portion is provided along the second direction, the first sub-connection portion is connected between the second electrode of the first light emission control transistor and the second sub-connection portion, and the second sub-connection portion is connected between the first sub-connection portion and the second electrode of the first reset transistor.

18. The display device of claim 17, wherein, A projection of the first sub-connection portion on the substrate partially overlaps with a projection of the second storage plate on the substrate, a part of a projection of the second sub-connection portion on the substrate overlaps with the projection of the second storage plate on the substrate, and another part of the projection of the second sub-connection portion on the substrate overlaps with a projection of the shielding portion on the substrate.

19. The display device of claim 18, wherein, The first connection portion is partially overlapped with a projection of the first storage plate on the substrate.

20. The display device of claim 18, wherein, The width of the shielding portion along the first direction is greater than the width of the second sub-connection portion along the first direction.

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