Display panel and display device

Abstract

A display panel and a display device. The display panel comprises a driving circuit (100). The driving circuit (100) comprises N-stage shift registers (110). In each shift register (110), a first control part (10) is used for controlling a first output signal (SN_NEXT), and in a second control part (20), a control unit (21) receives at least the first output signal (SN_NEXT), a frequency control signal (SN_Ctrl), a first voltage signal (V1) inputted by a first voltage input end (2101), and a second voltage signal (V2) inputted by a second voltage input end (2102), and controls a second output signal (SN_OUT). In the second output signal (SN_OUT), the voltage of an effective pulse is the same as that of the first voltage signal (V1), and the voltage of an ineffective pulse is the same as that of the second voltage signal (V2). In a first voltage stabilizing unit (22), a first end is electrically connected to the control unit (21), and a second end receives a fixed potential signal and is electrically insulated from the first voltage input end (2101). The present invention can prevent an operating state of a pixel circuit from being affected by fluctuations generated when the second output signal (SN_OUT) outputs an effective pulse, and solves the problem of display defects such as a bright line or a dark line on the display panel.

Description

Display panel and display device

[0001] The present application claims priority to the Chinese patent application No. 202411259873.4, filed with the State Intellectual Property Office on September 9, 2024 and entitled "Display panel and display device", the whole content of which is incorporated herein by reference. TECHNICAL FIELD

[0002] Embodiments of the present application relate to the technical field of display, in particular to a display panel and a display device. BACKGROUND

[0003] With the continuous development of display technology, more and more electronic devices with display function are widely used in people's daily life and work, which brings great convenience to people's daily life and work.

[0004] The main component of electronic devices to realize display function is display panel. The current display panel has the function of partitioning and frequency dividing, that is, different regions of the display area can have different refresh frequencies, so as to reduce the refresh frequency of part of the region to reduce the power consumption of the panel. However, the display panel with the function of partitioning and frequency dividing will produce display abnormality problems such as dark line or bright line at the boundary of different partitions, which affects the uniformity of display. SUMMARY

[0005] The present application provides a display panel and a display device to solve the problem of dark line or bright line at the boundary of different partitions, avoid display abnormality and improve display quality.

[0006] In a first aspect, embodiments of the present application provide a display panel, comprising:

[0007] A driving circuit, the driving circuit comprising N-stage shift registers cascaded with each other, N≥2;

[0008] The shift register comprises:

[0009] A first control part and a second control part;

[0010] The first control part is configured to control a first output signal, the first output signal of the i-th shift register being an input signal of the j-th shift register, 1≤i≤N, 1≤j≤N;

[0011] The second control part comprises a control unit and a first voltage stabilizing unit;

[0012] The control unit receives at least a frequency control signal, a first voltage signal input from a first voltage input terminal, and a second voltage signal input from a second voltage input terminal, and controls a second output signal; a voltage corresponding to an effective pulse in the second output signal is the same as a voltage of the first voltage signal, and a voltage corresponding to an ineffective pulse in the second output signal is the same as a voltage of the second voltage signal.

[0013] The first end of the first voltage stabilizing unit is electrically connected to the control unit, and the second end receives a fixed potential signal; and the second end of the first voltage stabilizing unit is electrically insulated from the first voltage input terminal.

[0014] In a second aspect, the embodiment of the present application further provides a display device including the display panel according to any one of the embodiments of the present application.

[0015] The technical scheme of the embodiment of the present application sets the first control unit and the second control unit in the shift register, controls the first output signal by the first control unit, and makes the first output signal of the i-th shift register the input signal of the j-th shift register, so that the cascade of at least two first control units can be realized; at the same time, the control unit receives at least a frequency control signal, a first voltage signal input from a first voltage input terminal, and a second voltage signal input from a second voltage input terminal, controls a second output signal, so that the voltage corresponding to an effective pulse in the second output signal is the same as the voltage of the first voltage signal, and the voltage corresponding to an ineffective pulse in the second output signal is the same as the voltage of the second voltage signal; the transformation of the effective pulse and the ineffective pulse of the second output signal can be realized by the frequency control signal, so as to control the pixel circuit and realize the adjustment of the refresh frequency of different regions of the display panel. In addition, the first end of the first voltage stabilizing unit is electrically connected to the control unit, the second end receives a fixed potential signal, and the second end is electrically insulated from the first voltage input terminal; the potential of the node connected to the control unit in the first voltage stabilizing unit can be stabilized by the first voltage stabilizing unit, the working state of the control unit is maintained, the second output signal of the control unit in the effective pulse stage is prevented from being truncated and unable to output a complete effective pulse, the second end of the first voltage stabilizing unit is prevented from interfering with the first voltage signal of the first voltage input terminal, and then the fluctuation of the second output signal in the output of the effective pulse is prevented, the working state of the pixel circuit is affected, so as to ensure that the light emitting element corresponding to the pixel circuit can emit light according to the target brightness, the display panel is prevented from appearing in the form of bright lines or dark lines, and the display quality is ensured. BRIEF DESCRIPTION OF DRAWINGS

[0016] FIG. 1 is a structural schematic diagram of a display panel in the related art;

[0017] FIG. 2 is a structural schematic diagram of a driving circuit in the display panel shown in FIG. 1;

[0018] FIG. 3 is a structural schematic diagram of a pixel circuit in the display panel shown in FIG. 1;

[0019] Fig. 4 is a structural schematic diagram of a gate-on circuit in the driving circuit shown in Fig. 2;

[0020] Fig. 5 is a driving timing diagram of the driving circuit shown in Fig. 2;

[0021] Fig. 6 is a driving timing diagram of the display panel shown in Fig. 1;

[0022] Fig. 7 is a structural schematic diagram of a display panel according to an embodiment of the present application;

[0023] Fig. 8 is a structural schematic diagram of a driving circuit in the display panel shown in Fig. 7;

[0024] Fig. 9 is a structural schematic diagram of a shift register in the driving circuit shown in Fig. 8;

[0025] Fig. 10 is a driving timing diagram of the shift register in the driving circuit shown in Fig. 8;

[0026] Fig. 11 is another structural schematic diagram of the shift register in the driving circuit shown in Fig. 8;

[0027] Figs. 12 and 13 are still other structural schematic diagrams of the shift register in the driving circuit shown in Fig. 8;

[0028] Figs. 14 and 15 are yet other structural schematic diagrams of the shift register in the driving circuit shown in Fig. 8;

[0029] Figs. 16-18 are still further structural schematic diagrams of the shift register in the driving circuit shown in Fig. 8;

[0030] Fig. 19 is still another structural schematic diagram of the shift register in the driving circuit shown in Fig. 8;

[0031] Fig. 20 is still another structural schematic diagram of the shift register in the driving circuit shown in Fig. 8;

[0032] Fig. 21 is a driving timing diagram of the first control unit in the shift register shown in Fig. 20;

[0033] Figs. 22-26 are structural schematic diagrams of five other pixel circuits according to embodiments of the present application;

[0034] Fig. 27 is a driving timing diagram of the display panel shown in Fig. 7;

[0035] Fig. 28 is another driving timing diagram of the display panel shown in Fig. 7;

[0036] Fig. 29 is a structural schematic diagram of a display device according to an embodiment of the present application. DETAILED DESCRIPTION

[0037] The application will be described in further detail below with reference to the drawings and embodiments. It is to be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application. In addition, it is to be understood that the drawings show only those structures directly related to the present application and do not show all of the structures of the device.

[0038] The terms used in the embodiments of the present application are merely used for the purpose of describing particular embodiments and are not intended to limit the present application. It should be noted that the terms "upper", "lower", "left", "right", and the like described in the embodiments of the present application are described in the angle shown in the drawings, and should not be understood as limiting the embodiments of the present application. In addition, it should be understood in the context that when referring to an element being formed "on" or "under" another element, it can be directly formed "on" or "under" another element, or indirectly formed "on" or "under" another element through an intermediate element. The terms "first", "second", and the like are only for the purpose of description and do not represent any order, number or importance, but are only used to distinguish different components. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0039] The term "comprising" and its variants used in the present application are open-ended, i.e. "including but not limited to". The term "based on" is "at least partially based on". The term "one embodiment" means "at least one embodiment".

[0040] It should be noted that the concepts of "first", "second", and the like mentioned in the present application are only used to distinguish the corresponding content, and are not used to limit the order or mutual dependency.

[0041] It should be noted that the modification of "one" or "multiple" mentioned in the present application is illustrative and not limiting, and those skilled in the art should understand that unless otherwise explicitly indicated in the context, it should be understood as "one or more".

[0042] FIG. 1 is a structural schematic diagram of a display panel in the related art, FIG. 2 is a structural schematic diagram of a driving circuit in the display panel shown in FIG. 1, and FIG. 3 is a structural schematic diagram of a pixel circuit in the display panel shown in FIG. 1. Referring to FIGS. 1-3, in the related art, the display panel includes a display area AA and a non-display area NA, wherein the non-display area NA is provided with a driving circuit 100, the display area AA includes a plurality of pixel circuits 200 arranged in an array and light emitting elements 300 electrically connected one by one with the pixel circuits 200. The driving circuit 100 sequentially provides driving signals to each row of pixel circuits 200 through a scan signal line 400, and the pixel circuits 200 control the corresponding electrically connected light emitting elements 300 to light up according to the driving signals. In one display frame, the light emitting elements 300 of the display area AA are sequentially controlled to light up, and through the color matching of adjacent light emitting elements 300 of different colors, a specific pixel can be realized, and thus the whole picture display can be realized in a macroscopic view.

[0043] With continuous reference to FIGS. 1-3, in the related art, the driving circuit 100 in the non-display area NA is provided with a plurality of cascaded shift register circuits 10, and a gating circuit 20 is further provided for each shift register circuit 10. The output end of each gating circuit 20 is connected to at least one row of pixel circuits 200 through at least one scan signal line 400. The shift register circuit 10 is responsible for outputting a scan pulse signal SN_NEXT of each stage, and the gating circuit 20 is connected to the output end of the shift register circuit 10, used to receive the scan pulse signal SN_NEXT and selectively output the scan pulse signal SN_NEXT through the control of a control signal SN_Ctrl. Thus, the output frequency of the scan pulse signal SN_NEXT can be controlled through the control signal SN_Ctrl to change the refresh frequency of the corresponding connected pixel row, so that different refresh frequencies can be controlled for different partitions of the display panel, realizing the partition frequency division function of the display panel and adapting to the display power consumption demand of different display scenarios.

[0044] FIG. 4 is a structural schematic diagram of a gating circuit in the driving circuit shown in FIG. 2, and FIG. 5 is a driving timing diagram of the driving circuit shown in FIG. 2. Referring to FIGS. 1-5, in the related art, the gating circuit 20 is provided with a capacitor C1, and the two ends of the capacitor C1 are connected to a first node N1 and a VGH signal line, respectively. The remaining circuit elements and connection relationships are not described in detail, and can be specifically referred to FIG. 4.

[0045] Referring to the signal timing of the i-th stage shift register circuit in FIG. 5, in the first stage T1_i, the SN_NEXT_i signal is at a low level, the P-type channel transistor M1 is turned on, the SN_Ctrl signal is at a high level, the capacitor C1 is charged, and the first node N1 is charged to a high level; in the second stage T2_i, that is, after the SN_NEXT_i signal is pulled high from a low level, the N-type channel transistors M4 and M5 are turned on, the VGL signal is charged to the second node N2 by the transistors M4 and M5, the P-type channel transistor M2 is turned on, the N-type channel transistor M3 is turned off, and the VGH signal is output by the transistor M2 to form the SN_OUT signal, that is, in the second stage T2_i, after the N_NEXT signal is pulled high from a low level, the SN_OUT signal is also pulled high from a low level; in the third stage T3_i, when the SN_NEXT signal and the SN_OUT are both output at a high level, the SN_Ctrl is pulled low from a high level, because the transistor M1 is turned off by the SN_NEXT signal, the SN_Ctrl signal cannot be written to the first node N1, and the first node N1 is maintained at a high level because of the capacitor C1, therefore, the SN_OUT signal cannot be truncated and can still be output as a complete effective pulse.

[0046] Similarly, referring to the signal timing of the j-th stage shift register circuit in FIG. 5, in the first stage T1_j, when the SN_Ctrl signal is at a low level signal and the SN_NEXT_j signal is also at a low level signal, the P-type channel transistor M1 is turned on, the capacitor C1 is charged, and the first node N1 is charged to a low level. At this time, the N-type channel transistor M5 is turned off, the P-type channel transistor M7 is turned on, the VGH signal is charged to the second node N2 by the transistor M7, the P-type channel transistor M2 is turned off, the N-type channel transistor M3 is turned on, and the SN_OUT_j outputs the VGL signal by the transistor M3; in the second stage T2_j, that is, after the SN_NEXT_j signal is pulled high from a low level, the transistor M1 is turned off, the SN_Ctrl_j signal cannot be written to the first node N1, and the potential of the first node N1 is maintained at a low level because of the capacitor C1, the second node N2 is still maintained at a high level, and the SN_OUT_j outputs the VGL signal by the transistor M3; thus, in the third stage T3_j, after the SN_Ctrl_j signal is pulled high from a low level, the SN_OUT_j signal is still output as the VGL signal by the transistor M3.

[0047] As can be seen from the above, in the related art, when the strobe circuit 20 is designed to control the SN_NEXT signal output by using the SN_Ctrl signal, the capacitor C1 is used to maintain the potential of the first node N1, so as to avoid the SN_NEXT signal being truncated when the SN_Ctrl signal is pulled low from a high level or pulled high from a low level, and to ensure that the SN_OUT outputs a complete pulse signal.

[0048] However, as can be seen from the structure and working principle of the above driving circuit, one end of the capacitor C1 is connected to the first node N1 of the driving circuit 100, for stabilizing the voltage of the first node N1, and the other end is connected to the VGH signal line, for stabilizing by the fixed potential signal, preventing the capacitor C1 from being disturbed by other signals to cause the potential of the first node N1 to fluctuate. However, when the SN Ctrl signal is pulled low from high or pulled high from low, it will affect the switching state of the transistor M1, causing the level of the first node N1 to fluctuate, and then through the capacitor C1, causing the VGH signal to fluctuate, as shown in FIG. 5, which will cause the i-th level output signal SN OUT i to produce the same ripple as the SN Ctrl signal jumping trend during the process of outputting a complete high level pulse.

[0049] FIG. 6 is a driving timing diagram of the display panel shown in FIG. 1, with reference to FIGS. 3, 5 and 6, first of all, it needs to be pointed out that, as shown in FIG. 6, the pulse width ratio size of the control signal SN Ctrl, the output signal SN OUT and the first scan signal S1 is only used for example, which may deviate from the actual situation, which is not limited here. For any row of pixel circuits 200, the gate of a specific transistor therein can receive the output signal SN OUT of the corresponding driving circuit 100, that is, the output signal SN OUT of the driving circuit 100 controls the switching of the specific transistor, so as to control the working process of the pixel circuit 200. Taking the gate of the N-type channel transistor T5 in the i-th row of pixel circuits 200 receiving the output signal SN OUT of the i-th level driving circuit 100 as an example, that is, the first scan signal S1_i received by the transistor T5 in the i-th row of pixel circuits 200 is the output signal SN OUT of the i-th level driving circuit 100, in the data writing stage Ta_i of the pixel circuit 200 in the i-th row, the first scan signal S1_i inputs an effective pulse to the gate of the transistor T1, controlling the transistor T1 to turn on. At the same time, when the output signal SN OUT_i of the i-th level driving circuit 100 is in the high level stage, that is, in the effective level stage of the N-type channel transistor T3, the transistor T3 is turned on, and the data signal Vdata is written to the first node N1 of the pixel circuit 200 through the transistor T1, the transistor T2 and the transistor T3 in turn.

[0050] However, due to the existence of the ripple in the high level pulse of the output signal SN_OUT of a certain stage of the driving circuit 100, the conduction state of the transistor T3 is affected by the ripple, and when the ripple is in the low level pulse stage of the first scanning signal S1 of the pixel circuit 200 of the corresponding row, that is, in the data writing stage Ta of the pixel circuit 200, the data writing process of the pixel circuit 200 is interfered, so that the potential of the first node N1 of the pixel circuit 200 is too high or too low, thereby making the corresponding light emitting element 300 of the row of pixel circuits 200 driven by the driving circuit 100 too dark or too bright, and a dark line or a bright line appears. As shown in FIG. 6, the ripple is in the low level pulse stage of the first scanning signal S1_i+1 of the i+1 row of pixels, that is, the ripple is in the data writing stage Ta_i+1 of the i+1 row of pixels. At this time, the conduction state of the transistor T3 is affected by the ripple, which interferes with the data writing process of the pixel circuit 200, so that the first node N1 of the i+1 row of pixel circuits 200 writes more charge, and the potential is too high, thereby making the corresponding light emitting element 300 of the row of pixel circuits 200 driven by the driving circuit 100 too dark, and a dark line appears. Moreover, the generation of the ripple is caused by the high-low level jump of the SN_Ctrl signal in the driving circuit 100, and the SN_Ctrl signal is a control signal for the driving circuit 100 to output the effective pulse of SN_OUT to the pixel circuit 200, that is, the level jump of the SN_Ctrl signal means that the current stage of the selection circuit 20 is in the process of controlling the corresponding row of pixel circuits 200 to change the refresh frequency, so that the ripple is generated in the display driving period of the boundary area of the two different refresh frequency partitions. Therefore, due to the existence of the capacitor C1 in the driving circuit 100, the effective pulse in the output signal SN_OUT generates a ripple, which further causes the display panel with the partition frequency adjustment function to generate a dark line or a bright line in the boundary area of different partitions, and a display abnormality problem occurs, which seriously affects the display effect.

[0051] Based on the above technical problem, the embodiment of the present application provides a display panel, which comprises a driving circuit, the driving circuit comprising N stages of shift registers cascaded with each other, N≥2. The shift register comprises a first control part and a second control part, and the first control part is electrically connected with the second control part; the first control part is used for controlling a first output signal, and the first output signal of the i-th stage of shift registers is the input signal of the j-th stage of shift registers, 1≤i≤N, 1≤j≤N.

[0052] The second control unit comprises a control unit and a first voltage stabilizing unit; the control unit receives at least a frequency control signal, a first voltage signal input from a first voltage input end and a second voltage signal input from a second voltage input end, and controls a second output signal; the voltage corresponding to an effective pulse in the second output signal is the same as the voltage of the first voltage signal, and the voltage corresponding to an ineffective pulse in the second output signal is the same as the voltage of the second voltage signal; the first end of the first voltage stabilizing unit is electrically connected with the control unit, and the second end receives a fixed potential signal; and the second end of the first voltage stabilizing unit is electrically insulated from the first voltage input end.

[0053] In the technical solution, the first control unit controls the first output signal, and the first output signal of the i-th stage of the shift register is the input signal of the j-th stage of the shift register, so that the cascade of at least two stages of the first control unit is realized; the control unit receives at least the frequency control signal, the first voltage signal input from the first voltage input end and the second voltage signal input from the second voltage input end, and controls the second output signal, so that the voltage corresponding to the effective pulse in the second output signal is the same as the voltage of the first voltage signal, and the voltage corresponding to the ineffective pulse in the second output signal is the same as the voltage of the second voltage signal; the frequency control signal is used to realize the conversion of the effective pulse and the ineffective pulse of the second output signal, so as to control the pixel circuit and realize the adjustment of the refresh frequency of different regions of the display panel. In addition, the first end of the first voltage stabilizing unit is electrically connected with the control unit, the second end receives the fixed potential signal and is electrically insulated from the first voltage input end, so that the potential of the node connected with the control unit in the control unit is stabilized by the first voltage stabilizing unit, the working state of the control unit is maintained, the second output signal of the control unit is prevented from being cut off in the effective pulse stage and unable to output the complete effective pulse, the second end of the first voltage stabilizing unit is prevented from interfering with the first voltage signal of the first voltage input end, and the fluctuation of the second output signal when the effective pulse is output is prevented, so as to affect the working state of the pixel circuit, so that the light emitting element corresponding to the pixel circuit can emit light according to the target brightness, the display panel is prevented from appearing the display defect problem in the form of bright lines or dark lines, and the display quality is ensured.

[0054] The above is the core idea of the present application, and the technical solutions in the embodiments of the present application will be described clearly and completely in combination with the drawings in the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor are within the scope of protection of the present application.

[0055] Figure 7 is a structural schematic diagram of a display panel according to an embodiment of the present application, Figure 8 is a structural schematic diagram of a driving circuit in the display panel shown in Figure 7, Figure 9 is a structural schematic diagram of a shift register in the driving circuit shown in Figure 8, and Figure 10 is a driving timing diagram of the shift registers at various stages in the driving circuit shown in Figure 8. Referring to Figures 7-10, the display panel includes a driving circuit 100, which includes N-stage shift registers 110 cascaded with each other, where N≥2. The shift registers 110 include a first control part 10 and a second control part 20, and the first control part 10 is electrically connected to the second control part 20. The first control part 10 is configured to control a first output signal SN_NEXT, and the first output signal SN_NEXT of the i-th shift register 110 is an input signal of the j-th shift register 110, where 1≤i≤N and 1≤j≤N.

[0056] The second control part 20 includes a control unit 21 and a first voltage stabilizing unit 22. The control unit 21 receives at least a frequency control signal SN_Ctrl, a first voltage signal V1 input from a first voltage input end 2101, and a second voltage signal V2 input from a second voltage input end 2102, and controls a second output signal SN_OUT. The voltage corresponding to the effective pulse in the second output signal SN_OUT is the same as the voltage of the first voltage signal V1, and the voltage corresponding to the ineffective pulse in the second output signal SN_OUT is the same as the voltage of the second voltage signal V2. The first voltage stabilizing unit 22 has a first end electrically connected to the control unit 21 and a second end receiving a fixed potential signal. The second end of the first voltage stabilizing unit 22 is electrically insulated from the first voltage input end 2101.

[0057] As shown in FIG. 8 and FIG. 9, the driving circuit 100 of the display panel is provided with at least two stages of shift registers 110, and the at least two stages of shift registers 110 form a cascade, that is, the output signal of a certain stage of shift registers 110 is the input signal of a certain stage of shift registers 110 below. Exemplarily, the output signal of the upper stage of shift registers 110 adjacent to each other in FIG. 8 is the input signal of the lower stage of shift registers 110. In the embodiment of the present application, the shift registers 110 are provided with the first control unit 10 and the second control unit 20, wherein the first control unit 10 in each stage of shift registers 110 actually forms the cascade described above, that is, the first output signal SN_NEXT output by the first control unit 10 in a certain stage of shift registers 110 is the input signal of the first control unit 10 in a certain stage of shift registers 110 below. For the second control unit 20 in each stage of shift registers 110, as shown in FIG. 8 and FIG. 9, the output end of the first control unit 10 outputting the first output signal SN_NEXT is electrically connected to the second control unit 20, that is, on the basis of the first output signal SN_NEXT provided by the first control unit 10 as the control signal of the second control unit 20, the second output signal SN_OUT is simultaneously controlled by the frequency control signal SN_Ctrl additionally input, so as to realize the output of the second output signal SN_OUT. In addition, the second control unit 20 is provided with the first voltage input end 2101 and the second voltage input end 2102, and the voltage corresponding to the effective pulse in the second output signal SN_OUT is the same as the voltage of the first voltage signal V1, and the voltage corresponding to the ineffective pulse in the second output signal SN_OUT is the same as the voltage of the second voltage signal V2. The essence is to synchronously control the working state of the second control unit 20 by the frequency control signal SN_Ctrl, output the first voltage signal V1 and the second voltage signal V2 at different time periods, and constitute two opposite level pulses, that is, the effective pulse and the ineffective pulse, of the second output signal SN_OUT. It should be noted that the effective pulse refers to the level pulse that can drive the connected circuit structure, component and the like to open, and the ineffective pulse refers to the level pulse that controls the connected circuit structure, component and the like to turn off. For the second output signal SN_OUT, the effective pulse refers to the level pulse that can drive the connected component in the pixel circuit to open, and the ineffective pulse refers to the level pulse that cannot open the component. The level size of the effective pulse and the ineffective pulse has a relative concept, and the second output signal SN_OUT can have the high-level pulse as the effective pulse and the low-level pulse as the ineffective pulse, that is, as shown in FIG. 10, the first voltage V1 is the high-level signal, and the second voltage V2 is the low-level signal. The second output signal SN_OUT can also have the low-level pulse as the effective pulse and the high-level pulse as the ineffective pulse, and the first voltage V1 is the low-level signal, and the second voltage V2 is the high-level signal.

[0058] In addition, in the embodiment of the present application, the second control unit 20 is provided with a control unit 21 and a first voltage stabilizing unit 22, wherein the control unit 21 is responsible for accepting the control of the frequency control signal SN_Ctrl and outputting the second output signal SN_OUT, and the first voltage stabilizing unit 22 is responsible for regulating the controlled output process of the control unit 21 to ensure the stable output of the control unit 21. Specifically, the first end of the first voltage stabilizing unit 22 is connected to the control unit 21, the second end is connected to a fixed potential signal and is electrically insulated from the first voltage input end 2101, and in fact, the fixed potential at the second end is used to stabilize the connection node in the control unit 21 and maintain the working state of the control unit 21. Moreover, since the control unit 21 essentially outputs the first voltage signal V1 input by the first voltage input end 2101 at a specific time to form an effective pulse when outputting an effective pulse, and the second end of the first voltage stabilizing unit 22 is electrically insulated from the first voltage input end 2101, the voltage stabilizing process of the first voltage stabilizing unit 22 will not interfere with the first voltage signal V1 input by the first voltage input end 2101, that is, the pulse of the second output signal SN_OUT will not be affected by the first voltage stabilizing unit 22 when the second output signal SN_OUT is in the effective pulse stage, which can avoid the generation of ripple in the effective pulse of the second output signal SN_OUT, thereby preventing interference with data writing of the pixel circuit and solving the problem of display abnormality such as the generation of dark lines or bright lines in the boundary area of different partitions of the display panel with the partition frequency adjustment function.

[0059] In addition, it is also intended to be supplemented that, as mentioned above, the output end of the first control unit 10 outputting the first output signal SN_NEXT is electrically connected to the second control unit 20, that is, the first output signal SN_NEXT provided by the first control unit 10 simultaneously serves as the control signal of the second control unit 20, which is only one embodiment of the present application, and in other embodiments of the present application, other connection positions of the first control unit 10 and the second control unit 20 can also be selected, for example, the second control unit 20 is connected to a specific node in the first control unit 10, and those skilled in the art can select and design according to actual needs, which is not limited here, and any reasonable modification based on the present application falls within the protection scope of the present application.

[0060] As shown in FIG. 9, in an optional embodiment, the second end of the first voltage stabilizing unit 22 is electrically connected to the second voltage input end 2102.

[0061] In this embodiment, the second end of the first voltage stabilizing unit 22 is electrically connected to the second voltage input end 2102. When the frequency control signal SN_Ctrl is pulled low by a high level or pulled high by a low level, the first voltage stabilizing unit 22 is affected by the control unit 21, and the effect is only exerted on the second voltage input end 2102 through the first voltage stabilizing unit 22. Since the control unit 21 outputs an invalid pulse by outputting the second voltage signal V2 input by the second voltage input end 2102 at a specific time, the jump of the frequency control signal SN_Ctrl only causes the second output signal SN_OUT to have a ripple in the invalid pulse stage. Since the second output signal SN_OUT in the invalid pulse stage cannot turn on the components in the pixel circuit connected thereto, the second output signal SN_OUT with the ripple has no effect on the normal working process of the pixel circuit. In summary, on the basis of stabilizing the control unit 21 and maintaining the working state thereof, the second end of the first voltage stabilizing unit 22 connected to the second voltage input end 2102 does not interfere with the working state of the pixel circuit, and solves the problem of abnormal display such as dark lines or bright lines in the boundary area of different partitions of the display panel with the partition frequency adjustment function. In addition, since the second end of the first voltage stabilizing unit 22 is connected to the second voltage input end 2102 and is stabilized through the second voltage input end 2102, the shift register circuit does not need to additionally set a fixed potential signal line for the first voltage stabilizing unit 22, which saves the number of signal lines in the shift register circuit, helps to realize a narrow frame of the display panel, and is also conducive to simplifying the structure and design of the driving chip.

[0062] In another optional embodiment of the present application, the second end of the first voltage stabilizing unit is electrically insulated from the second voltage input end. FIG. 11 is another structure diagram of the shift register in the driving circuit shown in FIG. 8. Referring to FIG. 11, in this embodiment, the display panel further includes a fixed potential signal line 500, which is electrically connected to the second end of the first voltage stabilizing unit 22 in the shift register 110.

[0063] Similarly, in this embodiment, since the second end of the first voltage stabilizing unit 22 is electrically connected to the fixed potential signal line 500, that is, the first voltage stabilizing unit 22 maintains the stability of the second end through the fixed potential provided by the fixed potential signal line 500, on the one hand, the first voltage stabilizing unit 22 can stabilize the control unit 21 and maintain its working state, on the other hand, the first voltage stabilizing unit 22 can avoid interfering with the first voltage V1 provided by the first voltage input end 2101 and the second voltage V2 provided by the second voltage input end 2102, thereby avoiding fluctuations in the valid pulses and invalid pulses in the second output signal SN_OUT, and further preventing interference with data writing of the pixel circuit, and solving the problem of display abnormality of the display panel with the partition frequency adjustment function in the boundary area of different partitions.

[0064] Further optionally, one of the first voltage signal V1 and the second voltage signal V2 is a high-level signal, and the other is a low-level signal; the voltage value V0 of the fixed potential signal satisfies: VGL≤V0≤VGH; wherein VGH is the voltage value of the high-level signal in the first voltage signal and the second voltage signal, and VGL is the voltage value of the low-level signal in the first voltage signal and the second voltage signal.

[0065] In this embodiment, the fixed potential signal on the fixed potential signal line 500 and the first voltage V1 provided to the first voltage input end 2101 and the second voltage V2 provided to the second voltage input end 2102 are generally provided by the driving chip, that is, the driving chip can provide the fixed potential signal V0, the high-level signal VGH and the low-level signal VGL to the shift register. In this embodiment, the fixed potential signal V0 is set within the range of the high-level signal VGH and the low-level VGL, indicating that the high-level signal VGH and the low-level VGL can be converted into the fixed potential signal V0 provided to the fixed potential signal line 500 through a simple voltage dividing circuit design, thereby simplifying the design difficulty of the driving chip and avoiding excessive chip power consumption caused by excessively high or low voltage of the fixed potential signal on the fixed potential signal line 500.

[0066] It can be understood that the fixed potential signal line 500 to which the second end of the first voltage stabilizing unit 22 is connected can be different from the signal line connected to the first voltage input end 2101 and the signal line connected to the second voltage input end 2102, so as to avoid the interference of the first voltage stabilizing unit 22 on the first voltage V1 provided by the first voltage input end 2101 and the second voltage V2 provided by the second voltage input end 2102.

[0067] Fig. 12 and Fig. 13 are schematic diagrams of another two structures of the shift register in the driving circuit shown in Fig. 8. With reference to Fig. 9, Fig. 11-13, first, in the embodiment of the present application, the control unit 21 can include a first control unit 211 and a second control unit 212. The first control unit 211 receives at least the first output signal SN_NEXT and the frequency control signal SN_Ctrl, and controls the signal of the first node N1; the first end of the first voltage stabilizing unit 22 is electrically connected with the first node N1; the second control unit 212 receives at least the signal of the first node N1, the first voltage signal V1 of the first voltage input end 2101 and the second voltage signal V2 of the second voltage input end 2102, and controls the second output signal SN_OUT.

[0068] Wherein, the first control unit 211 essentially controls the signal of the first node N1 according to the first output signal SN_NEXT and the frequency control signal SN_Ctrl, while the second control unit 212 essentially outputs the first voltage signal V1 and the second voltage signal V2 at different time periods according to the control of the signal of the first node N1, corresponding to the active pulse and the inactive pulse of the second output signal SN_OUT. Thus, it can be known that the first node N1 in the control unit 21 is the key node of controlling the second output signal SN_OUT. Based on this, in the embodiment of the present application, the first end of the first voltage stabilizing unit 22 is electrically connected with the first node N1, which means that the potential of the first node N1 can be stabilized by the first voltage stabilizing unit 22, thereby the active pulse or the inactive pulse of the second output signal SN_OUT can be maintained in the necessary time period, for example, when the frequency control signal SN_Ctrl jumps, the integrity of the active pulse and the inactive pulse is guaranteed, so that the second output signal SN_OUT can still output the same, complete active pulse or inactive pulse as the first output signal SN_NEXT.

[0069] Continuing to refer to Fig. 9, Fig. 11-13, more specifically, the second control unit 212 includes a first module 2121, a second module 2122 and a third module 2123. The first module 2121 receives the first output signal SN_NEXT, the signal of the first node N1 and the third voltage signal V3 of the third voltage input end 2103, and controls the signal of the second node N2. The second module 2122 receives the first output signal SN_NEXT, the signal of the first node N1 and the fourth voltage signal V4 of the fourth voltage input end 2104, and controls the signal of the second node N2. The third module 2123 receives the first voltage signal V1 of the first voltage input end 2101 and the second voltage signal V2 of the second voltage input end 2102, and receives at least the signal of the second node N2, and outputs the second output signal SN_OUT; one of the third voltage signal V3 and the fourth voltage signal V4 is a high-level signal, and the other is a low-level signal.

[0070] Further, with continuous reference to FIG. 12 and FIG. 13, the high level signal in the first voltage signal V1 and the second voltage signal V2 is a signal of different potential from the high level signal in the third voltage signal V3 and the fourth voltage signal V4; the low level signal in the first voltage signal V1 and the second voltage signal V2 is a signal of different potential from the low level signal in the third voltage signal V3 and the fourth voltage signal V4.

[0071] The second end of the first voltage stabilizing unit 22 is electrically connected with the third voltage input terminal 2103 or the fourth voltage input terminal 2104. As shown in FIG. 12, the second end of the first voltage stabilizing unit 22 is electrically connected with the third voltage input terminal 2103. As shown in FIG. 13, the second end of the first voltage stabilizing unit 22 is electrically connected with the fourth voltage input terminal 2104.

[0072] The high level signal in the first voltage signal V1 and the second voltage signal V2 is a signal of different potential from the high level signal in the third voltage signal V3 and the fourth voltage signal V4, and the low level signal in the first voltage signal V1 and the second voltage signal V2 is a signal of different potential from the low level signal in the third voltage signal V3 and the fourth voltage signal V4, which indicates that the third voltage input terminal 2103 and the fourth voltage input terminal 2104 are electrically insulated from the first voltage input terminal 2101 and the second voltage input terminal 2102 respectively, and the voltage of the third voltage input terminal 2103 and the fourth voltage input terminal 2104 will not affect the voltage of the first voltage input terminal 2101 and the second voltage input terminal 2102. Based on this, in the same way, in the two embodiments, since the second end of the first voltage stabilizing unit 22 is electrically connected with the third voltage input terminal 2103 or the fourth voltage input terminal 2104, on the one hand, the first voltage stabilizing unit 22 can realize voltage stabilization to the control unit 21 through the third voltage signal V3 or the fourth voltage signal V4 to maintain its working state, and on the other hand, the first voltage stabilizing unit 22 can avoid interference to the first voltage V1 provided by the first voltage input terminal 2101 and the second voltage V2 provided by the second voltage input terminal 2102, so as to avoid fluctuations of the effective pulse and the invalid pulse in the second output signal SN_OUT, and further prevent interference to data writing of the pixel circuit, and solve the problem of display abnormality such as dark line or bright line in the boundary area of different partitions of the display panel with the partition frequency adjustment function.

[0073] Fig. 14 and Fig. 15 are schematic diagrams of two other structures of the shift register in the driving circuit shown in Fig. 8. Referring to Fig. 14 and Fig. 15, in other embodiments of the present application, the high level signals in the first voltage signal V1 and the second voltage signal V2 and the high level signals in the third voltage signal V3 and the fourth voltage signal V4 can be the same potential signals; the low level signals in the first voltage signal V1 and the second voltage signal V2 and the low level signals in the third voltage signal V3 and the fourth voltage signal V4 can be the same potential signals.

[0074] In the embodiments shown in Fig. 14 and Fig. 15, the first voltage signal V1 is a high level signal and the second voltage signal V2 is a low level signal; the third voltage signal V3 is a low level signal and the fourth voltage signal V4 is a high level signal. In the embodiments, the high level signals in the first voltage signal V1 and the second voltage signal V2 and the high level signals in the third voltage signal V3 and the fourth voltage signal V4 are the same potential signals, i.e. V1 = V4 = VGH; the low level signals in the first voltage signal V1 and the second voltage signal V2 and the low level signals in the third voltage signal V3 and the fourth voltage signal V4 are the same potential signals, i.e. V2 = V3 = VGL. Thus, the first voltage input end 2101 and the fourth voltage input end 2104 can receive high level signals from the same high level voltage signal line, and the second voltage input end 2102 and the third voltage input end 2103 can receive low level signals from the same low level voltage signal line. Thus, the high level voltage signal line and the low level voltage signal line can be saved, the shift register circuit does not need too many signal lines, which is helpful for the display panel to realize narrow frame, and is also helpful for simplifying the structure and design of the driving chip, etc.

[0075] In other embodiments, the first voltage input end 2101 and the fourth voltage input end 2104 can receive the same high level signals, and the second voltage input end 2102 and the third voltage input end 2103 can receive the same low level signals. However, the voltage signal lines connected to the first voltage input end 2101 and the fourth voltage input end 2104 can be different signal lines, and the voltage signal lines connected to the second voltage input end 2102 and the third voltage input end 2103 can also be different signal lines.

[0076] Fig. 16-18 are schematic diagrams of three other structures of the shift register in the driving circuit shown in Fig. 8. The specific structure and working process of the shift register in the embodiments of the present application will be described below with reference to the shift register structures shown in Figs. 16-18. First of all, it should be noted that the shift registers shown in Figs. 16, 17 and 18 correspond to the specific circuit structures of the shift registers shown in Figs. 9, 14 and 15 respectively, and the same structures of the shift registers in other embodiments of the present application can be referred to Figs. 16-18, for example, the shift registers shown in Figs. 11-13.

[0077] First of all, in the embodiments of the present application, the first voltage stabilizing unit 22 can include at least one capacitor. As shown in Figs. 16 and 17, the first voltage stabilizing unit 22 can include a first capacitor C1. The first end of the first capacitor C1 is connected to the first node N1 in the control unit 21, and the second end is connected to the low-level signal line VGL as shown in Fig. 16, or is connected to the fixed potential signal line 500 as shown in Fig. 17.

[0078] Continuing to refer to Figs. 16-18, for the first control unit 211 in the control unit 21, it can include a first transistor M1, the gate of the first transistor M1 receives the first output signal SN_NEXT, the first pole of the first transistor M1 receives the frequency control signal SN_Ctrl, and the second pole of the first transistor M1 is electrically connected to the first node N1.

[0079] Further optionally, referring to Figs. 16-18, the first transistor M1 is a P-type channel transistor, and for the first transistor M1, the inactive pulse of the first output signal SN_NEXT is a low-level signal, and the active pulse is a high-level signal. Of course, in another optional embodiment of the present application, the first transistor M1 can also be an N-type channel transistor, in which case the inactive pulse of the first output signal is a high-level signal, and the active pulse is a low-level signal.

[0080] Continuing to refer to Figs. 16-18, for the second control unit 212 in the control unit 21, first of all, the third module 2123 therein includes a second transistor M2 and a third transistor M3; the channel types of the second transistor M2 and the third transistor M3 are different; the first pole of the second transistor M2 receives the first voltage signal V1, the second pole of the second transistor M2 is used for outputting the second output signal SN_OUT, and the gate of the second transistor M2 is electrically connected to the second node N2; the first pole of the third transistor M3 receives the second voltage signal V2, the second pole of the third transistor M3 is used for outputting the second output signal SN_OUT, and the gate of the third transistor M3 is electrically connected to the second node N2.

[0081] In this embodiment, the second transistor M2 is exemplified as a P-type channel transistor, the third transistor M3 is exemplified as an N-type channel transistor, and since the gates of the second transistor M2 and the third transistor M3 are both connected to the second node N2, the channel types of the two transistors are different, thus the third module 2123 is substantially to control one of the two transistors to be turned on and the other to be turned off through the second node N2, and the second output signal SN_OUT can only alternately output the first voltage signal V1 and the second voltage signal V2, thereby forming the effective pulse and the ineffective pulse.

[0082] For the second control unit 212 in the control unit 21, the first module 2121 therein can include a fourth transistor M4 and a fifth transistor M5; the first electrode of the fourth transistor M4 receives the third voltage signal V3, the second electrode of the fourth transistor M4 is electrically connected to the fourth node N4, and the gate of the fourth transistor M4 receives the first output signal SN_NEXT; the first electrode of the fifth transistor M5 is electrically connected to the fourth node N4, the second electrode of the fifth transistor M5 is electrically connected to the second node N2, and the gate of the fifth transistor M5 is electrically connected to the first node N1.

[0083] For the second control unit 212 in the control unit 21, the second module 2122 therein can include a sixth transistor M6 and a seventh transistor M7; the first electrode of the sixth transistor M6 receives the fourth voltage signal V4, the second electrode of the sixth transistor M6 is electrically connected to the second node N2, and the gate of the sixth transistor M6 receives the first output signal SN_NEXT; the first electrode of the seventh transistor M7 receives the fourth voltage signal V4, the second electrode of the seventh transistor M7 is electrically connected to the second node N2, and the gate of the seventh transistor M7 is electrically connected to the first node N1.

[0084] Firstly, with reference to FIGS. 9 and 16, optionally, the voltage value of the high-level signal in the first voltage signal V1 and the second voltage signal V2 is VGH1, the voltage value of the high-level signal in the third voltage signal V3 and the fourth voltage signal V4 is VGH2, and VGH1>VGH2; and / or, the voltage value of the low-level signal in the first voltage signal V1 and the second voltage signal V2 is VGL1, the voltage value of the low-level signal in the third voltage signal V3 and the fourth voltage signal V4 is VGL2, and VGL1

[0085] In this embodiment, VGH1>VGH2, VGL1VGL2, that is, V1>V4, V2V3, which means that the high level voltage signal VGH1 received by the first electrode of the second transistor M2 is higher than the high level voltage signal VGH2 received by the first electrodes of the sixth transistor M6 and the seventh transistor M7, and the low level voltage signal VGL1 received by the first electrode of the third transistor M3 is lower than the low level voltage signal VGL2 received by the first electrode of the fourth transistor M4, so that the second transistor M2 and the third transistor M3 can be more likely to work in the saturation state in the on state and can be better turned off in the off state, thereby reducing the power consumption of the second transistor M2 and the third transistor M3, ensuring that the effective pulse voltage of the second output signal SN_OUT is the same as the high level voltage signal VGH1, and the voltage of the invalid pulse is the same as the low level voltage signal VGL1, and ensuring that the second output signal SN_OUT normally drives the pixel circuit.

[0086] With reference to FIGS. 10 and 17, the control logic and the control process of the second control unit of the shift register will be described. First, it should be noted that the first transistor M1, the second transistor M2, the sixth transistor M6 and the seventh transistor M7 are low level on P-type channel transistors, and for these transistors, the effective pulse of the signal received by the control end is a low level signal, and the invalid pulse is a high level signal. The third transistor M3, the fourth transistor M4 and the fifth transistor M5 are high level on N-type channel transistors, and for these transistors, the effective pulse of the signal received by the control end is a high level signal, and the invalid pulse is a low level signal.

[0087] In the zeroth phase t0, the first output signal SN_NEXT is high, and the frequency control signal SN_Ctrl is switched from low to high. At this time, the first transistor M1 is off, the sixth transistor M6 is off, the fourth transistor M4 is on, the first node N1 maintains the low level state in the previous phase (the first output signal SN_NEXT is low, and the frequency control signal SN_Ctrl is low in the fourth phase t4), the fifth transistor M5 is off, the seventh transistor M7 is on, the fourth voltage signal V4 (the high level signal VGH) is input to the second node N2 through the sixth transistor M6, so that the second node N2 is in a high level state, the second transistor M2 is off, the third transistor M3 is on, the second voltage signal V2 (the low level signal VGL) is output through the third transistor M3, and the second output signal SN_OUT is an invalid pulse, i.e., low level at this time.

[0088] In the first phase t1, the first output signal SN_NEXT is low, and the frequency control signal SN_Ctrl is high. At this time, the first transistor M1 is on, the sixth transistor M6 is on, and the fourth transistor M4 is off. The frequency control signal SN_Ctrl is input to the first node N1 through the first transistor M1 and charges the first capacitor C1, so that the first node N1 maintains a high level state. The fifth transistor M5 is on, the seventh transistor M7 is off, the fourth voltage signal V4 (the high level signal VGH) is input to the second node N2 through the sixth transistor M6, so that the second node N2 is in a high level state. The second transistor M2 is off, the third transistor M3 is on, the second voltage signal V2 (the low level signal VGL) is output through the third transistor M3, and the second output signal SN_OUT is an invalid pulse, i.e., low level at this time.

[0089] In the second phase t2, the first output signal SN_NEXT is high, and the frequency control signal SN_Ctrl is high. At this time, the first transistor M1 is off, the sixth transistor M6 is off, the fourth transistor M4 is on, the first capacitor C1 is discharged, so that the potential of the first node N1 still maintains the high level state in the previous phase, i.e., the first phase t1. The fifth transistor M5 is on, the seventh transistor M7 is off, the third voltage signal V3 (the low level signal VGL) is input to the second node N2 through the fourth transistor M4 and the fifth transistor M5, so that the second node N2 is in a low level state. The second transistor M2 is on, the third transistor M3 is off, the first voltage signal V1 (the high level signal VGH) is output through the second transistor M2, and the second output signal SN_OUT is an effective pulse, i.e., high level at this time.

[0090] In the third stage t3, the first output signal SN_NEXT is high level, the frequency control signal SN_Ctrl is switched from high level to low level, at this time, the first transistor M1 is off, the sixth transistor M6 is off, the fourth transistor M4 is on, the first node N1 can continue to keep high level state through the discharge of the first capacitor C1, the fifth transistor M5 is on, the seventh transistor M7 is off, the third voltage signal V3 (low level signal VGL) is input to the second node N2 through the fourth transistor M4 and the fifth transistor M5, the second node N2 is in low level state, the second transistor M2 is on, the third transistor M3 is off, the first voltage signal V1 (high level signal VGH) is output through the second transistor M2, and the second output signal SN_OUT is an effective pulse at this time, that is, high level.

[0091] In the fourth stage t4, the first output signal SN_NEXT is low level, the frequency control signal SN_Ctrl is low level, at this time, the first transistor M1 is on, the sixth transistor M6 is on, and the fourth transistor M4 is off; the frequency control signal is input to the first node N1 through the first transistor M1 and charges the first capacitor C1, the first node N1 is in low level state, the fifth transistor M5 is off, the seventh transistor M7 is on, the fourth voltage signal V4 (high level signal VGH) is input to the second node N2 through the sixth transistor M6, so that the second node N2 is in high level state, the second transistor M2 is off, the third transistor M3 is on, the second voltage signal V2 (low level signal VGL) is output through the third transistor M3, and the second output signal SN_OUT is an invalid pulse at this time, that is, low level.

[0092] In the fifth stage t5, the first output signal SN_NEXT is high level, the frequency control signal SN_Ctrl is low level, at this time, the first transistor M1 is off, the sixth transistor M6 is off, the fourth transistor M4 is on, the first node N1 can continue to keep low level state through the discharge of the first capacitor C1, the fifth transistor M5 is off, the seventh transistor M7 is on, the fourth voltage signal V4 (high level signal VGH) is input to the second node N2 through the sixth transistor M6, so that the second node N2 is in high level state, the second transistor M2 is off, the third transistor M3 is on, the second voltage signal V2 (low level signal VGL) is output through the third transistor M3, and the second output signal SN_OUT is an invalid pulse at this time, that is, low level.

[0093] It should be noted that for the zeroth stage t0 and the third stage t3, the first transistor M1 is turned off because the first output signal SN_NEXT is high, and thus the frequency control signal SN Ctrl cannot be written to the first node N1, and the output of the second output signal SN_OUT cannot be controlled through the first node N1. However, because the first transistor M1 itself can be equivalent to a resistor, the frequency control signal SN Ctrl will still affect the potential of the first node N1 to some extent when it jumps, and then affect the level signal connected to the second end of the first capacitor C1.

[0094] For the third stage t3, the second transistor M2 is turned on, and the second output signal SN_OUT substantially outputs the first voltage signal V1 provided by the first voltage input terminal 2101. Because the second end of the first capacitor C1 is electrically insulated from the first voltage input terminal 2101, the second output signal SN_OUT will not be affected at this time. For the zeroth stage t0, the third transistor M3 is turned on, and the second output signal SN_OUT substantially outputs the second voltage signal V2 provided by the second voltage input terminal 2102. Although the second end of the first capacitor C1 is electrically connected to the second voltage input terminal 2102, the second output signal SN_OUT will fluctuate when outputting the second voltage signal V2, forming a ripple as shown in FIG. 10. However, because this stage is the invalid pulse stage of the second output signal SN_OUT, it will not affect the pixel circuit connected thereto and will not affect the display quality of the display panel.

[0095] It can also be known that because the second end of the first capacitor C1 in the shift register of other embodiments of the present application is electrically insulated from the first voltage input terminal 2101 used for outputting the valid pulse, as shown in FIGS. 9 and 12, is electrically connected to the low-level signal terminal used for outputting the invalid pulse, or as shown in FIG. 11, is electrically connected to the additional fixed potential signal line 500, or as shown in FIG. 13, is electrically connected to the high-level signal terminal not used for outputting the valid pulse, the second output signal SN_OUT will not be disturbed by the jump of the frequency control signal SN Ctrl to generate a ripple when outputting the second output signal SN_OUT, or even if a ripple is generated, it will only be generated in the invalid pulse stage of the second output signal SN_OUT, and thus will not affect the pixel circuit driven by the shift register, solving the problem of display abnormality such as dark or bright lines in the boundary area of different partitions of the display panel with the partition frequency adjustment function.

[0096] Figure 19 is a schematic diagram of another structure of the shift register in the driving circuit shown in Figure 8. Referring to Figure 19, in another optional embodiment of the present application, the third module 2123 includes a second transistor M2 and a third transistor M3; the channel types of the second transistor M2 and the third transistor M3 are the same; the first electrode of the second transistor M2 receives the first voltage signal V1, the second electrode of the second transistor M2 is used to output the second output signal SN_OUT, and the gate electrode of the second transistor M2 is electrically connected to the second node N2; the first electrode of the third transistor M3 receives the second voltage signal V2, the second electrode of the third transistor M3 is used to output the second output signal SN_OUT, and the gate electrode of the third transistor M3 is electrically connected to the third node N3; the third node N3 is one electrically connected node in the first control unit 10. In this embodiment, the second transistor M2 and the third transistor M3 are both PMOS transistors or both NMOS transistors (for example, both are PMOS transistors as shown in Figure 19), the gate electrode of the second transistor M2 is connected to the second node N2, and the gate electrode of the third transistor M3 is connected to the third node N3. The essence is to control one of the second transistor M2 and the third transistor M3 to be turned on and the other to be turned off through the second node N2 and the third node N3, so as to make the second output signal SN_OUT alternately output the active pulse and the inactive pulse. It should be noted that in the embodiment of the present application, the node in the first control unit 10 is led out as the third node N3, and the specific position and connection relationship thereof in the first control unit 10 will be described below, which will not be explained here.

[0097] As shown in the example in Figure 19, the third transistor M3 is a PMOS transistor, and its gate electrode is connected to the third node N3 for conduction control. The purpose is that since the second output signal SN_OUT is generally in the inactive pulse (low level) state for a long time, the third transistor M3 needs to be turned on for a long time. If the third transistor M3 is set to be an NMOS transistor, the gate electrode of the NMOS transistor will receive a high level signal for a long time, which will cause threshold drift of the NMOS transistor, resulting in unstable electrical characteristics of the transistor and abnormal switching. Conversely, by setting the third transistor M3 to be a PMOS transistor, the PMOS transistor is turned on when the gate electrode is at a low level, which will not cause threshold drift problem, can avoid the shift of the transistor characteristic curve, ensure the stability of the electrical characteristics of the transistor, and avoid abnormal switching.

[0098] Optionally, referring to Figure 19, in the embodiment of the present application, the second control unit 212 further includes a second voltage stabilizing unit 2120; the first end of the second voltage stabilizing unit 2120 is electrically connected to the gate electrode of the third transistor M3, and the second end of the second voltage stabilizing unit 2120 is electrically connected to the second electrode of the third transistor M3. Specifically, the second voltage stabilizing unit 2120 can also include at least one capacitor, and as shown in Figure 19, the second voltage stabilizing unit 2120 includes a second capacitor C2.

[0099] The second voltage stabilizing unit 2120 is used to stabilize the second output signal SN OUT, and since the first end of the second voltage stabilizing unit 2120 is electrically connected with the gate of the third transistor M3, the second voltage stabilizing unit 2120 can store the control signal of the control end of the third transistor M3 for a certain period of time, and maintain the state of the third transistor M3. Specifically, when the second voltage stabilizing unit 2120 is not provided, the gate of the third transistor M3 is directly controlled by the potential of the third node N3, and when the potential of the third node N3 jumps, i.e., from receiving a valid pulse to receiving an invalid pulse, the third transistor M3 is switched from off to on, and in this process, the second transistor M2 and the third transistor M3 jointly control the output of the second output signal SN OUT, the second output signal SN OUT jumps from high level to low level, and the jump process has an extra step, which causes the jump delay of the second output signal SN OUT, and affects the control of the pixel circuit by the second output signal SN OUT. In the embodiment, the second voltage stabilizing unit 2120, i.e., the second capacitor C2, is provided, and when the third transistor M3 receives a valid pulse to be turned on, the second capacitor C2 is charged, i.e., the valid pulse is stored, and when the third transistor M3 is switched to receive an invalid pulse, the second capacitor C2 is discharged, and the valid pulse of the third transistor M3 is maintained for a certain period of time, so that the third transistor M3 can still be turned on for a certain period of time, and the second output signal SN OUT can output a complete invalid pulse signal. On the contrary, when the third transistor M3 is switched from receiving an invalid pulse to receiving a valid pulse, the second voltage stabilizing unit 2120 can still maintain the off state of the third transistor M3 for a certain period of time, so that the second output signal SN OUT can output a complete valid pulse signal. Therefore, the second voltage stabilizing unit 2120 can eliminate the problem of extra step in the high-low level jump process of the second output signal SN OUT, avoid the delay of the pulse signal, and accurately control the pixel circuit, so as to ensure the normal work of the pixel circuit.

[0100] It should be noted that in other embodiments of the present application, the second voltage stabilizing unit 2120 can also be selected to be connected in parallel with the gate and the second electrode of the third transistor M3, so that the working state of the third transistor M3 can be maintained for a certain period of time, thereby ensuring the completeness of the pulse signal of the second output signal SN OUT. Here, no further examples are shown in the drawings.

[0101] As shown in the foregoing embodiment, the internal structure of the second control unit in the shift register and the working principle of outputting the second output signal according to the first output signal of the first control unit and the frequency control signal are introduced, and the internal structure of the first control unit and the working principle of controlling the first output signal are introduced below.

[0102] With reference back to FIGS. 9, 11-19, optionally, the first control portion 10 includes a third control unit 13, the third control unit 13 includes a first output module 131 and a second output module 132; one end of the first output module 131 receives the fifth voltage signal V5, the other end of the first output module 131 is used to output the first output signal SN_NEXT, and the control end of the first output module 131 is connected to the fifth node N5; one end of the second output module 132 receives the sixth voltage signal V6, the other end of the second output module 132 is used to output the first output signal SN_NEXT, and the control end of the second output module 132 is connected to the sixth node N6; one of the fifth voltage signal V5 and the sixth voltage signal V6 is a high-level signal, and the other is a low-level signal.

[0103] The first output module 131 and the second output module 132 are turned on or turned off according to the signal of the node to which the control end is connected, thereby outputting the fifth voltage signal V5 through the first output module 131 or outputting the sixth voltage signal V6 through the second output module 132. It can be understood that, since one of the fifth voltage signal V5 and the sixth voltage signal V6 is a high-level signal and the other is a low-level signal, the output control of the third control unit 13 can make the first output signal SN_NEXT switch between the active pulse and the inactive pulse, and control the timing of the first output signal SN_NEXT.

[0104] With reference back to FIGS. 9, 11-19, for the first output module 131 and the second output module 132 included in the third control unit 13 of the first control portion 10, the first output module 131 can include an eleventh transistor M11 and a fourth capacitor C4, and the second output module 132 can include a twelfth transistor M12; the gate of the eleventh transistor M11 is connected to the fifth node N5, the source receives the fifth voltage signal V5 (which is a high-level signal in the example shown in the figure), and the drain outputs the first output signal SN_NEXT; the first plate of the fourth capacitor C4 receives the fifth voltage signal V5, and the second plate is connected to the gate of the eleventh transistor M11; the gate of the twelfth transistor M12 is connected to the sixth node N6, the source receives the sixth voltage signal V6 (which is a low-level signal in the example shown in the figure), and the drain outputs the first output signal SN_NEXT.

[0105] Based on the structure of the third control unit 13, in the embodiment of the present application, the low level signal in the first voltage signal V1 and the second voltage signal V2 is the same potential signal as the low level signal in the fifth voltage signal V5 and the sixth voltage signal V6; and / or, the high level signal in the first voltage signal V1 and the second voltage signal V2 is the same potential signal as the high level signal in the fifth voltage signal V5 and the sixth voltage signal V6; and / or, the low level signal in the third voltage signal V3 and the fourth voltage signal V4 is the same potential signal as the low level signal in the fifth voltage signal V5 and the sixth voltage signal V6; and / or, the high level signal in the third voltage signal V3 and the fourth voltage signal V4 is the same potential signal as the high level signal in the fifth voltage signal V5 and the sixth voltage signal V6. As shown in FIGS. 17-19, the fifth voltage signal V5 and the first voltage signal V1 and the fourth voltage signal V4 are the same high level signal VGH, and the sixth voltage signal V6 and the second voltage signal V2 and the third voltage signal V3 are the same low level signal VGL.

[0106] The embodiment is essentially to multiplex at least two high level signals, or to multiplex at least two low level signals, thereby the number of high level signal lines or low level signal lines can be saved, which is helpful for the arrangement of the lines, and is helpful for simplifying the circuit structure of the shift register 110 and reducing the complexity of the shift register 110.

[0107] With reference to FIGS. 9, 11-19, in the embodiment of the present application, the first control unit 10 further comprises a fourth control unit 14; the fourth control unit 14 is configured to receive the input signal IN, the third voltage signal V3 and the fourth voltage signal V4, and the first clock signal CK and / or the second clock signal XCK, and control the potential of the fifth node N5 and the potential of the sixth node N6.

[0108] Specifically, the fourth control unit 14 can comprise a first control module 141 and a second control module 142. The first control module 141 is configured to receive the input signal IN, and control the signals of the twelfth node N12 and the thirteenth node N13 in response to the first clock signal CK, the twelfth node N12 being connected to the sixth node N6. The second control module 142 is configured to receive the seventh voltage signal V7 and the eighth voltage signal V8, and control the signal of the fifth node N5 in response to the signals of the twelfth node N12 and the thirteenth node N13, the first clock signal CK and the second clock signal XCK. One of the seventh voltage signal V7 and the eighth voltage signal V8 is a high level signal, and the other is a low level signal.

[0109] Specifically, the first control module 141 comprises a thirteenth transistor M13 and a fourteenth transistor M14. The source of the thirteenth transistor M13 is connected to the input signal IN, the drain is connected to the twelfth node N12, and the gate is connected to the first clock signal CK. The source of the fourteenth transistor M14 is connected to the input signal IN, the drain is connected to the thirteenth node N13, and the gate is connected to the first clock signal CK.

[0110] Specifically, the second control module 142 comprises a fifteenth transistor M15, a sixteenth transistor M16, a seventeenth transistor M17, an eighteenth transistor M18, a nineteenth transistor M19, a twentieth transistor M20, a twenty-first transistor M21, a twenty-second transistor M22, a twenty-third transistor M23, a twenty-fourth transistor M24, a twenty-fifth transistor M25, a fifth capacitor C5, and a sixth capacitor C6.

[0111] The source of the fifteenth transistor M15 receives the eighth voltage signal V8 (an example of a low-level signal in the figure), the gate receives the first clock signal CK, and the drain is connected to the fourteenth node N14. The gate of the sixteenth transistor M16 is connected to the twelfth node N12, the source receives the first clock signal CK, and the drain is connected to the fourteenth node N14. The source of the seventeenth transistor M17 is connected to the fourteenth node N14, the gate receives the eighth voltage signal V8, and the drain is connected to the fifteenth node N15. The source of the eighteenth transistor M18 receives the second clock signal XCK, the gate is connected to the fifteenth node N15, and the drain is connected to the sixteenth node N16. The first plate of the fifth capacitor C5 is connected to the fifteenth node N15, and the second plate is connected to the sixteenth node N16. The source of the nineteenth transistor M19 is connected to the sixteenth node N16, the drain is connected to the fifth node N5, and the gate receives the second clock signal XCK. The source of the twentieth transistor M20 receives the seventh voltage signal V7 (an example of a high-level signal in the figure), the drain is connected to the fifth node N5, and the gate is connected to the twelfth node N12. The source of the twenty-first transistor M21 is connected to the twelfth node N12, the drain is connected to the sixth node N6, and the gate receives the eighth voltage signal V8. The source of the twenty-second transistor M22 is connected to the thirteenth node N13, the drain is connected to the seventeenth node N17, and the gate receives the eighth voltage signal V8. The source and the gate of the twenty-third transistor M23 are both connected to the seventeenth node N17, and the drain is connected to the sixth node N6. The first plate of the sixth capacitor C6 is connected to the seventeenth node N17, and the second plate is connected to the eighteenth node N18. The source of the twenty-fourth transistor M24 receives the seventh voltage signal V7, the drain is connected to the eighteenth node N18, and the gate is connected to the fourteenth node N14. The source of the twenty-fifth transistor M25 receives the second clock signal XCK, the drain is connected to the eighteenth node N18, and the gate is connected to the seventeenth node N17.

[0112] The low level signal in the seventh voltage signal V7 and the eighth voltage signal V8 is the same potential signal as the low level signal in the fifth voltage signal V5 and the sixth voltage signal V6; and / or, the high level signal in the seventh voltage signal V7 and the eighth voltage signal V8 is the same potential signal as the high level signal in the fifth voltage signal V5 and the sixth voltage signal V6. As exemplarily shown in FIGS. 17-19, the seventh voltage signal V7 is a high level signal VGH, and the eighth voltage signal is a low level signal VGL.

[0113] For the embodiment as shown in FIG. 19, optionally, the third node N3 and the sixth node N6 are the same node.

[0114] At this time, the gate of the third transistor M3 in the third module 2123 is substantially connected to the same node as the control end of the first output module 131, thereby the third module 2123 can be synchronously driven with the second output module 132, and when the second output module 132 switches between the on and off states, the third module 2123 also switches between the on and off states. Thus, when the second output module 132 outputs the valid pulse or the invalid pulse, the third module 2123 can also directly output the valid pulse or the invalid pulse, thereby helping to simplify the control logic of the third module 2123 and simplify the structure of the control circuit.

[0115] Of course, in other embodiments of the present application, the third node N3 and the fifth node N5 can also be the same node. At this time, when the second output module 132 outputs the valid pulse or the invalid pulse, the third module 2123 can also directly output the valid pulse or the invalid pulse.

[0116] It should be noted that the control end of the third module 2123 and the control end of the first output module 131 or the second output module 132 are connected to the same node, which needs to be set according to the switching time sequence of the first output module 131 or the second output module 132 and the switching time sequence of the third module 2123. It can be understood that, as shown in FIG. 18, based on the synchronous switching of the third module 2123 and the second output module 132, when both of the modules are set as PMOS transistors, the control ends thereof can be connected to the same node, i.e., the sixth node N6. Based on this, those skilled in the art can set the third transistor M3 in the third module 2123 as an N-type channel transistor, and set the eleventh transistor M11 in the first output module 131 as a PMOS transistor, at this time, the control ends thereof can be connected to the same node, i.e., the fifth node N5. Of course, the type of the transistors in the above three modules and the connection mode of the control ends are all exemplary schemes, and the present application is not limited thereto.

[0117] Based on the same consideration of sharing the first control part node, the embodiment of the present application also provides a structure of the shift register based on the structure of the first control part. Fig. 20 is another structure diagram of the shift register in the driving circuit shown in Fig. 8. Referring to Fig. 20, in the embodiment, the second control unit 22 further comprises a fourth module 2124, and the fourth module 2124 comprises an eighth transistor M8, a ninth transistor M9 and a tenth transistor M10. The first electrode of the eighth transistor M8 is connected to the third node N3, the second electrode of the eighth transistor M8 is connected to the seventh node N7, and the gate of the eighth transistor M8 is connected to the second electrode. The first electrode of the ninth transistor M9 is connected to the eighth node N8, the second electrode of the ninth transistor M9 is connected to the third node N3, and the gate of the ninth transistor M9 is connected to the tenth node N10. The first electrode of the tenth transistor M10 is connected to the ninth node N9, the second electrode of the tenth transistor M10 is connected to the seventh node N7, and the gate of the tenth transistor M10 is connected to the tenth node N10.

[0118] Further, continuing to refer to Fig. 20, in the embodiment, the fourth module 2124 further comprises a third capacitor C3, and the first plate of the third capacitor C3 is connected to the eleventh node N11, and the second plate of the third capacitor C3 is connected to the seventh node N7.

[0119] Wherein, the eighth node N8 and the twelfth node N12 are the same node, the ninth node N9 and the thirteenth node N13 are the same node, and the eleventh node N11 and the eighteenth node N18 are the same node.

[0120] At this time, the eighth transistor M8, the ninth transistor M9, the tenth transistor M10, the eleventh transistor M11 and the second capacitor C3 in the fourth module 2124 are substantially the same structure as the twenty-first transistor M21, the twenty-second transistor M22, the twenty-third transistor M23 and the fifth capacitor C6 in the first control part 10. The fourth module 2124 in the second control part 20 is used to generate a signal completely synchronized with the signal on the sixth node N6 under the control of the signal on the twelfth node N12 and the thirteenth node N13, and to control the third transistor M3. It can be understood that in the embodiment shown in Fig. 20, not only can the fourth module 2124 generate a control signal synchronized with the signal on the sixth node N6, but also can isolate the influence of the gate of the twelfth transistor M12, i.e. the sixth node N6 to a certain extent, avoid the abnormal switching of the third transistor M3 caused by the unstable signal on the sixth node N6, solve the problem of interference of the switching of the twelfth transistor M12 caused by the connection of the gate of the third transistor M3, and help to stabilize the gate potential of the twelfth transistor M12 and avoid the abnormal switching of the twelfth transistor M12.

[0121] Fig. 21 is a driving timing diagram of the first control unit in the shift register shown in Fig. 20, and the working principle and process of the first control unit in the shift register of the embodiment of the present application will be introduced below with reference to Figs. 20 and 21:

[0122] In the Ta stage, the input signal IN is at high level, and the first clock signal CK is at low level. At this time, the thirteenth transistor M13, the fourteenth transistor M14 and the fifteenth transistor M15 are turned on, the input signal IN is transmitted to the twelfth node N12 and the thirteenth node N13 through the thirteenth transistor M13 and the fourteenth transistor M14 respectively, so that the twelfth node N12 and the thirteenth node N13 are both at high level, and the sixteenth transistor M16 and the twentieth transistor M20 are turned off. Meanwhile, the eighth voltage signal V8 (low level signal VGL) is transmitted to the fourteenth node N14 through the fifteenth transistor M15, the fourteenth node N14 is at low level, and the seventeenth transistor M17 is always on, so that the fifteenth node N15 is at low level, the eighteenth transistor M18 is turned on, the second clock signal XCK is at high level, the sixteenth node N16 keeps high level, the nineteenth transistor M19 is turned off, the fifth node N5 keeps low level, the eleventh transistor M11 is turned on, and the fifth voltage signal V5 (high level signal VGH) is transmitted to the output end, so that the first output signal SN_NEXT is at high level.

[0123] In the Tb stage, the input signal IN is at high level, and the first clock signal CK is at high level. At this time, the thirteenth transistor M13, the fourteenth transistor M14 and the fifteenth transistor M15 are turned off, the twelfth node N12 and the thirteenth node N13 keep high level, the sixteenth transistor M16 and the twentieth transistor M20 are turned off, the fourteenth node N14 keeps low level, the eighteenth transistor M18 is turned on, the second clock signal XCK is at low level and is transmitted to the sixteenth node N16 through the eighteenth transistor M18, so that the sixteenth node N16 is at low level, the eighteenth transistor M18 is turned on, the signal of the sixteenth node N16 is transmitted to the fifth node N5, so that the fifth node N5 is at low level, the eleventh transistor M11 is turned on, and the fifth voltage signal V5 (high level signal VGH) is transmitted to the output end, so that the first output signal SN_NEXT is at high level.

[0124] In the Tc stage, the input signal IN is at high level, and the first clock signal CK is at low level. At this time, the thirteenth transistor M13, the fourteenth transistor M14 and the fifteenth transistor M15 are turned on, the input signal IN is transmitted to the twelfth node N12 and the thirteenth node N13 through the thirteenth transistor M13 and the fourteenth transistor M14 respectively, so that the twelfth node N12 and the thirteenth node N13 are both at high level, and the sixteenth transistor M16 and the twentieth transistor M20 are turned off. Meanwhile, the eighth voltage signal V8 (low level signal VGL) is transmitted to the fourteenth node N14 through the fifteenth transistor M15, the fourteenth node N14 is at low level, and the seventeenth transistor M17 is always on. Therefore, the fifteenth node N15 is at low level, the eighteenth transistor M18 is turned on, the second clock signal XCK is at high level, the sixteenth node N16 keeps high level, the nineteenth transistor M19 is turned off, the fifth node N5 keeps low level, the eleventh transistor M11 is turned on, and the fifth voltage signal V5 (high level signal VGH) is transmitted to the output end, so that the first output signal SN_NEXT is at high level.

[0125] In the Td stage, the input signal IN is at low level, and the first clock signal CK is at high level. At this time, the thirteenth transistor M13, the fourteenth transistor M14 and the fifteenth transistor M15 are all turned off, the twelfth node N12 and the thirteenth node N13 keep high level, and the sixteenth transistor M16 and the twentieth transistor M20 are all turned off. The fourteenth node N14 keeps low level, and the seventeenth transistor M17 is always on. Therefore, the fifteenth node N15 is at low level, the eighteenth transistor M18 is turned on, the second clock signal XCK is at low level, the second clock signal XCK is transmitted to the sixteenth node N16 through the eighteenth transistor M18, so that the sixteenth node N16 is at low level. Meanwhile, the nineteenth transistor M19 is turned on, the signal of the sixteenth node N16 is transmitted to the fifth node N5 and is at low level, the eleventh transistor M11 is turned on, the fifth voltage signal V5 (high level signal VGH) is transmitted to the output end, so that the first output signal SN_NEXT is at high level.

[0126] In the Te stage, the input signal IN is at a low level, the first clock signal CK is at a low level, the thirteenth transistor M13, the fourteenth transistor M14 and the fifteenth transistor M15 are turned on, the input signal IN is transmitted to the twelfth node N12 and the thirteenth node N13 through the thirteenth transistor M13 and the fourteenth transistor M14 respectively, so that the twelfth node N12 and the thirteenth node N13 are both at a low level, the sixteenth transistor M16 and the twentieth transistor M20 are turned on; at the same time, the fifteenth transistor M15 is turned on, the eighth voltage signal V8 (a low level signal VGL) is transmitted to the fourteenth node N14 through the fifteenth transistor M15, the fourteenth node N14 is at a low level, and the seventeenth transistor M17 is always on, so that the fifteenth node N15 is at a low level, the eighteenth transistor M18 is turned on, the second clock signal XCK is at a high level, the sixteenth node N16 keeps at a high level, and the nineteenth transistor M19 is turned off; the twentieth transistor M20 is turned on, the seventh voltage signal V7 (a high level signal VGH) is transmitted to the fifth node N5 through the twentieth transistor M20, so that the fifth node N5 is at a high level, and the eleventh transistor M11 is turned off; at the same time, the twenty-first transistor M21 and the twenty-second transistor M22 are always on, the signal of the twelfth node N12 is transmitted to the sixth node N6, so that the sixth node N6 is at a low level, the twelfth transistor M12 is turned on, the sixth voltage signal V6 (a low level signal VGL) is transmitted to the output end, so that the first output signal SN_NEXT is at a low level.

[0127] It should be noted that, since the fourth module 2124 in the second control unit 20 is copied from the twenty-first transistor M21, the twenty-second transistor M22, the twenty-third transistor M23 and the sixth capacitor C6, the output third node N3 is substantially a synchronous signal with the sixth node N6, so that in the above-mentioned Ta-Td stage, the sixth node N6 and the third node N3 are both at a high level, and in the Te stage, the sixth node N6 and the third node N3 are substantially at a low level. Therefore, the third transistor M3 is turned off in the Ta-Td stage, turned on in the Te stage and outputs the second voltage signal V2 (a low level signal VGL), and the second output signal SN_OUT is at a low level in the Te stage.

[0128] In addition, it should be noted that, as shown in FIGS. 16-20, the transistors in the first control unit 10 are all exemplified as PMOS transistors, and those skilled in the art can change the type of the transistors according to actual needs, for example, using NMOS transistors, which is not limited here. In addition, the circuit structure of the first control unit 10 shown in FIGS. 16-20 is only part of the embodiments of the present application, and those skilled in the art can replace the first control unit with other circuit structures according to actual needs, which does not affect the core scheme of the present application, and reasonable modifications based on the embodiments shown in the present application also fall within the protection scope of the present application.

[0129] The embodiment of the present application further provides a pixel circuit, and FIG. 22-26 are structural schematic diagrams of five other pixel circuits provided by the embodiment of the present application; referring to FIG. 3 and FIG. 22-26, in the embodiment of the present application, the display panel further comprises a pixel circuit 200, and the second output signal SN_OUT of the driving circuit 100 is a control signal of a preset module of the pixel circuit 200; when the second output signal SN_OUT is a valid pulse, the preset module is turned on; and when the second output signal SN_OUT is an invalid pulse, the preset module is turned off.

[0130] The process that the driving circuit 100 of the present application drives the preset module in the pixel circuit 200 is introduced below by referring to the pixel circuit shown in FIG. 3 and FIG. 22-26. Firstly, as shown in FIG. 3 and FIG. 22-26, the pixel circuit 200 can comprise a data writing module 210, a driving module 220, a threshold compensation module 230, a gate reset module 250, an initialization module 260 and a light emitting control module 270; the driving module 220 comprises a driving transistor T2, which is used to provide a driving current for the light emitting element 300 of the display panel 100; the data writing module 210 is connected to the first pole (i.e. N2 node) of the driving transistor T2, and is used to provide a data signal for the driving transistor T2; the threshold compensation module 230 is connected between the gate (i.e. N1 node) and the second pole (i.e. N3 node) of the driving transistor, and is used to compensate the threshold voltage of the driving transistor T2; the gate reset module 250 is used to provide a reset signal Vref for the gate of the driving transistor T2; the initialization module 260 is used to provide an initialization signal Vini for the light emitting element 300; and the light emitting control module 270 is used to selectively allow the light emitting element 300 to enter a light emitting stage. Optionally, the light emitting control module 270 comprises a first light emitting control module 271 and a second light emitting control module 272, the first light emitting control module 271 is connected between the first power signal end and one pole of the driving transistor T2, and the second light emitting control module 272 is connected between the other pole of the driving transistor T2 and the light emitting element 300.

[0131] The control end of the data writing module 210 receives a first scan signal S1, the first scan signal S1 controls the opening and closing of the data writing module 210; the control end of the threshold compensation module 230 receives a second scan signal S2, the second scan signal S2 controls the opening and closing of the threshold compensation module 230; the control end of the gate reset module 250 receives a third scan signal S3, the third scan signal S3 controls the opening and closing of the gate reset module 250; the control end of the initialization module 260 receives a fourth scan signal S4, the fourth scan signal S4 controls the opening and closing of the initialization module 260; the control end of the light emitting control module 270 receives a light emitting control signal EM, the light emitting control signal EM controls the opening and closing of the light emitting control module 270.

[0132] The data writing module 210 includes a data writing transistor T1, the first scan signal S1 controls the opening and closing of the data writing transistor T1; the threshold compensation module 230 includes a compensation transistor T3, the second scan signal S2 controls the opening and closing of the compensation transistor T3; the gate reset module 250 includes a reset transistor T5, the third scan signal S3 controls the opening and closing of the reset transistor T5; the initialization module 260 includes an initialization transistor T6, the fourth scan signal S4 controls the opening and closing of the initialization transistor T6; the first light emitting control module 271 includes a first light emitting control transistor T7, the second light emitting control module 272 includes a second light emitting control transistor T8, the light emitting control signal EM controls the opening and closing of the first light emitting control transistor T7 and the second light emitting control transistor T8.

[0133] It should be noted that, as shown in FIGS. 23-26, the pixel circuit can further include a bias adjustment module 240 for providing a bias adjustment signal for the driving transistor T2. Optionally, as shown in FIGS. 23 and 25, the bias adjustment module 240 is connected to the first electrode (i.e. N2 node) of the driving transistor T2; as shown in FIGS. 24 and 26, the bias adjustment module 240 is connected to the second electrode (i.e. N3 node) of the driving transistor T2. Optionally, the control end of the bias adjustment module 240 receives a bias adjustment control signal SV, the bias adjustment control signal SV controls the opening and closing of the bias adjustment module 240; the bias adjustment module 240 includes a bias adjustment transistor T4, the bias adjustment control signal SV controls the opening and closing of the bias adjustment transistor T4.

[0134] In addition, it should be noted that, as shown in FIG. 3, FIG. 23, and FIG. 25, the pixel circuit includes a driving transistor T2 which is a PMOS transistor. The pixel circuit further includes a storage capacitor C1, a first electrode of the storage capacitor C1 is connected to a first power signal terminal, and a second electrode of the storage capacitor C1 is connected to a gate of the driving transistor T2, for storing a signal transmitted to the gate of the driving transistor T2. As shown in FIG. 22, FIG. 24, and FIG. 26, the pixel circuit includes a driving transistor T2 which is an NMOS transistor. The pixel circuit further includes a storage capacitor C1, a first electrode of the storage capacitor C1 is connected to the light emitting element 300, and a second electrode of the storage capacitor C1 is connected to a gate of the driving transistor T2, for storing a signal transmitted to the gate of the driving transistor T2.

[0135] In the embodiment, the pixel circuit receives a power signal PVDD and a power signal PVEE, and generates a driving current through a potential difference between the power signal PVDD and the power signal PVEE, so as to drive the light emitting element to emit light. The power signal PVDD can be a positive power signal, and the power signal PVEE can be a negative power signal.

[0136] In addition, FIG. 3 and FIG. 22-FIG. 26 only exemplarily provide structures of several pixel circuits, but do not include all, and other pixel circuits whose power signals PVDD and PVEE meet the definition in the present application also belong to the protection scope of the embodiment of the present application, and the embodiment will not be described here.

[0137] Based on the pixel circuits described above, the driving circuit 100 in the embodiment can provide a control signal to the threshold compensation module 230 or the gate reset module 250, that is, the preset module of the pixel circuit 200 can be the threshold compensation module 230 or the gate reset module 250, and the second output signal SN_OUT of the driving circuit 100 can be the control signal of the threshold compensation module 230 or the gate reset module 250.

[0138] Taking the second output signal SN_OUT of the driving circuit 100 as an example of the control signal of the threshold compensation module 230, the preset module is the threshold compensation module 230, and continuing to refer to FIG. 3 and FIG. 22-FIG. 26, the preset module can include an N-type channel transistor, and the second output signal SN_OUT is a control signal of the N-type channel transistor, wherein when the second output signal SN_OUT is a high-level signal, the N-type channel transistor is controlled to be turned on when the second output signal SN_OUT is in an effective pulse stage. Of course, in other embodiments of the present application, the preset module can also include a P-type channel transistor, and the second output signal SN_OUT is a control signal of the P-type channel transistor, wherein when the second output signal SN_OUT is a low-level signal, the P-type channel transistor is controlled to be turned on when the second output signal SN_OUT is in an effective pulse stage.

[0139] The second output signal SN_OUT of the driving circuit 100 is used as a threshold compensation module 230 control signal, and the threshold compensation module 230 is a preset module. The threshold compensation module 230 includes an N-type channel transistor. The driving principle of the pixel circuit 200 is described below.

[0140] Referring to FIG. 10, generally, different stages of the shift register 110 provide driving signals to different rows of pixel circuits 200, i.e., provide data write control signals to the data write module 210 in different rows of pixel circuits 200. Taking any stage of the shift register as an example, as described above, in the second stage t2 and the third stage t3, the second output signal SN_OUT is an effective pulse, i.e., a high-level signal. At this time, the gate of the N-type channel transistor T3 in the threshold compensation module 230 receives a high-level signal and is turned on, and the threshold compensation module 230 is in an open state. Thus, when the pixel circuit 200 is in a pixel write stage, i.e., the data write module 210 is synchronously opened, the pixel circuit 200 starts to write a data signal, and the storage capacitor C1 starts to charge. When the pixel circuit 200 is in a light-emitting stage, the first light-emitting control module 271 and the second light-emitting control module 272 are opened, the storage capacitor C1 starts to discharge, and the driving transistor T2 is controlled by the potential of the first node N1 to realize light emission. Moreover, in the third stage t3, since the second end of the first capacitor C1 in the driving circuit 100 is electrically insulated from the first voltage input end 2101, the second output signal SN_OUT at this time is not affected, so that the data write stage can normally write a data signal to the first node N1 of the pixel circuit 200, so that the light-emitting element can emit light according to the target brightness in the light-emitting stage, thereby solving the problem of display abnormality, such as dark lines or bright lines, in the boundary area of different partitions of a display panel with a partition frequency adjustment function.

[0141] In the zeroth phase t0, the first phase t1, the fourth phase t4 and the fifth phase t5, the second output signal SN_OUT is a low level signal, at this time, the gate of the N-type channel transistor T3 in the threshold compensation module 230 receives a low level signal and is cut off, and the threshold compensation module 230 is in an off state. Thus, even if the pixel circuit 200 is in a data writing phase, that is, the data writing module 210 is synchronously turned on, the pixel circuit 200 cannot write a data signal to the first node N1, and cannot affect the actual data writing process of the pixel circuit 200. Even if the invalid pulse of the second output signal SN_OUT in the zeroth phase t0 is affected by the level jump of the frequency control signal SN_Ctrl in the driving circuit 100 to generate ripple, it will not affect the data writing of the pixel circuit 200, and the pixel circuit 200 can still normally write a data signal, control the light emitting element to emit light according to the target brightness in the light emitting phase, and solve the problem of display abnormality such as dark lines or bright lines in the boundary area of different partitions of the display panel with the partition frequency adjustment function.

[0142] Those skilled in the art can know that for the gate reset module 250 in the pixel circuit 200, the opening process thereof in each data refresh period also directly affects whether the corresponding light emitting element 300 can be driven to emit light by the pixel circuit 200. In other words, when the gate reset module 250 uses the second output signal SN_OUT as a control signal, the shift register 110 can also control whether the corresponding light emitting element 300 can normally emit light. Those skilled in the art can deduce the implementation mode of the specific function of each module, which will not be described here.

[0143] FIG. 27 is a driving timing diagram of the display panel shown in FIG. 7. Referring to FIGS. 7 and 27, in the embodiment of the present application, the display panel can include a first display area AA1 and a second display area AA2, the first display area AA1 includes a first pixel circuit 201, and the second display area AA2 includes a second pixel circuit 202; the driving circuit 100 includes a first shift register 111 and a second shift register 112; the preset module in the first pixel circuit 201 is a first preset module, and the preset module in the second pixel circuit 202 is a second preset module; the second output signal SN_OUT1 output by the first shift register 111 is a control signal of the first preset module, and the second output signal SN_OUT2 output by the second shift register 112 is a control signal of the second preset module; wherein the pulse change frequency of the second output signal SN_OUT1 received by the first preset module is F1, and the pulse change frequency of the second output signal SN_OUT2 received by the second preset module is F2; wherein F1>F2.

[0144] Firstly, referring to FIG. 10, in the shift register 110, the frequency control signal SN_Ctrl directly determines the output of the valid pulses of the second output signal SN_OUT. Therefore, for different regions of the display panel, by providing different frequency control signals SN_Ctrl to the corresponding shift register 110, the second output signal SN_OUT outputted by the shift register 110 received by different partitions of the display panel can have different number of valid pulses, i.e., have different pulse change frequencies. As shown in FIG. 7 and FIG. 10, by providing the first frequency control signal SN_Ctrl1 to the first shift register 111 corresponding to the first display area AA1, providing the second frequency control signal SN_Ctrl2 to the second shift register 112 corresponding to the second display area AA2, and reasonably setting the valid pulse duration Wc1 of the first frequency control signal SN_Ctrl1 to be greater than the valid pulse duration Wc2 of the second frequency control signal SN_Ctrl2, the number of valid pulses of the second output signal SN_OUT1 outputted by the first shift register 111 can be greater than the number of valid pulses of the second output signal SN_OUT2 outputted by the second shift register 112, i.e., the pulse change frequency F1 of the second output signal SN_OUT1 outputted by the first shift register 111 can be greater than the pulse change frequency F2 of the second output signal SN_OUT2 outputted by the second shift register 112.

[0145] It should be noted that, as shown in FIG. 27, the way of adjusting the pulse change frequency of the second output signal SN_OUT outputted by the shift register 110 received by different partitions by changing the valid pulse duration Wc of the frequency control signal SN_Ctrl is only one embodiment of the present application, in other embodiments of the present application, the pulse change frequency of the frequency control signal SN_Ctrl or the same frequency control signal SN_Ctrl can also be used to adjust the pulse change frequency of the second output signal SN_OUT outputted by the shift register 110 received by different partitions.

[0146] FIG. 28 is another driving timing diagram of the display panel shown in FIG. 7, referring to FIG. 7 and FIG. 28, the frequency control signal SN_Ctrl1 received by the first shift register 111 and the frequency control signal SN_Ctrl2 received by the second shift register 112 can be the same.

[0147] The first output signal SN_NEXT outputted by the first control unit 10 in each shift register 110 is the input signal of the first control unit 10 in the next shift register 110 due to the cascade connection of the shift registers 110. Therefore, the first output signal SN_NEXT outputted by the first control unit 10 in each shift register 110 is sequentially shifted in time sequence, as shown in FIG. 28, in which the active pulse of the first output signal SN_NEXT1 of the first shift register 111 and the active pulse of the first output signal SN_NEXT2 of the second shift register 112 are misaligned in time sequence. Based on this, in this embodiment, the same frequency control signal SN_Ctrl can be used to control the first shift register 111 corresponding to the first display area AA1 and the first shift register 112 corresponding to the second display area AA2 to output different numbers of active pulses by reasonably setting the pulse width, frequency and time sequence of the active pulse of the frequency control signal SN_Ctrl. In other words, according to the working principle of the driving circuit 100 in which the second output signal SN_OUT is controlled by the frequency control signal SN_Ctrl and the first output signal SN_NEXT in this embodiment, the first output signal SN_NEXT corresponding to different display areas can be used to make the active pulse of the first output signal SN_NEXT and the active pulse of the frequency control signal SN_Ctrl have different overlapping states on the basis of the same frequency control signal SN_Ctrl, so as to make the second output signal SN_OUT output different numbers of active pulses, and make the second output signal SN_OUT received by the first display area AA1 and the second output signal SN_OUT received by the second display area AA2 have different pulse change frequencies, thereby realizing different refresh frequencies of the first display area AA1 and the second display area AA2.

[0148] With continuous reference to FIGS. 7 and 28, the display process of the display panel can also optionally include a first stage TA and a second stage TB, and the second stage TB includes a first sub-stage TB1 and a second sub-stage TB2. In the first stage TA and the first sub-stage TB1, the level of the frequency control signal SN_Ctrl received by the first shift register 111 and the level of the frequency control signal SN_Ctrl received by the second shift register 112 are both the first level, and the second output signal SN_OUT1 received by the first preset module and the second output signal SN_OUT2 received by the second preset module both include active pulses. In the second sub-stage TB2, the level of the frequency control signal SN_Ctrl received by the first shift register 111 is the first level, the second output signal SN_OUT1 received by the first preset module includes active pulses, the level of the frequency control signal SN_Ctrl received by the second shift register 112 is the second level, and the second output signal SN_OUT2 received by the second preset module includes inactive pulses.

[0149] In the first stage TA, the frequency control signal SN Ctrl received by the first shift register 111 and the second shift register 112 has the same level state, i.e., the first level, for example, the high level, so that the first display area AA1 corresponding to the first shift register 111 and the second display area AA2 corresponding to the second shift register 112 have the same working state, i.e., the same refresh frequency. The first stage TA can be understood as the first working mode of the display panel, i.e., the high-frequency refresh mode. In the high-frequency refresh mode, the pixel circuit 200 in the first display area AA1 and the second display area AA2 performs a complete driving display process in each frame, the pixel circuit 200 writes a new data signal in each frame, and the display panel displays a new picture.

[0150] In the second stage TB, for the first sub-stage TB1, the level state of the frequency control signal SN Ctrl is the same as that in the first stage T1, i.e., the first level. The first display area AA1 corresponding to the first shift register 111 and the second display area AA2 corresponding to the second shift register 112 have the same working state.

[0151] In the second sub-stage TB2 of the second stage TB, the level of the frequency control signal SN Ctrl received by the first shift register 111 at the t1 stage shown in FIG. 28 is the first level, and the second output signal SN OUT1 received by the first preset module includes a valid pulse, indicating that the first output signal SN NEXT1 output by the first control part 10 in the first shift register 111 in the first sub-stage TB1 has a valid pulse. At the same time, because the frequency control signal SN Ctrl is the first level at this time, it is the valid pulse stage, so that the second control part 20 can output a valid pulse, i.e., in the t1 stage, the second output signal SN OUT1 provided by the first shift register 111 to the first preset module has a valid pulse. The level of the frequency control signal SN Ctrl received by the second shift register 112 at the t2 stage shown in FIG. 28 is the second level, and the second output signal SN OUT2 received by the second preset module includes an invalid pulse, indicating that the first output signal SN NEXT2 output by the first control part 10 in the second shift register 112 in the second sub-stage TB2 has a valid pulse. Because the frequency control signal SN Ctrl is the second level at this time, it is the invalid pulse stage, so that the second control part 20 outputs an invalid pulse, i.e., in the second sub-stage TB2, the second output signal SN OUT2 provided by the second shift register 112 to the second preset module has no valid pulse.

[0152] Therefore, the second stage TB can be understood as a second working mode of the display panel, i.e., a low-power refresh mode, in which, for the first display area AA1, the pixel circuit 200 can effectively write a new data signal in the first sub-stage TB1 and the second sub-stage TB2, and the first display area AA1 displays a new picture, in other words, in the second stage TA, the first display area AA1 is still in a high-frequency refresh display state, which is not different from the first stage TA. For the second display area AA2, the first sub-stage TB1 can be understood as a refresh frame, and the second sub-stage TB2 can be understood as a plurality of holding frames (in other possible embodiments, the second sub-stage TB2 can also include only one holding frame), the pixel circuit 200 writes a new data signal in the first sub-stage TB1, i.e., the refresh frame, and the second display area AA2 also displays a new picture, but in the second sub-stage TB2, i.e., the holding frame, the pixel circuit 200 has no new data signal written, and it maintains the light-emitting state of the light-emitting element 300 by using the data signal written in the refresh frame, and the second display area AA2 displays the picture of the refresh frame.

[0153] Based on the same inventive concept, the embodiment of the present application also provides a display device. FIG. 30 is a structural schematic diagram of a display device provided by an embodiment of the present application. As shown in FIG. 30, the display device includes the display panel 1 provided by any of the embodiments of the present application. Therefore, the display device provided by the embodiment of the present application has the corresponding beneficial effects of the display panel provided by the embodiment of the present application, which will not be described here. For example, the display device can be a mobile phone, a computer, a smart wearable device (for example, a smart watch), a vehicle-mounted display device, or other electronic devices, which are not limited by the embodiment of the present application.

[0154] It should be noted that the above are only the preferred embodiments of the present application and the technical principles applied. Those skilled in the art will understand that the present application is not limited to the specific embodiments described herein, and those skilled in the art can make various obvious changes, re-adjustments, mutual combinations and substitutions without departing from the scope of the present application. Therefore, although the present application has been described in more detail through the above embodiments, the present application is not limited to the above embodiments, and can include more other equivalent embodiments without departing from the concept of the present application, and the scope of the present application is determined by the scope of the appended claims.

Claims

1. A display panel, characterized by, The display panel comprises: a driving circuit comprising N-stage shift registers connected in cascade, N≥2; the shift registers comprise: a first control unit and a second control unit, the first control unit being electrically connected with the second control unit; the first control unit is used for controlling a first output signal, the first output signal of an i-th stage shift register being an input signal of a j-th stage shift register, 1≤i≤N, 1≤j≤N; the second control unit comprises a control unit and a first voltage stabilizing unit; the control unit receives at least a frequency control signal, a first voltage signal input from a first voltage input terminal and a second voltage signal input from a second voltage input terminal, and controls a second output signal; a voltage corresponding to an effective pulse in the second output signal is the same as a voltage of the first voltage signal, and a voltage corresponding to an ineffective pulse in the second output signal is the same as a voltage of the second voltage signal; a first end of the first voltage stabilizing unit is electrically connected with the control unit, and a second end receives a fixed potential signal; the second end of the first voltage stabilizing unit is electrically insulated from the first voltage input terminal.

2. The display panel of claim 1, wherein, the second end of the first voltage stabilizing unit is electrically connected with the second voltage input terminal.

3. The display panel of claim 1, wherein, the second end of the first voltage stabilizing unit is electrically insulated from the second voltage input terminal.

4. The display panel of claim 3, wherein, The display panel further comprises a fixed potential signal line, which is electrically connected with the second end of the first voltage stabilizing unit in the shift register.

5. The display panel of claim 4, wherein, one of the first voltage signal and the second voltage signal is a high-level signal, and the other is a low-level signal; a voltage value V0 of the fixed potential signal satisfies: VGL≤V0≤VGH; wherein, VGH is a voltage value of the high-level signal in the first voltage signal and the second voltage signal, and VGL is a voltage value of the low-level signal in the first voltage signal and the second voltage signal.

6. The display panel of claim 1, wherein, the control unit comprises a first control unit and a second control unit; the first control unit receives at least the first output signal and the frequency control signal, and controls a signal of a first node; a first end of the first voltage stabilizing unit is electrically connected with the first node; the second control unit receives at least the signal of the first node, the first voltage signal of the first voltage input terminal and the second voltage signal of the second voltage input terminal, and controls the second output signal.

7. The display panel of claim 6, wherein, the second control unit comprises a first module, a second module and a third module; the first module receives the first output signal, the signal of the first node and a third voltage signal of a third voltage input terminal, and controls a signal of a second node; the second module receives the first output signal, the signal of the first node and a fourth voltage signal of a fourth voltage input terminal, and controls the signal of the second node; the third module receives the first voltage signal of the first voltage input terminal and the second voltage signal of the second voltage input terminal, and receives at least the signal of the second node, and outputs the second output signal; one of the third voltage signal and the fourth voltage signal is a high-level signal, and the other is a low-level signal.

8. The display panel of claim 7, wherein, One of the first voltage signal and the second voltage signal is a high level signal, and the other is a low level signal; The high level signal in the first voltage signal and the second voltage signal is a signal of different potential from the high level signal in the third voltage signal and the fourth voltage signal; The low level signal in the first voltage signal and the second voltage signal is a signal of different potential from the low level signal in the third voltage signal and the fourth voltage signal; The second end of the first voltage stabilizing unit is electrically connected to the third voltage input end or the fourth voltage input end.

9. The display panel of claim 8, wherein, The voltage value of the high level signal in the first voltage signal and the second voltage signal is VGH1, the voltage value of the high level signal in the third voltage signal and the fourth voltage signal is VGH2, and VGH1>VGH2; and / or, The voltage value of the low level signal in the first voltage signal and the second voltage signal is VGL1, the voltage value of the low level signal in the third voltage signal and the fourth voltage signal is VGL2, and VGL1 10. The display panel of claim 7, wherein, The high level signal in the first voltage signal and the second voltage signal is a signal of same potential as the high level signal in the third voltage signal and the fourth voltage signal; The low level signal in the first voltage signal and the second voltage signal is a signal of same potential as the low level signal in the third voltage signal and the fourth voltage signal.

11. The display panel of claim 7, wherein, The third module comprises a second transistor and a third transistor, and the channel types of the second transistor and the third transistor are different; The first electrode of the second transistor receives the first voltage signal, the second electrode of the second transistor is configured to output the second output signal, and the gate electrode of the second transistor is electrically connected to the second node; The first electrode of the third transistor receives the second voltage signal, the second electrode of the third transistor is configured to output the second output signal, and the gate electrode of the third transistor is electrically connected to the second node.

12. The display panel of claim 7, wherein, The third module comprises a second transistor and a third transistor, and the channel types of the second transistor and the third transistor are different; The first electrode of the second transistor receives the first voltage signal, the second electrode of the second transistor is configured to output the second output signal, and the gate electrode of the second transistor is electrically connected to the second node; The first electrode of the third transistor receives the second voltage signal, the second electrode of the third transistor is configured to output the second output signal, and the gate electrode of the third transistor is electrically connected to the third node; The third node is one of the electrically connected nodes in the first control unit.

13. The display panel of claim 11 or 12, wherein, The second control unit further comprises a second voltage stabilizing unit, the first end of the second voltage stabilizing unit is electrically connected to the gate electrode of the third transistor, and the second end of the second voltage stabilizing unit is electrically connected to the second electrode of the third transistor.

14. The display panel of claim 7, wherein, The first module comprises a fourth transistor and a fifth transistor; a first electrode of the fourth transistor receives the third voltage signal, a second electrode of the fourth transistor is electrically connected to a fourth node, and a gate electrode of the fourth transistor receives the first output signal; a first electrode of the fifth transistor is electrically connected to the fourth node, a second electrode of the fifth transistor is electrically connected to the second node, and a gate electrode of the fifth transistor is electrically connected to the first node.

15. The display panel of claim 7, wherein the second module comprises a sixth transistor and a seventh transistor; a first electrode of the sixth transistor receives the fourth voltage signal, a second electrode of the sixth transistor is electrically connected to the second node, and a gate electrode of the sixth transistor receives the first output signal; a first electrode of the seventh transistor receives the fourth voltage signal, a second electrode of the seventh transistor is electrically connected to the second node, and a gate electrode of the seventh transistor is electrically connected to the first node.

16. The display panel of claim 6, wherein the first control unit comprises a first transistor, a gate electrode of the first transistor receives the first output signal, a first electrode of the first transistor receives the frequency control signal, and a second electrode of the first transistor is electrically connected to the first node.

17. The display panel of claim 16, wherein the first transistor is a P-type channel transistor, an inactive pulse of the first output signal is a low-level signal, and an active pulse is a high-level signal; or the first transistor is an N-type channel transistor, an inactive pulse of the first output signal is a high-level signal, and an active pulse is a low-level signal. the first voltage stabilizing unit comprises at least one capacitor.

18. The display panel of claim 1, wherein, The display panel further comprises a pixel circuit, and the second output signal of the driving circuit is a control signal of a preset module of the pixel circuit; 19. The display panel of claim 1, wherein, when the second output signal is in an active pulse stage, the preset module is turned on; when the second output signal is in an inactive pulse stage, the preset module is turned off.

20. The display panel of claim 19, wherein the preset module comprises a P-type channel transistor, and the second output signal is a control signal of the P-type channel transistor, wherein when the second output signal is a low-level signal, the second output signal is in an active pulse stage, and the P-type channel transistor is controlled to be turned on; or the preset module comprises an N-type channel transistor, and the second output signal is a control signal of the N-type channel transistor, wherein when the second output signal is a high-level signal, the second output signal is in an active pulse stage, and the N-type channel transistor is controlled to be turned on. the pixel circuit comprises a driving transistor, a threshold compensation module, and a gate reset module; a first end of the threshold compensation module and a first end of the gate reset module are both electrically connected to a gate electrode of the driving transistor; the preset module comprises the threshold compensation module, and / or the preset module comprises the gate reset module.

21. The display panel of claim 19, wherein, ​ ​ 22. The display panel of claim 19, wherein, The display panel comprises a first display area and a second display area, the first display area comprises a first pixel circuit, and the second display area comprises a second pixel circuit; the driving circuit comprises a first shift register and a second shift register; The preset module in the first pixel circuit is a first preset module, the preset module in the second pixel circuit is a second preset module, the second output signal output by the first shift register is a control signal of the first preset module, and the second output signal output by the second shift register is a control signal of the second preset module; wherein, The pulse change frequency of the second output signal received by the first preset module is F1, and the pulse change frequency of the second output signal received by the second preset module is F2; wherein, F1>F2.

23. The display panel of claim 22, wherein, The display process of the display panel comprises a first stage and a second stage; the second stage comprises a first sub-stage and a second sub-stage; In the first stage and the first sub-stage, the level of the frequency control signal received by the first shift register and the level of the frequency control signal received by the second shift register are both a first level; the second output signal received by the first preset module and the second output signal received by the second preset module both comprise valid pulses; In the second sub-stage, the level of the frequency control signal received by the first shift register is the first level, and the second output signal received by the first preset module comprises valid pulses; the level of the frequency control signal received by the second shift register is a second level, and the second output signal received by the second preset module comprises invalid pulses.

24. The display panel of claim 22, wherein, The frequency control signal received by the first shift register is the same as the frequency control signal received by the second shift register.

25. A display device comprising: The display panel of any one of claims 1-24.

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