Image sensor and electronic device

Abstract

Disclosed in the present application are an image sensor and an electronic device. The image sensor comprises: a SPAD pixel array, wherein the SPAD pixel array comprises SPAD pixels which are arranged in multiple rows and multiple columns; each SPAD pixel comprises a SPAD and a register; the register is electrically connected to the SPAD; and in the same column of SPAD pixels, an output end of a register of an i-th SPAD pixel is electrically connected to an input end of a register of an (i+a)-th SPAD pixel, and an output end of a last-stage register among a plurality of cascaded registers in the same column of SPAD pixels is connected to an input end of a column scanning circuit, where a is greater than or equal to 1.

Description

Image sensor and electronic device

[0001] Cross Reference to Related Applications

[0002] This application claims priority to Chinese Patent Application No. 202411237145.3, filed on September 4, 2024, entitled “Image sensor and electronic device”, the entire contents of which are incorporated herein by reference. TECHNICAL FIELD

[0003] The present application belongs to the field of image technology, and specifically relates to an image sensor and an electronic device. BACKGROUND

[0004] Compared with a pinned photodiode (PPD) in a conventional complementary metal-oxide semiconductor (CMOS) image sensor (CIS), a single-photon avalanche diode (SPAD) has higher sensitivity. Each photon irradiated on the SPAD will excite a corresponding electrical signal, which forms a square wave pulse signal after rectification, and is output as a SPAD pixel signal after counting. In recent years, researchers have begun to study replacing the PPD with the SPAD as a SPAD pixel photosensitive element of a general visible light RGB camera CIS, so as to fully utilize the ultra-high sensitivity of the SPAD single-photon sensing level and play a role of imaging beyond the human eye in the extremely dark night scene.

[0005] However, each SPAD pixel in the related art needs to include a counter, and the structure of the counter is relatively complex, which leads to an excessively large size of the SPAD pixel, and thus a large number of SPAD pixels cannot be integrated in a unit chip area to improve the effective resolution of the CIS. SUMMARY

[0006] The present application aims to provide an image sensor and an electronic device, which can solve the problem that the size of the SPAD pixel is excessively large in the prior art, and thus a large number of SPAD pixels cannot be integrated in a unit chip area to improve the effective resolution of the CIS.

[0007] To solve the above technical problems, the present application is implemented as follows:

[0008] In a first aspect, the embodiments of the present application provide an image sensor, comprising a SPAD pixel array, the SPAD pixel array comprising SPAD pixels arranged in multiple rows and multiple columns, each SPAD pixel comprising a SPAD and a register, the register being electrically connected to the SPAD, and an output terminal of the register of an i-th SPAD pixel in a same column of SPAD pixels being electrically connected to an input terminal of the register of an i+a-th SPAD pixel, and an output terminal of a last register in the multiple cascaded registers in the same column of SPAD pixels being connected to an input terminal of a column scanning circuit, where the a is greater than or equal to 1.

[0009] In a second aspect, the embodiments of the present application provide an electronic device, comprising a central processing unit and the image sensor as described in the embodiments of the first aspect.

[0010] In the embodiments of the present application, each SPAD pixel comprises a SPAD and a register, the register being electrically connected to the SPAD, and the registers of multiple SPAD pixels in a same column are cascaded with each other to form a shift register, so that the signal generated by the SPAD can be transferred in a pixel-by-pixel manner through the cascaded registers, and the signal is output to the column scanning circuit by the last register; in the embodiments of the present application, the registers of the SPAD pixels in the same column are cascaded, so that the light signal captured by the SPAD device can be processed and output at a high speed and effectively, and the operation efficiency of the pixel is improved; and the SPAD pixel does not contain a complex counter and a clock control circuit required by the counter, so that the circuit structure of the SPAD pixel is simplified, the unit area occupied by a single SPAD pixel is reduced, so that more SPAD pixels can be integrated in a unit chip area to improve the effective resolution of the CIS; and the SPAD pixel does not contain a complex counter, so that the composition and complexity of the circuit on the chip are simplified, more auxiliary modules can be provided, and it is possible to make the size of the logic layer and the pixel layer chips consistent.

[0011] Additional aspects and advantages of the present application will be made apparent from the following description, which, taken in conjunction with the accompanying drawings, that will be part hereof. BRIEF DESCRIPTION OF DRAWINGS

[0012] The above and / or additional aspects and advantages of the present application will become apparent and be readily understood from the following description, taken in conjunction with the accompanying drawings, in which:

[0013] FIG. 1 is a circuit diagram and working principle schematic diagram of a CIS chip of a SPAD in the related art;

[0014] FIG. 2 is an architecture schematic diagram of an image sensor in the related art;

[0015] FIG. 3 is a structure schematic diagram of a counter in the related art;

[0016] Fig. 4 is a schematic diagram of a structure of an image sensor according to an embodiment of the present application;

[0017] Fig. 5 is a schematic diagram of another structure of an image sensor according to an embodiment of the present application;

[0018] Fig. 6 is a schematic diagram of still another structure of an image sensor according to an embodiment of the present application;

[0019] Fig. 7 is a schematic diagram of still another structure of an image sensor according to an embodiment of the present application;

[0020] Fig. 8 is a schematic diagram of a structure of a column scanning circuit in an image sensor according to an embodiment of the present application;

[0021] Fig. 9 is a schematic diagram of a structure of a clock and control circuit in an image sensor according to an embodiment of the present application;

[0022] Fig. 10 is a schematic diagram of still another structure of an image sensor according to an embodiment of the present application;

[0023] Fig. 11 is a schematic diagram of a structure of an electronic device according to an embodiment of the present application.

[0024] BRIEF DESCRIPTION OF THE DRAWINGS 1, SPAD pixel; 11, SPAD; 12, register; 13, first switching device; 14, shaping circuit; 15, selector; 21, selection signal line; 22, clock signal line; 23, control signal line; 24, switching control signal line; 3, column scanning circuit; 31, gating circuit; 32, first demultiplexer; 33, first counter; 4, clock and control circuit; 41, second counter; 42, first clock circuit; 43, second clock circuit; 44, second demultiplexer; 5, signal processing circuit; 6, port circuit; 01, pixel layer; 02, logic layer. DETAILED DESCRIPTION

[0025] Embodiments of the present application will be described in detail below with reference to drawings, examples of which are shown in the accompanying drawings, in which the same or similar components have the same or similar reference numerals throughout. The embodiments described below by reference to the drawings are exemplary and are for the purpose of explanation only and are not to be understood as limiting the present application. All other embodiments obtained by those skilled in the art based on the embodiments in the present application without creative effort fall within the scope of the present application.

[0026] The terms "first", "second" in the description and claims of the present application can explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of "a plurality of" is two or more, unless otherwise specified and limited. In addition, "and / or" in the specification and claims means at least one of the connected objects, and " / " generally means that the front and rear associated objects are in an "or" relationship.

[0027] In the description of the present application, it should be noted that, unless otherwise specified and limited, the terms "mounting", "connection", "connection" should be understood in a broad sense, for example, it can be fixedly connected, or it can be detachably connected, or integrally connected; it can be mechanically connected, or it can be electrically connected; it can be directly connected, or it can be indirectly connected through an intermediate medium; it can be the communication inside two elements. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0028] At present, single photon avalanche diode (SPAD) is widely used in direct time-of-flight (dToF) image sensor (CIS) chip. The circuit structure and working principle of SPAD pixel in the related art are shown in FIG. 1.

[0029] Among them, the SPAD has no structural difference from the PPD used in the conventional CIS pixel, and the high bias voltage (VDD-VSS) makes the PPD work in the avalanche effect region (Avalanche Region). Compared with PPD, SPAD has higher sensitivity, and each photon (Photon) irradiated on SPAD will excite the corresponding electrical signal. In the typical SPAD pixel structure shown in FIG. 1, the SPAD receives photons to pull down the Vc voltage (called SPAD quenching), and then the energy charging clock jumps to pull up the Vc voltage (called SPAD re-charging) to make the Vc waveform a pulse signal. After rectification by the inverter (NOT gate, also called NOT gate), a square wave pulse signal Vp is formed. The PMOS transistor switch connected with the power supply voltage VDD is equivalent to a variable resistor, which mainly controls the size of the pulse signal flowing through the SPAD to prevent the Vc signal from being too large or too small. The Vp signal is connected to a counter (Counter), and in theory, the counter counts once after each photon is received by the SPAD. N photons reach the SPAD, and the counter counts N times.

[0030] Due to the SPAD pixel circuit architecture of the CMOS single photon image sensor based on the SPAD device, compared with the current mainstream CMOS image sensor based on the PPD pixel, a corresponding digital counter must be integrated in each SPAD pixel circuit. Therefore, the SPAD pixel is too large and difficult to be reduced. For example, a typical n-bit digital counter circuit design in a SPAD pixel is shown in FIG. 3. In order to output n-bit (S1S2…Sn) digital count, N D flip-flops are designed in series. The N D flip-flops are respectively denoted as DFF1-DFFN. The large size of the SPAD pixel leads to that a large number of SPAD pixels cannot be integrated in a unit chip area to improve the effective resolution of the CIS. At the same time, the SPAD pixel circuit array occupies a large area of the logic layer chip and must be one-to-one corresponding to the SPAD array in the SPAD pixel layer. Therefore, the auxiliary modules such as the image signal processing (ISP) module and the port module can only be placed outside the SPAD pixel circuit array, which leads to that the size of the SPAD pixel layer chip and the logic layer chip is inconsistent and affects the stacking and optical design of the CIS chip in the camera module.

[0031] In order to solve the above technical problems, the present application provides an image sensor and an electronic device. The technical concept of the present application is that a shift register is used in the SPAD pixel to realize a counter-free SPAD pixel circuit, thereby reducing the size of the SPAD pixel. Since no counter is used, the circuit modules required by the logic layer of the image sensor can be simplified, which is conducive to achieving the consistency of the size of the SPAD pixel layer chip and the logic layer chip and optimizing the stacking and optical design of the CIS chip in the camera module.

[0032] The image sensor and the electronic device provided by the embodiments of the present application will be described in detail below with reference to the accompanying drawings and specific embodiments.

[0033] Fig. 4 is a schematic diagram of a structure of an image sensor according to an embodiment of the present application. Fig. 5 is another schematic diagram of a structure of an image sensor according to an embodiment of the present application. As shown in Fig. 4 or Fig. 5, the image sensor provided by the embodiments of the present application includes a SPAD pixel array, the SPAD pixel array includes SPAD pixels 1 arranged in multiple rows and multiple columns, the SPAD pixel 1 includes a SPAD and a register 12, wherein the SPAD is marked as 11 in the figure, the register 12 is electrically connected with the SPAD, and the output end of the register 12 of the i-th SPAD pixel in the same column of SPAD pixels is electrically connected with the input end of the register 12 of the i+a-th SPAD pixel, and the output end of the last register in the multiple cascaded registers in the same column of SPAD pixels is connected with the input end of the column scanning circuit 3, where a is greater than or equal to 1. It can be understood that i is an integer, and the i-th SPAD pixel and the i+a-th SPAD pixel are any two SPAD pixels in the same column of SPAD pixels.

[0034] The SPAD generates a corresponding electrical signal after being exposed to light, the register is electrically connected with the SPAD, and the register can be used to transmit and temporarily store the signal generated by the SPAD after being exposed to light.

[0035] The output end of the register of the i-th SPAD pixel in the same column is electrically connected with the input end of the register of the i+a-th SPAD pixel, and the multiple registers electrically connected with each other can form a shift register. In the two registers connected with each other, the output end of the upper register is electrically connected with the input end of the lower register, the upper register can transfer the signal generated by the SPAD device after being exposed to light to the lower shift register, and then to the last shift register, and output to the column scanning circuit 3 by the last shift register. For example, the registers of the m1 SPAD pixels in the same column are cascaded with each other, the first register can transfer the signal generated by the SPAD device after being exposed to light to the second register, then the second register can transfer the signal to the third register, and so on, until the signal is transferred to the last register (such as the m1 register), and the signal can be output to the column scanning circuit 3 through the last register.

[0036] For example, the column scanning circuit 3 can be arranged outside the image sensor, or the image sensor includes the column scanning circuit 3.

[0037] For example, in the same column of SPAD pixels, the SPAD pixels without a cascaded relationship are connected with different input ends of the column scanning circuit 3. The SPAD pixels in different columns are connected with different input ends of the column scanning circuit 3, so that the column scanning circuit can distinguish the signals belonging to the SPAD pixels.

[0038] According to the image sensor provided in the embodiment of the present application, the SPAD pixel comprises a SPAD and a register, the register is electrically connected with the SPAD, and the registers of the plurality of SPAD pixels in the same column are cascaded with each other to form a shift register. The signal generated by the SPAD photosensitive can be transferred in a pixel-by-pixel manner through the cascaded register, and the signal is output to the column scanning circuit by the last-stage register. In the embodiment of the present application, the light signal captured by the SPAD device can be processed and output at high speed and effectively through the design of the register cascade of the SPAD pixels in the same column, so as to improve the pixel operation efficiency. The SPAD pixel does not contain a complex counter and a clock control circuit required by the counter, so that the circuit structure of the SPAD pixel is simplified, the unit area occupied by a single SPAD pixel is greatly reduced, so as to facilitate the integration of a larger number of SPAD pixels in a unit chip area to improve the effective resolution of the CIS. Moreover, the SPAD pixel does not contain a complex counter, so that the composition and complexity of the circuit on the chip are simplified, space is provided for more auxiliary modules, and it is possible to make the logic layer and the pixel layer chip size consistent.

[0039] In some optional embodiments, as shown in FIG. 4, when a is equal to 1, the registers 12 of the plurality of SPAD pixels 1 in the same column are electrically connected in sequence.

[0040] In this example, the register 12 in each row of SPAD pixels 1 in the same column of SPAD pixels is electrically connected to the corresponding register 12 in the SPAD pixel 1 located in the next row (Row). For example, all the SPAD pixels on each row (Row) can receive the same pixel control signal provided by the clock and control circuit 4, so as to realize row-by-row scanning.

[0041] The signal output by the SPAD on each row in the same column of SPAD pixels in a time period is received by the register 12 in the SPAD pixel and transferred to the register 12 in the SPAD pixel on the next row in the next time period. When the signal is transferred to the register 12 in the last row of SPAD pixels, the register 12 in the last row of SPAD pixels outputs the signal. For example, the output end of the register 12 in the last row of SPAD pixels is electrically connected to the column scanning circuit 3, and the register 12 in the last row of SPAD pixels can output the signal to the column scanning circuit 3. The column scanning circuit 3 can continuously scan the SPAD pixel signal transmitted by each column and output to the signal processing circuit 5, and finally, the final signal is output to the outside of the chip by the port circuit 6.

[0042] For example, in the same column, in a scanning frame, the registers 12 in the first row to the last row of SPAD pixels transfer the signals generated by the first row of SPAD pixels in sequence, and the signals generated by the first row of SPAD pixels are output by the register 12 in the last row of SPAD pixels. Then, the registers 12 in the second row to the last row of SPAD pixels transfer the signals generated by the second row of SPAD pixels in sequence, and the signals generated by the second row of SPAD pixels are output by the register 12 in the last row of SPAD pixels. Then, the registers 12 in the third row to the last row of SPAD pixels transfer the signals generated by the third row of SPAD pixels in sequence, and the signals generated by the third row of SPAD pixels are output by the register 12 in the last row of SPAD pixels. Until the signals generated by the last row of SPAD pixels are directly output by the register 12 in the last row of SPAD pixels.

[0043] In some optional embodiments, as shown in FIG. 5, when a>1, the output end of the register 12 of the i+b th SPAD pixel 1 in the same column of SPAD pixels 1 is electrically connected to the input end of the register 12 of the i+a+b th SPAD pixel 1, and b is any one of 1 to a-1. That is, the register of the embodiment of the present application is interlaced cascaded.

[0044] As an example, a=2, and b=1. Taking an example of a pixel array having 8 rows of SPAD pixels.

[0045] When i=1, in the same column of SPAD pixels, the output end of the register 12 of the first row of SPAD pixels is electrically connected to the input end of the register 12 of the third row of SPAD pixels, and the output end of the register 12 of the second row of SPAD pixels is electrically connected to the input end of the register 12 of the fourth row of SPAD pixels.

[0046] When i=5, in the same column of SPAD pixels, the output end of the register 12 of the fifth row of SPAD pixels is electrically connected to the input end of the register 12 of the seventh row of SPAD pixels, and the output end of the register 12 of the sixth row of SPAD pixels is electrically connected to the input end of the register 12 of the eighth row of SPAD pixels.

[0047] In this example, in the same column, the registers 12 in the 1st, 3rd, 5th, and 7th rows of SPAD pixels constitute a first shift register, which sequentially shifts the signals generated by the 1st, 3rd, 5th, and 7th rows of SPAD pixels, and outputs the signals by the register 12 in the 7th row of SPAD pixels. The registers 12 in the 2nd, 4th, 6th, and 8th rows of SPAD pixels constitute a second shift register, which sequentially shifts the signals generated by the 2nd, 4th, 6th, and 8th rows of SPAD pixels, and outputs the signals by the register 12 in the 8th row of SPAD pixels.

[0048] For example, in the above example, the 1st and 2nd rows of SPAD pixels are scanned simultaneously, then the 3rd and 4th rows of SPAD pixels are scanned simultaneously, then the 5th and 6th rows of SPAD pixels are scanned simultaneously, and finally the 7th and 8th rows of SPAD pixels are scanned simultaneously. That is, in this example, 2 rows of SPAD pixels can be scanned simultaneously.

[0049] As another example, a = 3, and b = 1 or 2. For example, the pixel array has 12 rows of SPAD pixels.

[0050] When i = 1, in the same column of SPAD pixels, the output end of the register 12 of the 1st row of SPAD pixels is electrically connected to the input end of the register 12 of the 4th row of SPAD pixels; when b = 1, the output end of the register 12 of the 2nd row of SPAD pixels is electrically connected to the input end of the register 12 of the 5th row of SPAD pixels; and when b = 2, the output end of the register 12 of the 3rd row of SPAD pixels is electrically connected to the input end of the register 12 of the 6th row of SPAD pixels.

[0051] When i = 7, in the same column of SPAD pixels, the output end of the register 12 of the 7th row of SPAD pixels is electrically connected to the input end of the register 12 of the 10th row of SPAD pixels; when b = 1, the output end of the register 12 of the 8th row of SPAD pixels is electrically connected to the input end of the register 12 of the 11th row of SPAD pixels; and when b = 2, the output end of the register 12 of the 9th row of SPAD pixels is electrically connected to the input end of the register 12 of the 12th row of SPAD pixels.

[0052] In this example, the registers 12 in the 1st, 4th, 7th and 10th rows of SPAD pixels in the same column form a third shift register, which sequentially transfers the signals generated by the 1st, 4th, 7th and 10th rows of SPAD pixels, and outputs the signals by the register 12 in the 10th row of SPAD pixels. The registers 12 in the 2nd, 5th, 8th and 11th rows of SPAD pixels form a fourth shift register, which sequentially transfers the signals generated by the 2nd, 5th, 8th and 11th rows of SPAD pixels, and outputs the signals by the register 12 in the 11th row of SPAD pixels. The registers 12 in the 3rd, 6th, 9th and 12th rows of SPAD pixels form a fifth shift register, which sequentially transfers the signals generated by the 3rd, 6th, 9th and 12th rows of SPAD pixels, and outputs the signals by the register 12 in the 12th row of SPAD pixels.

[0053] In this example, three rows of SPAD pixels can be scanned at the same time. For example, in the above example, the 1st, 2nd and 3rd rows of SPAD pixels are scanned at the same time, then the 4th, 5th and 6th rows of SPAD pixels are scanned at the same time, then the 7th, 8th and 9th rows of SPAD pixels are scanned at the same time, and finally the 10th, 11th and 12th rows of SPAD pixels are scanned at the same time.

[0054] It can be understood that when a > 1, that is, when the registers 12 are in the interlaced cascade state, a rows of SPAD pixels can be scanned at the same time. Scanning multiple rows of pixels at the same time can speed up the scanning speed.

[0055] In some embodiments, as shown in FIG. 6, the SPAD pixel further includes a first switching device 13, a shaping circuit 14 and a selector 15, and the register 12 includes a D flip-flop. The shaping circuit 14 includes a NOT gate, and the selector 15 includes a multiplexer (MUX). The shaping circuit 14 is configured to convert the sensing signal of the SPAD into a square wave pulse signal, and the selector 15 is configured to selectively output the signal at the first input end or the second input end thereof.

[0056] The first switching device 13 is connected in series with the SPAD. Specifically, the first end of the first switching device 13 is configured to be connected to a first voltage VDD, the second end of the first switching device 13 is configured to be connected to a control signal S CLK , and the third end of the first switching device 13 is connected to the first end of the SPAD. The second end of the SPAD is configured to be connected to a second voltage VSS, and the second voltage is less than the first voltage.

[0057] The first switching device 13 can be implemented by a MOS tube, for example, which can be a PMOS or an NMOS. When the PMOS is selected, the source of the PMOS is connected to the first voltage, which can be a power supply voltage VDD, the drain is connected to the cathode of the SPAD, and the gate is connected to the control signal S CLKWhen the NMOS is selected, the drain of the NMOS is connected to a first voltage, i.e. a power supply voltage VDD, the source is connected to the cathode of the SPAD, and the gate is connected to a control signal S CLK The anode of the SPAD can be connected to a second voltage, which can be ground or a negative voltage VSS.

[0058] The connection point of the first switching device 13 and the SPAD is electrically connected to the input terminal of the shaping circuit 14, the output terminal of the shaping circuit 14 is electrically connected to the first input terminal of the selector 15, the output terminal of the selector 15 is electrically connected to the input terminal of the D flip-flop, and the second input terminal of the selector 15 in the next-stage SPAD pixel 1 is electrically connected to the output terminal of the D flip-flop in the previous-stage SPAD pixel 1.

[0059] The selection control terminal of the selector 15 is connected to a selection signal S SEL Under the control of the selection signal S SEL , the selector 15 transmits the signal from the shaping circuit 14 to the D flip-flop, or transmits the signal output from the previous-stage D flip-flop to the current-stage D flip-flop.

[0060] In this embodiment, the signal generated by the SPAD device under light is converted into a digital signal by the shaping circuit 14, and then transmitted to the first input terminal of the selector 15, and then transmitted to the D flip-flop through the selector 15. The signal SOUT output by the D flip-flop in the previous-stage SPAD pixel can be transmitted to the second input terminal of the selector MUX in the next-stage SPAD pixel, and then transmitted to the D flip-flop in the next-stage SPAD pixel through the selector 15. That is, under the driving of the clock signal of the D flip-flop, the D flip-flops in a column of pixels form a shift register and transfer the S OUT signal in the previous row of pixels to the D flip-flop in the next row of pixels in a unit of time, and this cycle continues until the last-stage D flip-flop, and the signal is output by the last-stage D flip-flop. For example, the last-stage D flip-flop outputs the signal to a column scan circuit module. Of course, in other examples, the signal output by the register can also be read by other reading modules, and the other reading modules can be arranged outside the image sensor.

[0061] In this embodiment, the selector 15 and the D flip-flop are arranged to realize the step-by-step transmission of the signal, and the structure is relatively simple and the occupied area is small.

[0062] It can be understood that for any SPAD pixel, if it needs to transfer the S OUTIf it needs to transfer the signal generated by its own SPAD device, the first input end of the SPAD in-pixel selector 15 is in communication with the input end of the D flip-flop.

[0063] In the plurality of cascaded SPAD pixels, the second input end of the first-stage SPAD in-pixel selector 15 can be left unconnected, or the first-stage SPAD in-pixel can not include a selector, and the output end of the shaping circuit 14 in the first-stage SPAD in-pixel is directly connected to the input end of the D flip-flop.

[0064] In some embodiments, as shown in FIG. 6, the selection control ends of the plurality of selectors 15 in the same row of SPAD pixels 1 are electrically connected to the same selection signal line 21, which is used to transmit the selection signal S SEL The clock ends of the plurality of D flip-flops in the same row of SPAD pixels 1 are electrically connected to the same clock signal line 22, which is used to transmit the clock signal S D_CLK required by the D flip-flop; and the selection control ends of the plurality of selectors 15 in different rows of SPAD pixels 1 are electrically connected to different selection signal lines 21, and the clock ends of the plurality of D flip-flops in different rows of SPAD pixels 1 are electrically connected to different clock signal lines 22.

[0065] In this example, the input selection control of all the selectors 15 in a row of SPAD pixels shares one selection signal S SEL , and all the D flip-flops in a row of SPAD pixels share one D flip-flop clock signal S D_CLK . The selection control signal S SEL of the selector 15 of the SPAD pixel and the clock signal S D_CLK of the D flip-flop are row-parallel (Row Parallel) signals.

[0066] For example, the image sensor can be provided with a clock and control circuit 4, and the selection signal S SEL and the clock signal S D_CLK required by the D flip-flop can be provided by the clock and control circuit 4. Of course, in other examples, the selection signal S SEL and the clock signal S D_CLK required by the D flip-flop can also be provided by other modules, and the modules are arranged outside the image sensor.

[0067] It can be understood that at the same time, the states of all the selector MUXs of the same row of SPAD pixels are the same, that is, all the selector MUXs of the same row of SPAD pixels output the signal at the first input end thereof, or all the selector MUXs of the same row of SPAD pixels output the signal at the second input end thereof. At the same time, the states of all the D flip-flops of the same row of SPAD pixels are the same, that is, all the D flip-flops of the same row of SPAD pixels output the signal generated by the photosensitive of the previous row of SPAD pixels, or all the D flip-flops of the same row of SPAD pixels output the signal generated by the photosensitive of the current row of SPAD pixels.

[0068] In some other embodiments, as shown in FIG. 7, the selection control ends of the plurality of selectors 15 in the same column of SPAD pixels 1 are electrically connected with the same selection signal line 21, and the selection signal line 21 is used for transmitting the selection signal S SEL The clock ends of the plurality of D flip-flops in the same column of SPAD pixels 1 are electrically connected with the same clock signal line 22, and the clock signal line 22 is used for transmitting the clock signal S D_CLK required by the D flip-flop; and the selection control ends of the plurality of selectors 15 in different columns of SPAD pixels are electrically connected with different selection signal lines 21, and the clock ends of the plurality of D flip-flops in different columns of SPAD pixels are electrically connected with different clock signal lines 22.

[0069] In this example, the difference between the example shown in FIG. 7 and FIG. 6 includes that the input selection control of all the selectors 15 in a column of SPAD pixels share one selection signal S SEL , and all the D flip-flops in a column of SPAD pixels share one D flip-flop clock signal S D_CLK . The selection control signal S SEL of the selector 15 of the SPAD pixel and the clock signal S D_CLK of the D flip-flop are column parallel signals.

[0070] In the column parallel design mode, a column of SPAD pixels will receive the same selection signal S SEL and clock signal S D_CLK . When a column of SPAD pixels is selected, the selection signal S SEL and the clock signal S D_CLKThe shift register in each column of SPAD pixels is controlled to shift the signal generated by the SPAD device in each pixel until it is output to the D flip-flop in the last stage of SPAD pixels and output from the D flip-flop in the last stage of SPAD pixels, for example, to the column scanning circuit. Since the signal generated by all the SPAD pixels in each column must be output before moving to the next column, in the embodiments of the present application, the circuit for reading the output signal of the register (for example, the column scanning circuit 3) will work at a lower scanning frequency, and the energy efficiency of the column scanning circuit 3 and the corresponding circuit will be greatly improved when implementing the reading and output steps of the SPAD pixels. The workload of the column scanning circuit 3 can be greatly reduced.

[0071] For example, as shown in FIG. 6 or FIG. 7, the switch control signal S CLK The on and off of the first switch device 13 (such as PMOS) in the SPAD is controlled, and the control ends of the plurality of switch elements in the same row of SPAD pixels 1 are electrically connected to the same switch control signal line 23, and the switch control signal line 23 is used to transmit the switch control signal S CLK .

[0072] The basic structure and implementation of the clock and control circuit 4 in the structure shown in FIG. 6 and FIG. 7 can be consistent. The difference includes: in FIG. 6, the selection control signal S SEL of the selector 15 of the SPAD pixel, the clock signal S D_CLK of the D flip-flop, and the switch control signal S CLK are all row parallel signals, and in FIG. 7, the selection control signal S SEL of the selector 15 of the SPAD pixel, the clock signal S D_CLK of the D flip-flop are column parallel signals, and the switch control signal S CLK is a row parallel signal.

[0073] In some embodiments, as shown in FIG. 4, the image sensor further includes a column scanning circuit 3, and the output end of the last stage register 12 in the plurality of cascaded registers 12 in the same column of SPAD pixels 1 is connected to the input end of the column scanning circuit 3. In the case of a=1, that is, in the case of the registers of the plurality of SPAD pixels in the same column being electrically connected in turn, the plurality of input ends of the column scanning circuit 3 correspond one-to-one to the plurality of SPAD pixel columns.

[0074] For example, the image sensor includes N columns of SPAD pixels 1, and the column scanning circuit 3 can include N inputs, and the N inputs of the column scanning circuit 3 and the N columns of SPAD pixels 1 are electrically connected one by one. In this way, in the case of line-by-line scanning, the column scanning circuit 3 can simultaneously access the signals output by the same row of SPAD pixels in the N columns of SPAD pixels; in the case of multi-line simultaneous scanning, the column scanning circuit 3 can simultaneously access the signals output by multiple rows of SPAD pixels in the N columns of SPAD pixels.

[0075] In other embodiments, as shown in FIG. 5, a is greater than 1, the output end of the register 12 of the i+bth SPAD pixel in the same column of SPAD pixels is electrically connected to the input end of the register 12 of the i+a+bth SPAD pixel, b is any one of 1 to a-1, and the output end of the last register 12 cascaded by the register 12 of the ith SPAD pixel is connected to the output end of the last register 12 cascaded by the register 12 of the i+bth SPAD pixel, and the output end is connected to different inputs of the column scanning circuit 3.

[0076] For example, in FIG. 5, the registers 12 of the odd-numbered SPAD pixels in the same column of SPAD pixels are cascaded, and the registers 12 of the even-numbered SPAD pixels in the same column of SPAD pixels are cascaded, and the last register 12 of the odd-numbered SPAD pixels and the last register 12 of the even-numbered SPAD pixels are connected to different inputs of the column scanning circuit 3. For example, a column has 8 SPAD pixels, wherein the registers 12 of the 1st, 3rd, 5th, and 7th SPAD pixels are cascaded, the registers 12 of the 2nd, 4th, 6th, and 8th SPAD pixels are cascaded, and the register 12 of the 7th SPAD pixel and the register 12 of the 8th SPAD pixel in the same column are connected to different inputs of the column scanning circuit 3.

[0077] In addition, it can be understood that the last register 12 of different columns is connected to different inputs of the column scanning circuit 3.

[0078] Fig. 5, the input terminals of the column scanning circuit 3 can be doubled. Alternatively, in other examples, the number of column scanning circuits 3 can be doubled in a cascaded manner of the registers 12 shown in Fig. 5. For example, the registers 12 of the odd-numbered SPAD pixels in the same column are cascaded, the registers 12 of the even-numbered SPAD pixels in the same column are cascaded, and two column scanning circuits 3 can be provided, one of which is connected with the registers 12 of the odd-numbered SPAD pixels and the other of which is connected with the registers 12 of the even-numbered SPAD pixels. As shown in Fig. 4, the image sensor further includes a signal processing circuit 5 and a port circuit 6, the column scanning circuit 3 transmits the signal output by the SPAD pixels to the signal processing circuit 5, the signal processing circuit 5 processes the signal, and the processed signal is output through the port circuit 6.

[0079] As an example, as shown in Fig. 8, the column scanning circuit 3 includes N input terminals, and the column scanning circuit 3 includes a gating circuit 31 and a first demultiplexer 32. In the case where the SPAD pixel array includes N columns of SPAD pixels, the first demultiplexer 32 can be an N-bit demultiplexer (N-bit DEMUX).

[0080] The gating circuit 31 includes N switches, which are marked as SW1-SWN in Fig. 8. The first ends of the N switches correspond to the N input terminals one by one, i.e., the first ends of the N switches are respectively the N input terminals, and the second ends of the N switches are electrically connected to each other. The first demultiplexer 32 is configured to control the N switches to be turned on in turn.

[0081] As an example, please refer to Figs. 4 and 8, in the case where a=1, i.e., the registers of the plurality of SPAD pixels in the same column are connected in turn, for a SPAD pixel array having N columns (Columns), the output signal S OUT of each column of SPAD pixels can be transmitted to the column scanning circuit 3. In the column scanning circuit 3, there is a controllable switch (SW1, SW2...SWN) corresponding to each column of SPAD pixels on the link. The control of each controllable switch comes from an N-bit first demultiplexer 32. For example, under the control of an N-bit first counter 33 or an external control signal, the first demultiplexer 32 outputs the control signals (SW1, SW2...SWN) of the N switches to control the opening and closing of the controllable switches. The links corresponding to all the columns of SPAD pixels are merged after passing through the respective controllable switches and are output in one way. In a unit time, only the link corresponding to one column of SPAD pixels is turned on and off. Therefore, after N unit times, the signals of all the columns are output. All the output signals S OUTThe signals are transmitted to the signal processing circuit 5 for subsequent signal processing.

[0082] As another example, as shown in FIG. 5, a is greater than 1, the output end of the register 12 of the i+bth SPAD pixel in the same column of SPAD pixels is electrically connected with the input end of the register 12 of the i+a+bth SPAD pixel, and b is any one of 1 to a-1. Taking a=2 as an example, the registers 12 of the odd-numbered SPAD pixels in the same column of SPAD pixels are cascaded, and the registers 12 of the even-numbered SPAD pixels in the same column of SPAD pixels are cascaded, and then the column scanning circuit 3 needs to be configured with two input ends for a column of SPAD pixels. For example, there are 100 columns of SPAD pixels, and then the column scanning circuit 3 can be configured with 200 input ends, and correspondingly, the column scanning circuit 3 can be configured with 200 switches. Among them, the two switches corresponding to the same column of SPAD pixels can be turned on at the same time, or can be turned on at different times.

[0083] In some embodiments, as shown in FIG. 4, the image sensor further includes a clock and control circuit 4 electrically connected with the SPAD pixel 1. The clock and control circuit 4 is used to provide the clock signal and the control signal required by the SPAD pixel 1.

[0084] As an example, as shown in FIG. 9, the clock and control circuit 4 includes a second counter 41, a first clock circuit 42, a second clock circuit 43, and a plurality of second demultiplexers 44. For a pixel array with M rows of SPAD pixels, the second counter 41 can be an M-bit counter, and the second demultiplexer 44 is an M-bit demultiplexer.

[0085] The second counter 41 is electrically connected with the plurality of second demultiplexers 44, one of the second demultiplexers 44 is electrically connected with the first clock circuit 42, and another of the second demultiplexers 44 is electrically connected with the second clock circuit 43. The plurality of second demultiplexers 44 outputs the clock and control signal required by the SPAD pixel under the control of the second counter 41, the first clock circuit 42 and the second clock circuit 43.

[0086] For example, one of the second demultiplexers 44 outputs the selection control signal S SEL , another of the second demultiplexers 44 outputs the clock signal S D_CLK , and another of the second demultiplexers 44 outputs the switch control signal S CLK . For example, the selection control signal S SEL required by the in-pixel selector 15 is provided by an M-bit second counter 41 controlling an M-bit second demultiplexer 44. Similarly, the clock signal S D_CLKThe switching control signal S of the SPAD pixel-internal switching element (e.g., PMOS) is provided by an M-bit second counter 41 and a first clock circuit 42 controlling another M-bit second demultiplexer 44. CLK The clock signal is provided by an M-bit second counter 41 and a second clock circuit 43, which controls another M-bit second demultiplexer 44. Additionally, the clock and control circuit 4 may include a column scan circuit controller 45, which can also provide the counter clock signal and control signal required by the column scan circuit 3. For example, the clock and control circuit 4 may further include a column scan circuit controller 45, which provides the counting clock signal / control signal required by the column scan circuit 3.

[0087] In some embodiments, as shown in FIG4, the image sensor includes a pixel layer 01 and a logic layer 02. In the figures marked with 01 and 02, the dashed box marked 01 represents the pixel layer, and the dashed box marked 02 represents the logic layer. The pixel array is disposed on the pixel layer 01, and the column scanning circuit 3, clock and control circuit 4, signal processing circuit 5, and port circuit 6 of the image sensor are disposed on the logic layer 02. It is understood that the SPAD device and register 12 in the SPAD pixel 1 are located on the pixel layer 01. When the SPAD pixel includes a first switching device 13, a shaping circuit 14, and a selector 15, the first switching device 13, the shaping circuit 14, and the selector 15 are also located on the pixel layer 01.

[0088] In this embodiment, the circuit layout on the logic layer 02 chip is modified, and no digital counters or similar circuits are used at all. That is, the logic layer 02 no longer has a counter that corresponds one-to-one with the SPAD pixels. This greatly simplifies the composition and complexity of the circuit on the logic layer 02 chip, which can provide space for more auxiliary modules and also makes it possible for the logic layer 02 chip to be the same size as the pixel layer 01 chip.

[0089] In some embodiments, pixel layer 01 and logic layer 02 are connected via through-silicon vias (TSVs), or they are connected via bonding, such as copper-copper bonding. It is understood that signals between pixel layer 01 and logic layer 02 are transmitted via TSVs or bonding terminals.

[0090] In some embodiments, as shown in FIG10, SPAD pixel 1 includes a plurality of SPADs connected in parallel. For example, the plurality of SPADs within the same SPAD pixel 1 are all electrically connected to a first switching device 13, and the plurality of SPADs share a first switching device 13.

[0091] For some high-resolution image scenes, the pixels on the CIS chip can use a binning structure. For example, for a Y-by-1 pixel, the design of a single SPAD pixel can include Y SPAD devices. As shown in FIG. 10, each SPAD device is connected to a separate gate switch transistor TX. FIG. 10 takes Y gate switch transistors TX as an example, which are TX1-TXY, respectively. The gate switch transistor is controlled by an independent switch control signal S TX Control. The switch control signal S TX is generated by the clock and control circuit 4 and conducted to each row of SPAD pixels through a row of parallel switch control signal lines 24. The signals generated by all SPAD devices are collected after passing through the respective separate gate switch transistors, share a quenching circuit (for example, a PMOS switch transistor) and subsequent shaping circuit (NOT) and selector MUX and D flip-flop. For different light scenes, one or more SPAD devices generate analog pulse signals that increase in time domain. For example, in a dark scene, all SPAD devices are enabled to increase the unit photosensitive area. After the corresponding gate switch transistor of each SPAD device is turned on and connected to the PMOS transistor to complete the charging process after quenching. In a bright scene, because the number of photons is large, one SPAD device can be enabled by controlling the switch control signal STX, and the transistors TX of the other SPAD devices remain disconnected.

[0092] It can be understood that the gate switch transistors TX1-TXy can be electrically connected to the clock and control circuit 4 through different signal lines, respectively.

[0093] Based on the same inventive concept, the embodiments of the present application also provide an electronic device, which includes a central processing unit and an image sensor as described in any of the above embodiments. It can be understood that the electronic device has the beneficial effects of the image sensor provided by the embodiments of the present application, and specific descriptions can be referred to the specific descriptions of the image sensor in the above embodiments, which will not be repeated here.

[0094] For example, as shown in FIG. 11, the electronic device includes N compact camera modules (CCM), which are CCM1-CCMN, respectively, and each CCM is provided with an image sensor; each image sensor is connected to an image signal processing (ISP) module in the central processing unit.

[0095] The image sensor CIS chip is a photosensitive component and is a core component of the compact camera module CCM. A system structure of a typical mobile communication device represented by a mobile phone is shown in FIG. 11. N CCM module systems can be provided, each of which is equipped with a CIS chip, and the CIS chips are in bidirectional communication with an ISP module in an application processor (AP) or system on chip (SoC) through a port link. The AP / SoC sends a control signal to the CIS chip in each CCM, and the CIS chip returns an image signal to the ISP module for backend processing.

[0096] It should be noted that the embodiment is an implementation of an electronic device corresponding to the embodiment shown in FIG. 4, and the specific implementation can refer to the related description in the foregoing embodiment and achieve the same technical effect. To avoid repetition, details are not described herein.

[0097] The electronic device can be a terminal or other device. For example, the electronic device can be a mobile phone, a tablet computer, a notebook computer, a palm computer, a vehicle-mounted electronic device, a mobile Internet device (MID), an augmented reality (AR) / virtual reality (VR) device, a robot, a wearable device, an ultra-mobile personal computer (UMPC), a netbook, or a personal digital assistant (PDA), and can also be a server, a network attached storage (NAS), a personal computer (PC), a television (TV), a teller machine, or a self-service machine. The embodiment is not limited in this regard.

[0098] In the description of the present specification, the description of the terms "one embodiment", "some embodiments", "exemplary embodiment", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In the present specification, the exemplary description of the above terms does not necessarily mean the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.

[0099] While embodiments of the application have been shown and described, it is to be understood that the embodiments described are merely divergences of the principles and application of the present application and that numerous modifications, changes, substitutions, and alterations can be made thereto without departing from the spirit and scope of the present application, which is defined by the following claims and their equivalents.

Claims

1. An image sensor comprising a SPAD pixel array, the SPAD pixel array comprising SPAD pixels arranged in multiple rows and multiple columns, the SPAD pixel comprising a SPAD and a register, the register being electrically connected with the SPAD, and an output terminal of the register of an i th SPAD pixel in a same column of SPAD pixels being electrically connected with an input terminal of the register of an i+a th SPAD pixel, an output terminal of a last register in a plurality of cascaded registers in the same column of SPAD pixels being connected with an input terminal of a column scanning circuit, where the a is greater than or equal to 1.

2. The image sensor of claim 1, wherein, The a is equal to 1, and the registers of a plurality of the SPAD pixels in the same column are electrically connected in sequence.

3. The image sensor of claim 1, wherein, The a is greater than 1, an output terminal of the register of an i+b th SPAD pixel in the same column of SPAD pixels being electrically connected with an input terminal of the register of an i+a+b th SPAD pixel, b being any one of 1 to a-1. 4.The image sensor according to any one of claims 1 to 3, the SPAD pixel further comprising a first switching device, a shaping circuit, a selector, the register comprising a D flip-flop; the first switching device and the SPAD being connected in series, a connection point of the first switching device and the SPAD being electrically connected with an input terminal of the shaping circuit, an output terminal of the shaping circuit being electrically connected with a first input terminal of the selector, an output terminal of the selector being electrically connected with an input terminal of the D flip-flop, a second input terminal of the selector in a next level SPAD pixel being electrically connected with an output terminal of the D flip-flop in a previous level SPAD pixel among two SPAD pixels to which two cascaded registers belong; the shaping circuit being configured to convert a sensing signal of the SPAD into a square wave pulse signal, and the selector being configured to selectively output a signal of the first input terminal or the second input terminal thereof.

5. The image sensor of claim 4, wherein, selection control terminals of a plurality of the selectors in the same row of SPAD pixels being electrically connected with a same selection signal line, and clock terminals of a plurality of the D flip-flops in the same row of SPAD pixels being electrically connected with a same clock signal line; and selection control terminals of a plurality of the selectors in different rows of SPAD pixels being electrically connected with different selection signal lines, and clock terminals of a plurality of the D flip-flops in different rows of SPAD pixels being electrically connected with different clock signal lines.

6. The image sensor of claim 4, wherein, selection control terminals of a plurality of the selectors in the same column of SPAD pixels being electrically connected with a same selection signal line, and clock terminals of a plurality of the D flip-flops in the same column of SPAD pixels being electrically connected with a same clock signal line; and selection control terminals of a plurality of the selectors in different columns of SPAD pixels being electrically connected with different selection signal lines, and clock terminals of a plurality of the D flip-flops in different columns of SPAD pixels being electrically connected with different clock signal lines. 7.The image sensor according to any one of claims 1 to 3, further comprising the column scanning circuit; when the a is equal to 1, a plurality of input terminals of the column scanning circuit correspond to a plurality of columns of SPAD pixels one by one. Or, the a is greater than 1, the output end of the register of the i+bth SPAD pixel in the same column of SPAD pixels is electrically connected with the input end of the register of the i+a+bth SPAD pixel, b is any one of 1 to a-1, and the output end of the last register cascaded by the register of the i SPAD pixel is connected with the output end of the last register cascaded by the register of the i+bth SPAD pixel and different input ends of the column scanning circuit.

8. The image sensor of claim 7, wherein, The column scanning circuit comprises N input ends, and the column scanning circuit comprises a gating circuit and a first demultiplexer. The gating circuit comprises N switches, the first end of the N switches corresponds to the N input ends one by one, the second end of the N switches is electrically connected with each other, and the first demultiplexer is used for controlling the N switches to be turned on in turn.

9. The image sensor according to any one of claims 1 to 3, further comprising a clock and control circuit, the clock and control circuit being electrically connected with the SPAD pixels. The clock and control circuit comprises a counter, a first clock circuit, a second clock circuit and a plurality of second demultiplexers, the counter, the first clock circuit and the second clock circuit are electrically connected with the plurality of second demultiplexers, and the plurality of second demultiplexers output clock and control signals required by the SPAD pixels under the control of the counter, the first clock circuit and the second clock circuit.

10. The image sensor according to any one of claims 1 to 3, wherein, The image sensor comprises a pixel layer and a logic layer, the SPAD pixel array is arranged in the pixel layer, and the column scanning circuit, the clock and control circuit, the signal processing circuit and the port circuit of the image sensor are arranged in the logic layer.

11. The image sensor according to any one of claims 1 to 3, wherein, The SPAD pixel comprises a plurality of SPADs, and the plurality of SPADs are connected in parallel.

12. An electronic device comprising a central processing unit and the image sensor according to any one of claims 1 to 11.

Images