Display panel and display apparatus

Abstract

Disclosed in the present invention are a display panel and a display apparatus. The display panel comprises a driving circuit. A shift register of the driving circuit comprises: a shift control module receiving an input signal, a first clock signal, and a second clock signal, and controlling signals of a first node and of a second node; a shift output module receiving the signal of the first node, the signal of the second node, a first level signal, and a second level signal, and controlling an output shift signal; an output control module receiving an output control signal and the shift signal, and controlling a signal of a third node; a transmission control module receiving the signal of the second node and the signal of the third node, and controlling a signal of a fourth node; a potential holding module receiving a fixed level signal, and maintaining the signal of the third node; and a drive output module receiving the signal of the fourth node, the signal of the first node, the first level signal, and the second level signal, and controlling an output gate driving signal, wherein the fixed level signal is at least different from the second level signal.

Description

Display panel and display device

[0001] The present application claims priority from the Chinese patent application No. 202411262755.9 filed on September 09, 2024, and entitled "Display panel and display device", the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] Embodiments of the present application relate to the technical field of display, in particular to a display panel and a display device. BACKGROUND

[0003] A plurality of pixels arranged in an array are usually provided in the display panel, and each pixel is scanned row by row by using a driving circuit, so that data signals and the like are written into each pixel row by row, so that each pixel can display and emit light according to the data signals received thereby, thereby presenting a corresponding display image.

[0004] Usually, a plurality of stages of shift registers are provided in the driving circuit, and by controlling the signals of corresponding nodes in each stage of shift registers, the gate drive signals output by the shift registers can be controlled. However, since some nodes in the shift registers are associated with the gate drive signals, when the some nodes change, the gate drive signals will fluctuate, thereby affecting the accuracy of the gate drive signals output by the shift registers, and further affecting the display quality of the display panel. SUMMARY

[0005] Embodiments of the present application provide a display panel and a display device to improve the influence of node signal jump on the gate drive signals, improve the accuracy of the gate drive signals output by the shift registers, and thereby improve the display quality of the display panel.

[0006] In a first aspect, the present application provides a display panel, comprising: a driving circuit; the driving circuit comprises N stages of shift registers connected in cascade;

[0007] The shift register comprises:

[0008] a shift control module configured to receive at least an input signal, a first clock signal and a second clock signal, and control a signal of a first node and a signal of a second node;

[0009] a shift output module configured to receive at least the signal of the first node, the signal of the second node, a first level signal and a second level signal, and control an output shift signal; the shift signal output by the shift register of the xth stage is the input signal received by the shift register of the yth stage, 1≤x≤N, 1≤y≤N, x≠y, and x, y and N are positive integers;

[0010] an output control module configured to receive at least the output control signal and the shift signal, and control a path of transmission of the output control signal to the third node under control of the shift signal;

[0011] a transmission control module configured to receive at least a signal of the second node and a signal of the third node, and control a signal of the fourth node;

[0012] a potential maintaining module configured to receive a fixed level signal, and maintain the signal of the third node;

[0013] a driving output module configured to receive at least the signal of the fourth node, the signal of the first node, the first level signal and the second level signal, and control an output gate driving signal;

[0014] wherein the fixed level signal is different from at least the second level signal.

[0015] In a second aspect, the present application further provides a display device comprising the display panel.

[0016] The technical scheme of the present application, by setting the cascaded N-stage shift register in the driving circuit, and the shift control module in each stage of the shift register can control the shift output module to output the shift signal as the input signal of the other stage of the shift register, and the shift signal is used to control the output control module to transmit the output control signal to the third node, so that the transmission control module can control the driving output module to output the gate driving signal according to the signal of the third node, so that in the same shift register, the shift output module for signal stage transmission and the driving output module for outputting the gate driving signal are two different modules, so that the signal stage transmission and the output of the gate driving signal are independent of each other, thereby ensuring that the signal stage transmission between the shift registers can be flexibly controlled while the gate driving signal output by each stage of the shift register, and further enabling the display panel to meet diversified display requirements and broaden the application scenarios of the display panel. At the same time, the potential maintaining module is also arranged in the shift register to receive the fixed level signal and maintain the signal of the third node, and the fixed level signal is different from at least the second level signal, so as to prevent the fluctuation of the second level signal caused by the change of the signal of the third node from affecting the gate driving signal output by the driving output module, thereby facilitating to improve the accuracy of the gate driving signal output by the driving output module, and further facilitating to improve the display quality of the display panel. BRIEF DESCRIPTION OF DRAWINGS

[0017] FIG. 1 is a structural schematic diagram of a display panel according to an embodiment of the present application;

[0018] FIG. 2 is a structural schematic diagram of a driving circuit according to an embodiment of the present application;

[0019] Figure 3 is a schematic diagram of a shift register provided in an embodiment of the present invention;

[0020] Figure 4 is a schematic diagram of another shift register provided in an embodiment of the present invention;

[0021] Figure 5 is a schematic diagram of another driving circuit provided in an embodiment of the present invention;

[0022] Figure 6 is a schematic diagram of another driving circuit provided in an embodiment of the present invention;

[0023] Figure 7 is a schematic diagram of another shift register provided in an embodiment of the present invention;

[0024] Figure 8 is a schematic diagram of another shift register provided in an embodiment of the present invention.

[0025] Figure 9 is a schematic diagram of another shift register provided in an embodiment of the present invention;

[0026] Figure 10 is a schematic diagram of another driving circuit provided in an embodiment of the present invention;

[0027] Figure 11 is a schematic diagram of another driving circuit provided in an embodiment of the present invention;

[0028] Figure 12 is a schematic diagram of another driving circuit provided in an embodiment of the present invention;

[0029] Figure 13 is a driving timing diagram of a display panel provided in an embodiment of the present invention;

[0030] Figure 14 is a driving timing diagram of another display panel provided in an embodiment of the present invention;

[0031] Figure 15 is a schematic diagram of a pixel structure provided in an embodiment of the present invention;

[0032] Figure 16 is a driving timing diagram of another display panel provided in an embodiment of the present invention;

[0033] Figure 17 is a driving timing diagram of another display panel provided in an embodiment of the present invention;

[0034] Figure 18 is a driving timing diagram of another display panel provided in an embodiment of the present invention;

[0035] Figure 19 is a driving timing diagram of another display panel provided in an embodiment of the present invention;

[0036] Figure 20 is a schematic diagram of another shift register provided in an embodiment of the present invention;

[0037] Figure 21 is a schematic diagram of another shift register provided in an embodiment of the present invention;

[0038] Fig. 22 is a structural schematic diagram of another shift register according to an embodiment of the present application;

[0039] Fig. 23 is a structural schematic diagram of another shift register according to an embodiment of the present application;

[0040] Fig. 24 is a structural schematic diagram of another shift register according to an embodiment of the present application;

[0041] Fig. 25 is a structural schematic diagram of another shift register according to an embodiment of the present application;

[0042] Fig. 26 is a structural schematic diagram of another shift register according to an embodiment of the present application

[0043] Fig. 27 is a structural schematic diagram of another shift register according to an embodiment of the present application;

[0044] Fig. 28 is a structural schematic diagram of another shift register according to an embodiment of the present application;

[0045] Fig. 29 is a driving timing diagram of a shift register according to an embodiment of the present application;

[0046] Fig. 30 is a structural schematic diagram of another shift register according to an embodiment of the present application;

[0047] Fig. 31 is a structural schematic diagram of another shift register according to an embodiment of the present application;

[0048] Fig. 32 is a driving timing diagram of another shift register according to an embodiment of the present application;

[0049] Fig. 33 is a structural schematic diagram of another shift register according to an embodiment of the present application;

[0050] Fig. 34 is a structural schematic diagram of another driving circuit according to an embodiment of the present application;

[0051] Fig. 35 is a structural schematic diagram of another driving circuit according to an embodiment of the present application;

[0052] Fig. 36 is a structural schematic diagram of another driving circuit according to an embodiment of the present application;

[0053] Fig. 37 is a structural schematic diagram of another driving circuit according to an embodiment of the present application;

[0054] Fig. 38 is a structural schematic diagram of another driving circuit according to an embodiment of the present application

[0055] Fig. 39 is a structural schematic diagram of another shift register according to an embodiment of the present application;

[0056] Figure 40 is a schematic diagram of another shift register according to an embodiment of the present application;

[0057] Figure 41 is a schematic diagram of another shift register according to an embodiment of the present application;

[0058] Figure 42 is a schematic diagram of another shift register according to an embodiment of the present application;

[0059] Figure 43 is a schematic diagram of another shift register according to an embodiment of the present application;

[0060] Figure 44 is a schematic diagram of another shift register according to an embodiment of the present application;

[0061] Figure 45 is a schematic diagram of a partial cross-sectional structure of a display panel according to an embodiment of the present application;

[0062] Figure 46 is a schematic diagram of a partial cross-sectional structure of another display panel according to an embodiment of the present application;

[0063] Figure 47 is a schematic diagram of a partial cross-sectional structure of another display panel according to an embodiment of the present application;

[0064] Figure 48 is a schematic diagram of another shift register according to an embodiment of the present application;

[0065] Figure 49 is a schematic diagram of another shift register according to an embodiment of the present application;

[0066] Figure 50 is a schematic diagram of another shift register according to an embodiment of the present application;

[0067] Figures 51 to 55 are schematic diagrams of top views of respective film layers of a shift register according to an embodiment of the present application;

[0068] Figure 56 is a schematic diagram of another shift register according to an embodiment of the present application;

[0069] Figure 57 is a schematic diagram of another shift register according to an embodiment of the present application;

[0070] Figure 58 is a schematic diagram of another shift register according to an embodiment of the present application;

[0071] Figure 59 is a schematic diagram of a top view of a shift register according to an embodiment of the present application;

[0072] Figure 60 is a schematic diagram of a cross-sectional structure along A-A in Figure 59;

[0073] Figure 61 is a schematic diagram of another shift register according to an embodiment of the present application;

[0074] FIG. 62 is a schematic view of a partial film layer structure of a display panel according to an embodiment of the present application;

[0075] FIG. 63 is a schematic view of a partial film layer structure of a display panel according to an embodiment of the present application;

[0076] FIG. 64 is a schematic view of a display device according to an embodiment of the present application. DETAILED DESCRIPTION

[0077] In order to make the objects, technical solutions and advantages of the present application clearer, the following will be combined with the accompanying drawings for a complete description of the technical solutions of the present application by means of specific embodiments. Obviously, the described embodiments are only a part of the embodiments of the present application, and various modifications and changes can be made in the present application without departing from the spirit or scope of the present application, which will be apparent to those skilled in the art. Therefore, the present application is intended to cover the modifications and changes of the present application falling within the scope of the corresponding claims (the claimed technical solutions) and their equivalents.

[0078] Also, the "first", "second", and similar words used in the embodiments of the present disclosure do not mean any order, number, or importance, but are only used to distinguish different components. Similarly, "one", "an", or "the" and similar words do not mean a quantity limitation, but mean that at least one exists. "Include" or "contain" and similar words mean that the elements or objects before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right", and the like are only used to represent relative positional relationships, and when the absolute positions of the described objects change, the relative positional relationships can also change accordingly. In addition, the same, equal, and similar descriptions involved in the embodiments of the present disclosure do not mean that the two objects are exactly equal in size and exactly the same in shape, but allow them to be approximately the same and approximately equal within a certain error range.

[0079] It should be noted that the embodiments provided by the embodiments of the present application can be combined with each other without contradiction.

[0080] As described in the background, the shift register of the driving circuit includes a plurality of nodes, by controlling the signals of the nodes, the gate driving signal outputted by the driving output module in the shift register can be controlled, especially for the shift register which can meet the diversified display requirements of the display panel, by outputting the control signal, the gate driving signal outputted by the shift register can be controlled to adapt to the current display requirements, for example, when the shift signal is at the effective level, if the output control signal is at the effective level, the effective level of the gate driving signal outputted by the shift register is controlled, and when the shift signal is at the effective level and the output control signal is at the invalid level, the invalid level of the gate driving signal outputted by the shift register is controlled.

[0081] When the signal refresh of each pixel partition in the display panel is carried out within the display time of a frame of picture, the shift register providing the gate driving signal for the pixels needing signal refresh should output the gate driving signal including the effective level, when the shift register outputs the effective level of the shift signal, the output control signal should be kept at the effective level; and the shift register providing the gate driving signal for the pixels not needing signal refresh should keep the outputted gate driving signal at the invalid level, when the shift register outputs the effective level of the shift signal, the output control signal should be kept at the invalid level. In this way, within the display time of a frame of picture, the output control signal will jump between the effective level and the invalid level, and the effective level of the gate driving signal outputted by the shift register in the driving circuit will fluctuate due to the jumping of the output control signal, which will affect the accuracy of the signal refresh of the pixels, and further affect the display luminance of the pixels, and then affect the display quality of the display panel.

[0082] To solve the above technical problems, the display panel provided by the embodiment of the present application comprises: a driving circuit; the driving circuit comprises N-stage cascaded shift registers; the shift register comprises: a shift control module, configured to receive at least an input signal, a first clock signal and a second clock signal, control a signal of a first node and a signal of a second node; a shift output module, configured to receive at least the signal of the first node, the signal of the second node, a first level signal and a second level signal, control an output shift signal; a shift signal output by an xth-stage shift register is an input signal received by a yth-stage shift register, 1≤x≤N, 1≤y≤N, x≠y, and x, y and N are all positive integers; an output control module, configured to receive at least an output control signal and the shift signal, and control a path through which the output control signal is transmitted to a third node under the control of the shift signal; a transmission control module, configured to receive at least the signal of the second node and the signal of the third node, control a signal of a fourth node; a potential maintaining module, configured to receive a fixed level signal, maintain the signal of the third node; a driving output module, configured to receive at least the signal of the fourth node, the signal of the first node, the first level signal and the second level signal, control an output gate driving signal; and the fixed level signal is different from at least the second level signal.

[0083] By adopting the above technical solution, the N-stage cascaded shift registers are arranged in the driving circuit, the shift control module in each shift register can control the shift output module to output a shift signal as an input signal of another shift register, and the output control module is controlled to transmit the output control signal to the third node by using the shift signal, so that the transmission control module can control the driving output module to output the gate driving signal according to the signal of the third node. In this way, in the same shift register, the shift output module for signal stage transmission and the driving output module for outputting the gate driving signal are two different modules, so that the signal stage transmission and the output of the gate driving signal are independent of each other, thereby ensuring that the signal stage transmission between the shift registers can be performed while the gate driving signals output by the shift registers can be flexibly controlled, and the display panel can meet diversified display requirements and widen the application scenarios of the display panel. Meanwhile, the potential maintaining module is arranged in the shift register to receive the fixed level signal and maintain the signal of the third node, and the fixed level signal is different from at least the second level signal, so as to prevent the fluctuation of the second level signal caused by the change of the signal of the third node from affecting the gate driving signal output by the driving output module, thereby facilitating the improvement of the accuracy of the gate driving signal output by the driving output module and the improvement of the display quality of the display panel.

[0084] The above is the core idea of the present application. Based on the embodiments of the present application, all other embodiments obtained by those of ordinary skill in the art without creative labor fall within the scope of protection of the present application. The technical solutions in the embodiments of the present application will be described clearly and completely in combination with the accompanying drawings of the embodiments of the present application.

[0085] FIG. 1 is a structural schematic diagram of a display panel according to an embodiment of the present application, FIG. 2 is a structural schematic diagram of a driving circuit according to an embodiment of the present application, and FIG. 3 is a structural schematic diagram of a shift register according to an embodiment of the present application. Referring to FIGS. 1 to 3, the display panel 100 includes a driving circuit 10. The driving circuit 10 includes N-stage shift registers G in cascade. The shift register G includes: a shift control module 110, configured to receive at least an input signal Vin, a first clock signal CK and a second clock signal XCK, control a signal of a first node N1 and a signal of a second node N2; a shift output module 120, configured to receive at least the signal of the first node N1, the signal of the second node N2, a first level signal Vgl and a second level signal Vgh, control an output shift signal Vnext; an output control module 130, configured to receive at least an output control signal Vctrl and the shift signal Vnext, and control a path of the output control signal Vctrl transmitted to a third node N3 under control of the shift signal Vnext; a transmission control module 140, configured to receive at least the signal of the second node N2 and the signal of the third node N3, control a signal of a fourth node N4; a potential maintaining module 150, configured to receive a fixed level signal Vh, maintain the signal of the third node N3; a driving output module 160, configured to receive at least the signal of the fourth node N4, the signal of the first node N1, the first level signal Vgl and the second level signal Vgh, control an output gate driving signal Gout; wherein the fixed level signal Vh is different from at least the second level signal Vgh; the shift signal Vnext output by an xth-stage shift register Gx is the input signal received by a yth-stage shift register Gy, 1≤x≤N, 1≤y≤N, x≠y, and x, y and N are positive integers.

[0086] Further, the shift register G can further include a signal input terminal IN, a first clock terminal Ck, a second clock terminal Xck, a first level terminal VGL, a second level terminal VGH, a fixed signal terminal VH, an output control terminal Ctrl, a shift signal terminal Next, and a driving signal terminal OUT. The signal input terminal IN is configured to receive an input signal. The first clock terminal Ck is configured to receive a first clock signal CK. The second clock terminal Xck is configured to receive a second clock signal XCK. The first level terminal VGL is configured to receive a first level signal Vgl. The second level terminal VGH is configured to receive a second level signal Vgh. The fixed signal terminal VH is configured to receive a fixed level signal Vh. The output control terminal Ctrl is configured to receive an output control signal Vctrl. The shift signal terminal Next is configured to output a shift signal Vnext. The driving signal terminal OUT is configured to output a gate driving signal Gout.

[0087] The shift control module 110 is electrically connected to the signal input terminal IN, the first clock terminal Ck, the second clock terminal Xck, the first node N1, and the second node N2. The shift control module 110 is configured to receive an input signal Vin of the signal input terminal IN, a first clock signal CK of the first clock terminal Ck, and a second clock signal of the second clock terminal Xck, and control a signal of the first node N1 and a signal of the second node N2. For example, when the signal of the first node N1 is at an active level, the signal of the second node N2 can be controlled to be at an inactive level. Alternatively, when the signal of the second node N2 is at an active level, the signal of the first node N1 can be controlled to be at an inactive level.

[0088] The shift output module 120 is electrically connected to the first node N1, the second node N2, the first level terminal VGL, the second level terminal VGH, and the shift signal output terminal Next. The shift output module 120 is configured to control a shift signal Vnext output by the shift signal output terminal Next based on a signal of the first node N1, a signal of the second node N2, a first level signal Vgl of the first level terminal VGL, and a second level signal Vgh of the second level terminal VGH. For example, when the signal of the first node N1 is at an active level, the shift output module 120 can be controlled to transmit the first level signal Vgl to the shift signal output terminal Next, so that the shift signal Vnext of the shift signal output terminal Next is consistent with the first level signal Vgl. When the signal of the second node N2 is at an active level, the shift output module 120 can be controlled to transmit the second level signal Vgh to the shift signal output terminal Next, so that the shift signal Vnext of the shift signal output terminal Next is consistent with the second level signal Vgh. The first level signal Vgl and the second level signal Vgh can be two fixed signals with different polarities. Thus, one of the first level signal Vgl and the second level signal Vgh can be an active level of the shift signal Vnext, and the other can be an inactive level of the shift signal Vnext.

[0089] It can be understood that the polarities of the first level signal Vgl and the second level signal Vgh can be different, one of the first level signal Vgl and the second level signal Vgh is a high level signal, and the other is a low level signal, for example, the first level signal Vgl can be a low level signal, and the second level signal Vgh can be a high level signal, or the first level signal Vgl can be a high level signal, and the second level signal Vgh can be a high level signal, which can be set according to actual needs, and the embodiments of the present application do not make specific limitations.

[0090] The output control module 130 is electrically connected with at least the output control end Ctrl, the shift signal end Next and the third node N3, so as to control the path of the output control signal Vctrl of the output control end Ctrl to the third node N3 according to the shift signal Vnext of the shift signal end Next, for example, the shift signal Vnext of the shift signal end Next can control the output control module 130 to be turned on or turned off, and when the shift signal Vnext controls the output control module 130 to be turned on, the output control module 130 can transmit the output control signal Vctrl to the third node N3, so that the signal of the third node N3 can be consistent with the output control signal Vctrl, and when the shift signal Vnext controls the output control module 130 to be turned off, the transmission of the output control signal Vctrl to the third node N3 can be stopped, so that the signal of the third node N3 can remain unchanged.

[0091] The transmission control module 140 is electrically connected with at least the second node N2, the third node N3 and the fourth node N4, so as to control the signal of the fourth node N4 according to the signals of the second node N2 and the third node N3, for example, the signal of the third node N3 can control the transmission control module 140 to be turned on or turned off, and when the signal of the third node N3 controls the transmission control module 140 to be turned on, the signal of the second node N2 can be transmitted to the fourth node N4, so that the signal of the fourth node N4 can be consistent with the signal of the second node N2; and when the signal of the third node N3 controls the transmission control module 140 to be turned off, the signal of the second node N2 cannot be transmitted to the fourth node N4, so that the signal of the fourth node N4 can remain the signal written in the last stage, that is, the signal of the fourth node N4 can remain unchanged.

[0092] The driving output module 160 is electrically connected with the fourth node N4, the first node N1, the first level terminal VGL, the second level terminal VGH and the driving signal terminal OUT, to control the gate driving signal Gout output by the driving signal terminal OUT according to the signal of the fourth node N4, the signal of the first node N1, the first level signal Vgl of the first level terminal VGL and the second level signal Vgh of the second level terminal VGH. For example, when the signal of the first node N1 is a valid level, the driving output module 160 can be controlled to transmit the first level signal Vgl to the driving signal terminal OUT, so that the gate driving signal Gout of the driving signal terminal OUT can be consistent with the first level signal Vgl; when the signal of the fourth node N4 is a valid level, the driving output module 160 can be controlled to transmit the second level signal Vgh to the driving signal terminal OUT, so that the gate driving signal Gout of the driving signal terminal OUT can be consistent with the second level signal Vgh. One of the first level signal Vgl and the second level signal Vgh can be a valid level of the gate driving signal Gout, and the other can be an invalid level of the gate driving signal Gout.

[0093] The potential maintaining module 140 is electrically connected with the fixed signal terminal VH and the third node N3, so that the potential maintaining module 140 maintains the signal of the third node N3 under the action of the fixed level signal Vh of the fixed signal terminal VH. The fixed level signal Vh is different from the second level signal Vgh at least, that is, the fixed level signal Vh and the second level signal Vgh can be provided by different signal terminals respectively, in other words, the fixed signal terminal VH and the second level terminal VGH are different signal terminals, and at this time, the voltage of the fixed level signal Vh can be the same as or different from the voltage of the second level signal Vgh.

[0094] It can be understood that, since the potential maintaining module 140 is electrically connected between the fixed signal end VH and the third node N3, when the third node N3 and the fixed level signal Vh remain unchanged, the potential maintaining module 140 can ensure a fixed voltage difference between the first node N3 and the fixed level signal Vh based on the principle of charge conservation, that is, the signal of the third node N3 and the fixed level signal Vh of the fixed signal end VH remain unchanged; however, since when the shift signal Vnext controls the output control module 130 to be in the conductive state, the signal of the third node N3 will change with the change of the output control signal Vctrl, that is, if the output control signal Vctrl jumps during the time when the output control module is in the conductive state, the signal of the third node N3 will jump, or, if the output control signal Vctrl transmitted by the output control module 130 at the current time period is different from the output control signal Vctrl transmitted by the output control module 130 at the last time when the output control module 130 is in the conductive state, the signal of the third node N3 will also jump. When the signal of the third node N3 changes, the signal of the fixed signal end VH will instantaneously fluctuate due to the principle of charge conservation of the potential maintaining module 140.

[0095] With continuous reference to FIGS. 1 to 4, when the shift output module 120 controls the first level signal Vgl to be transmitted to the shift signal end Next according to the signal of the first node N1, the first level signal Vgl can serve as an invalid level of the shift signal Vnext; and when the shift output module 120 controls the second level signal Vgh to be transmitted to the shift signal end Next according to the signal of the second node N2, the second level signal Vgh can serve as a valid level of the shift signal Vnext; at this time, since the fixed level signal is at least different from the second level signal Vgh, when the signal of the third node N3 changes and the signal of the fixed signal end VH instantaneously fluctuates, at least the valid level of the shift signal Vnext output by the shift output module 120 will not be affected, ensuring the valid level of the shift signal Vnext. In this way, when the shift signal Vnextx output by the xth shift register Gx is taken as the input signal Viny of the yth shift register Gy, since the xth shift register Gx can stably output the valid level of the shift signal Vnextx, at least when the input signal Viny of the yth shift register Gy is a valid level, the shift control module 110 of the yth shift register Gy can accurately control the signals of the first node N1 and the second node N2, ensuring the stability and accuracy of the shift signal Vnext output by the yth shift register Gy, and further ensuring that the shift signals Vnext of the shift registers G in the driving circuit 10 can be transmitted in sequence.

[0096] Similarly, when the driving output module 160 controls the first level signal Vgl to be transmitted to the driving signal end OUT according to the signal of the first node N1, the first level signal Vgl can be an invalid level of the gate driving signal Gout; and when the driving output module 160 controls the second level signal Vgh to be transmitted to the driving signal end OUT according to the signal of the fourth node N4, the second level signal Vgh can be a valid level of the gate driving signal Gout; at this time, since the fixed level signal Vh is different from at least the second level signal Vgh, when the signal of the third node N3 changes and the signal of the fixed signal end VH fluctuates instantaneously, at least the valid level of the gate driving signal Gout output by the driving output module 160 is not affected, thereby ensuring the output stability of the valid level of the gate driving signal Gout. In this way, when the gate driving signal Gout is used to control the display panel to refresh signals, since each stage of the shift register G can stably output the valid level of the gate driving signal Gout, the display panel can accurately refresh signals at least when the shift register G is in the valid level, thereby being conducive to improving the accuracy of signal refreshing in the display panel and improving the display quality of the display panel.

[0097] Alternatively, under the premise that the fixed level signal Vh is different from at least the second level signal Vgh, the fixed level signal Vh can also be different from the first level signal Vgl, so that the fixed level signal Vh and the first level signal Vgl are provided by different signal ends, that is, the fixed signal end VH and the first level end VGL are different signal ends. At this time, the voltage of the fixed level signal Vh can be the same as or different from the voltage of the first level signal Vgl. In this way, since the fixed level signal Vh is different from the first level signal Vgl and the second level signal Vgh, when the signal of the fixed signal end VH fluctuates instantaneously, the valid level and the invalid level of the gate driving signal Gout output by the driving output module 160 are not affected, thereby ensuring the output stability of the gate driving signal Gout. In this way, when the gate driving signal Gout controls the display panel to refresh signals, since each stage of the shift register G can stably output the gate driving signal Gout, the display panel can accurately refresh signals, thereby being conducive to improving the accuracy of signal refreshing in the display panel and improving the display quality of the display panel.

[0098] In another alternative embodiment, the fixed level signal Vh can also be the same as the first level signal Vgl, at this time, the first level signal Vgl can be multiplexed as the fixed level signal Vh, so as to reduce the number of signals provided to the shift register G, thereby being conducive to simplifying the driving mode of the shift register G and reducing the driving cost of the shift register G.

[0099] It can be understood that when the shift output module 120 outputs the first level signal Vgl as the invalid level of the shift signal Vnext, and the driving output module 160 outputs the first level signal Vgl as the invalid level of the gate driving signal Gout, because the invalid level time of the shift signal Vnext and the gate driving signal Gout is a relatively long time in the display time of a frame of picture, and the signal refresh will not be controlled in this time period, so that the first level signal Vgl is less affected by the fluctuation of the signal refresh accuracy in the display panel. At the same time, because the first level signal Vgl is a fixed signal, by multiplexing the first level signal Vgl as a fixed level signal, the signal refresh accuracy requirement of the display panel 100 can be met under the premise of reducing the driving cost.

[0100] In the embodiment of the present application, the fixed signal end VH for receiving the fixed level signal Vh and the first level end VGL for receiving the first level signal Vgl can be different signal ends or the same signal end when the fixed level signal Vh is the same as the first level signal Vgl, and the embodiment of the present application does not make specific limitation to this.

[0101] Optionally, referring to FIGS. 1-3, the display panel 100 can further include at least one first signal transmission line 41; the first signal transmission line 41 is used for transmitting the first level signal Vgl; in the same shift register G, when the fixed signal end VH and the first level end VGL are different signal ends, the driving output module 160 and the potential holding module 150 can be electrically connected to different first signal transmission lines 41 respectively, so that the first signal transmission line 41 electrically connected to the driving output module 160 can transmit the first level signal Vgl to the first level end VGL to control the driving output module 160 to output the corresponding gate driving signal Gout as needed, and the first signal transmission line 41(42) electrically connected to the potential holding module 150 can transmit the same fixed level signal Vh as the first level signal Vgl to the fixed signal end VH to control the potential holding module 150 to maintain the signal of the third node N3.

[0102] In another optional embodiment, FIG. 5 is a structural schematic diagram of another driving circuit provided by the embodiment of the present application. In combination with reference to FIGS. 1, 3 and 5, when the display panel 100 includes at least one first signal transmission line 41, and the first signal transmission line 41 is used to transmit the first level signal Vgl, the driving output module 160 and the potential holding module 150 can be electrically connected with the same first signal transmission line 41. In this way, the driving output module 160 and the potential holding module 150 of the same shift register G share one first signal transmission line 41, which is beneficial to reduce the number of first signal transmission lines 41 electrically connected with the same shift register G, thereby being beneficial to simplify the structure of the display panel 100, and when the first signal transmission line 41 is arranged in the non-display area of the display panel 100, it is beneficial to reduce the size of the non-display area of the display panel 100, thereby being beneficial to the narrow frame of the display panel 100.

[0103] It should be noted that when the driving output module 160 and the potential holding module 150 of the same shift register G share one first signal transmission line 41, the fixed signal end VH and the first level end VGL of the same shift register G can be different signal ends, at this time, the potential holding module 150 and the driving output module 160 of the same shift register G need to be electrically connected with the first signal transmission line 41 through different connection structures (as shown in FIG. 5). In another optional embodiment, as shown in FIG. 6, the first level end VGL in the same shift register G can also be the same signal end as the fixed signal end VH, at this time, the potential holding module 150 and the driving output module 160 of the same shift register G need to be electrically connected with the first signal transmission line 41 through the same connection structure, in this way, the number of connection structures arranged in the display panel 100 can be reduced, which is beneficial to simplify the structure of the display panel 100, thereby being beneficial to reduce the manufacturing cost of the display panel.

[0104] Optionally, FIGS. 7 to 9 are structural schematic diagrams of another shift register provided by the embodiment of the present application. In combination with reference to FIGS. 2, 5 to 9, in the same shift register G, the shift output module 120 is electrically connected with the first signal transmission line 41 through the potential holding module 150 and / or the driving output module 160.

[0105] When the fixed level signal Vh is the same as the first level signal Vgl, the fixed signal terminal VH for receiving the fixed level signal Vh can be the same signal terminal as the first level terminal VGL2 for providing the first level signal Vgl to the shift output module 120. In this case, the shift output module 120 can be electrically connected to the fixed signal terminal VH through the potential holding module 150, and then electrically connected to the first signal transmission line 41 through the fixed signal terminal VH, while the driving output module 160 is electrically connected to the first signal transmission line 41 through the first level terminal VGL1 (as shown in FIG. 5 and FIG. 7); or the first level terminal VGL2 for providing the first level signal Vgl to the shift output module 120 can be the same signal terminal as the first level terminal VGL1 for providing the first level signal Vgl to the driving output module 160. In this case, the shift output module 120 can be electrically connected to the first level terminal VGL1 through the driving output module 160, and then electrically connected to the first signal transmission line 41 through the first level terminal VGL1, while the potential holding module 150 can be directly electrically connected to the first signal transmission line 41 through the fixed signal terminal VH (as shown in FIG. 5 and FIG. 8); or the fixed signal terminal VH, the first level terminal VGL2 for providing the first level signal Vgl to the shift output module 120, and the first level terminal VGL1 for providing the first level signal Vgl to the driving output module 160 can be the same signal terminal. In this case, the shift output module 120 can be electrically connected to the first level terminal VGL1 through the potential holding module 150 and the driving output module 160 in sequence, and then electrically connected to the first signal transmission line 41 through the first level terminal VGL1.

[0106] Thus, when the shift output module 120 is electrically connected to the first signal transmission line 41 through the driving output module 160 and / or the potential holding module 150, the number of connection structures electrically connected to the first signal transmission line 41 can be reduced, which is conducive to simplifying the structure of the shift register G, making the structure of the shift register G more compact, reducing the size of the shift register G, and thus reducing the overall manufacturing cost of the display panel, which is conducive to the narrow frame of the display panel.

[0107] In another optional embodiment, FIG. 10 is a structural schematic diagram of another driving circuit provided by an embodiment of the present application. Referring to FIG. 4 and FIG. 10, in the same shift register G, the driving output module 160 and the shift output module 120 are electrically connected to different first signal transmission lines 41 (411, 412).

[0108] The driving output module 160 can be electrically connected with the first signal transmission line 411 through the first voltage level terminal VGL1, and the shift output module 120 can be electrically connected with the first signal transmission line 412 through the first voltage level terminal VGL2, so that the first signal transmission line 411 can provide the first voltage level signal Vgl to the driving output module 160, and the first signal transmission line 412 can provide the first voltage level signal Vgl to the shift output module 120. At this time, the first voltage level signal Vgl transmitted by the first signal transmission line 411 can be the same as or different from the first voltage level signal Vgl transmitted by the first signal transmission line 411, and can be flexibly designed according to actual needs, so as to meet different display requirements of the display panel 100 and widen the application scenarios of the display panel 100. At the same time, when different first signal transmission lines 41 are used to provide the first voltage level signal Vgl to the shift output module 120 and the driving output module 160 respectively, each first signal transmission line 41 can have a smaller load, so that each first signal transmission line 41 can have a smaller voltage drop, thereby facilitating the accuracy of the first voltage level signal Vgl transmitted by each first signal transmission line 41.

[0109] Optionally, referring to FIGS. 2-10, the driving output module 160 of each stage of the shift register G is electrically connected with the same first signal transmission line 41; the line width of the first signal transmission line 41 electrically connected with the driving output module 160 is greater than or equal to 12 μm.

[0110] In the driving circuit 10, the driving output module 160 of each stage of the shift register G is electrically connected with the same first signal transmission line 41, so that it is not necessary to separately provide the first signal transmission line 41 for transmitting the first voltage level signal Vgl for each stage of the shift register G, thereby facilitating the simplification of the structure of the driving circuit 10, the reduction of the occupied size of the driving circuit 10, and further facilitating the narrow frame of the display panel 100.

[0111] In addition, it can be understood that, since the driving output module 160 is capable of outputting a corresponding gate driving signal Gout according to the first level signal Vgl transmitted by the first signal transmission line 41 electrically connected thereto, and the gate driving signal Gout can be used to control the display panel to perform signal refreshing, when the first level signal Vgl transmitted by the first signal transmission line 41 has a large voltage drop, the gate driving signal Gout output by the driving output module 160 will be inaccurate, so that the display panel cannot be accurately controlled to perform signal refreshing. At this time, by making the first signal transmission line 41 electrically connected to the driving output module 160 of each stage of shift registers G have a large line width, for example, the line width size is greater than 12 μm, so that the first signal transmission line 41 can have a large cross-sectional area, thereby being capable of reducing the resistance of the first signal transmission line 41, reducing the voltage drop of the first level signal Vgl transmitted by the first signal transmission line 41, accurately providing the first level signal Vgl to each stage of shift registers G, and further being capable of making each stage of shift registers G accurately output the gate driving signal Gout, so that the display panel can accurately perform signal refreshing, and the display quality of the display panel is improved. It can be understood that the line width of the signal line refers to the size of the signal line in the direction perpendicular to the extension direction thereof, or it can also be understood as the size of the shorter side of the signal line.

[0112] In another optional embodiment, FIGS. 11-12 are structural schematic diagrams of another driving circuit provided by an embodiment of the present application. Referring to FIGS. 11 and 12, the driving output module 160 of any two adjacent stages of shift registers G is electrically connected to different first signal transmission lines 41, respectively.

[0113] In an exemplary embodiment, as shown in FIG. 11, the odd-numbered stage of shift registers G can be electrically connected to the first signal transmission line 401, and the even-numbered stage of shift registers G can be electrically connected to the first signal transmission line 402, so that any two adjacent stages of shift registers G are electrically connected to different first signal transmission lines 41, respectively. At this time, each first signal transmission line 41 can be electrically connected to fewer shift registers G, so that the load on each first signal transmission line 41 can be reduced, thereby being capable of reducing the voltage drop of the first level signal Vgl transmitted by the first signal transmission line 41, accurately providing the first level signal Vgl to each stage of shift registers G, and further being capable of making each stage of shift registers G accurately output the gate driving signal Gout, so that the display panel can accurately perform signal refreshing, and the display quality of the display panel is improved.

[0114] In another exemplary embodiment, as shown in FIG. 12, when the shift output module 120 and the driving output module 160 of the same shift register G are respectively electrically connected with different first signal transmission lines, under the premise that the driving output modules 160 of any two adjacent shift registers G are respectively electrically connected with different first signal transmission lines 41, the shift output modules 120 of any two adjacent shift registers G can also be respectively electrically connected with different first signal transmission lines 41, for example, the driving output module 160 of the odd-numbered shift register is electrically connected with the first signal transmission line 4011, the shift output module 120 of the odd-numbered shift register is electrically connected with the first signal transmission line 4012, the driving output module 160 of the even-numbered shift register is electrically connected with the first signal transmission line 4021, and the shift output module 120 of the even-numbered shift register is electrically connected with the first signal transmission line 4022, and so on. In this way, each first signal transmission line 41 has a smaller load, so as to enable the shift registers G to accurately output the gate driving signal Gout, thereby facilitating the improvement of the display quality of the display panel.

[0115] It should be noted that FIGS. 11 and 12 exemplarily take the case that the fixed level signal Vh is the same as the first level signal, and the fixed level terminal VH is the same as the first level terminal VGL1 and / or the second level terminal VGL2 as an example for exemplarily description, and in the embodiments of the present application, when the fixed level terminal VH is different from the first level terminal VGL1 and the second level terminal VGL2, a corresponding signal transmission line can also be separately arranged for transmitting the fixed level signal Vh, and the line width of the signal transmission line and the connection mode of the signal transmission line and the shift registers G can be designed according to actual needs, which is not specifically limited in the embodiments of the present application. For the convenience of description, under the premise that there is no special limitation, the technical solutions of the embodiments of the present application are exemplarily described taking the case that the fixed level signal Vh is the same as the first level signal Vgl, and the shift output module 120 in the same shift register G is sequentially connected with the first signal transmission line 41 through the point holding module 150 and the driving output module 160 as an example.

[0116] With reference to FIG. 11, since the shift signal Vnextx output by the xth shift register Gx is the input signal Viny received by the yth shift register Gy, the xth shift register Gx can be electrically connected with the yth shift register Gy, specifically, a shift signal output end Next in the xth shift register Gx for outputting the shift signal Vnextx can be electrically connected with a signal input end IN in the yth shift register Gy for receiving the input signal Viny. For example, when x = i, y can be equal to i + 1, at this time, the shift signal output end Next of the ith shift register Gi can be electrically connected with the signal input end IN of the i + 1th shift register Gi + 1, so that the i + 1th shift register Gi + 1 can output the shift signal Vnexti + 1 under the control of the shift signal Vnexti output by the ith shift register Gi, ensuring that the starting time of the valid level of the shift signal Vnext output by each shift register G can be shifted in turn; wherein i is a positive integer.

[0117] Exemplarily, FIG. 13 is a driving timing diagram of a display panel provided by an embodiment of the present application. In combination with reference to FIG. 1, FIG. 9, FIG. 11 and FIG. 13, the shift control module 110 of the first stage shift register G1 can receive the start control signal STV received by the signal input end IN thereof as the input signal Vin1 thereof, so that the shift control module 110 of the first stage shift register G1 can control the signals of the first node N1 and the second node N2 according to the start control signal STV, and further so that the shift output module 120 of the first stage shift register G1 can start to output the active level of the shift signal Vnext1 at the time T11 according to the signals of the first node N1 and the second node N2. The shift signal Vnext1 output by the first stage shift register G1 is taken as the input signal Vin2 of the second stage shift register G2, so that the shift control module 110 of the second stage shift register G2 can control the signals of the first node N1 and the second node N2 thereof according to the shift signal Vnext1 output by the first stage shift register G1, and further so that the shift output module 120 of the second stage shift register G2 can start to output the active level of the shift signal Vnext2 at the time T12 according to the signals of the first node N1 and the second node N2. Similarly, the i-th stage shift register Gi can start to output the active level of the shift signal Vnexti at the time T1i according to the input signal Vini received thereby, the (i+1)-th stage shift register Gi+1 can start to output the active level of the shift signal Vnexti+1 at the time T1i+1 according to the input signal Vini+1 received thereby, and the N-th stage shift register GN can start to output the active level of the shift signal VnextN at the time T1N according to the input signal VinN received thereby. The time T12 is after the time T11, the time T1i+1 is after the times T11, T12, …, T1i, and the time T1N is after the times 11, T12, …, T1i, T1i+1, … T1N-1, so that the starting times of the active levels of the shift signals Vnext output by the shift registers G are sequentially shifted.

[0118] It should be noted that the active level time of the shift signal Vnext output by the shift registers G can be the same or different, and can be designed according to actual needs. In this embodiment, the active level time of the shift signal Vnext output by the shift registers G is taken as an example for exemplarily description. When the starting times of the active levels of the shift signals Vnext output by the shift registers G are sequentially shifted, the ending times of the active levels of the shift signals Vnext output by the shift registers G will also be sequentially shifted.

[0119] The above only exemplarily shows the cascaded case of the shift registers of each stage when x is less than y and x=i and y=i+1, and in the embodiment of the present application, the values of x and y can be designed according to actual needs, and the values of x and y are not specifically limited in the embodiment of the present application on the premise that x is not equal to y.

[0120] With continued reference to FIGS. 1, 9, 11 and 13, since the shift signal Vnextx output by the xth shift register Gx is taken as the input signal Viny of the yth shift register Gy, and the shift signal Vnext and the gate driving signal Gout in the same shift register G are provided by the shift output module 120 and the driving output module 160 respectively, the shift signal Vnext is not affected by the gate driving signal Gout, so that the effective level starting time of the shift signal Vnext output by each shift register G is sequentially shifted while ensuring that the gate driving signal Gout output by each shift register G can be flexibly controlled by controlling the output control signal Vctrl received by each shift register G and the output control module 130 and the signal transmission module 140 of each shift register G, thereby enabling the gate driving signal Gout output by each shift register G to meet the diversified display requirements of the display panel 100.

[0121] It should be noted that since the gate driving signal Gout can be flexibly controlled, the duration of the effective level of the gate driving signal Gout output by the same shift register G can be the same as or different from the duration of the effective level of the shift signal Vnext, and the effective level starting / ending time of the gate driving signal Gout output by the same shift register G can be the same as or different from the effective level starting / ending time of the shift signal Vnext, and on the premise that the signal level of each shift register G can be transmitted and meets different display requirements of the display panel 100, the effective level time of the shift signal Vnext and the gate driving signal Gout output by the same shift register G is not specifically limited in the embodiment of the present application.

[0122] It can be understood that the active level and the inactive level of the shift signal Vnext are two opposite concepts, i.e., the active level of the shift signal Vnext can be a high level and the inactive level can be a low level, or the active level of the shift signal Vnext can be a low level and the inactive level can be a high level, which is not limited in the embodiment of the present application. In a driving period, the shift signal Vnext can include a high level and a low level, and in the embodiment, one of the high level and the low level with a shorter existing time can be regarded as the active level of the shift signal Vnext, and the other one with a longer existing time can be regarded as the inactive level of the shift signal Vnext, so that the active level and the inactive level of the shift signal Vnext are irrelevant to the specific structure of the output control module 130 and / or the shift control module 110 of the other stage shift register G which is specifically controlled by the shift signal Vnext. Based on the same principle, in a driving period, the active level of the gate drive signal Gout is one of the high level and the low level with a shorter existing time, and the inactive level of the gate drive signal Gout is one of the high level and the low level with a longer existing time. However, in the embodiment of the present application, the active level and the inactive level of other signals except the shift signal Vnext and the gate drive signal Gout can be determined according to the on and off conditions of the actual control module structure, which is not limited in the embodiment of the present application. For convenience of description, the active level of the shift signal Vnext and the gate drive signal Gout is taken as a high level and the inactive level is taken as a low level, and the technical solution of the embodiment of the present application is exemplarily described.

[0123] In an optional embodiment, FIG. 14 is a driving timing diagram of another display panel provided by the embodiment of the present application, referring to FIG. 1, FIG. 9, FIG. 11 and FIG. 14, in the same shift register G, the gate drive signal Gout is in the inactive level in the time period when the shift signal Vnext is in the active level.

[0124] Specifically, since the shift signal Vnextx output by the xth shift register Gx is used as the input signal Viny of the yth shift register Gy, in order to enable the yth shift register Gy to work normally, the xth shift register Gx needs to provide the shift signal Vnextx including the enable level to the yth shift register Gy to meet the requirement of signal level transmission; meanwhile, since the gate drive signal Gout output by each shift register G is used to control the signal refresh of the display panel 100, when the display panel 100 needs to perform signal refresh, the gate drive signal Gout output by the shift register G can include the effective level, and when the display panel 100 does not need to perform signal refresh, the gate drive signal Gout output by the shift register G should include the effective level. In this way, by enabling the gate drive signal Gout to be invalid during the period in which the shift signal Vnext is valid in the same shift register G, the signal refresh requirement of the display panel 100 can be met.

[0125] In another optional embodiment, continuing to refer to FIGS. 1, 9, 11 and 14, in the same shift register G, the effective level time of the gate drive signal Gout overlaps with the effective level time of the shift signal Vnext. In this way, the display panel 100 can perform signal refresh while the shift register G performs signal level transmission, that is, the signal refresh of the display panel 100 is synchronized with the signal level transmission of the shift register G, so as to prevent the display time of a frame of the display panel 100 from being affected due to the asynchronization between signal level transmission and signal refresh, thereby facilitating the shortening of the display time of a frame of the display panel 100, and facilitating the improvement of the refresh frequency of the display panel 100 while meeting the diversified display requirement of the display panel 100.

[0126] It can be understood that when the display panel 100 can achieve diversified display, the display panel 100 can include multiple display modes, and the display panel can have different display brightness and / or refresh frequency in different display modes. At this time, the effective level time and / or period of the gate drive signal Gout output by each shift register G can be controlled to be different in different display modes; or the number of display sub-areas included in the display panel is different in different display modes, and the picture refresh frequency and / or display brightness of each display sub-area are different in the same mode. At this time, in the same display mode, the gate drive signal output by each shift register G can be controlled to have different effective level time and / or period. In this way, by flexibly setting the effective level time and / or period of the gate drive signal Gout output by each shift register G, the display requirement of the display panel in different display modes can be met.

[0127] In an optional embodiment, referring to FIG. 1, the display panel 100 can include a plurality of pixels 20 arranged in an array, each of the pixels 20 can include a pixel circuit P and a light emitting element D, the pixel circuit P can provide a driving current to the light emitting element D according to a written data signal to drive the light emitting element D to emit light. At this time, when the gate driving signal Gout output by the shift register G is used to control the writing of the data signal of the pixel circuit P, the control of the signal refresh frequency of the pixel circuit P can be realized by controlling the period of the active level of the gate driving signal Gout output by the shift register G, thereby realizing the control of the picture refresh frequency of each display sub-area in the display panel; when the gate driving signal Gout output by the shift register G is used to control the time length of the driving current provided by the pixel circuit P to the light emitting element D, the control of the overall light emitting brightness of the light emitting element D can be realized by controlling the time length of the active level of the gate driving signal Gout output by the shift register G, thereby realizing the control of the picture display brightness of each display sub-area in the display panel 100.

[0128] It should be noted that the structure of the pixel circuit P of each pixel 20 in the display panel 100 can be designed according to actual needs, and the embodiments of the present application do not make specific limitations thereon. In an optional embodiment, as shown in FIG. 15, the pixel circuit P can at least include a compensation module 230, a data writing module 220 and a driving module 210; the driving module 210 includes a driving transistor T1; the data writing module 220 is used to control the writing of a data signal Vdata to the driving module 210; the compensation module 230 is used to compensate the threshold voltage of the driving transistor T1 to the driving module 210; the driving module 210 is used to selectively provide a driving current to the light emitting element D to control the display light emitting brightness of the light emitting element D.

[0129] In addition, the pixel circuit P can further include a pixel reset module 240, the pixel reset module 240 is at least used to provide a reset signal Vref to the gate of the driving transistor T1 to reset the gate of the driving transistor T1; an initialization module 250, used to provide an initialization signal Vini to the light emitting element D to initialize the light emitting element D; a light emitting control module 260, used to control the time of providing the driving current to the light emitting element D; optionally, the light emitting control module 260 can include a first light emitting control module 261 and a second light emitting control module 262, the first light emitting control module 261 is connected between the first power signal end and one pole of the driving transistor T1, the second light emitting control module 262 is connected between the other pole of the driving transistor T1 and one pole of the light emitting element D, and the other pole of the light emitting element D is electrically connected with the second power signal end.

[0130] The control end of the data writing module 220 receives a first scanning signal S1, the first scanning signal S1 controls the opening and closing of the data writing module 220; the control end of the compensation module 230 receives a second scanning signal S2, the second scanning signal S2 controls the opening and closing of the compensation module 230; the control end of the pixel reset module 240 receives a third scanning signal S3, the third scanning signal S3 controls the opening and closing of the pixel reset module 240; the control end of the initialization module 250 receives a fourth scanning signal S4, the fourth scanning signal S4 controls the opening and closing of the initialization module 250; and the control end of the light emitting control module 260 receives a light emitting control signal EM, the light emitting control signal EM controls the opening and closing of the light emitting control module 260.

[0131] In an exemplary embodiment, the data writing module 220 includes a data writing transistor T2, the first scanning signal S1 controls the opening and closing of the data writing transistor T2; the compensation module 230 includes a compensation transistor T3, the second scanning signal S2 controls the opening and closing of the compensation transistor T3; the pixel reset module 240 includes a reset transistor T4, the third scanning signal S3 controls the opening and closing of the reset transistor T4; the initialization module 250 includes an initialization transistor T5, the fourth scanning signal S4 controls the opening and closing of the initialization transistor T5; the first light emitting control module 261 includes a first light emitting control transistor T6, the second light emitting control module 262 includes a second light emitting control transistor T7, and the light emitting control signal EM controls the opening and closing of the first light emitting control transistor T6 and the second light emitting control transistor T7.

[0132] Optionally, the pixel circuit P can further include a storage capacitor Cst, the first pole of the storage capacitor Cst is connected to the first power signal end, and the second pole is connected to the gate of the driving transistor T1, for storing the gate signal of the driving transistor T1, so that the driving transistor T1 can continuously provide a driving current in the light emitting stage, and ensure that the light emitting element D can accurately emit light.

[0133] It can be understood that the first power signal end can provide a first power signal PVDD, and the second power signal end can provide a second power signal PVEE, the first power signal PVDD and the second power signal PVEE have a potential difference, so that a driving current is generated between the first power signal PVDD and the second power signal PVEE, thereby driving the light emitting element D to display and emit light.

[0134] It can also be understood that in the pixel circuit P, the types of the driving transistor T1, the data writing transistor T2, the compensation transistor T3, the reset transistor T4, the initialization transistor T5, the first light-emitting control transistor T6, and the second light-emitting control transistor T7 can be designed according to actual needs, and the embodiments of the present application do not make specific limitations thereon. In an exemplary embodiment, the reset transistor T4 and the compensation transistor T3 can be NMOS type transistors, and the driving transistor T1, the data writing transistor T2, the initialization transistor T5, the first light-emitting control transistor T6, and the second light-emitting control transistor T7 can all be PMOS type transistors. In other alternative embodiments, the driving transistor T1, the data writing transistor T2, the compensation transistor T3, the reset transistor T4, the initialization transistor T5, the first light-emitting control transistor T6, and the second light-emitting control transistor T7 can also all be PMOS type transistors. Among them, for the NMOS type transistor, when the signal received by the gate thereof is high, it is turned on, and when it is low, it is turned off; for the PMOS type transistor, when the signal received by the gate thereof is low, it is turned on, and when it is high, it is turned off; thus, when the types of the transistors are changed, the signals received by the gates of the transistors can be adjusted correspondingly to enable the same working timing to be achieved.

[0135] It should be noted that FIG. 15 exemplarily shows the structure of the pixel circuit, and the structure of the pixel circuit in the embodiments of the present application is not limited thereto, and the pixel circuit with the corresponding transistors and other structures added or reduced thereon is also applicable to the embodiments of the present application, and the embodiments of the present application will not be exemplified one by one. For ease of description, under the premise of no special limitation, the technical solutions of the embodiments of the present application are exemplarily described taking the pixel circuit shown in FIG. 1 as an example.

[0136] Referring to FIGS. 11 and 15, in the present embodiment, the gate driving signal Gout output by the shift register G can control at least one of the data writing module 220, the compensation module 230, the pixel reset module 240, the initialization module 250, and the light-emitting control module 260 to be turned on or turned off, that is, the gate driving signal Gout output by the shift register G can be at least one of the first scanning signal S1, the second scanning signal S2, the third scanning signal S3, the fourth scanning signal S4, and the light-emitting control signal EM. Under the premise of being able to achieve the core inventive point of the embodiments of the present application, the embodiments of the present application do not make specific limitations thereon.

[0137] In the embodiment, the compensation module 230 and the initialization module 240 are directly connected to the gate of the driving transistor T1, and thus, when the gate driving signal Gout output by the shift register G controls the compensation module 230 or the initialization module 240 to be turned on or turned off, the data signal of the previous pixel period can be cleared when the gate driving signal Gout output by the shift register G is at the effective level, so that the data signal of the current pixel period can be accurately written, thereby realizing the signal refreshing of the pixel circuit P. When the gate driving signal Gout output by the shift register G controls the turn-on duration of the light-emitting control module 260, the duration of the driving current provided to the light-emitting element D can be controlled, thereby controlling the overall display luminance of the light-emitting element D.

[0138] Thus, in different modes, the display area of the display panel includes different display sub-areas, and in the same display mode, the display luminance of each display sub-area is different, the gate driving signal with different effective level durations output by the shift register electrically connected to the pixel circuit of each display sub-area can be controlled in the same display mode. In the same display mode, the refresh frequency of each display sub-area is different, and the effective level with different frequencies output by the shift register electrically connected to the pixel circuit of each display sub-area can be controlled in the same display mode.

[0139] For ease of description, without special limitation, the technical solutions of the embodiments of the present application are exemplarily described by taking the number of display sub-areas included in the display panel being different in different display modes and the refresh frequency of each display sub-area being different in the same display mode as examples.

[0140] Optionally, with reference to FIGS. 1, 9, 11 and 14, the working mode of the display panel 100 includes a first mode. In the first mode, at least part of the shift registers G is a first shift register, and the output control signal Vctrl includes an effective level and an ineffective level. In at least part of the time in the first mode, in the first shift register, the frequency of the shift signal Vnext is greater than the frequency of the gate driving signal Gout.

[0141] When the shift output module 120 outputs the shift signal Vnext to control the output control module 130 to be turned on, the output control module 130 can transmit the output control signal Vctrl to the third node N3, so that the signal of the third node N3 is consistent with the output control signal Vctrl. At this time, if the output control signal Vctrl is a valid level, the signal of the third node N3 will also be a valid level, and if the output control signal Vctrl is an invalid level, the signal of the third node N3 will also be an invalid level; when the signal of the third node N3 is a valid level, the transmission control module 140 can be controlled to transmit the signal of the second node N2 to the fourth node N4, so that the signal of the fourth node N4 can be consistent with the signal of the second node N2, at this time, the shift signal Vnext output by the shift output module 120 can be controlled to be consistent with the gate drive signal Gout output by the drive output module 160, that is, when the shift signal Vnext is a valid level, the gate drive signal Gout will also be a valid level; when the signal of the third node N3 is an invalid level, the transmission control module 140 cannot be controlled to transmit the signal of the second node N2 to the fourth node N4, so that the gate drive signal Gout cannot be kept as a valid level synchronously with the shift signal Vnext.

[0142] In this embodiment, by including the valid level and the invalid level in the output control signal Vctrl, the signal at the third node N3 can be the valid level when the shift output module 120 of the first shift register outputs the valid level of the shift signal Vnext in a part of time period (for example, the frame picture display time DF1), so that the first shift register can output the valid level of the gate drive signal Gout in this time period, and the pixel 20 electrically connected with the first shift register can perform signal refreshing; and the signal at the third node N3 can be the invalid level when the shift output module 120 of the first shift register outputs the valid level of the shift signal Vnext in another part of time period (for example, the frame picture display time DF2), so that the first shift register cannot output the valid level of the gate drive signal Gout, that is, the gate drive signal Gout output by the first shift register continuously maintains the invalid level in this time period, and the pixel 20 electrically connected with the first shift register cannot perform signal refreshing. In this way, the interval time of the valid level of the shift signal Vnext output by the first shift register is less than the interval time of the valid level of the gate drive signal Gout output by the first shift register, that is, the frequency of the shift signal Vnext output by the first shift register is greater than the frequency of the gate drive signal Gout output by the first shift register, so that the signal level transmission of each shift register G can be ensured in each time period (the display time DF1 and DF2 of each frame picture), and according to the signal refreshing requirement of the pixel 20 electrically connected with the first shift register in the display panel 100, the gate drive signal Gout output by the first shift register has the long interval time of the valid level, the signal refreshing period of the pixel 20 is prolonged, the signal refreshing frequency of the pixel 20 in a unit time is reduced, which is beneficial to reducing the power consumption caused by the signal refreshing of the pixel 20, and further beneficial to the low power consumption of the display panel 100.

[0143] It can be understood that at least part of the shift registers G are the first shift register, that is, part of the shift registers G are the first shift register or all the shift registers G are the first shift register, which can be designed according to actual needs, and the embodiments of the present application do not make specific limitation thereto.

[0144] In an optional embodiment, when all the shift registers G are the first shift register, in the first mode, there are interval times of the valid level of the gate drive signal Gout corresponding to each shift register G, and the interval times of the valid level of the gate drive signal Gout of the shift registers G can be the same or different in the same time period, which can be designed according to actual needs, and the embodiments of the present application do not make specific limitation thereto.

[0145] In another optional embodiment, when in the first mode, the partial shift register G is the first shift register, the second shift register can be included in another partial shift register G, and in the second shift register, the frequency of the shift signal Vnext can be equal to the frequency of the gate drive signal Gout.

[0146] It can be understood that in the second shift register, the frequency of the shift signal Vnext equal to the frequency of the gate drive signal Gout is that the effective level interval time of the shift signal Vnext of the second shift register is the same as the interval time of the gate drive signal Gout, for example, when the second shift register outputs the effective level of the shift signal Vnext, the second shift register can simultaneously output the effective level of the gate drive signal Gout, so that the signal refresh period of the pixel 20 electrically connected to the second shift register can be consistent with the period of signal level transmission of each stage of shift register, and thus the signal refresh frequency of the pixel 20 electrically connected to the second shift register can be greater than the signal refresh frequency of the pixel 20 electrically connected to the first shift register, so that the pixels 20 in the display panel 100 can be refreshed in zones within the display time (DF1) of a frame of picture, for example, the pixels 20 in the display sub-zone with higher display quality requirements can be controlled to have a higher signal refresh frequency, and the pixels 20 in the display sub-zone with lower display quality requirements have a lower signal refresh frequency, thereby meeting the high-quality display requirements of the display panel 100 on the premise of lower power consumption of the display panel 100.

[0147] In an exemplary embodiment, continuing to refer to FIGS. 1, 9, 11 and 14, in the first mode, the display panel 100 includes two display sub-zones, and the display sub-zone where the pixels 20 electrically connected to each stage of shift register G (G1, G2, …, Gi) in the first stage shift register G1 to the i-th stage shift register Gi can be a high refresh frequency display sub-zone, and the display sub-zone where the pixels 20 electrically connected to each stage of shift register G (Gi+1, …, GN) in the i+1-th stage shift register Gi+1 to the N-th stage shift register GN can be a low refresh frequency display sub-zone, for example, at this time, each stage of shift register G (G1, G2, …, Gi) in the first stage shift register G1 to the i-th stage shift register Gi can be a second shift register, and the i+1-th stage shift register G1 to the N-th stage shift register GN can be a first shift register.

[0148] In the display mode of the display panel 100 is the first mode, the display panel can include a plurality of display periods, each display period can include a plurality of frame display time, for example, each display period can include two frame display time, in the first frame display time DF1, the output control signal Vctrl can be controlled to keep the effective level, so that the signal transmitted to the third node N3 of each stage shift register G (G1, G2, …, Gi, Gi+1, …, GN) is all effective level, so that in the first frame display time DF1, each stage shift register G (G1, G2, …, Gi, Gi+1, …, GN) will also output the effective level of the gate drive signal Gout (Gout1, Gout2, …, Gouti, Gouti+1, …, GoutN) in turn, so that the pixels 20 electrically connected with the first stage shift register G1 to the i stage shift register Gi and the pixels 20 electrically connected with the i+1 stage shift register G1 to the N stage shift register GN can refresh the signal at the same time; in the second frame display time DF2, when the output control signal Vctrl is transmitted to the third node N3 of each stage shift register G (G1, G2, …, Gi) of the first stage shift register G1 to the i stage shift register Gi, the output control signal Vctrl can be controlled to keep the effective level, so that in the first stage shift register G1 to the i stage shift register Gi, each stage shift register G (G1, G2, …, Gi) will also output the effective level of the gate drive signal Gout (Gout1, Gout2, …, Gouti, ) in turn, so that the pixels 20 electrically connected with each stage shift register G (G1, G2, …, Gi) of the first stage shift register G1 to the i stage shift register Gi can refresh the signal.

[0149] In the display time DF2 of the second frame picture, when the output control signal Vctrl is transmitted to the third node N3 of each stage of the first stage shift register G1 to the i-th stage shift register Gi, the output control signal Vctrl can be controlled to be at the effective level, so that when each stage of the first stage shift register G1 to the i-th stage shift register Gi (G1, G2, …, Gi) outputs the effective level of the shift signal Vnext (Vnext1, Vnext2, …, Vnexti) in turn, each stage of the first stage shift register G1 to the i-th stage shift register Gi (G1, G2, …, Gi) also outputs the effective level of the gate drive signal Gout (Gout1, Gout2, …, Gouti) in turn, so that the pixels 20 electrically connected to each stage of the first stage shift register G1 to the i-th stage shift register Gi (G1, G2, …, Gi) can perform signal refreshing; when the output control signal Vctrl is transmitted to the third node N3 of each stage of the i+1-th stage shift register Gi+1 to the N-th stage shift register GN, the output control signal Vctrl can be controlled to be at the invalid level, so that when each stage of the i+1-th stage shift register Gi+1 to the N-th stage shift register GN (Gi+1, …, GN) outputs the effective level of the shift signal Vnext (Vnexti+1, …, VnextN) in turn, each stage of the i+1-th stage shift register Gi+1 to the N-th stage shift register GN (Gi+1, …, GN) cannot output the effective level of the gate drive signal Gout (Gouti+1, …, GoutN), so that the pixels 20 electrically connected to each stage of the i+1-th stage shift register Gi+1 to the N-th stage shift register GN (Gi+1, …, GN) cannot perform signal refreshing.

[0150] Thus, in one display period of the display panel, the frequency of the shift signal Vnext (Vnext1, Vnext2, …, Vnexti) of the second shift register G (G1, G2, …, Gi) is controlled to be equal to the frequency of its gate drive signal Gout (Gout1, Gout2, …, Gouti), and the frequency of the shift signal Vnext (Vnexti+1, …, VnextN) of the first shift register G (Gi+1, …, GN) is controlled to be greater than the frequency of its gate drive signal Gout (Gouti+1, …, GoutN), so that the signal refreshing time of the pixels 20 in each display sub-area in the display panel 100 can be controlled as needed, and the diversified display requirements of the display panel 100 can be met.

[0151] It can be understood that the shift signal Vnext output by the shift output module 120 in the same shift register G can control the output control module 130 to be turned on or turned off, so that the output control signal Vctrl can be transmitted to the third node N3 when the shift signal Vnext controls the output control module 130 to be turned on, and the signal of the third node N3 can control the transmission control module 140 to be turned on or turned off, and when the signal of the third node N3 controls the transmission control module 140 to be turned on, the signal of the fourth node N4 can be consistent with the signal of the second node N2, and accordingly the gate drive signal Gout output by the drive output module 160 can be consistent with the shift signal Vnext, so that the gate drive signal Gout can also be at an effective level when the shift signal Vnext is at an effective level. When the signal of the third node N3 controls the transmission control module 140 to be turned off, the signal of the fourth node N4 cannot be consistent with the signal of the second node N2, so that when the shift signal Vnext becomes an effective level, the gate drive signal Gout cannot become an effective level. In this way, the signal of the third node N3 is related to the effective level time of the gate drive signal Gout output by the drive output module 160, so that when the shift output module 120 outputs the shift signal Vnext at an effective level, if the signal of the third node N3 changes between the invalid level and the effective level, it will affect the effective level time of the gate drive signal Gout output by the drive output module 160, resulting in inaccurate gate drive signal output by the drive output module 160.

[0152] To solve the above technical problems, in the same shift register G, before the shift signal Vnext becomes an effective level, the output control module 130 can be controlled to be in a turned-on state to transmit the output control signal Vctrl to the third node N3, and when the shift signal Vnext becomes an effective level, the output control module 130 is controlled to be in a turned-off state, so that the output control signal Vctrl cannot be transmitted to the third node N3, so that the signal of the third node N3 will not change with the change of the output control signal Vctrl, ensuring that when the shift signal Vnext is at an effective level, the signal of the third node N3 is a stable signal that does not change, thereby ensuring that the drive output module 160 can stably and accurately output the gate drive signal Gout.

[0153] In an optional embodiment, in order to make the frequency of the gate drive signal Gout output by the first shift register less than the frequency of the shift signal Vnext, the output control signal Vctrl can be controlled to change from the active level to the inactive level before the shift signal Vnext changes to the active level, that is, the inactive level time of the shift signal Vnext overlaps with the inactive level time of the output control signal Vctrl, so that the inactive level of the output control signal Vctrl can be transmitted to the third node N3, so that the signal of the third node N3 can control the fourth node N4 to remain at the inactive level, so that the gate drive signal Gout can be at the inactive level when the shift signal Vnext is at the active level.

[0154] In an optional embodiment, FIG. 16 is a driving timing diagram of another display panel provided by an embodiment of the present application, referring to FIGS. 1, 9, 11 and 16, in the first shift register G, the time when the output control signal Vctrl jumps from the active level to the inactive level is the first time Tc1, and the starting time of the active level of the shift signal Vnext is the second time Ti+1; the first time Tc is located before the second time Ti+1.

[0155] In an optional embodiment, FIG. 16 is a driving timing diagram of another display panel provided by an embodiment of the present application, referring to FIGS. 1, 9, 11 and 16, in the first shift register G, the time when the output control signal Vctrl jumps from the active level to the inactive level is the first time Tc1, and the starting time of the active level of the shift signal Vnext is the second time Ti+1; the first time Tc is located before the second time Ti+1.

[0156] In another optional embodiment, FIG. 17 is a driving timing diagram of another display panel according to an embodiment of the present application. Referring to FIGS. 1, 9, 11 and 17, in the second shift register G, the time when the output control signal Vctrl jumps from the invalid level to the valid level is the third time Tc2, and the starting time of the valid level of the shift signal Vnext is the fourth time Ti; the third time Tc2 is after the fourth time Ti.

[0157] In the first mode, since the frequency of the gate driving signal Gout of the second shift register G is equal to the frequency of the shift signal Vnext, when the second shift register G outputs the valid level of the shift signal Vnext, the gate driving signal Gout will also be in the valid level. By controlling the third time Tc2 to be after the fourth time Ti, the valid level of the output control signal Vctrl can be ensured to be transmitted to the third node N3 of the second shift register G before the output control module 130 of the second shift register G is closed, so that the valid level of the output control signal Vctrl can be transmitted to the third node N3 of the second shift register G, and the signal of the third node N3 of the second shift register G can be kept in the valid level when the shift signal Vnext of the second shift register G is in the valid level. Therefore, when the second shift register G outputs the valid level of the shift signal Vnext, the second shift register G can continuously and stably output the valid level of the gate driving signal Gout, so that the display sub-area where the pixel 20 electrically connected to the second shift register G can meet the display requirement of higher refresh frequency.

[0158] In an exemplary embodiment, referring to FIG. 1, FIG. 9, FIG. 11 and FIG. 16, when the driving circuit comprises the first shift register and the second shift register simultaneously, if the i-th shift register Gi is the second shift register and the i+1-th shift register Gi+1 is the first shift register, the first time Tc1 at which the output control signal Vctrl jumps from the active level to the inactive level during the display time DF of a frame can be located between the active level start time Ti of the shift signal Vnexti of the i-th shift register Gi and the active level start time of the shift signal Vnexti+1 of the i+1-th shift register Gi+1. In this way, the signal of the third node N3 of the i-th shift register Gi can be the active level during the period in which the shift signal Vnexti of the i-th shift register Gi is the active level, so that the i-th shift register Gi can accurately output the active level of the gate driving signal Gout. Before the shift signal Vnexti+1 of the i+1-th shift register Gi+1 becomes the active level, the output control signal Vctrl is controlled to be the inactive level, so that the signal of the third node N3 of the i+1-th shift register Gi+1 is the inactive level when the shift signal Vnexti+1 of the i+1-th shift register Gi+1 becomes the active level, thereby enabling the i+1-th shift register Gi+1 to stably output the inactive level of the gate driving signal Gout.

[0159] In another exemplary embodiment, referring to FIG. 1, FIG. 9, FIG. 11 and FIG. 17, if the i-th shift register Gi is the first shift register and the i+1-th shift register Gi+1 is the second shift register, the third time Tc2 at which the output control signal Vctrl jumps from the inactive level to the active level during the display time DF of a frame can be located between the active level start time Ti of the shift signal Vnexti of the i-th shift register Gi and the active level start time of the shift signal Vnexti+1 of the i+1-th shift register Gi+1. In this way, the signal of the third node N3 of the i-th shift register Gi can be the inactive level during the period in which the shift signal Vnexti of the i-th shift register Gi is the active level, so that the i-th shift register Gi can continuously output the inactive level of the gate driving signal Gout. Before the shift signal Vnexti+1 of the i+1-th shift register Gi+1 becomes the active level, the output control signal Vctrl is controlled to be the active level, so that the signal of the third node N3 of the i+1-th shift register Gi+1 is the active level when the shift signal Vnexti+1 of the i+1-th shift register Gi+1 becomes the active level, thereby enabling the i+1-th shift register Gi+1 to accurately output the active level of the gate driving signal Gout.

[0160] It should be noted that the above only exemplarily illustrates that the output control signal jumps between the effective level and the ineffective level once in the display time of a frame of picture, and in other embodiments of the present application, the output control signal can jump twice or more than twice in the display time of a frame of picture, and the specific jumping condition can be designed according to actual needs, and the embodiments of the present application do not make specific limitations thereon.

[0161] Exemplarily, FIG. 18 is a driving timing diagram of another display panel provided by an embodiment of the present application. With reference to FIGS. 1, 9, 11 and 18, taking each stage of the shift register G in the first stage shift register G1 to the i-th stage shift register Gi and the j+1-th stage shift register Gj+1 to the N-th stage shift register GN as the first shift register, and the i+1-th stage shift register Gi+1 to the j-th stage shift register Gj as the second shift register as an example, then in the display time DF of a frame of picture, the third time Tc3 at which the output control signal Vctrl jumps from the ineffective level to the effective level can be specifically located between the effective level start time Ti of the shift signal Vnexti of the i-th stage shift register Gi and the effective level start time of the shift signal Vnexti+1 of the i+1-th stage shift register Gi+1, and the first time Tc1 at which the output control signal Vctrl jumps from the effective level to the ineffective level can be specifically located between the effective level start time Tj of the shift signal Vnextj of the j-th stage shift register Gj and the effective level start time of the shift signal Vnextj+1 of the j+1-th stage shift register Gj+1; in this way, the signal of the third node N3 of each stage of the shift register G in the i+1-th stage shift register Gi+1 to the j-th stage shift register Gj can be the effective level in the time period during which the shift signal Vnext (Vnexti+1, …, Vnextj) output by each stage of the shift register G in the i+1-th stage shift register Gi+1 to the j-th stage shift register Gj is the effective level, so that the third node N3 of each stage of the shift register G in the i+1-th stage shift register Gi+1 to the j-th stage shift register Gj can output the effective level of the gate drive signal Gout (Gouti+1, …, Goutj) in turn, and when the shift signal Vnext (Vnext1, Vnext2, …, Vnexti, Vnextj+1, …, VnextN) of each stage of the shift register G in the first stage shift register G1 to the i-th stage shift register Gi and the j+1-th stage shift register Gj+1 to the N-th stage shift register GN is the effective level, each stage of the shift register G in the first stage shift register G1 to the i-th stage shift register Gi and the j+1-th stage shift register Gj+1 to the N-th stage shift register GN still maintains the ineffective level of the gate drive signal Gout (Gout1, Gout2, …, Gouti, Goutj+1, …, GoutN).

[0162] It should be noted that the above only exemplarily illustrates the change of the output control signal of the display panel in the first mode and the case of the gate drive signal output by the shift register in each stage. In the embodiment of the present application, the display panel can include multiple display modes. The change of the gate-on control and the case of the gate drive signal output by the shift register in each stage in each display mode can be designed according to actual needs, and the embodiment of the present application does not make specific limitation on this.

[0163] Optionally, FIG. 19 is a driving timing diagram of another display panel provided by the embodiment of the present application. Referring to FIGS. 1, 9, 11 and 19, the working mode of the display panel 100 further includes a second mode. In the second mode, the output control signal Vctrl is at an effective level, and the frequency of the shift signal Vnext is equal to the frequency of the gate drive signal Gout.

[0164] In the second mode, when the output control signal Vctrl continuously is at the effective level, the signal of the third node N3 of the shift register G in each stage can continuously be kept at the effective level in the display time DT of each frame of picture, so that the shift register G in each stage can output the effective level of the gate drive signal Gout, and the starting time of the effective level of the gate drive signal Gout output by the shift register G in each stage can be shifted in turn, so that all the pixels 20 in the display panel 100 can be refreshed.

[0165] It can be understood that when the display mode of the display panel 100 is the second mode, the shift register G in each stage can output the gate drive signal Gout whose starting time of the effective level is shifted in turn in the display time DT of each frame of picture of the display panel 100, so that each pixel 20 in the display panel 100 can be refreshed at a fixed frequency, thereby preventing the situation that the display and light emitting brightness of the pixel 20 which has not been refreshed for a long time in the pixel 20 is low. Therefore, when the display mode of the display panel 100 is the second mode, by continuously keeping the output control signal Vctrl at the enable level, the display uniformity of the display panel 100 is improved, and the display brightness of the display panel 100 is ensured to be high.

[0166] It should be noted that the above only exemplarily illustrates the structure of the shift register in each stage and the working principle of the gate drive signal output by the shift register, and the specific structure and working principle of the shift register in each stage are not limited in the embodiment of the present application on the premise that the shift register in each stage can accurately output the gate drive signal. The structure of the shift register in the embodiment of the present application is exemplarily illustrated by a typical example.

[0167] Optionally, FIG. 20 is a structural schematic diagram of another shift register according to an embodiment of the present application. As shown in FIG. 20, the shift control module includes a first shift control submodule 111 and a second shift control submodule 112. The first shift control submodule 111 is configured to receive at least an input signal Vin and a first clock signal CK, and control the signal of a first node N1. The second shift control submodule 112 is configured to receive at least the first clock signal CK, a second clock signal XCK, a first level signal Vgl, and the signal of the first node N1, and control the signal of a second node N2.

[0168] The first clock signal CK and the second clock signal XCK can be periodic signals. The first clock signal CK and the second clock signal XCK can each include an active level and an inactive level. The active level time of the first clock signal CK can not overlap with the active level time of the second clock signal XCK, i.e., the active level time of the first clock signal CK can overlap with the inactive level time of the second clock signal XCK, and the active level time of the second clock signal XCK can overlap with the inactive level time of the first clock signal CK. The first level signal Vgl received by the second shift control submodule 112 can be provided by a first level terminal VGL3. The first level terminal VGL3 can be the same signal terminal as or different from a first level terminal VGL2 that provides the first level signal Vgl to the shift output module 120 and / or a first level terminal VGL1 that provides the first level signal Vgl to the drive output module 160. The first level terminals VGL3, VGL2, and VGL1 can be electrically connected to the same first signal transmission line or different first signal transmission lines, which can be designed according to actual needs, and the present application does not make a specific limitation in this regard.

[0169] Specifically, the first shift control sub-module 111 controls the signal of the first node N1 according to the input signal Vin, the first clock signal CK and the second clock signal XCK received thereby, so that the signal of the first node N1 can control the time when the shift output module 120 outputs the first level signal Vgl, i.e. when the signal of the first node N1 is at the valid level that controls the shift output module 120 to be turned on, the shift output module 120 can transmit the first level signal Vgl to the shift signal terminal Next, so that the first level signal Vgl can serve as the shift signal Vnext; the second shift control sub-module 112 controls the signal of the second node N2 according to the first clock signal CK, the second clock signal XCK, the first level signal Vgl and the signal of the first node N1 received thereby, so that the signal of the second node N2 can control the time when the shift output module 120 outputs the second level signal Vgh, i.e. when the signal of the second node N2 is at the valid level that controls the shift output module 120 to be turned on, the shift output module 120 can transmit the second level signal Vgh to the shift signal terminal Next, so that the second level signal Vgh can serve as the shift signal Vnext. In this way, by controlling one of the signal of the first node N1 and the signal of the second node N2 to be at the valid level at the same time, the shift output module Vnext can correspondingly output the valid level or the invalid level of the shift signal Vnext, so that the starting time of the valid level of the shift signal Vnext can be shifted in turn.

[0170] Optionally, FIG. 21 is a structural schematic diagram of another shift register according to an embodiment of the present application. As shown in FIG. 21, the first shift control sub-module 111 includes a first input unit 1111 and a second charge pump unit 1112; the first input unit 1111 is configured to receive at least the input signal Vin and the first clock signal CK, and control the signal of the first node N1; the second charge pump unit 1112 is configured to receive at least the second clock signal XCK, and control the amount of the signal of the second clock signal XCK coupled to the first node N1.

[0171] The first input unit 1111 can be electrically connected with the signal input end IN, the first clock end Ck and the first node N1 respectively. The first clock signal CK of the first clock end Ck can control the time when the first input unit 1111 transmits the input signal Vin received by the signal input end IN to the first node N1, thereby realizing the control of the signal of the first node N1. Meanwhile, since the effective level time of the first clock signal CK and the second clock signal XCK does not overlap, the second clock signal XCK will jump from the invalid level to the effective level in the time period when the first clock signal CK is in the invalid level, so that the jump variable jumping from the invalid level to the effective level can be coupled to the first node N1 by the second charge pump unit 1112, the signal of the first node N1 is supplemented, and the stability of the signal of the first node N1 is ensured.

[0172] Optionally, continuing to refer to FIG. 21, the first input unit 1111 includes a first input transistor M11. The gate of the first input transistor M11 receives the first clock signal CK, the first pole of the first input transistor M11 receives the input signal Vin, and the first pole of the first input transistor M11 is electrically connected to the first node N1. In this way, the first clock signal CK can control the conduction or closing of the first input transistor M11, and when the first clock signal CK controls the conduction of the first input transistor M11, the input signal Vin can be transmitted to the first node N1 through the first input transistor M11, so that the signal of the first node N1 can be consistent with the input signal Vin.

[0173] In another optional embodiment, FIG. 22 is a structural schematic diagram of another shift register provided by an embodiment of the present application. As shown in FIG. 22, the first shift control sub-module 111 can further include a second voltage stabilizing unit 1113. At this time, the second pole of the first input transistor M11 is electrically connected to the first node N1 through the second voltage stabilizing unit 1113. The second voltage stabilizing unit 1113 can stabilize the signal of the first node N1 and the signal at the second pole of the first input transistor M11, so that the signal of the first node N1 does not affect the signal at the second pole of the first input transistor M11 when a transient peak occurs in the signal of the first node N1, or the signal of the first node N1 does not affect the signal at the second pole of the first input transistor M11 when a transient peak occurs in the input signal Vin. In this way, the second voltage stabilizing unit 1113 is used to isolate the first input transistor M11 and the first node N1, which can stabilize the signal of the first node N1 and the signal at the second pole of the first input transistor M11, ensure the accuracy of the signal of the first node N1 and the signal at the second pole of the first input transistor M11, improve the accuracy of the shift signal Vnext output by the shift register G, and thereby facilitate the accurate signal stage transmission of the shift register G.

[0174] Optionally, with continuous reference to FIG. 22, the second voltage stabilizing unit 1113 can include a second voltage stabilizing transistor M12; a gate of the second voltage stabilizing transistor M12 receives the first level signal Vgl, a first pole of the second voltage stabilizing transistor M12 is electrically connected with a second pole of the first input transistor M11, and a second pole of the second voltage stabilizing transistor M12 is electrically connected to the first node N1.

[0175] The first level signal Vgl can control the second voltage stabilizing transistor M12 to be in a conductive state when a difference between the signal at the second pole of the second voltage stabilizing transistor M12 and the signal at the first node N1 is within a preset range, so as to avoid the signal at the second pole of the second voltage stabilizing transistor M12 and / or the signal at the first node N1 from instantaneously increasing or decreasing, and to affect the stability of the signal at the second pole of the second voltage stabilizing transistor M12 or the signal at the first node N1, thereby facilitating to improve the working stability of the shift register G.

[0176] It can be understood that when the first shift control sub-module 111 includes the second voltage stabilizing unit 1113, the second shift control sub-module 112 can be directly electrically connected with the first node N1, or can be electrically connected with the first node N1 through the second voltage stabilizing unit 113, and the present embodiment does not make a specific limitation to this on the premise that the second shift control sub-module 112 can receive the signal of the first node N1.

[0177] Optionally, with reference to FIG. 21 or FIG. 22, the second charge pump unit 1113 includes a second capacitor C2; a first pole plate of the second capacitor C2 receives the second clock signal XCK, and a second pole plate of the second capacitor C2 is coupled to the first node N1. In this way, due to the charge conservation principle of the capacitor, when the second clock signal XCK received by the first pole plate of the second capacitor C2 changes between the effective level and the ineffective level, the signal of the first node N1 electrically connected with the second pole plate of the second capacitor C2 will change accordingly, so that the signal of the second pole plate of the second capacitor C2 has the same change amount as the signal of the first pole plate thereof, thereby being able to supplement the signal for the first node N1 through the second capacitor C2 when the first clock signal CK controls the first input unit 111 to be closed and stop transmitting the input signal Vin to the first node N1, and to ensure the stability of the signal of the first node N1.

[0178] The second pole plate of the second capacitor C2 being coupled to the first node N1 can be understood as that the second pole plate of the second capacitor C2 is directly electrically connected with the first node N1, or the second pole plate of the second capacitor C2 is electrically connected with the first node N1 through other conductive structures or devices, and the specific design can be made according to actual needs, and the present embodiment does not make a specific limitation to this.

[0179] Based on the above-mentioned embodiments, optionally, FIG. 23 to FIG. 24 are structural schematic diagrams of another shift register according to the embodiments of the present application. As shown in FIG. 23 or FIG. 24, the first shift control sub-module 111 further comprises a second input unit 1114 and a filter unit 1115; the second charge pump unit 1112 is electrically connected to the first node N2 through the filter unit 1115, and the second charge pump unit 1112 and the filter unit 1115 are coupled to the sixth node N6; the second input unit 1114 is configured to receive at least an input signal Vin and a first clock signal Ck, and control the signal of the sixth node N6; the filter unit 1115 is configured to receive at least the coupling signal of the second charge pump unit 1112 and the signal of the sixth node N6, and control the signal of the first node N1.

[0180] The first clock signal CK can control the time when the second input unit 1114 transmits the input signal Vin to the sixth node N6, so as to control the signal of the sixth node N6. The second charge pump unit 1112 can couple the jump value of the second clock signal XCK to the sixth node N6, so as to control the signal of the sixth node N6, and then control the signal of the first node N1 according to the voltage difference between the signals of the sixth node N6 and the first node N1 through the filter unit 1115. For example, when the voltage difference between the signals of the first node N1 and the sixth node N6 is within a preset voltage range, the filter unit 1115 can control the signal of the sixth node N6 to be transmitted to the first node N1, so that the signal of the sixth node N6 is consistent with the signal of the first node N1. When the voltage difference between the signals of the first node N1 and the sixth node N6 is not within the preset voltage range, the filter unit 1115 stops transmitting the signal of the sixth node N6 to the first node N1. In this way, when the voltage of the signal of the sixth node N6 is relatively high or low, the transmission of the signal of the sixth node N6 to the first node N1 is prevented, so as to prevent the signal of the first node N1 from changing greatly, and to maintain the stability of the signal of the first node N1.

[0181] Optionally, referring to FIG. 23, the second input unit 1114 can comprise a second input transistor M13. The gate of the second input transistor M13 receives the first clock signal CK, the first electrode of the second input transistor M13 receives the input signal Vin, and the first electrode of the second input transistor M13 is electrically connected to the sixth node N6. In this way, the first clock signal CK can control the conduction or closing of the second input transistor M13. When the first clock signal CK controls the conduction of the second input transistor M13, the input signal Vin can be transmitted to the sixth node N6 through the second input transistor M13, so that the signal of the sixth node N6 can be consistent with the input signal Vin.

[0182] Optionally, referring to FIG. 24, the first shift control sub-module 111 can further include a third voltage stabilizing unit 1116, and the second electrode of the second input transistor M13 can be electrically connected to the sixth node N6 through the third voltage stabilizing unit 1116.

[0183] The third voltage stabilizing unit 1116 can stabilize the signal of the sixth node N6 and the signal at the second electrode of the second input transistor M13, so that the signal of the sixth node N6 will not be affected when a transient peak occurs in the signal of the sixth node N6, or the signal of the sixth node N6 will not be affected when a transient peak occurs in the input signal Vin. In this way, the third voltage stabilizing unit 1116 can isolate the second input transistor M13 from the sixth node N6, stabilize the signal of the sixth node N6 and the signal at the second electrode of the second input transistor M13, ensure the accuracy of the signal of the sixth node N6 and the signal at the second electrode of the second input transistor M13, and improve the accuracy of the shift signal Vnext output by the shift register G, thereby facilitating accurate signal level transmission of the shift register G.

[0184] Optionally, continuing to refer to FIG. 24, the third voltage stabilizing unit 1116 includes a third voltage stabilizing transistor M14.

[0185] The gate of the third voltage stabilizing transistor M14 receives a first level signal Vgl, the first electrode of the third voltage stabilizing transistor M14 is electrically connected to the second electrode of the second input transistor M13, and the second electrode of the third voltage stabilizing transistor M13 is electrically connected to the sixth node N6.

[0186] The first level signal Vgl can control the third voltage stabilizing transistor M13 to be in a conductive state when the difference between the signal at the second electrode of the third voltage stabilizing transistor M13 and the signal of the sixth node N6 is within a preset range, so as to avoid the signal at the second electrode of the third voltage stabilizing transistor M13 and / or the signal of the sixth node N6 from being instantaneously increased or decreased, thereby affecting the stability of the signal at the second electrode of the third voltage stabilizing transistor M13 or the signal of the sixth node N6, and facilitating improvement of the working stability of the shift register G.

[0187] Optionally, continuing to refer to FIG. 23 or FIG. 24, the filtering unit 1115 includes a filtering transistor M15; the gate and the first electrode of the filtering transistor M15 are electrically connected to the sixth node N6, and the second electrode of the filtering transistor M15 is electrically connected to the first node N1; and the second charge pump unit 1112 is electrically connected to the gate of the filtering transistor M15.

[0188] The gate of the filter transistor M15 is electrically connected with the first electrode of the filter transistor M15, so that the filter transistor M15 can be equivalent to a diode. When the voltage difference between the signal of the sixth node N6 and the signal of the first node N1 meets the turn-on condition of the filter transistor M15, the filter transistor M15 can be in the turn-on state, so that the signal of the sixth node N6 can be transmitted to the first node N1.

[0189] For example, when the signal of the sixth node N6 is lower than the signal of the first node N1, and the voltage difference between the signal of the sixth node N6 and the signal of the first node N1 reaches the turn-on voltage of the filter transistor M15, the filter transistor M15 is turned on. When the second clock signal XCK jumps from the high level Vmax to the low level Vmin, the second charge pump unit 1112 couples the jump value (Vmin-Vmax) to the sixth node N6, so that the signal of the sixth node N6 has a lower voltage, and the filter transistor M15 can be turned on, so as to pull down the signal of the first node N1, so that the signal of the first node N1 has a lower voltage. When the second clock signal XCK jumps from the low level Vmin to the high level Vmax, the second charge pump unit 1112 couples the jump value (Vmax-Vmin) to the sixth node N6, so that the signal of the sixth node N6 has a higher voltage, and the voltage difference between the signal of the sixth node N6 and the signal of the first node N1 does not reach the turn-on voltage of the filter transistor M15, so that the filter transistor M15 is in the off state, and cannot pull down the signal of the first node N1, so that the first node N1 is stably maintained.

[0190] Optionally, FIG. 25 is a structural schematic diagram of another shift register provided by the embodiment of the present application. As shown in FIG. 25, the first shift control sub-module 111 further includes a first coupling control unit 1117. The first coupling control unit 1117 is electrically connected between the second charge pump unit 1112 and the second clock terminal Xck, and the first coupling control unit 1117 is also electrically connected with the sixth node N6. The first coupling control unit 1117 is used for controlling the path of the second clock signal XCK of the second clock terminal Xck transmitted to the second charge pump unit 1112 according to the signal of the sixth node N6.

[0191] The first coupling control unit 1117 can be turned on or turned off under the control of the sixth node N6, and when the first coupling control unit 1117 is turned on under the control of the signal of the sixth node N6, the second clock signal Xck can be transmitted to the second charge pump unit 1112 through the first coupling control unit 1117, so that the second charge pump unit 1112 can control the signal of the sixth node N6 according to the jump amount of the second clock signal Xck. In this way, the second charge pump unit 1112 and the first coupling control unit 1117 can balance each other, thereby improving the stability and accuracy of the signal of the sixth node N6.

[0192] Optionally, continuing to refer to FIG. 25, the first coupling control unit 1117 can include a first coupling control transistor M16. The gate of the first coupling control transistor M16 is electrically connected with the sixth node N6, the first electrode of the first coupling control transistor M16 receives the second clock signal Xck, and the second electrode of the first coupling control transistor M16 is electrically connected with the second charge pump unit 1112. In this way, the first coupling control transistor M16 can be turned on or turned off under the control of the signal of the sixth node N6, and when the first coupling control transistor M16 is turned on under the control of the signal of the sixth node N6, the second clock signal Xck can be transmitted to the second charge pump unit 1112, so that the second charge pump unit 1112 can control the signal of the sixth node N6 based on the second clock signal Xck transmitted by the first coupling control transistor M16.

[0193] Optionally, FIG. 26 is a structural schematic diagram of another shift register provided by an embodiment of the present application. As shown in FIG. 26, the first shift control sub-module 111 can further include a second coupling control unit 1118. The second coupling control unit 1118 is electrically connected between the second charge pump unit 1112 and the second voltage level terminal VGH, and the second coupling control unit 1118 is also electrically connected with the second shift control sub-module 112. The second coupling control unit 1118 is configured to control the path through which the second voltage level signal Vgh of the second voltage level terminal VGH is transmitted to the second charge pump unit 1112 under the control of the second shift control sub-module 112.

[0194] The second coupling control unit 1118 can be turned on or turned off under the control of the second shift control sub-module 112, and when the second shift control sub-module 112 controls the second coupling control unit 1118 to be turned on, the second level signal Vgh can be provided to the second charge pump unit 1112, so that the signal received by the second charge pump unit 1112 can change between the second level signal Vgh and the second clock signal XCK transmitted by the first coupling control unit 1117, so that the signal received by the second charge pump unit 1112 can have a larger signal change amount, so that when the change amount is coupled to the sixth node N6, the signal of the sixth node N6 can have a lower voltage, so that the signal of the first node N1 can be pulled down to a low enough voltage, ensuring that the signal of the first node N1 can accurately control the shift output module 120 to output the shift signal Vnext, improving the working stability and accuracy of the shift register G, and ensuring that the signal can be accurately transmitted between the shift registers G.

[0195] Optionally, continuing to refer to FIG. 26, the second coupling control unit 1118 includes a second coupling control transistor M17; the gate of the second coupling control transistor M17 is electrically connected with the second shift control sub-module 112, the first electrode of the second coupling control transistor M17 receives the second level signal Vgh, and the second electrode of the second coupling control transistor M17 is electrically connected with the second charge pump unit 1112. In this way, the second coupling control transistor M17 can be turned on or turned off under the control of the second shift control sub-module 112, and when the signal of the sixth node N6 controls the second coupling control transistor M17 to be turned on, the second level signal Vgh can be transmitted to the second charge pump unit 1112, so that the second charge pump unit 1112 can control the signal of the sixth node N6 based on the second level signal Vgh transmitted by the second coupling control transistor M17.

[0196] Optionally, continuing to refer to FIG. 26, the first shift control sub-module 111 can further include a reset unit 1119, which receives at least a reset signal Vrst and a second level signal Vgh to control the signal of the first node N1. At this time, the reset unit 1119 can be electrically connected with a reset signal end RST for providing the reset signal Vrst, a second level end VGH for providing the second level signal Vgh, and the first node N1, so that the reset unit 1119 can reset the first node N1 under the control of the reset signal Vrst and the second level signal Vgh.

[0197] Based on the above-mentioned embodiments, optionally, FIG. 27 is a structural schematic diagram of another shift register according to an embodiment of the present application. As shown in FIG. 27, the second shift control submodule 112 can include a first control transistor M21, a second control transistor M22, a third control transistor M23, a fourth control transistor M24, and a control capacitor C3. The gate of the first control transistor M21 receives the first clock signal CK, the first electrode of the first control transistor M21 receives the first level signal Vgl, and the second electrode of the first control transistor M21 is electrically connected to the seventh node N7. The gate of the second control transistor M22 is coupled to the first node N1, the first electrode of the second control transistor M22 receives the first clock signal CK, and the second electrode of the second control transistor M22 is electrically connected to the seventh node N7. The gate of the third control transistor M23 is coupled to the seventh node N7, the first electrode of the third control transistor M23 receives the second clock signal XCK, and the second electrode of the third control transistor M23 is electrically connected to the eighth node N8. The gate of the fourth control transistor M24 receives the second clock signal XCK, the first electrode of the fourth control transistor M24 is electrically connected to the eighth node N8, and the second electrode of the fourth control transistor M24 is electrically connected to the second node N2. The control capacitor C3 is electrically connected between the seventh node N7 and the eighth node N8.

[0198] In this way, the first clock signal CK can control the first control transistor M21 to be turned on or turned off, the signal of the first node N1 can control the second control transistor M22 to be turned on or turned off, the signal of the seventh node N7 can control the third control transistor M23 to be turned on or turned off, the second clock signal XCK can control the fourth control transistor M24 to be turned on or turned off, and the control capacitor C3 can balance the signals of the seventh node N7 and the eighth node N8.

[0199] Optionally, continuing to refer to FIG. 27, the second shift control submodule 112 can further include a fifth control transistor M25. The gate of the fifth control transistor M25 is electrically connected to the first node N1, the first electrode of the fifth control transistor M25 receives the second level signal Vgh, and the second electrode of the fifth control transistor M25 is electrically connected to the second node N2. In this way, the fifth control transistor M25 can be turned on or turned off under the control of the signal of the first node N1, so that when the signal of the first node N1 is the active level, the second level signal Vgh can be transmitted to the second node N2, so that the signal of the second node N2 is the inactive level, ensuring that one of the signal of the first node N1 and the signal of the second node N2 is the active level and the other is the inactive level in the same time period, so that the shift output module 120 can accurately output the shift signal Vnext under the control of the signal of the first node N1 and the signal of the second node N2.

[0200] Optionally, FIG. 28 is a structural schematic diagram of another shift register according to an embodiment of the present application. As shown in FIG. 28, the second shift control submodule 112 can further include a fourth voltage stabilizing transistor M26. In this case, the gate of the third control transistor M23 can be electrically connected to the seventh node N7 through the fourth voltage stabilizing transistor M26, so that the fourth voltage stabilizing transistor M26 can stabilize the signal of the seventh node N7 and the gate of the third control transistor M23.

[0201] Optionally, continuing to refer to FIG. 28, the shift output module 120 can include a first shift output transistor M10 and a second shift output transistor M20. The gate of the first shift output transistor M10 is coupled to the first node N1, the first electrode of the first shift output transistor M10 receives the first level signal Vgl, and the second electrode of the first shift output transistor M10 is used to output the shift signal Vnext. The gate of the second shift output transistor M20 is electrically connected to the second node N2, the first electrode of the second shift output transistor M20 receives the second level signal Vgh, and the second electrode of the second shift output transistor M20 is used to output the shift signal Vnext.

[0202] In this case, the signal of the first node N1 can control the first shift output transistor M10 to be turned on or turned off, so that when the signal of the first node N1 controls the first shift output transistor M10 to be turned on, the first level signal Vgl can be transmitted to the shift signal terminal Next to serve as the shift signal Vnext, so that the shift signal Vnext can be consistent with the first level signal Vgl. The signal of the second node N2 can control the second shift output transistor M20 to be turned on or turned off, so that when the signal of the second node N2 controls the second shift output transistor M20 to be turned on, the second level signal Vgh can be transmitted to the shift signal terminal Next to serve as the shift signal Vnext, so that the shift signal Vnext can be consistent with the second level signal Vgh. In this way, by controlling the signal of the first node N1 and the signal of the second node N2, the shift signal Vnext can be changed between the first level signal Vgl and the second level signal Vgh, so that the shift signal Vnext includes the valid level and the invalid level.

[0203] In addition, the shift output module 120 can further include a fourth capacitor C4, which is electrically connected between the second level terminal VGH and the second node N2, so that the fourth capacitor C4 can store and maintain the signal of the second node N2, ensuring that the signal of the second node N2 can accurately control the second shift output transistor M20 to be turned on or turned off.

[0204] It can be understood that the above only exemplarily illustrates the structure of the shift control module and the shift output module, and in the embodiments of the present application, the shift control module and the shift output module are not specifically limited as long as the effective level start time of the shift signals output by the shift registers at each stage can be ensured to be shifted in turn. For the convenience of description, under the premise of no special limitation, the technical solutions of the embodiments of the present application are exemplarily illustrated by taking the shift control module 110 and the shift output module 120 shown in FIG. 28 as examples.

[0205] Exemplarily, taking each transistor in the shift control module and the shift output module as a PMOS transistor as an example, FIG. 29 is a driving timing diagram of a shift register provided by an embodiment of the present application, and the working principle and working process of the shift register are exemplarily illustrated below with reference to FIG. 28 and FIG. 29.

[0206] Before the Ta1 stage, the input signal Vin is low. When the first clock signal Ck is low and the second clock signal XCK is high, the first input transistor M11 and the second input transistor M13 are controlled to be turned on, and the low level of the input signal Vin can be transmitted to the first node N1 and the sixth node N6. The signals of the first node N1 and the sixth node N6 are both low, so that the signal of the sixth node N6 can control the first coupling control transistor M16 to be turned on. The high level of the second clock signal XCK can be transmitted to the second plate of the second capacitor C2, so that the second plate of the second capacitor C2 is high. The signal of the first node N1 can control the first shift output transistor M10 to be turned on, and the first level signal Vgl is transmitted to the shift signal end Next, so that the shift signal Vnext can be consistent with the first level signal Vgl. When the first clock signal Ck is high and the second clock signal XCK is low, the first input transistor M11 and the second input transistor M13 are turned off, and the signal of the sixth node N6 remains the low level signal written in the last stage, so that the first coupling control transistor M16 is still in the turned-on state. The low level signal of the second clock signal XCK can be transmitted to the first plate of the second capacitor C2, so that the signal of the first plate of the second capacitor C2 changes from high to low. The jump variable is coupled to the sixth node N6 through the second capacitor C2, so that the sixth node N6 can have a lower potential, and the filter transistor M15 is controlled to be turned on, so as to further pull down the signal of the first node N1. The signal of the first node N1 can accurately control the first shift output transistor M10 to be stably turned on, and the shift signal end Next can stably and accurately output the low level of the shift signal Vnext. At the same time, since the signal of the first node N1 is low, the fifth control transistor M25 is turned on under the control of the signal of the first node N1, so that the second level signal Vgh is transmitted to the second node N2, and the second node N2 remains high. The second shift output transistor M20 is in the turned-off state.

[0207] In the Ta1 stage, the input signal Vin becomes high level, the first clock signal CK is low level, and the second clock signal XCK is high level. At this time, the first input transistor M11, the second input transistor M14 and the first control transistor M21 are turned on, the input signal Vin is transmitted to the first node N1 and the sixth node N6 through the first input transistor M11 and the second input transistor M13 respectively, so that the first node N1 and the sixth node N6 are both high level, and the second control transistor M22 and the fifth control transistor M25 remain closed. Meanwhile, the first level signal Vgl of low level is transmitted to the seventh node N7 through the first control transistor M21, the seventh node N7 is low level, the third control transistor M23 is turned on, the second clock signal XCK of high level is transmitted to the eighth node N8, so that the eighth node N8 is high level, and because the fourth control transistor M24 and the fifth control transistor M25 are both in the closed state, the signal of the second node N2 remains high level, the second shift output transistor M20 is closed, and the shift signal Vnext remains low level unchanged.

[0208] In the Ta2 stage, the input signal Vin continues to remain high level, the first clock signal CK becomes high level, and the second clock signal XCK becomes low level. At this time, the first input transistor M11, the second input transistor M13 and the first control transistor M21 are closed, and the second control transistor M22 and the fifth control transistor M25 are closed, the seventh node N7 is low level, the third control transistor M23 is turned on, the second clock signal XCK of low level is transmitted to the eighth node N8 through the third control transistor M23, so that the eighth node N8 is low level, the fourth control transistor M24 is turned on, the signal of the eighth node N8 is transmitted to the second node N2, so that the second node N2 is low level, the second shift output transistor M20 is turned on, the second level signal Vgh is transmitted to the shift signal end Next, so that the output shift signal Vnext becomes high level.

[0209] In the Ta3 stage, the input signal Vin continues to be at a high level, the first clock signal CK is at a low level, and the second clock signal XCK is at a high level. At this time, the second input transistor M13, the first input transistor M11, and the first control transistor M21 are turned on, the input signal Vin is transmitted to the first node N1 and the sixth node N6 through the second input transistor M13 and the first input transistor M11 respectively, so that the first node N1 and the sixth node N6 are both at a high level, and the second control transistor M22 and the fifth control transistor M25 are turned off. Meanwhile, the first level signal Vgl is transmitted to the seventh node N7 through the first control transistor M21, the seventh node N7 is at a low level, the third control transistor M23 is turned on, the second clock signal XCK is at a high level, the eighth node N8 is kept at a high level, the fourth control transistor M24 is turned off, the second node N2 is kept at a low level, and the second shift output transistor M20 is turned on, so that the shift signal Vnext continues to be at a high level.

[0210] In the Ta4 stage, the input signal Vin becomes at a low level, the first clock signal CK is at a high level, and the second clock signal XCK is at a low level. At this time, the second input transistor M13, the first input transistor M11, and the first control transistor M21 are all turned off, the first node N1 and the sixth node N6 are both kept at a high level, and the second control transistor M22 and the fifth control transistor M25 are both turned off. The seventh node N7 is kept at a low level, the third control transistor M23 is turned on, the low level of the second clock signal XCK is transmitted to the eighth node N8 through the third control transistor M23, so that the eighth node N8 is at a low level, the fourth control transistor M24 is turned on, the signal of the eighth node N8 is transmitted to the second node N2, the signal of the second node N2 is at a low level, the second shift output transistor M20 is turned on, and the second level signal Vgh is transmitted to the shift signal end Next, so that the shift signal Vnext continues to be at a high level.

[0211] In the Ta5 stage, the input signal Vin is at a low level, the first clock signal CK is at a low level, the second clock signal XCK is at a high level, the second input transistor M13, the first input transistor M11 and the first control transistor M21 are turned on, the input signal Vin is transmitted to the first node N1 and the sixth node N6 through the second input transistor M13 and the first input transistor M11 respectively, so that the first node N1 and the sixth node N6 are both at a low level, the second control transistor M22 and the fifth control transistor M25 are turned on; at the same time, the first control transistor M21 is turned on, the first level signal Vgl is transmitted to the seventh node N7 through the first control transistor M21, the seventh node N7 is at a low level, the third control transistor M23 is turned on, the second clock signal XCK is at a high level, the eighth node N8 keeps at a high level, and the fourth control transistor M24 is turned off; the second level signal Vgh is transmitted to the second node N2 through the fifth control transistor M25, so that the second node N2 is at a high level, and the second shift output transistor M20 is turned off; at the same time, the first node N1 is at a low level, the first shift output transistor M10 is turned on, and the first level signal Vgl is transmitted to the shift signal end Next, so that the shift signal Vnext becomes a low level.

[0212] After the Ta5 stage, the input signal Vin keeps at a low level, so that no matter how the first clock signal CK and the second clock signal XCK change, the signal of the first node N1 keeps at a low level, and the signal of the second node N2 keeps at a high level, so that the first shift output transistor M10 can be continuously turned on, the second shift output transistor M20 is continuously turned off, and the shift signal Vnext is always at a low level, until the next driving period, the signal of the first node N1, the signal of the second node N2 and the shift signal Vnext again experience changes as above.

[0213] In this way, through the structure and related timing of the above shift control module 110, the shift control module 110 can control the starting moment of the enable level of the shift signal Vnext output by the shift output module 120 to be after the starting moment of the enable level of the input signal Vin received by the shift control module 110, and the shift control module 110 can control the ending moment of the enable level of the shift signal Vnext output by the shift output module 120 to be after the ending moment of the enable level of the input signal Vin received by the shift control module 110, thereby meeting the signal level transmission requirements of each stage of the shift register G.

[0214] It should be noted that the working principle of the shift register is described above by taking the PMOS transistors in the shift control module 110 and the shift output module 120 as an example, and the transistors in the shift control module 110 and the shift output module 120 in the embodiment of the present application can also include NMOS transistors, which can be designed according to actual needs. For the PMOS transistors, the gate receives a high-level signal to turn on and a low-level signal to turn off. For the NMOS transistors, the gate receives a low-level signal to turn on and a high-level signal to turn off. Therefore, when the type of the transistor changes, the similar working principle can be achieved by adjusting the signal provided to the gate, and the same parts can be referred to the description above, which will not be described here.

[0215] Optionally, FIG. 30 is a structural schematic diagram of another shift register according to an embodiment of the present application. As shown in FIG. 30, the output control module 130 includes an output control transistor M30. The gate of the output control transistor M30 receives a shift signal Vnext, the first pole of the output control transistor M30 receives an output control signal Vctrl, and the second pole of the output control transistor M30 is electrically connected to the third node N3. In this way, the output control transistor M30 can be turned on or turned off under the control of the shift signal Vnext, and when the output control transistor M30 is turned on, the output control signal Vctrl can be transmitted to the third node N3, so that the signal of the third node N3 can be consistent with the output control signal Vctrl.

[0216] Optionally, FIG. 31 is a structural schematic diagram of another shift register according to an embodiment of the present application. As shown in FIG. 31, the output control transistor M30 is a double-gate transistor.

[0217] Wherein, since the output control transistor M30 is used for transmitting the output control signal Vctrl to the third node N3, and the signal of the third node N3 can control the transmission path of the signal of the second node N2 to the fourth node N4, and the signal of the fourth node N4 can control the output of the gate drive signal Gout of the driving output module 160; at the same time, after the shift signal Vnext becomes the effective level, the output control transistor M30 will be in the closed state, at this time, the signal of the third node N3 needs to be kept unchanged. Based on the characteristics of the transistor, when the output control transistor M30 is in the closed state, there will be a certain leakage current, when the leakage current is large, the signal of the third node N3 will change greatly, so that the signal of the third node N3 cannot accurately control the time of forming the conduction path between the second node N2 and the fourth node N4, so that the signal of the fourth node N4 is inaccurate, which affects the accuracy of the gate drive signal Gout output by the driving output module 160. Therefore, by setting the output control transistor M30 as a double-gate transistor, when the output control transistor M30 is in the closed state, the output control transistor M30 can have a smaller leakage current, improve the stability and accuracy of the signal of the third node N3, so that the signal of the third node N3 can accurately control the conduction path between the second node N2 and the fourth node N4, thereby improving the accuracy and stability of the gate drive signal Gout output by the driving output module 160.

[0218] It should be noted that the above only exemplarily describes the case that the output control transistor M30 is a double-gate transistor. For the transistor electrically connected with other nodes or signal terminals, when the signal of the node or signal terminal electrically connected therewith also needs high accuracy and stability, the transistor can also be set as a double-gate transistor, which can be designed according to actual needs, and the embodiments of the present application do not make specific limitation thereon.

[0219] Optionally, referring to FIG. 30 or FIG. 31, the transmission control module 140 comprises a transmission control transistor M40; the gate of the transmission control transistor M40 is electrically connected to the third node N3, the first pole of the transmission control transistor M40 is electrically connected to the second node N2, and the second pole of the transmission control transistor M40 is electrically connected to the fourth node N4. Therefore, the transmission control transistor M40 can be turned on or off under the control of the signal of the third node N3, and when the transmission control transistor M40 is turned on, the signal of the second node N2 can be transmitted to the fourth node N4, so that the signal of the fourth node N4 is consistent with the signal of the second node N2.

[0220] Optionally, referring to FIG. 30 or FIG. 31, the potential holding module 150 includes a potential holding capacitor C6; a first plate of the potential holding capacitor C6 receives the fixed level signal Vh, and a second plate of the potential holding capacitor C6 is electrically connected to the third node N3. In this way, the signal of the third node N3 can be stored in the potential holding capacitor C6, so that when the output control module 130 no longer transmits the output control signal Vctrl, the potential holding capacitor C6 can maintain the stability of the signal of the third node N3, so that the signal of the third node N3 can stably control the transmission control module 140 to be turned on or off.

[0221] Optionally, continuing to refer to FIG. 30 or FIG. 31, the drive output module 160 includes a first drive output transistor M61 and a second drive output transistor M62; a gate of the first drive output transistor M61 is coupled to the first node N1, a first electrode of the first drive output transistor M61 receives the first level signal Vgl, and a second electrode of the first drive output transistor M61 is used to output a gate drive signal Gout; a gate of the second drive output transistor M62 is electrically connected to the fourth node N4, a first electrode of the second drive output transistor M62 receives the second level signal Vgh, and a second electrode of the second drive output transistor M62 is used to output the gate drive signal Gout.

[0222] Wherein, the signal of the first node N1 can control the first drive output transistor M61 to be turned on or off, so that when the signal of the first node N1 controls the first drive output transistor M61 to be turned on, the first level signal Vgl can be transmitted to the drive signal end OUT to serve as the gate drive signal Gout, so that the gate drive signal Gout can be consistent with the first level signal Vgl; the signal of the fourth node N4 can control the second drive output transistor M62 to be turned on or off, so that when the signal of the fourth node N4 controls the second drive output transistor M62 to be turned on, the second level signal Vgh can be transmitted to the drive signal end OUT to serve as the gate drive signal Gout, so that the gate drive signal Gout can be consistent with the second level signal Vgh. In this way, by controlling the signal of the first node N1 and the signal of the fourth node N4, the gate drive signal Gout can be changed between the first level signal Vgl and the second level signal Vgh, so that the gate drive signal Gout can include an effective level and an ineffective level, meeting the diversified display requirements of the display panel.

[0223] In addition, the drive output module 160 can further include a fifth capacitor C5, which is electrically connected between the second level end VGH and the fourth node N4, so that the fifth capacitor C5 can store and maintain the signal of the fourth node N4, ensuring that the signal of the fourth node N4 can accurately control the second drive output transistor M62 to be turned on or off.

[0224] It can be understood that the above only exemplarily illustrates the structure of the output control module, the transmission control module and the drive output module, and in the embodiment of the present application, the embodiment of the present application does not make specific limitation as long as the effective level or the ineffective level of the gate drive signal output by the shift register at each level can be ensured as required.

[0225] Exemplarily, taking the transistors in the output control module, the transmission control module and the drive output module as all PMOS transistors for example, FIG. 32 is a drive timing diagram of another shift register provided by the embodiment of the present application, and the working principle and working process of the shift register as the first shift register will be exemplarily illustrated below in combination with reference to FIG. 30 and FIG. 32.

[0226] In the embodiment of the present application, the output control signal Vctrl can be set to have the same level as the signal of the first node N1 in the first mode, and the output control signal Vctrl can be set to have the same level as the signal of the third node N3 in the second mode. For example, as shown in FIG. 32, in the display time DF1 of one frame, the output control signal Vctrl continuously keeps low, and in the display time DF2 of another frame, the output control signal Vctrl jumps to high before the shift signal Vnext becomes high.

[0227] Before the Tb11 stage of the display time DF1 of the frame, the signal of the first node N1 is low, the signal of the second node N2 is high, the shift signal Vnext is low, the output control transistor M30 is turned on, the low level of the output control signal Vctrl is transmitted to the third node N3, so that the signal of the third node N3 can keep consistent with the output control signal Vctrl, that is, the signal of the third node N3 is low; the signal of the third node N3 can control the transmission control transistor M40 to be turned on, the signal of the second node N2 is transmitted to the fourth node N4, and the signal of the second node N2 keeps consistent with the signal of the fourth node N4, that is, the signal of the fourth node N4 is high, and the second drive output transistor M62 is in the closed state; at the same time, because the signal of the first node N1 is low, the first drive output transistor M61 is turned on, and the first level signal Vgl is taken as the gate drive signal Gout, that is, the gate drive signal Gout is low.

[0228] In the Tb11 stage, the signal of the first node N1 becomes high level, the signal of the second node N2 remains high level, the shift signal Vnext remains low level, the output control transistor M30 continues to keep the on state, the signal of the third node N3 remains consistent with the low level of the output control signal Vctrl, the transmission control transistor M40 is turned on, the high level of the second node N2 is transmitted to the fourth node N4, so that the fourth node N4 remains high level, and the second driving output transistor M62 keeps the off state; at the same time, the signal of the first node N1 becomes high level, so that the first driving output transistor M61 also becomes the off state, and the gate drive signal Gout remains the low level of the previous stage.

[0229] In the Tb12 stage, the signal of the first node N1 remains high level, the signal of the second node N2 becomes low level, the shift signal Vnext becomes high level, the output control transistor M30 is turned off, the signal of the third node N3 remains the low level written in the previous stage, so that the transmission control transistor M40 continues to keep the on state, the high level signal of the second node N2 is transmitted to the fourth node N4, so that the signal of the fourth node N4 can control the second driving output transistor M62 to be turned on, the second level signal Vgh is transmitted to the driving signal end OUT, the gate drive signal Gout becomes consistent with the second level signal Vgh, that is, the gate drive signal Gout becomes high level; at the same time, the signal of the first node N1 is high level, so that the first driving output transistor M61 continues to keep the off state.

[0230] After the Tb12 stage of the display time DF1 of the frame picture, the signal of the first node N1 becomes low level again, the signal of the second node N2 becomes high level again, and the shift signal Vnext becomes low level again, so that the first driving output transistor M61 is turned on, the second driving output transistor M62 is turned off, and the gate drive signal Gout becomes low level again.

[0231] After entering the Tb21 stage of the display time DF2 of the frame picture, the output control signal Vctrl becomes high level, the shift signal Vnext is low level, the output control transistor M30 is turned on, the output control signal Vctrl is transmitted to the third node N3, the signal of the third node N3 becomes high level, the transmission control transistor M40 is turned off, the signal of the second node N2 cannot be transmitted to the fourth node N4, the signal of the fourth node N4 remains high level in the previous stage, and the second driving output transistor M62 is turned off; the signal of the first node N1 is low level, so that the first driving output transistor M61 is turned on, the gate drive signal Gout is consistent with the first level signal Vgl, and the gate drive signal Gout is low level.

[0232] In the Tb22 stage, the signal of the first node N1 becomes high level, the signal of the second node N2 also becomes high level, the shift signal Vnext continues to keep low level, the output control transistor M30 continues to be turned on, and the high level output control signal Vctrl is continuously provided to the third node N3, the signal of the third node N3 controls the transmission control transistor M40 to continue to keep the off state, the signal of the fourth node N4 continues to keep high level, and the second driving output transistor M61 is turned off; at the same time, the signal of the first node N1 controls the first driving output transistor M62 to be turned off, and the gate drive signal Gout keeps the low level of the previous stage.

[0233] In the Tb23 stage, the signal of the first node N1 continues to keep high level, the signal of the second node N2 is low level, the shift signal Vnext becomes high level, the output control transistor M30 is turned off, so that the third node N3 keeps the high level written in the previous stage, the transmission control transistor M40 continues to keep the off state, the signal of the fourth node N4 continues to keep high level, and the second driving output transistor M62 is still in the off state; at the same time, the signal of the first node N1 continues to control the first driving output transistor M61 to be in the off state, so that the gate drive signal Gout continues to keep the low level of the previous stage.

[0234] After the Tb23 stage of the display time DF2 of the frame picture, if the output control signal Vctrl continues to keep high level, the signal of the third node N3 and the signal of the fourth node N4 continue to keep high level, and the second driving output transistor M62 keeps the off state; or if the output control signal Vctrl becomes low level, the signal of the third node N3 is low level, and the transmission control transistor M40 is turned on, but at this time, the signal of the second node N2 is high level, and after the high level signal of the second node N2 is transmitted to the fourth node N4, the fourth node N4 still keeps high level, and the second driving output transistor M62 also keeps the off state; at the same time, because the signal of the first node N1 becomes low level, the low level signal controls the first driving output transistor M61 to be turned on again, the gate drive signal Gout continues to keep low level, until the next driving period is entered.

[0235] In this way, by controlling the active level and inactive level jump time of the output control signal Vctrl, the gate drive signal Gout output by the shift register G can be kept consistent with the shift signal Vnext, or the gate drive signal Gout output by the shift register G can be continuously kept low level, so as to meet the diversified display requirements of the display panel.

[0236] Optionally, FIG. 33 is a structural schematic diagram of another shift register according to an embodiment of the present application. As shown in FIG. 33, the shift register G further comprises a node control module 171 configured to receive the signal of the first node N1 and the second level signal Vgh, and control the signal of the fourth node N4.

[0237] The node control module 171 is configured to transmit the second level signal Vgh to the fourth node N4 under the control of the signal of the first node N1. In this way, when the signal of the third node N3 remains at a high level for a long time and the transmission control module 140 fails to transmit the signal of the second node N2 to the fourth node N4, the node control module 171 can be turned on by the signal of the first node N1, so that the node control module 171 can transmit the second level signal Vgh to the fourth node N4 to supplement the signal of the fourth node N4, so that the signal of the fourth node N4 can control the second drive output transistor M62 to remain in the off state, preventing the signal of the fourth node N4 from being insufficient to control the second drive output transistor M62 to be off, and affecting the output accuracy of the gate drive signal Gout.

[0238] It can be understood that the node control module 171 can be directly or indirectly electrically connected to the first node N1. For example, when the first shift control submodule 111 comprises the second voltage stabilizing transistor M12, the node control module 171 can be electrically connected to the first node N1 through the second voltage stabilizing transistor M12. Alternatively, when the first shift control submodule 111 comprises the filter transistor M15, the node control module 171 can be electrically connected to the first node N1 through the filter transistor M15, i.e., the node control module 171 can be electrically connected to the sixth node N6 first, and then electrically connected to the first node N1 through the filter transistor M15. Alternatively, when the first shift control submodule 111 comprises the filter transistor M15 and the third voltage stabilizing transistor M14, the node control module 171 can be electrically connected to the first node N1 through the third voltage stabilizing transistor M14 and the filter transistor M15 in sequence. The specific connection mode can be designed according to actual needs, and the present application is not limited in this regard. For ease of description, the node control module 171 is electrically connected to the first node N1 as an example for illustrative description in the absence of specific limitations.

[0239] Optionally, continuing to refer to FIG. 33, the node control module 171 can comprise a node control transistor M71; a gate of the node control transistor M71 is electrically connected to the first node N1, a first pole of the node control transistor M71 receives the second level signal Vgh, and a second pole of the node control transistor M71 is electrically connected to the fourth node N4. In this way, the node control transistor M71 can be turned on or turned off under the control of the signal of the first node N1, and when the node control transistor M71 is turned on under the control of the signal of the first node N1, the second level signal Vgh can be transmitted to the fourth node N4, so that the signal of the fourth node N4 can be consistent with the second level signal Vgh.

[0240] In this way, the node control transistor M71, the first shift output transistor M10, and the first drive output transistor M61 can have the same channel type, i.e., the new red of the first node N1 can control the node control transistor M71, the first shift output transistor M10, and the first drive output transistor M61 to be turned on or turned off at the same time, so that when the signal of the first node N1 is the active level, the signal of the fourth node N4 can be the inactive level, thereby ensuring the output accuracy of the gate drive signal Gout.

[0241] Optionally, FIG. 34 is a structural schematic diagram of another driving circuit according to an embodiment of the present application. Referring to FIGS. 33 and 34, the display panel can further comprise at least one second signal transmission line 42; the second signal transmission line 42 is used for transmitting the second level signal Vgh; in the same shift register G, the shift output module 120 and the node control module 171 are electrically connected to the same second signal transmission line 42.

[0242] In this way, the shift output module 120 and the node control module 171 of the same shift register G share one second signal transmission line 42, which is conducive to reducing the number of second signal transmission lines 42 electrically connected to the same shift register G, thereby facilitating the simplification of the structure of the display panel 100, and when the second signal transmission line 42 is arranged in the non-display area of the display panel 100, it is conducive to reducing the size of the non-display area of the display panel 100, thereby facilitating the narrow frame of the display panel 100.

[0243] Optionally, continuing to refer to FIG. 34, in the same shift register G, the shift output module 120 and the drive output module 160 are respectively electrically connected to different second signal transmission lines 42.

[0244] The driving output module 160 can be electrically connected to the second signal transmission line 421 through the second level terminal VGH1, and the shift output module 120 can be electrically connected to the second signal transmission line 422 through the second level terminal VGH2, so that the second signal transmission line 421 can provide the second level signal Vgh to the driving output module 160, and the second signal transmission line 422 can provide the second level signal Vg2 to the shift output module 120. At this time, the second level signal Vgh transmitted by the second signal transmission line 421 can be the same as or different from the second level signal Vgh transmitted by the second signal transmission line 421, and can be flexibly designed according to actual needs, so as to meet different display requirements of the display panel 100 and widen the application scenarios of the display panel 100. At the same time, when different second signal transmission lines 42 are used to provide the second level signal Vgh to the shift output module 120 and the driving output module 160 respectively, each second signal transmission line 42 can have a smaller load, so that each second signal transmission line 42 can have a smaller voltage drop, thereby facilitating the accuracy of the second level signal Vgh transmitted by each second signal transmission line 42.

[0245] In other optional embodiments, as shown in FIG. 35, when the shift output module 120 and the driving output module 160 are respectively electrically connected to different second signal transmission lines 42, the node control module 171 can also be electrically connected to the same second signal transmission line 421 as the driving output module 160. Alternatively, as shown in FIG. 36, the node control module 171, the driving output module 160 and the shift output module 120 can also be respectively electrically connected to different second signal transmission lines 42, for example, the driving output module 160 can be electrically connected to the second signal transmission line 421 through the second level terminal VGL1, the shift output module 120 can be electrically connected to the second signal transmission line 422 through the second level terminal VGL2, and the node control module 171 can be electrically connected to the second signal transmission line 423 through the second level terminal VGL3. It should be noted that the specific connection mode of the node control module 171, the driving output module 160 and the shift output module 120 to the second signal transmission line 42 can be designed according to actual needs, and the embodiments of the present application do not make specific limitations thereon. For the convenience of description, without special limitation, the technical solutions of the embodiments of the present application are exemplarily described taking the shift output module 120 and the driving output module 160 in the same shift register G being respectively electrically connected to different second signal transmission lines 42, and the shift output module 120 and the node control module 171 being electrically connected to the same second signal transmission line 422 as examples.

[0246] On the basis of the above-mentioned embodiments, optionally, Fig. 37 is a structural schematic diagram of another driving circuit according to an embodiment of the present application. In combination with Fig. 33 and Fig. 37, the driving output module 160 of any two adjacent shift registers G is electrically connected with different second signal transmission lines 42 respectively.

[0247] In an exemplary embodiment, the driving output module 160 of the odd-numbered shift register G can be electrically connected with the second signal transmission line 4211, and the driving output module 160 of the even-numbered shift register G can be electrically connected with the second signal transmission line 4212, so that any two adjacent shift registers G are electrically connected with different second signal transmission lines 42 respectively. At this time, each second signal transmission line 42 can be electrically connected with fewer shift registers G, thereby reducing the load of each second signal transmission line 42, and thus facilitating the reduction of the voltage drop of the second level signal Vgh transmitted by the second signal transmission line 42, so as to accurately provide the second level signal Vgh to each shift register G, and further to enable each shift register G to accurately output the gate driving signal Gout, and the display panel can accurately refresh the signal, thereby improving the display quality of the display panel.

[0248] Optionally, in combination with Fig. 33 and Fig. 38, the shift output module 120 of any two adjacent shift registers G can also be electrically connected with different second signal transmission lines 422 respectively, for example, the shift output module 120 of the odd-numbered shift register G can be electrically connected with the second signal transmission line 4221 through the second level terminal VGL2, and the shift output module 120 of the even-numbered shift register G can be electrically connected with the second signal transmission line 4222 through the second level terminal VGL2. In this way, the load of the second signal transmission line 422 providing the second level signal Vgh to the shift output module 120 can be reduced, thereby facilitating the accuracy of the second level signal Vgh and improving the accuracy of the shift signal Vnext output by the shift output module 120.

[0249] In an optional embodiment, when the signal of the fourth node N4 in the same shift register G is at the effective level, the driving output module 160 can transmit the second level signal Vgh of the second level terminal VGL1 to the driving signal terminal OUT as the effective level of the gate driving signal Gout, so that the accuracy of the signal transmitted by the second signal transmission line 421 electrically connected to the driving output module 160 will affect the accuracy of the effective level of the gate driving signal Gout. Therefore, by setting the line width of the second signal transmission line 421 electrically connected to the driving output module 160 to be greater than or equal to 12 μm, the second signal transmission line 421 can have a larger line width, which is beneficial to reduce the voltage drop of the second level signal Vgh when transmitted by the second signal transmission line 421, and ensure that the second signal transmission line 421 can accurately transmit the second level signal Vgh to each stage of the shift register G, and improve the accuracy of the gate driving signal Gout output by each stage of the shift register G.

[0250] In addition, the display panel can further include an enabling signal line 47, a control signal line 46, and at least two clock signal lines (44 and 45). The enabling signal line 47 can transmit an enabling control signal to the first stage of the shift register G1, the control signal line 46 can transmit an output control signal Vctrl to each stage of the shift register, and the two clock signal lines (44 and 45) can respectively transmit a first clock signal CK and a second clock signal XCK to each stage of the shift register G. In order to ensure that each stage of the shift register G can accurately output the shift signal Vnext, the first clock terminals Ck of adjacent two stages of the shift register G are respectively electrically connected to different clock signal transmission lines, and the second clock terminals Xck of adjacent two stages of the shift register G are respectively electrically connected to different clock signal lines. At this time, the first clock terminals Ck of the odd-numbered stages of the shift register G and the second clock terminals Xck of the even-numbered stages of the shift register G can be connected to the same clock signal line 44, and the second clock terminals Xck of the odd-numbered stages of the shift register G and the first clock terminals Ck of the even-numbered stages of the shift register G can be connected to the same clock signal line 45, so that the first clock signal CK of the odd-numbered stages of the shift register G can be reused as the second clock signal XCK of the even-numbered stages of the shift register G, and the second clock signal XCK of the odd-numbered stages of the shift register G can be reused as the first clock signal CK of the even-numbered stages of the shift register G.

[0251] Based on the above-mentioned embodiments, optionally, FIG. 39 is a structural schematic diagram of another shift register according to an embodiment of the present application. As shown in FIG. 39, the shift register G can further include a first reset module 181 configured to receive at least a first reset signal Vrst1 and a second level signal Vgh, and control the signal of the third node N3. In this way, the first reset module 181 can reset the third node N3 according to the first reset signal Vrst1 and the second level signal Vgh.

[0252] Optionally, with continued reference to FIG. 39, the first reset module 181 includes a first reset transistor M81. The gate of the first reset transistor M81 receives the first reset signal Vrst1, the first electrode of the first reset transistor M81 receives the second level signal Vgh, and the second electrode of the first reset transistor M81 is electrically connected to the third node N3. In this way, the first reset transistor M81 can be turned on or off under the control of the first reset signal Vrst1, and when the first reset transistor M81 is turned on by the first reset signal Vrst1, the second level signal Vgh can be transmitted to the third node N3 to reset the third node N3.

[0253] In an exemplary embodiment, before the effective level of the shift signal Vnext output by each stage of the shift register G starts, the first reset transistor M81 of each stage of the shift register G can receive the same or different first reset signal Vrst1, so that the first reset transistor M81 of each stage of the shift register G can be controlled to be turned on at the same time or at different times, so that the third node N3 of each stage of the shift register G can be reset at the same time or at different times, to ensure that the signal of the third node N3 of each stage of the shift register G can be prepared for the accurate output of the gate drive signal Gout by each stage of the shift register G.

[0254] It can be understood that in the shift register G, the signal of the first node N1 and the signal of the second node N2 can control the output shift signal Vnext of the shift register G, and generally when the signal of the first node N1 is at the effective level, the shift register G can be controlled to output the invalid level of the shift signal Vnext, and when the signal of the second node N2 is at the effective level, the shift register G can be controlled to output the effective level of the shift signal Vnext. Therefore, before the shift register G outputs the effective level of the shift signal Vnext, the signal of the first node N1 includes the effective level, at this time, the signal of the first node N1 can be multiplexed as the first reset signal Vrst1, so that the first reset transistor M81 in the shift register G can be turned on under the control of the signal of the first node N1, and the on time of the first reset transistor M81 is at least in the period before the shift signal Vnext is at the effective level, so that the third node N3 can be reset before the shift signal Vnext becomes the effective level; meanwhile, when the signal of the first node N1 is multiplexed as the first reset signal Vrst1, the number of signals provided to the shift register G can be reduced, which is beneficial to simplify the structure of the shift register G and reduce the driving cost of the shift register G.

[0255] Optionally, FIG. 40 is a structural schematic diagram of another shift register provided by an embodiment of the present application. As shown in FIG. 40, the shift register G can further include a second reset module 182, which is configured to receive at least the second reset signal Vrst2 and the first level signal Vgl, and control the signal of the third node N3. In this way, the second reset module 182 can reset the third node N3 according to the second reset signal Vrst2 and the first level signal Vgl.

[0256] Optionally, continuing to refer to FIG. 40, the second reset module can include a second reset transistor M82. The gate of the second reset transistor M82 receives the second reset signal Vrst2, the first pole of the second reset transistor M82 receives the first level signal Vgl, and the second pole of the second reset transistor M82 is electrically connected to the third node N3. In this way, the second reset transistor M82 can be turned on or turned off under the control of the second reset signal Vrst2, and when the second reset signal Vrst2 controls the second reset transistor M82 to be turned on, the first level signal Vgl can be transmitted to the third node N3 to reset the third node N3.

[0257] The time for the second reset transistor M82 to transmit the first level signal Vgl to the third node N3 can be the same as or different from the transmission time of the first reset transistor M81, and the embodiments of the present application do not make a specific limitation thereon. In an exemplary embodiment, after each stage of the shift register G ends outputting the active level of the shift signal Vnext, the second reset transistor M82 of each stage of the shift register G can receive the same or different second reset signal Vrst2, so that the second reset transistor M82 of each stage of the shift register G can be controlled to be turned on at the same time or at different times, so that the third node N3 of each stage of the shift register G can be reset at the same time or at different times, to ensure that the signal of the third node N3 of each stage of the shift register G can be prepared for the accurate output of the gate drive signal Gout of each stage of the shift register G.

[0258] It can be understood that, before and after the shift register G outputs the active level of the shift signal Vnext, the signal of the first node N1 includes the active level, at this time, the signal of the first node N1 can be multiplexed as the second reset signal Vrst2, so that the second reset transistor M82 can accurately reset the third node N3, while the number of signals provided to the shift register G is reduced, the structure of the shift register G is simplified, and the driving cost of the shift register G is reduced.

[0259] It should be noted that FIGS. 39 and 40 only exemplarily show the case where only the first reset module 181 or only the second reset module 182 exists in the shift register G, and in the embodiments of the present application, the first reset module 181 and the second reset module 182 can also exist at the same time, at this time, the first reset module 181 and the second reset module 182 can be turned on at different times, and the embodiments of the present application do not make a specific limitation on the premise of being able to realize the core inventive point of the present application. For ease of description, on the premise that there is no special limitation, the embodiments of the present application all take the shift register G including only the first reset module 181 as an example to exemplarily describe the technical solutions of the embodiments of the present application.

[0260] Optionally, FIG. 41 is a structural schematic diagram of another shift register provided by the embodiments of the present application, as shown in FIG. 41, the shift register G can further include a charging control module 172; the charging control module 172 is electrically connected between the output control module 130 and the third node N3; the charging control module 172 at least receives a charging control signal Vcha to control the transmission path of the output control signal Vctrl transmitted by the output control module 130 to the third node N3.

[0261] The charging control signal Vcha can be provided by a charging signal terminal CHA, so that the charging control signal Vcha controls the charging control module 172 to be turned on, a conduction path can be formed between the third node N3 and the output control module 130, and when the charging control signal Vcha controls the charging control module 172 to be turned off, the third node N3 and the output control module 130 cannot form a path, so that the output control signal Vctrl transmitted by the output control module 130 cannot be transmitted to the third node N3. In this way, when the charging control module 172 and the output control module 130 are turned on at the same time, the output control signal Vctrl can be transmitted to the third node N3, and when the charging control module 172 and the output control module 130 are turned on at the same time, the output control time of the output control signal Vctrl can be controlled to be shifted in turn and not to overlap each other, so that the time when each stage of the shift register G transmits the output control signal Vctrl to the third node N3 does not affect each other, which is beneficial to improve the accuracy of the output control signal Vctrl transmitted to the third node N3, and further beneficial to improve the accuracy of the gate drive signal Gout output by the shift register G.

[0262] Optionally, continuing to refer to FIG. 41, the charging control module 172 includes a charging control transistor M72; the gate of the charging control transistor M72 receives the charging control signal Vcha, the first electrode of the charging control transistor M72 is electrically connected with the output control module 130, and the second electrode of the charging control transistor M72 is electrically connected to the third node N3. In this way, the charging control transistor M72 can be turned on or turned off under the control of the charging control signal Vcha, and when the charging control signal Vcha controls the charging control transistor M72 to be turned on, a path can be formed between the output control module 130 and the third node N2. At this time, if the output control module 130 is also in a conduction state, the output control signal Vctrl can be transmitted to the third node N3 through the output control module 130 and the charging control transistor M72 in turn, so that the signal of the third node N3 can be consistent with the output control signal Vctrl.

[0263] In an exemplary embodiment, when the output control module 130 comprises an output control transistor M30, and the output control transistor M30 is turned on under the control of the shift signal Vnext being at an inactive level, because the active level start time of the shift signal Vnext output by each stage of the shift register G is shifted in turn, the active level start time of the shift signal Vnext output by the current stage of the shift register G has a certain shift time compared to the active level start time of the shift signal Vnext output by the previous stage of the shift register G, and the shift time of the active level start time of the shift signal Vnext output by each stage of the shift register G compared to the active level start time of the shift signal Vnext output by the previous stage of the shift register G do not overlap with each other, for example, when the shift time of the active level start time of the shift signal output by the second stage of the shift register compared to the active level start time of the shift signal output by the first stage of the shift register is a first shift time, and the shift time of the active level start time of the shift signal output by the third stage of the shift register compared to the active level start time of the shift signal output by the second stage of the shift register is a second shift time, the first shift time and the second shift time do not overlap with each other. Therefore, in the same shift register G, the time when the output control module 130 and the charging control module 172 are turned on at the same time can be set as the shift time of the active level start time of the shift signal Vnext output by the shift register G, which can make the time when each stage of the shift register G transmits the output control signal Vctrl to the third node N3 not overlap, i.e., the output control signals Vctrl transmitted by each stage of the shift register G to the third node N3 do not affect each other.

[0264] In an optional embodiment, the input signal Vin can be multiplexed as the charging control signal Vcha, so that the charging control transistor M72 can be turned on or off under the control of the input signal Vin.

[0265] When the shift output module 120 includes the first shift output transistor M10 and the second shift output transistor M20, the channel types of the first shift output transistor M10 and the second shift output transistor M20 are different from the channel type of the charge control transistor M72. Meanwhile, since the first shift output transistor M10 is turned on or off under the control of the signal of the first node N1, and the signal of the first node N1 is controlled by the first shift control sub-module 111, when the first shift control sub-module 111 includes a first input unit (a first input transistor M11), the first input unit (the first input transistor M11) can be turned on or off under the control of the first clock signal CK. When the first clock signal CK controls the first input unit (the first input transistor M11) to be turned on, the input signal Vin can be transmitted to the first node N1, so that the signal of the first node N1 is consistent with the input signal Vin, that is, when the input signal Vin is at a low level, the signal of the first node N1 is also at a low level, and when the input signal Vin is at a high level, the signal of the first node N1 is also at a high level. In this way, the time when the signal of the first node N1 controls the first shift output transistor M10 to be turned on can overlap with the time when the input signal Vin controls the charge control transistor M72 to be turned off, and the time when the signal of the first node N1 controls the first shift output transistor M10 to be turned off can overlap with the time when the input signal Vin controls the charge control transistor M72 to be turned on.

[0266] For example, when the charge control transistor M72 is an NMOS type transistor, and the output control transistor M30 and the first shift output transistor M10 are PMOS type transistors, the charge control transistor M72 is turned on when the input signal Vin is at a high level, and the first shift output transistor M10 is turned on when the signal of the first node N1 is at a low level. Since the signal of the first node N1 will be changed to a high level after the input signal Vin is changed to a high level, at this time, the first level signal Vgl cannot be transmitted to the shift signal end Next. Meanwhile, due to the certain hysteresis of the signal change of the second node N2, the signal of the second node N2 will also remain at a high level for a period of time when the first node N1 is changed to a high level, and the shift signal Vnext will remain at a low level, so that the shift signal Vnext can control the output control transistor M30 to be in a turned-on state, that is, during this period of time, the output control transistor M30 and the charge control transistor M72 are turned on at the same time, so that the output control signal Vctrl can be transmitted to the third node N3. In this way, by multiplexing the input signal Vin as the charge control signal Vcha, the time when the output control signal Vctrl is provided to the third node N3 of each stage of the shift register G does not overlap with each other on the premise of reducing the number of signals provided to the shift register G, which is conducive to improving the accuracy of the gate drive signal Gout output by each stage of the shift register G.

[0267] Optionally, FIG. 42 is a structural schematic diagram of another shift register according to an embodiment of the present application. As shown in FIG. 42, the shift register G can further include a compensation control module 191 and an output compensation module 192. The compensation control module 191 is configured to receive at least a signal of the first node N1, a signal of the fourth node N4, the first voltage level signal Vgl and the second voltage level signal Vgh, and control a signal of the fifth node N5. The output compensation module 192 is configured to receive at least the signal of the fifth node N5 and the first voltage level signal Vgl, and compensate the gate drive signal Gout.

[0268] The compensation control module 191 can control the signal of the fifth node N5 according to the first node N1, the fourth node N4, the first voltage level signal Vgl and the second voltage level signal Vgh. For example, when the signal of the first node N1 is at an effective voltage level, the compensation control module 191 can be controlled to transmit the first voltage level signal Vgl to the fifth node N5, so that the signal of the fifth node N5 can be consistent with the first voltage level signal Vgl. When the signal of the fourth node N4 is at an effective voltage level, the compensation control module 191 can be controlled to transmit the second voltage level signal Vgh to the fifth node N5, so that the signal of the fifth node N5 can be consistent with the second voltage level signal Vgh. In this way, the signal of the fifth node N5 can change between the first voltage level signal Vgl and the second voltage level signal Vgh. When the first voltage level signal Vgl is an effective voltage level for turning on the output compensation module 192, and the second voltage level signal Vgh is an ineffective voltage level for turning off the output compensation module 192, the output compensation module 192 can be controlled to turn on or turn off by controlling the signal of the fifth node N5. When the output compensation module 192 is turned on by the signal of the fifth node N5, the output compensation module 192 can transmit the first voltage level signal Vgl to the drive signal terminal OUT, so that the gate drive signal Gout can be kept at a low level by the first voltage level signal Vgl transmitted by the output compensation module 192 when the signal of the first node N1 cannot control the drive output module 160 to transmit the first voltage level signal Vgl to the drive signal terminal OUT, and the shift register G needs to output a low-level gate drive signal Gout. Therefore, the output accuracy of the gate drive signal can be improved.

[0269] Optionally, continuing to refer to FIG. 42, the compensation control module 191 comprises a first compensation control transistor M91 and a second compensation control transistor M92; a gate of the first compensation control transistor M91 is electrically connected to the first node N1, a first electrode of the first compensation control transistor M91 receives the first level signal Vgl, and a second electrode of the first compensation control transistor M91 is electrically connected to the fifth node N5; in this way, the first compensation control transistor M91 can be turned on or turned off under the control of the signal at the first node N1, and when the first compensation control transistor M91 is turned on under the control of the signal at the first node N1, the first compensation control transistor M91 can transmit the first level signal Vgl to the fifth node N5, so that the signal at the fifth node N5 can be consistent with the first level signal Vgl.

[0270] A gate of the second compensation control transistor M92 is electrically connected to the fourth node N4, a first electrode of the second compensation control transistor M92 receives the second level signal Vgh, and a second electrode of the second compensation control transistor M92 is electrically connected to the fifth node N5; in this way, the second compensation control transistor M92 can be turned on or turned off under the control of the signal at the fourth node N4, and when the second compensation control transistor M92 is turned on under the control of the signal at the fourth node N4, the second compensation control transistor M92 can transmit the second level signal Vgh to the fifth node N5, so that the signal at the fifth node N5 can be consistent with the second level signal Vgh.

[0271] In this way, the turn-on time of the first compensation control transistor M91 can be at least consistent with the turn-on time of the first drive output transistor M61, and the turn-on time of the second compensation control transistor M92 can be at least consistent with the turn-on time of the second drive output transistor M62, so that the signal at the fifth node N5 can be consistent with the signal of the gate drive signal Gout. When the signal at the fifth node N5 is used to control the output compensation module 192 to compensate the gate drive signal Gout, the gate drive signal Gout compensated by the output compensation module 192 can be consistent with the gate drive signal Gout output by the drive output module 160, thereby facilitating to improve the accuracy of the gate drive signal Gout.

[0272] Optionally, continuing to refer to FIG. 42, the output compensation module 192 comprises an output compensation transistor M93; a first electrode of the output compensation transistor M92 receives the first level signal Vgl, a second electrode of the output compensation transistor M93 is used to output a compensation signal of the gate driving signal Gout, and a gate of the output compensation transistor M93 is electrically connected to the fifth node N5; in this way, the output compensation transistor M93 can be turned on or turned off under the control of the signal of the fifth node N5, and when the output compensation transistor M93 is turned on under the control of the signal of the fifth node N5, the first level signal Vgl can be transmitted to the driving signal end OUT to compensate the gate driving signal Gout output by the driving signal end OUT.

[0273] In another optional embodiment, FIG. 43 is a structural schematic diagram of another shift register provided by an embodiment of the present application. As shown in FIG. 43, the shift register G can further comprise a first voltage stabilizing unit 193, and in this case, the gate of the output compensation transistor M93 can be electrically connected to the fifth node N5 through the first voltage stabilizing unit 193. In this way, the first voltage stabilizing unit 193 is used to isolate the compensation control module 191 and the output compensation transistor M93, which can stabilize the signals at the compensation control module 191 and the output compensation transistor M93, ensure the accuracy of the signals at the compensation control module 191 and the output compensation transistor M93, and improve the accuracy of the gate driving signal Gout output by the shift register G.

[0274] Optionally, continuing to refer to FIG. 43, the first voltage stabilizing unit 193 can comprise a first voltage stabilizing transistor M94; a first electrode of the first voltage stabilizing transistor M94 is electrically connected to the fifth node, a second electrode of the first voltage stabilizing transistor M94 is electrically connected to the gate of the output compensation transistor M93, and a gate of the first voltage stabilizing transistor M94 receives the first level signal Vgl.

[0275] In this case, the first level signal Vgl can control the first voltage stabilizing transistor M94 to be in a conductive state when the difference between the signal of the second electrode of the first voltage stabilizing transistor M94 and the signal of the second electrode is within a preset range, so as to avoid the signal at the second electrode of the first voltage stabilizing transistor M94 and / or the signal at the first electrode being instantaneously increased or decreased, which affects the stability of the signal at the second electrode or the signal at the first electrode of the first voltage stabilizing transistor M94, and is beneficial to improve the working stability of the shift register G.

[0276] Optionally, FIG. 44 is a structural schematic diagram of another shift register provided by an embodiment of the present application. As shown in FIG. 44, the shift register G can further comprise a first charge pump module 194, and the first charge pump module 194 is used to receive at least the first clock signal CK to control the signal amount of the first clock signal CK coupled to the fifth node N5.

[0277] The first clock signal CK changes between a valid level and an invalid level. When the first clock signal CK jumps and the compensation control module 191 stops transmitting the first level signal Vgl or the second level signal Vgh to the fifth node N5, the first charge pump module 194 can couple the jump amount of the first clock signal CK to the fifth node N5, so that the signal of the fifth node N5 changes accordingly to meet the conduction requirement of the output compensation module 192.

[0278] Optionally, continuing to refer to FIG. 44, the first charge pump module 194 includes a first capacitor C1. The first plate of the first capacitor C1 receives the first clock signal CK, and the second plate of the first capacitor C1 is electrically connected to the fifth node N5. Thus, according to the charge conservation principle of the capacitor, when the first clock signal CK received by the first plate of the first capacitor C1 changes between the valid level and the invalid level, the signal of the fifth node N5 electrically connected to the second plate of the first capacitor C1 changes accordingly. The signal of the second plate of the first capacitor C1 has the same change amount as the signal of the first plate, so that the first capacitor C1 can supplement the signal of the fifth node N5 when the signals of the first node N1 and the second node N4 both control the compensation control module 191 to stop transmitting the first level signal Vgl or the second level signal Vgh to the fifth node N5, thereby ensuring the stability of the signal of the fifth node N5.

[0279] It should be noted that the above only exemplarily describes the specific structure of the shift register. Under the premise of realizing the core invention point of the embodiments of the present application, after simple deformation of the shift register involved in each of the above embodiments, the obtained shift register also belongs to the protection scope of the embodiments of the present application, and will not be described again. For the convenience of description, the technical solutions of the embodiments of the present application will be exemplarily described taking the structure of one of the shift registers in the above embodiments as an example.

[0280] On the basis of the above embodiments, optionally, FIG. 45 is a partial cross-sectional structure schematic diagram of a display panel provided by the embodiments of the present application, as shown in FIG. 45, the shift register G can include at least one first transistor M1. The first transistor M1 includes a first gate Mg1 and a second gate Mg2, and the first gate Mg1 is electrically connected to the second gate Mg2.

[0281] The first gate Mg1 and the second gate Mg2 of the same first transistor M1 are electrically connected, so that the first gate Mg1 and the second gate Mg2 of the first transistor M1 can receive the same signal, thereby when the signal received by the first gate Mg1 and the second gate Mg2 controls the first transistor M1 to be turned on, the first transistor M1 can be quickly turned on, and the response speed of the first transistor M1 is improved; when the signal received by the first gate Mg1 and the second gate Mg2 controls the first transistor M1 to be turned off, the first transistor M1 can have a smaller leakage current, thereby the stability of the signal at the node electrically connected to the first transistor M1 can be improved.

[0282] It can be understood that, as shown in FIG. 45, the first gate Mg1 and the second gate Mg2 of the first transistor M1 can be arranged in the same layer, or in other embodiments, the first gate Mg1 and the second gate Mg2 of the first transistor M1 can also be located in different film layers, which can be designed according to actual needs, and the embodiment of the present application does not make specific limitation.

[0283] Optionally, FIG. 46 is a partial cross-sectional structure schematic diagram of another display panel provided by an embodiment of the present application, as shown in FIG. 46, the display panel 100 further includes: a substrate L1; a first metal layer L2 located on one side of the substrate L1; the first metal layer L2 includes a first gate Mg1; a semiconductor layer L3 located on a side of the first metal layer L2 away from the substrate L1; the first transistor M1 further includes a first active layer Mp1; the semiconductor layer L3 includes the first active layer Mp1; a second metal layer L4 located on a side of the semiconductor layer L3 away from the substrate L1; the second metal layer L4 includes a second gate Mg2.

[0284] The first metal layer L2 and the second metal layer L4 are located on opposite sides of the semiconductor layer L3, and the first metal layer L2, the semiconductor layer L3 and the second metal layer L4 are insulatively and separately arranged, so that a corresponding insulating layer L11 can be arranged between the first metal layer L2 and the semiconductor layer L3, and a corresponding insulating layer L12 can be arranged between the semiconductor layer L3 and the second metal layer L4. At the same time, since the first metal layer L1 includes the first gate Mg1, the second metal layer L4 includes the second gate Mg2, and the semiconductor layer L3 includes the first active layer Mp1, in the same first transistor M1, the first gate Mg1 and the second gate Mg2 are located on opposite sides of the first active layer Mp1, at this time, the first gate Mg1 can be the bottom gate of the first transistor M1, and the second gate Mg2 can be the top gate of the first transistor M1, so that the first transistor M1 has a top-bottom double-gate structure.

[0285] It can be understood that the first active layer Mp1 of the first transistor M1 can include a source region, a drain region and a channel region, the channel region connecting the source region and the drain region, and the first gate Mg1 and the second gate Mg2 both overlap with the channel region to control the number of carriers moving in a directional direction between the source region and the drain region in the channel region through signals received by the first gate Mg1 and the second gate Mg2, thereby controlling the turn-on or turn-off of the first transistor M1. At the same time, since the first gate Mg1 and the second gate Mg2 are the bottom gate and the top gate of the first transistor M1 respectively, and the first gate Mg1 is electrically connected with the second gate Mg2, when the signals received by the first gate Mg1 and the second gate Mg2 control the turn-on of the first transistor M1, it is beneficial to increase the electric field applied to the first active layer Mp1 of the first transistor M1, increase the number of carriers moving in a directional direction between the source region and the drain region, that is, equivalent to reduce the threshold voltage of the first transistor M1, so that the first transistor M1 can be quickly turned on and accurately transmit signals. Wherein, for the case that the first transistor M1 is a PMOS type transistor, the threshold voltage of the first transistor M1 is usually negative, at this time, reducing the threshold voltage of the first transistor M1 can be understood as making the threshold voltage of the first transistor M1 positive bias, that is, reducing the absolute value of the threshold voltage of the first transistor M1.

[0286] It should be noted that when the first gate Mg1 and the second gate Mg2 are located in different film layers, the corresponding via can be directly arranged between the first gate Mg1 and the second gate Mg2, so that the first gate Mg1 and the second gate Mg2 can be electrically connected through the via, or the first gate Mg1 and the second gate Mg2 can also be electrically connected by means of other connection structures.

[0287] Optionally, FIG. 47 is a schematic diagram of a partial cross-sectional structure of another display panel provided by an embodiment of the present application, as shown in FIG. 47, the display panel 100 can further include: a third metal layer L5 located on the side of the second metal layer L4 away from the substrate L1; the third metal layer L5 includes at least one gate connection structure E1; in the same first transistor, the first gate Mg1 is electrically connected with the gate connection structure E1 through the first via H1, and the gate connection structure E1 is electrically connected with the second gate Mg2 through the second via H2.

[0288] The third metal layer L5 and the second metal layer L4 can be provided with a corresponding insulating layer L13 therebetween, so that the third metal layer L5 and the second metal layer L4 can be insulated from each other. Meanwhile, the first gate Mg1 and the second gate Mg2 can be electrically connected to each other by means of the gate connection structure E1 of the third metal layer L5, that is, the gate connection structure E1 is different from the first gate Mg1 and the second gate Mg2 in layer, so that the setting position and size of the gate connection structure E1 are not limited by the size and position of the first gate Mg1 and the second gate Mg2 of the first transistor M1, thereby facilitating flexible setting of the gate connection structure E1 and compact structure of the shift register G and reducing the size of the shift register G.

[0289] Optionally, with reference to FIG. 47, the size w1 of the first via H1 is greater than the size w2 of the second via H2.

[0290] The third metal layer L5 provided with the gate connection structure E1 is located on the side of the second metal layer L4 away from the substrate L1, so that the distance between the third metal layer L5 and the second metal layer L4 is less than the distance between the third metal layer L5 and the first metal layer L2, that is, the depth of the first via H1 connected to the first gate Mg1 of the gate connection structure E1 is greater than the depth of the second via H2 connected to the second gate Mg2 of the gate connection structure E1. By setting the size w1 of the first via H1 to be greater than the size w2 of the second via H2, the first via H1 with a greater depth can have a greater size, thereby facilitating the setting of the first via H1. Meanwhile, when the first via H1 has a greater size, the gate connection structure E1 and the first gate Mg1 can have a greater contact area, thereby facilitating reduction of the contact impedance between the gate connection structure E1 and the first gate Mg1, balancing the problem of greater impedance difference caused by the connection distance, and facilitating improvement of the consistency of the signals received by the first gate Mg1 and the second gate Mg2, thereby accurately controlling the conduction or turn-off of the first transistor M1.

[0291] Optionally, FIG. 48 is a structural schematic diagram of another shift register according to an embodiment of the present application, FIG. 49 is a structural schematic diagram of another shift register according to an embodiment of the present application, and FIG. 50 is a structural schematic diagram of another shift register according to an embodiment of the present application. Referring to FIGS. 48-50, when the first input unit includes a first input transistor M11, the gate of the first input transistor M11 receives a first clock signal CK, the first electrode of the first input transistor M11 receives an input signal Vin, and the first electrode of the first input transistor M11 is coupled to a first node N1, and the second input unit includes a second input transistor M13, the gate of the second input transistor M13 receives the first clock signal CK, the first electrode of the second input transistor M13 receives the input signal Vin, and the first electrode of the second input transistor M13 is coupled to a sixth node N6, the first input transistor M11 and / or the second input transistor M13 is the first transistor M1.

[0292] As shown in FIG. 48, when only the first input transistor M11 is the first transistor M1, the first input transistor M11 includes a first gate Mg1 and a second gate Mg2, so that when the first clock signal CK controls the first input transistor M11 to be turned on, the first input transistor M11 can have a smaller threshold voltage, thereby accurately transmitting the input signal Vin to the first node N1 and improving the accuracy of the signal of the first node N1. As shown in FIG. 49, when only the second input transistor M13 is the first transistor M1, the second input transistor M13 includes a first gate Mg1 and a second gate Mg2, so that when the first clock signal CK controls the second input transistor M13 to be turned on, the second input transistor M13 can have a smaller threshold voltage, thereby accurately transmitting the input signal Vin to the sixth node N6 and improving the accuracy of the signal of the sixth node N6. Alternatively, as shown in FIG. 50, when the first input transistor M11 and the second input transistor M13 are both the first transistor M1, the accuracy of the signal of the first node N1 and the signal of the sixth node N6 can be improved simultaneously.

[0293] Optionally, FIGS. 51-55 are respectively top structure schematic diagrams of each film layer of a shift register according to an embodiment of the present application. In combination with FIGS. 50-55, when the first input transistor M11 and the second input transistor M13 are both the first transistor M1, the first gate Mg1 of the first input transistor M11 and the first gate Mg1 of the second input transistor M13 are electrically connected and are an integral structure, and the second gate Mg2 of the first input transistor M11 and the second gate Mg2 of the second input transistor M13 are electrically connected and are an integral structure; the first gate Mg1 of the first input transistor M11 and the first gate Mg1 of the second input transistor M13 are electrically connected with the gate connection structure E11 through the same first first via H11; and the gate connection structure E11 is electrically connected with the second gate Mg2 of the first input transistor M11 and the second gate Mg2 of the second input transistor M13 through the same first second via H21.

[0294] In the above embodiment, the gates of the first input transistor M11 and the second input transistor M13 both receive the first clock signal, that is, the first gate Mg1 of the first input transistor M11, the second gate Mg2 of the first input transistor M11, the first gate Mg1 of the second input transistor M13, and the second gate Mg2 of the second input transistor M13 all receive the first clock signal. At this time, the first gate Mg1 of the first input transistor M11 and the first gate Mg1 of the second input transistor M13 can be set as an integral structure, which is conducive to reducing the size of the first gates Mg1 of the first input transistor M11 and the second input transistor M13 in the first metal layer L2. Meanwhile, the second gate Mg2 of the first input transistor M11 and the second gate Mg2 of the second input transistor M13 can be set as an integral structure, which is conducive to reducing the size of the second gates Mg2 of the first input transistor M11 and the second input transistor M13 in the second metal layer L4, thereby facilitating the compact design of the first input transistor M11 and the second input transistor M13. Meanwhile, after the first gate Mg1 of the first input transistor M11 and the first gate Mg1 of the second input transistor M13 are set as an integral structure, and the second gate Mg2 of the first input transistor M11 and the second gate Mg2 of the second input transistor M13 are set as an integral structure, the first gate Mg1 of the first input transistor M11 and the first gate Mg1 of the second input transistor M13 can be electrically connected with the gate connection structure E11 through the same first first via H11, and the second gate Mg2 of the first input transistor M11 and the second gate Mg2 of the second input transistor M13 can be electrically connected with the gate connection structure E11 through the same first second via H21, which can reduce the number of settings of the first via, the second via, and the gate connection structure, thereby facilitating the simplification of the structure of the shift register G and the simplification of the preparation process of the display panel, and reducing the preparation cost of the display panel.

[0295] On the basis of the above-mentioned embodiments, optionally, FIG. 56 is a structural schematic diagram of another shift register according to an embodiment of the present application, FIG. 57 is a structural schematic diagram of another shift register according to an embodiment of the present application, and FIG. 58 is a structural schematic diagram of another shift register according to an embodiment of the present application. Referring to FIGS. 56-58, when the shift output module 120 includes a first shift output transistor M10 and a second shift output transistor M20, and the drive output module 160 includes a first drive output transistor M61 and a second drive output transistor M62, the gate of the first shift output transistor M10 is coupled to the first node N1, the first electrode of the first shift output transistor M10 receives the first level signal Vgl, and the second electrode of the first shift output transistor M10 is used to output the shift signal Vnext; the gate of the second shift output transistor M20 is electrically connected to the second node N2, the first electrode of the second shift output transistor M20 receives the second level signal Vgh, and the second electrode of the second shift output transistor M20 is used to output the shift signal Vnext; the gate of the first drive output transistor M61 is coupled to the first node N1, the first electrode of the first drive output transistor M61 receives the first level signal Vgl, and the second electrode of the first drive output transistor M61 is used to output the gate drive signal Gout; the gate of the second drive output transistor M62 is electrically connected to the fourth node N4, the first electrode of the second drive output transistor M62 receives the second level signal Vgh, and the second electrode of the second drive output transistor M62 is used to output the gate drive signal Gout; wherein the first shift output transistor M10 and / or the first drive output transistor M61 is the first transistor M1.

[0296] As shown in FIG. 56, when only the first shift output transistor M10 is the first transistor M1, the first shift output transistor M10 includes the first gate Mg1 and the second gate Mg2, so that when the signal at the first node N1 controls the first shift output transistor M10 to be turned on, the first shift output transistor M10 can have a smaller threshold voltage, thereby accurately transmitting the first level signal Vgl to the shift signal terminal Next, and improving the accuracy of the shift signal Vnext output by the shift signal terminal Next; as shown in FIG. 57, when only the first drive output transistor M61 is the first transistor M1, the first drive output transistor M61 includes the first gate Mg1 and the second gate Mg2, so that when the signal at the first node N1 controls the first drive output transistor M61 to be turned on, the first drive output transistor M61 can have a smaller threshold voltage, thereby accurately transmitting the first level signal Vgl to the drive signal terminal OUT, and improving the accuracy of the gate drive signal Gout output by the drive signal terminal OUT. Alternatively, as shown in FIG. 58, when both the first shift output transistor M10 and the first drive output transistor M61 are the first transistor M1, the accuracy of the shift signal Vnext and the gate drive signal Gout can be improved simultaneously.

[0297] Alternatively, as shown in FIGS. 51-55 and 58, when both the first shift output transistor M10 and the first drive output transistor M61 are the first transistor M1, the first gate Mg1 of the first shift output transistor M10 and the first gate Mg1 of the first drive output transistor M61 are electrically connected and form an integrated structure, and the second gate Mg2 of the first shift output transistor M10 and the second gate Mg2 of the first drive output transistor M61 are electrically connected and form an integrated structure; the first gate Mg1 of the first shift output transistor M10 and the first gate Mg1 of the first drive output transistor M61 are electrically connected to the gate connection structure E12 through the same second first via H12; and the gate connection structure E12 is electrically connected to the second gate Mg2 of the first shift output transistor M10 and the second gate Mg2 of the first drive output transistor M61 through the same second second via H22.

[0298] The first gate Mg1 of the first shift output transistor M10 and the first gate Mg1 of the first drive output transistor M61 are set as an integral structure, which is beneficial to reducing the size of the first gate Mg1 of the first shift output transistor M10 and the first drive output transistor M61 in the first metal layer L2. Meanwhile, the second gate Mg2 of the first shift output transistor M10 and the second gate Mg2 of the first drive output transistor M61 are set as an integral structure, which is beneficial to reducing the size of the second gate Mg2 of the first shift output transistor M10 and the first drive output transistor M61 in the second metal layer L4, thereby facilitating the compact design of the first shift output transistor M10 and the first drive output transistor M61. Meanwhile, after the first gate Mg1 of the first shift output transistor M10 and the first gate Mg1 of the first drive output transistor M61 are set as an integral structure, and the second gate Mg2 of the first shift output transistor M10 and the second gate Mg2 of the first drive output transistor M61 are set as an integral structure, the first gate Mg1 of the first shift output transistor M10 and the first gate Mg1 of the first drive output transistor M61 can be electrically connected with the gate connection structure E12 through the same second first via H12, and the second gate Mg2 of the first shift output transistor M10 and the second gate Mg2 of the first drive output transistor M61 can be electrically connected with the gate connection structure E12 through the same second second via H22, which can reduce the number of settings of the first via, the second via, and the gate connection structure, thereby facilitating the simplification of the structure of the shift register G, the simplification of the preparation process of the display panel, and the reduction of the preparation cost of the display panel.

[0299] Optionally, continuing to refer to FIGS. 51-55, when the potential maintaining module 150 includes a maintaining capacitor C6, the first plate C61 of the maintaining capacitor C6 receives a fixed level signal Vh, the second plate C62 of the maintaining capacitor C6 is electrically connected to the third node N3, the first shift output transistor M10 and the second shift output transistor M20 are arranged along the first direction Y when the fixed level signal Vh is the same as the first level signal Vgl, the first drive output transistor M61 and the second drive output transistor M62 are arranged along the first direction Y, the first shift output transistor M10 and the first drive output transistor M61 are arranged along the second direction X, the maintaining capacitor C4 is located between the first shift output transistor M10 and the first drive output transistor M61, and the first direction Y intersects the second direction X.

[0300] In this way, the holding capacitor C6 is located in the region surrounded by the first shift output transistor M10, the second shift output transistor M20, the first drive output transistor M61 and the second drive output transistor M62, so that the holding capacitor C6 can have a larger size, which is conducive to the compact design of the shift register G, reduces the size of the shift register G, and thus can reduce the occupied area of the driving circuit as a whole, which is conducive to the narrow frame of the display panel.

[0301] Optionally, FIG. 59 is a top view of a shift register according to an embodiment of the present application, and FIG. 60 is a cross-sectional view of the shift register along the A-A section in FIG. 59. In combination with FIGS. 59 and 60, the display panel can further include a fourth metal layer L6 located on the side of the third metal layer L5 away from the substrate L1; the fourth metal layer L6 includes at least one first signal transmission line 41; a fifth metal layer L7 located on the side of the second metal layer L4 away from the substrate L1, and the fifth metal layer L7 is insulated from the third metal layer L5 and the fourth metal layer L6; the second metal layer L4 includes a second plate of the holding capacitor C6, and the fifth metal layer L7 includes a first plate of the holding capacitor C6; the third metal layer L5 further includes a first connection structure E2; the first connection structure E2 is electrically connected to the first electrode of the first shift output transistor M10 through the fifth via H5, electrically connected to the first plate of the holding capacitor C6 through the sixth via H6, electrically connected to the first electrode of the first drive output transistor M61 through the seventh via H7, and electrically connected to the first signal transmission line 41 through the eighth via H8.

[0302] In this way, the first drive output transistor M61, the holding capacitor C6 and the first shift output transistor M10 are electrically connected to the same first connection structure E2 and electrically connected to the same first signal transmission line 41 through the same first connection structure E2, which is conducive to reducing the number of first connection structures in the display panel and reducing the number of vias, thereby simplifying the structure and preparation process of the shift register, and conducive to the low cost and high production yield of the display panel.

[0303] It can be understood that the relative position relationship between the fifth metal layer L7 and the fourth metal layer L6 and the third metal layer L5 is exemplarily shown in FIG. 60, for example, the fifth metal layer L7 is located between the second metal layer L4 and the third metal layer L5, the third metal layer L4 is located between the fifth metal layer L7 and the fourth metal layer L6, at this time, the third metal layer L5 and the fifth metal layer L7 should be provided with an insulating layer L14, and the third metal layer L5 and the fourth metal layer L6 should also be provided with an insulating layer L15, so that the structures in each metal layer are insulated from each other, and the transmitted signals do not interfere with each other. In the embodiment of the application, the relative position relationship of each film layer is not limited to the arrangement mode in FIG. 60, and can be designed according to actual needs, which will not be described here.

[0304] Optionally, FIG. 61 is a structural schematic diagram of another shift register provided by the embodiment of the application, as shown in FIG. 61, the driving output module 160 further includes a bootstrap capacitor C7; a first plate of the bootstrap capacitor is electrically connected with the gate of the first driving output transistor M61, and a second plate of the bootstrap capacitor is electrically connected with the second electrode of the first driving output transistor M61. In this way, when the signal at the first node N1 changes from an invalid level to a valid level, the first driving output transistor M61 starts to conduct, so that the first level signal Vgl can be transmitted to the second electrode of the first driving output transistor M61, that is, the second electrode output of the first driving output transistor M61, and the shift signal Vnext changes from a valid level to an invalid level; at this time, due to the existence of the bootstrap capacitor C7, the jump of the shift signal Vnext is coupled to the first node N1, so that the signal at the first node N1 can control the first driving output transistor M61 to further conduct, thereby reducing the output impedance of the first driving output transistor M61, improving the output step of the shift signal Vnext, and improving the output accuracy of the shift signal Vnext.

[0305] Optionally, in combination with FIGS. 59 to 61, at least part of the gate of the first driving output transistor M61 is multiplexed as the first plate of the bootstrap capacitor C7; the fifth metal layer L7 includes the second plate of the bootstrap capacitor C7; the third metal layer L5 further includes the first electrode lead Md1 of the first driving output transistor M61; the first electrode lead Md1 is electrically connected with the second electrode in the first active layer through the ninth via hole H9; and the second plate of the bootstrap capacitor C7 is electrically connected with the first electrode lead Md1 of the first driving output transistor M61 through the third via hole H3.

[0306] The first plate of the bootstrap capacitor C7 is electrically connected with the gate of the first driving output transistor M61, at least part of the gate of the first driving output transistor M61 can be reused as the bootstrap capacitor C7, the structure of the shift register is simplified, and the size of the shift register is reduced under the premise of ensuring the accuracy of the bootstrap capacitor C7 and the first driving output transistor M61. Meanwhile, the second plate of the bootstrap capacitor C7 is electrically connected with the first electrode lead Md1 through the third via hole H3, so that the bootstrap capacitor C7 can be accurately electrically connected with the second plate of the first driving output transistor M61, and the shift register can accurately output the gate driving signal Gout.

[0307] Optionally, with reference to FIGS. 59-61, the shortest distance between the seventh via hole H7 and the ninth via hole H9 is greater than the minimum width of the bootstrap capacitor C7. In this way, the seventh via hole H7 and the ninth via hole H9 can be prevented from being short-circuited with the bootstrap capacitor C7, so as to ensure that the shift register can accurately output the gate driving signal Gout, and the production yield of the display panel is improved.

[0308] Optionally, with reference to FIGS. 48, 59-61, when the display panel further includes a fourth metal layer L6 located on the side of the third metal layer L5 away from the substrate L1, the fourth metal layer L6 can include a plurality of signal transmission lines; the signal transmission lines can include at least one first signal transmission line 41, at least one second signal transmission line 42, a first clock signal line 44, a second clock signal line 45, and a control signal line 46; the first signal transmission line 41 is used for transmitting a first level signal Vgl; the second signal transmission line 42 is used for transmitting a second level signal Vgh; the first clock signal line 44 is used for transmitting a first clock signal CK of an odd-stage shift register and a second clock signal XCK of an even-stage shift register; the second clock signal line 45 is used for transmitting the second clock signal XCK of the odd-stage shift register and the first clock signal CK of the even-stage shift register; and the control signal line 46 is used for transmitting the output control signal Vctrl of each stage of shift register. In this way, each signal line is arranged on the fourth metal layer L6, and each signal line can be electrically connected with transistors, capacitors and other structures through corresponding connection structures.

[0309] Optionally, with reference to FIG. 59, the distance between any two adjacent first signal transmission lines 41 and second signal transmission lines 42 is a first distance D1; the distance between the first clock signal line 44 and the second clock signal line 45 is a second distance D2; and the first distance D1 is greater than the second distance D2.

[0310] The first clock signal line 44 and the second clock signal line 45 are used to transmit clock signals (CK, XCK) changing between an effective level and an ineffective level, so that the clock signals (CK, XCK) can continuously charge and discharge the first clock signal line 44 and the second clock signal line 45, and the accuracy of the clock signals transmitted by the first clock signal line 44 and the second clock signal line 45 can be ensured when the distance between the first clock signal line 44 and the second clock signal line 45 is short; the first level signal Vgl transmitted by the first signal transmission line 41 and the second level signal Vgh transmitted by the second signal transmission line 42 are fixed level signals, so that when the first level signal Vgl and the second level signal Vgh are interfered by external signals, the transmission accuracy of the first level signal Vgl and the second level signal Vgh will be affected, and the first level signal Vgl and the second level signal Vgh are two signals with opposite polarities, so that a coupling capacitor will be formed between the first signal transmission line 41 and the second signal transmission line 42, at this time, by setting the first distance D1 between the first signal transmission line 41 and the second signal transmission line 41 to a relatively long distance, the capacitance of the coupling capacitor can be reduced, so that the influence of the first level signal Vgl on the second level signal Vgh and the influence of the second level signal Vgh on the first level signal Vgl can be improved, and the accuracy of the shift signal Vnext output by the shift register and the gate drive signal Gout can be improved.

[0311] Optionally, the first clock signal line 44 and the second clock signal line 45 are two adjacent signal transmission lines in the plurality of signal transmission lines. In this way, the first clock signal line 44 and the second clock signal line 45 transmitting alternating signals are set as two adjacent signal lines, so that the coupling amount of the clock signals transmitted by the first clock signal line 44 and the second clock signal line 45 to other signal lines can be reduced, and the accuracy of the signals transmitted by the signal transmission lines can be improved.

[0312] Optionally, with reference to FIGS. 59 and 61, when the first shift control submodule 111 includes the first coupling control transistor M16, and the second shift control submodule 112 includes at least the first control transistor M21, the second control transistor M22, the third control transistor M23, the fourth control transistor M24, and the control capacitor C3, the gate of the first coupling control transistor M16 is electrically connected to the sixth node N6, the first electrode of the first coupling control transistor M16 receives the second clock signal XCK, and the second electrode of the first coupling control transistor M16 is electrically connected to the second charge pump unit (C2); the gate of the first control transistor M21 receives the first clock signal CK, the first electrode of the first control transistor M21 receives the first voltage level signal Vgl, and the second electrode of the first control transistor M21 is electrically connected to the seventh node N7; the gate of the second control transistor M22 is coupled to the first node N1, the first electrode of the second control transistor M22 receives the first clock signal CK, and the second electrode of the second control transistor M22 is electrically connected to the seventh node N7; the gate of the third control transistor M23 is coupled to the seventh node N7, the first electrode of the third control transistor M23 receives the second clock signal XCK, and the second electrode of the third control transistor M23 is electrically connected to the eighth node N8; the gate of the fourth control transistor M24 receives the second clock signal XCK, the first electrode of the fourth control transistor M24 is electrically connected to the eighth node N8, and the second electrode of the fourth control transistor M24 is electrically connected to the second node N2; and the control capacitor C3 is electrically connected between the seventh node N7 and the eighth node N8.

[0313] Correspondingly, the third metal layer can further include a second connection structure E3; the third control transistor M23 and the fourth control transistor M24 of the odd-stage shift register and the first coupling control transistor M21 of the even-stage shift register are electrically connected to the second clock signal line 45 through the same second connection structure E3. In this way, in the adjacent two-stage shift registers, the transistors that are closer and electrically connected to the same signal transmission line can be electrically connected to the same connection structure, thereby reducing the number of connection structures provided in the shift register, which is conducive to simplifying the structure of the shift register and facilitating the small size of the shift register.

[0314] It should be noted that the above only exemplarily illustrates the structure of the shift register including the first transistor M1, and the shift register in the embodiments of the present application includes at least one first transistor M1, i.e., the number of the first transistors M1 can be one or more, which can be set according to actual needs, and the embodiments of the present application do not make specific limitations thereon. When a part of the transistors in the shift register are the first transistors M1, the other part of the transistors can be the second transistors.

[0315] Optionally, FIG. 62 is a schematic view of a partial film layer structure of still another display panel according to an embodiment of the present application. As shown in FIG. 62, the shift register further includes a plurality of second transistors M2; the second transistor M2 includes a second active layer Mp2 and a third gate Mg3; the semiconductor layer L3 further includes the second active layer Mp2; and the second metal layer L4 further includes the third gate Mg3. In this way, the second active layer Mp2 of the second transistor M2 is arranged in the same layer as the first active layer Mp1 of the first transistor M1, and the third gate Mg3 of the second transistor M2 is arranged in the same layer as the second gate Mg2 of the first transistor M1, so that no additional film layer needs to be arranged for the second transistor M2, which is conducive to the thinning of the display panel.

[0316] Optionally, FIG. 63 is a schematic view of a partial film layer structure of still another display panel according to an embodiment of the present application. As shown in FIG. 63, the first metal layer L2 further includes a first light shielding structure Mb; and the first light shielding structure Mb covers the channel region of each second active layer Mp2 in the thickness direction Z of the display panel.

[0317] The active layer of the semiconductor layer is irradiated by light to generate a certain amount of photo-generated carriers, which affect the characteristics of the transistor, for example, affecting the leakage current of the transistor when the transistor is off, and affecting the accuracy of the signal transmitted by the transistor when the transistor is on.

[0318] Since the first metal layer L2 is located on the side of the semiconductor layer L3 away from the second metal layer L4, and the third gate Mg3 of the second transistor M2 is arranged in the second metal layer L4, the third gate Mg3 is a top gate of the second transistor, so that the point gate Mg3 can block the light incident from the side away from the second metal layer L4 from irradiating the second active layer Mp2. Meanwhile, the first light shielding structure Mb arranged in the first metal layer L1 can shield the light incident from the side of the substrate L1, thereby improving the accuracy of the signal transmitted by the second transistor M2.

[0319] In addition, during the transportation and assembly of the display panel, a certain amount of static electricity is generated, which affects the conduction characteristics of the transistor and even damages the transistor. At this time, the first light shielding structure Mb can also play a certain role in static electricity discharge, so that the static electricity is discharged through the first light shielding structure Mb, preventing the accumulation of static electricity from damaging the transistor and other devices.

[0320] Optionally, the first light shielding structure Mb can receive a shielding signal, which can shield external signals from interfering with the signal transmitted by the second transistor M2, thereby improving the accuracy of the signal transmitted by the second transistor M2.

[0321] The flat panel signal received by the first light shielding structure Mb overlapping with the second active layer Mp2 of each second transistor M2 can be the same or different, and embodiments of the present application do not make specific limitation thereon, and in an optional embodiment, a corresponding shielding signal can be provided according to the channel type of each second transistor M2, and the threshold voltage of the second transistor M2 can be regulated by the shielding signal, so that the threshold voltage of the second transistor M2 can be small enough to meet the conduction characteristics of the second transistor M2.

[0322] In another optional embodiment, the voltage of the shielding signal is V0, the voltage of the first level signal Vgl is V1, and the voltage of the second level signal Vgh is V2, wherein |V0|<|V1| and |V0|<|V2|. In this way, the threshold voltage of the second transistor M2 is positively biased, thereby facilitating the conduction characteristics of the second transistor.

[0323] Based on the same inventive concept, embodiments of the present application also provide a display device, which comprises the display panel provided by the embodiments of the present application. Therefore, the display device has the technical features of the display panel and the driving method provided by the embodiments of the present application, and can achieve the beneficial effects of the display panel provided by the embodiments of the present application. The same parts can be referred to the above description of the display panel provided by the embodiments of the present application, and will not be described here.

[0324] For example, FIG. 64 is a structural schematic diagram of a display device provided by an embodiment of the present application. As shown in FIG. 64, the display device 200 comprises the display panel 100 provided by an embodiment of the present application. The display device 200 provided by the embodiments of the present application can be any electronic product with display function, including but not limited to the following categories: mobile phone, television, notebook computer, desktop display, tablet computer, digital camera, smart bracelet, smart glasses, vehicle-mounted display, medical equipment, industrial control equipment, touch interaction terminal, etc., and the embodiments of the present application do not make special limitation thereon.

[0325] It should be noted that the above are only the preferred embodiments of the present application and the technical principles applied. Those skilled in the art will understand that the present application is not limited to the specific embodiments described herein, and those skilled in the art can make various obvious changes, readjustments and substitutions without departing from the scope of the present application. Therefore, although the present application has been described in more detail through the above embodiments, the present application is not limited to the above embodiments, and can include more other equivalent embodiments without departing from the concept of the present application, and the scope of the present application is determined by the appended claims.

Claims

A display panel, characterized by comprising: The application relates to a driving circuit. The driving circuit comprises a cascade N-stage shift register. The shift register comprises: a shift control module for receiving at least an input signal, a first clock signal and a second clock signal, controlling a signal of a first node and a signal of a second node; a shift output module for receiving at least the signal of the first node, the signal of the second node, a first level signal and a second level signal, controlling an output shift signal; the shift signal output by the shift register of an xth stage is the input signal received by the shift register of a yth stage, 1<=x<=N, 1<=y<=N, x!=y, and x, y and N are positive integers; an output control module for receiving at least an output control signal and the shift signal, and controlling a path of the output control signal transmitted to a third node under the control of the shift signal; a transmission control module for receiving at least the signal of the second node and the signal of the third node, and controlling a signal of a fourth node; a potential holding module for receiving a fixed level signal, and maintaining the signal of the third node; a driving output module for receiving at least the signal of the fourth node, the signal of the first node, the first level signal and the second level signal, and controlling an output gate driving signal. The fixed level signal is different from at least the second level signal. The fixed level signal is also different from the first level signal. The display panel according to claim 1, characterized in that, The fixed level signal is the same as the first level signal. The display panel according to claim 1, characterized in that, The application further comprises at least one first signal transmission line; the first signal transmission line is used for transmitting the first level signal. The display panel according to claim 3, characterized in that, In the same shift register, the driving output module and the potential holding module are electrically connected to the same first signal transmission line. In the same shift register, the shift output module is electrically connected to the first signal transmission line through the potential holding module and / or the driving output module. The display panel according to claim 4, characterized in that, In the same shift register, the shift output module and the driving output module are respectively electrically connected to different first signal transmission lines. The display panel according to claim 4, characterized in that, The driving output modules of any two adjacent shift registers are respectively electrically connected to different first signal transmission lines. The display panel according to claim 4, characterized in that, The driving output modules of all the shift registers are electrically connected to the same first signal transmission line. The display panel according to claim 4, characterized in that, The line width of the first signal transmission line electrically connected to the driving output module is greater than or equal to 12 mu m. The shift register further comprises: The display panel according to claim 1, characterized in that, a node control module for receiving the signal of the first node and the second level signal, and controlling the signal of the fourth node. The application further comprises: The display panel according to claim 9, characterized in that, at least one second signal transmission line; the second signal transmission line is used for transmitting the second level signal; In the same shift register, the shift output module and the node control module are electrically connected to the same second signal transmission line. In the same shift register, the shift output module and the driving output module are respectively electrically connected to different second signal transmission lines. The display panel according to claim 10, characterized in that, The driving output modules of any two adjacent shift registers are respectively electrically connected to different second signal transmission lines. The display panel according to claim 10, characterized in that, ​ The display panel according to claim 10, characterized in that, A line width of the second signal transmission line electrically connected with the driving output module is greater than or equal to 12 μm. The display panel according to claim 9, characterized in that, The node control module comprises a node control transistor. A gate of the node control transistor is electrically connected to the first node, a first pole of the node control transistor receives the second level signal, and a second pole of the node control transistor is electrically connected to the fourth node. The display panel according to claim 1, characterized in that, The potential holding module comprises a potential holding capacitor. A first pole plate of the potential holding capacitor receives the fixed level signal, and a second pole plate of the potential holding capacitor is electrically connected to the third node. The display panel according to claim 1, characterized in that, The transmission control module comprises a transmission control transistor. A gate of the transmission control transistor is electrically connected to the third node, a first pole of the transmission control transistor is electrically connected to the second node, and a second pole of the transmission control transistor is electrically connected to the fourth node. The display panel according to claim 1, characterized in that, The output control module comprises an output control transistor. A gate of the output control transistor receives the shift signal, a first pole of the output control transistor receives the output control signal, and a second pole of the output control transistor is electrically connected to the third node. The display panel of claim 17, wherein The output control transistor is a double-gate transistor. The display panel according to claim 1, characterized in that, The shift register further comprises a charging control module. The charging control module is electrically connected between the output control module and the third node, and the charging control module at least receives a charging control signal to control a transmission path of the output control signal transmitted by the output control module to the third node. The display panel of claim 19, wherein The charging control module comprises a charging control transistor. A gate of the charging control transistor receives the charging control signal, a first pole of the charging control transistor is electrically connected to the output control module, and a second pole of the charging control transistor is electrically connected to the third node. The display panel according to claim 20, wherein The shift output module comprises a first shift output transistor and a second shift output transistor. A gate of the first shift output transistor is coupled to the first node, a first pole of the first shift output transistor receives the first level signal, and a second pole of the first shift output transistor is used for outputting the shift signal. A gate of the second shift output transistor is electrically connected to the second node, a first pole of the second shift output transistor receives the second level signal, and a second pole of the second shift output transistor is used for outputting the shift signal. The display panel of claim 21, wherein The input signal is multiplexed as the charging control signal. The channel type of the first shift output transistor and the second shift output transistor is different from the channel type of the charging control transistor. The display panel according to claim 1, characterized in that, The shift register further comprises: A first reset module for at least receiving a first reset signal and the second level signal to control the signal of the third node. The display panel according to claim 23, characterized in that, The first reset module comprises a first reset transistor. A gate of the first reset transistor receives the first reset signal, a first pole of the first reset transistor receives the second level signal, and a second pole of the first reset transistor is electrically connected to the third node. According to the shift register of claim 23, the signal of the first node is multiplexed as the first reset signal. The display panel according to claim 1, characterized in that, The shift register further comprises: a second reset module configured to receive at least a second reset signal and the first level signal, and control a signal of the third node. The display panel of claim 26, wherein The second reset module comprises a second reset transistor. A gate of the second reset transistor receives the second reset signal, a first pole of the second reset transistor receives the first level signal, and a second pole of the second reset transistor is electrically connected to the third node. The display panel of claim 26, wherein The signal of the first node is multiplexed as the second reset signal. The display panel according to claim 1, characterized in that, The shift register further comprises: a compensation control module configured to receive at least a signal of the first node, a signal of the fourth node, the first level signal and the second level signal, and control a signal of a fifth node; an output compensation module configured to receive at least the signal of the fifth node and the first level signal, and compensate the gate drive signal. The display panel of claim 29, wherein The output compensation module comprises an output compensation transistor. A first pole of the output compensation transistor receives the first level signal, a second pole of the output compensation transistor is configured to output a compensation signal of the gate drive signal, and a gate of the output compensation transistor is electrically connected to the fifth node, or the gate of the output compensation transistor is electrically connected to the fifth node through a first voltage stabilizing unit. The display panel of claim 30, wherein The first voltage stabilizing unit comprises a first voltage stabilizing transistor. A first pole of the first voltage stabilizing transistor is electrically connected to the fifth node, a second pole of the first voltage stabilizing transistor is electrically connected to the gate of the output compensation transistor, and a gate of the first voltage stabilizing transistor receives a first level signal. The display panel of claim 29, wherein The compensation control module comprises a first compensation control transistor and a second compensation control transistor. A gate of the first compensation control transistor is electrically connected to the first node, a first pole of the first compensation control transistor receives the first level signal, and a second pole of the first compensation control transistor is electrically connected to the fifth node. A gate of the second compensation control transistor is electrically connected to the fourth node, a first pole of the second compensation control transistor receives the second level signal, and a second pole of the second compensation control transistor is electrically connected to the fifth node. The display panel of claim 29, wherein The shift register further comprises: a first charge pump module configured to receive at least the first clock signal, and control a signal amount of the first clock signal coupled to the fifth node. The display panel of claim 33, wherein The first charge pump module comprises a first capacitor. A first pole plate of the first capacitor receives the first clock signal, and a second pole plate of the first capacitor is electrically connected to the fifth node. The display panel according to claim 1, characterized in that, The shift control module comprises a first shift control submodule and a second shift control submodule. The first shift control submodule is configured to receive at least the input signal and the first clock signal, and control the signal of the first node. The second shift control submodule is configured to receive at least the first clock signal, the second clock signal, the first level signal and the signal of the first node, and control the signal of the second node. The display panel of claim 35, wherein The first shift control submodule comprises a first input unit and a second charge pump unit. The first input unit is configured to receive at least the input signal and the first clock signal, and control a signal of the first node; The second charge pump unit is configured to receive at least the second clock signal, and control an amount of the second clock signal coupled to the first node. The display panel of claim 36, wherein The first input unit comprises a first input transistor; The gate of the first input transistor receives the first clock signal, the first pole of the first input transistor receives the input signal, and the first pole of the first input transistor is electrically connected to the first node, or the second pole of the first input transistor is electrically connected to the first node through a second voltage stabilizing unit. The display panel of claim 37, wherein The second voltage stabilizing unit comprises a second voltage stabilizing transistor; The gate of the second voltage stabilizing transistor receives the first level signal, the first pole of the second voltage stabilizing transistor is electrically connected to the second pole of the first input transistor, and the second pole of the second voltage stabilizing transistor is electrically connected to the first node. The display panel of claim 36, wherein The second charge pump unit comprises a second capacitor; The first plate of the second capacitor receives the second clock signal, and the second plate of the second capacitor is coupled to the first node. The display panel of claim 36, wherein The first shift control sub-module further comprises a second input unit and a filter unit; The second charge pump unit is electrically connected to the first node through the filter unit, and the second charge pump unit and the filter unit are coupled to a sixth node; The second input unit is configured to receive at least the input signal and the first clock signal, and control a signal of the sixth node; The filter unit is configured to receive at least a coupling signal of the second charge pump unit and a signal of the sixth node, and control a signal of the first node. The display panel of claim 40, wherein The second input unit comprises a second input transistor; The gate of the second input transistor receives the first clock signal, the first pole of the second input transistor receives the input signal, and the first pole of the second input transistor is electrically connected to the sixth node, or the second pole of the second input transistor is electrically connected to the sixth node through a third voltage stabilizing unit. The display panel of claim 41, wherein The third voltage stabilizing unit comprises a third voltage stabilizing transistor; The gate of the third voltage stabilizing transistor receives the first level signal, the first pole of the third voltage stabilizing transistor is electrically connected to the second pole of the second input transistor, and the second pole of the third voltage stabilizing transistor is electrically connected to the sixth node. The display panel of claim 40, wherein The filter unit comprises a filter transistor; The gate and the first pole of the filter transistor are both electrically connected to the sixth node, and the second pole of the filter transistor is electrically connected to the first node. The display panel of claim 40, wherein The first shift control sub-module further comprises a first coupling control unit; The first coupling control unit is electrically connected between the second charge pump unit and a second clock terminal, and the first coupling control unit is also electrically connected to the sixth node; the first coupling control unit is configured to control a path of the second clock signal of the second clock terminal transmitted to the second charge pump unit according to a signal of the sixth node. The display panel of claim 44, wherein The first coupling control unit comprises a first coupling control transistor; A gate of the first coupling control transistor is electrically connected with the sixth node, a first pole of the first coupling control transistor receives the second clock signal, and a second pole of the first coupling control transistor is electrically connected with the second charge pump unit. The display panel of claim 44, wherein The first shift control sub-module further comprises a second coupling control unit; The second coupling control unit is electrically connected between the second charge pump unit and a second voltage level terminal, and the second coupling control unit is also electrically connected with the second shift control sub-module; the second coupling control unit is configured to control a path of the second voltage level signal of the second voltage level terminal to the second charge pump unit under control of the second shift control sub-module. The display panel of claim 46, wherein The second coupling control unit comprises a second coupling control transistor. A gate of the second coupling control transistor is electrically connected with the second shift control sub-module, a first pole of the second coupling control transistor receives the second voltage level signal, and a second pole of the second coupling control transistor is electrically connected with the second charge pump unit. The display panel according to claim 1, characterized in that, The shift register further comprises at least one first transistor; The first transistor comprises a first gate and a second gate, and the first gate is electrically connected with the second gate. The display panel of claim 40, wherein The display panel further comprises: a substrate; a first metal layer located on one side of the substrate; the first metal layer comprises the first gate; a semiconductor layer located on a side of the first metal layer away from the substrate; the first transistor further comprises a first active layer; the semiconductor layer comprises the first active layer; a second metal layer located on a side of the semiconductor layer away from the substrate; the second metal layer comprises the second gate. The display panel of claim 49, wherein The display panel further comprises: a third metal layer located on a side of the second metal layer away from the substrate; the third metal layer comprises at least one gate connection structure; In the same first transistor, the first gate is electrically connected with the gate connection structure through a first via, and the gate connection structure is electrically connected with the second gate through a second via. The display panel of claim 50, wherein The size of the first via is greater than the size of the second via. The display panel of claim 50, wherein The first input unit comprises a first input transistor; a gate of the first input transistor receives the first clock signal, a first pole of the first input transistor receives the input signal, and the first pole of the first input transistor is coupled to the first node; The second input unit comprises a second input transistor; A gate of the second input transistor receives the first clock signal, a first pole of the second input transistor receives the input signal, and the first pole of the second input transistor is coupled to the sixth node; The first input transistor and / or the second input transistor are the first transistor. The display panel of claim 52, wherein When the first input transistor and the second input transistor are both the first transistor, the first gate of the first input transistor and the first gate of the second input transistor are electrically connected and form an integral structure, and the second gate of the first input transistor and the second gate of the second input transistor are electrically connected and form an integral structure. The first gate of the first input transistor and the first gate of the second input transistor are electrically connected with the gate connection structure through the same first first via hole; The gate connection structure is electrically connected with the second gate of the first input transistor and the second gate of the second input transistor through the same first second via hole. The display panel of claim 50, wherein The shift output module comprises a first shift output transistor and a second shift output transistor; the gate of the first shift output transistor is coupled to the first node, the first pole of the first shift output transistor receives the first level signal, and the second pole of the first shift output transistor is used for outputting the shift signal; the gate of the second shift output transistor is electrically connected to the second node, the first pole of the second shift output transistor receives the second level signal, and the second pole of the second shift output transistor is used for outputting the shift signal; The driving output module comprises a first driving output transistor and a second driving output transistor; The gate of the first driving output transistor is coupled to the first node, the first pole of the first driving output transistor receives the first level signal, and the second pole of the first driving output transistor is used for outputting the gate driving signal; The gate of the second driving output transistor is electrically connected to the fourth node, the first pole of the second driving output transistor receives the second level signal, and the second pole of the second driving output transistor is used for outputting the gate driving signal; The first shift output transistor and / or the first driving output transistor are the first transistor. The display panel of claim 54, wherein When the first shift output transistor and the first driving output transistor are the first transistor, the first gate of the first shift output transistor and the first gate of the first driving output transistor are electrically connected and form an integrated structure, and the second gate of the first shift output transistor and the second gate of the first driving output transistor are electrically connected and form an integrated structure; The first gate of the first shift output transistor and the first gate of the first driving output transistor are electrically connected with the gate connection structure through the same second first via hole; The gate connection structure is electrically connected with the second gate of the first shift output transistor and the second gate of the first driving output transistor through the same second second via hole. The display panel of claim 54, wherein The potential holding module comprises a holding capacitor; the first pole plate of the holding capacitor receives the fixed level signal, and the second pole plate of the holding capacitor is electrically connected to the third node; the fixed level signal is the same as the first level signal; The first shift output transistor and the second shift output transistor are arranged along a first direction; the first driving output transistor and the second driving output transistor are arranged along the first direction; the first shift output transistor and the first driving output transistor are arranged along a second direction; the holding capacitor is located between the first shift output transistor and the first driving output transistor; the first direction intersects the second direction. The display panel of claim 56, wherein Further comprising: A fourth metal layer is located on a side of the third metal layer away from the substrate; the fourth metal layer includes at least one first signal transmission line; A fifth metal layer is located on a side of the second metal layer away from the substrate, and the fifth metal layer is insulated from the third metal layer and the fourth metal layer; the second metal layer includes a second plate of the holding capacitor, and the fifth metal layer includes a first plate of the holding capacitor; The third metal layer further includes a first connection structure; The first connection structure is electrically connected to the first electrode of the first shift output transistor through a fifth via, electrically connected to the first plate of the holding capacitor through a sixth via, electrically connected to the first electrode of the first drive output transistor through a seventh via, and electrically connected to the first signal transmission line through an eighth via. The display panel of claim 57, wherein The drive output module further includes a bootstrap capacitor; at least part of the gate of the first drive output transistor is multiplexed as a first plate of the bootstrap capacitor; and the fifth metal layer includes a second plate of the bootstrap capacitor. The third metal layer further includes a first electrode lead of the first drive output transistor; and the first electrode lead is electrically connected to the second electrode in the first active layer through a ninth via. The second plate of the bootstrap capacitor is electrically connected to the first electrode lead of the first drive output transistor through a third via. The display panel of claim 58, wherein The shortest distance between the seventh via and the ninth via is greater than the minimum width of the bootstrap capacitor. The display panel of claim 50, wherein Further comprising: A fourth metal layer is located on a side of the third metal layer away from the substrate; the fourth metal layer includes a plurality of signal transmission lines; The signal transmission lines include at least one first signal transmission line, at least one second signal transmission line, a first clock signal line, a second clock signal line, and a control signal line; The first signal transmission line is used for transmitting the first level signal; The second signal transmission line is used for transmitting the second level signal; The first clock signal line is used for transmitting the first clock signal of the odd-stage shift register and the second clock signal of the even-stage shift register; The second clock signal line is used for transmitting the second clock signal of the odd-stage shift register and the first clock signal of the even-stage shift register; The control signal line is used for transmitting the output control signal of each stage of the shift register. The display panel of claim 60, wherein The distance between any two adjacent first signal transmission lines and second signal transmission lines is a first distance; The distance between the first clock signal line and the second clock signal line is a second distance; The first distance is greater than the second distance. The display panel of claim 60, wherein The first clock signal line and the second clock signal line are two adjacent signal transmission lines in the plurality of signal transmission lines. The display panel of claim 60, wherein The first shift control submodule further includes a first coupling control transistor; a gate of the first coupling control transistor is electrically connected to the sixth node, a first electrode of the first coupling control transistor receives the second clock signal, and a second electrode of the first coupling control transistor is electrically connected to the second charge pump unit; The second shift control submodule includes at least a first control transistor, a second control transistor, a third control transistor, a fourth control transistor, and a control capacitor; a gate of the first control transistor receives the first clock signal, a first electrode of the first control transistor receives the first level signal, and a second electrode of the first control transistor is electrically connected to a seventh node; A gate of the second control transistor is coupled to the first node, a first electrode of the second control transistor receives the first clock signal, and a second electrode of the second control transistor is electrically connected to the seventh node; A gate of the third control transistor is coupled to the seventh node, a first electrode of the third control transistor receives the second clock signal, and a second electrode of the third control transistor is electrically connected to an eighth node; A gate of the fourth control transistor receives the second clock signal, a first electrode of the fourth control transistor is electrically connected to the eighth node, and a second electrode of the fourth control transistor is electrically connected to the second node; and the control capacitor is electrically connected between the seventh node and the eighth node; The third metal layer further includes a second connection structure; the third control transistor and the fourth control transistor of the odd-stage shift register and the first coupling control transistor of the even-stage shift register are electrically connected to the second clock signal line through the same second connection structure. The display panel of claim 50, wherein The shift register further includes a plurality of second transistors; the second transistors include a second active layer and a third gate; The semiconductor layer further includes the second active layer; and the second metal layer further includes the third gate. The display panel of claim 64, wherein The first metal layer further includes a first light shielding structure; In a thickness direction of the display panel, the first light shielding structure covers a channel region of each second active layer. The display panel of claim 65, wherein The first light shielding structure receives a shielding signal. The display panel of claim 66, wherein A voltage of the shielding signal is V0; a voltage of the first level signal is V1, and a voltage of the second level signal is V2; wherein |V0|<|V1| and |V0|<|V2|. The display panel according to claim 1, characterized in that, In the same shift register, the gate drive signal is at an invalid level during a time period in which the shift signal is at a valid level. The display panel according to claim 1, characterized in that, In the same shift register, a valid level time of the gate drive signal overlaps with a valid level time of the shift signal. The display panel according to claim 1, characterized in that, The working mode of the display panel includes a first mode; In the first mode, at least part of the shift registers are first shift registers, and the output control signal includes a valid level and an invalid level; In at least part of the time in the first mode, in the first shift register, a frequency of the shift signal is greater than a frequency of the gate drive signal. The display panel of claim 70, wherein The time of the invalid level of the shift signal overlaps with the time of the invalid level of the output control signal in the first shift register. The display panel of claim 71, wherein The time when the output control signal jumps from the valid level to the invalid level is the first time, and the starting time of the valid level of the shift signal is the second time in the first shift register; the first time is before the second time. The display panel of claim 70, wherein Part of the shift registers are second shift registers in the first mode. The frequency of the shift signal is equal to the frequency of the gate driving signal in the second shift register in the first mode. The display panel according to claim 1, characterized in that, The working mode of the display panel further includes a second mode. The output control signal is a valid level, and the frequency of the shift signal is equal to the frequency of the gate driving signal in the second mode. A display device characterized by comprising: Comprising: The display panel of any one of claims 1-74.

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